Identified regions in the shared region for optimal parity

Abstract

The present invention discloses a storage device that is capable of identifying zones for sharing parity blocks across zones. Valid zones can be separated across multiple valid zones with similar zone attributes, and the valid zones can be grouped so that parity buffers can be shared. By identifying zones for optimal parity sharing, the storage device and system can: (i) maintain independent parity for all zones during initial zone writes (i.e., during the erase state where data is written directly to the page without writing to the zone), (ii) track zone write pointers and the frequency of writes in the zone, (iii) separate zones with higher correlation and group them together, (iv) utilize these groups placed across various channels so that zones with high correlation (including zones written together and zones written at the same rate) share the parity buffer, and (v) load and XOR each parity buffer for optimal parity sharing across all zones.

Description

[0001] Priority

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 076,233, filed September 9, 2020, which is incorporated herein in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to storage devices. More particularly, these embodiments relate to storage devices having identified zones for optimal parity sharing across zones. Background Art

[0004] There are many forms of non-volatile memory, including electrically erasable programmable read-only memory (EEPROM). EEPROM can be erased and reprogrammed in blocks rather than one byte at a time. Typical flash memory includes a memory array that includes a large number of memory cells. These cells are usually grouped into segments called "erase blocks." Each cell in the erase block can be electrically programmed. All memory cells in an erase block are erased in a single operation.

[0005] Flash memory devices are widely used for both primary and secondary storage in computer systems. The density and size of flash memory have increased with semiconductor scaling. Consequently, cell size has decreased, leading to lower inherent durability in next-generation commodity flash memory devices. The low durability of flash memory devices can severely limit the applications in which flash memory can be used and has a significant impact on solid-state drive (SSD) storage devices.

[0006] Recently, methods for improving SSD endurance, including reducing write amplification, have included clustering and the use of extent maps (extent maps). Clustering refers to storing related data for a table in a sorted order in contiguous on-disk data blocks. An extent map is then added to index the clustered data stored on disk. Specifically, the extent map divides the clustered data into contiguous on-disk "zones" or "extents" of contiguous disk blocks. The extent map allows the SSD to appropriately map the data to the physical media.

[0007] For zone mapping, the host needs to utilize the full bandwidth of the SSD device with minimal latency for partition commands. Existing methods typically involve utilizing a parity buffer for zone mapping and sharing zones based on their physical location. However, these methods often produce undesirable results, including continuous parity loading and interruptions from the single-level cell (SLC) cache. In fact, higher write operations to the SLC result in higher write amplification, leading to inefficient use of the DRAM buffer. Therefore, endurance management techniques are needed to extend the endurance of SSDs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of several embodiments of the present disclosure will become more apparent from the following description presented in conjunction with the following drawings.

[0009] Figure 1A An exemplary block diagram of a nonvolatile memory system according to an embodiment of the present disclosure is shown;

[0010] Figure 1B An exemplary block diagram of a memory module having a memory system according to an embodiment of the present disclosure is shown;

[0011] Figure 1C An exemplary block diagram of a hierarchical storage system according to an embodiment of the present disclosure is shown;

[0012] Figure 2 A schematic block diagram of a system having a host computing device and a storage device according to an embodiment of the present disclosure is shown;

[0013] Figure 3A A schematic block diagram illustrating an embodiment of a controller of a storage device configured to identify zones for optimal parity sharing across zones according to an embodiment of the present disclosure is shown;

[0014] Figure 3B A schematic block diagram illustrating an embodiment of a non-volatile memory device of a storage device configured to identify regions for optimal parity sharing across regions according to an embodiment of the present disclosure;

[0015] Figure 4 A schematic block diagram illustrating planes in a memory structure according to an embodiment of the present disclosure;

[0016] Figures 5A to 5E An exemplary block diagram depicting a partition map structure according to an embodiment of the present disclosure is shown. Figure 6 blocks, regions, parity bits, and dies used by the controller during the process of

[0017] Figure 6 A flowchart illustrating a process for identifying zones for optimal parity sharing across zones is shown, according to an embodiment of the present disclosure;

[0018] 7A to 7D shows an exemplary block diagram depicting a partition map structure including blocks, regions, parity bits, and dies according to an embodiment of the present disclosure; and

[0019] Figures 8A to 8BAn exemplary block diagram depicting a partition map structure including blocks, regions, parity bits, and dies is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The embodiments described herein relate to storage devices, systems, and related methods for identifying zones for optimal parity sharing across zones. As described in more detail below, these embodiments also include separating multiple valid zones with similar zone attributes (i.e., zones with higher correlation) and grouping them for sharing parity buffers. By identifying zones for optimal parity sharing, these embodiments enable storage devices and systems to: (i) maintain independent parity for all zones during initial zone writes (i.e., an initial erased state in which the zones do not share parity), (ii) track zone write pointers and write frequencies in zones, (iii) separate zones with higher correlation and group them together, (iv) utilize these groups placed across various channels so that zones with higher correlation (i.e., zones that are cut in together and zones that are written at the same rate) share a parity buffer, and (v) load each parity buffer and perform an XOR operation on it for optimal parity sharing across all zones.

[0021] Such embodiments ultimately benefit storage devices and systems with the following advantages: optimizing DRAM buffer usage and reducing parity loads and interruptions between the SLC cache and the DRAM. Furthermore, as described in the embodiments below, reducing continuous parity loads and interruptions also enables lower write amplification and improved overall performance of the storage device and system.

[0022] Aspects of the present disclosure may be embodied as devices, systems, methods, or computer program products. Therefore, aspects of the present disclosure may take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, all of which may be collectively referred to herein as "functions," "modules," "devices," or "systems." In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable program code and / or computer-executable program code. Many of the functional units described in this specification have been labeled as functions in order to more specifically emphasize the implementation independence of these functional units. For example, a function may be implemented as a hardware circuit comprising a custom VLSI circuit or gate array, a readily available semiconductor such as a logic chip, a transistor, or other discrete components. Functions may also be implemented in a programmable hardware device such as via a field programmable gate array, a programmable array logic unit, a programmable logic device, or the like.

[0023] Functionality may also be implemented at least in part in software for execution by various types of processors. An identified executable code function may, for example, comprise one or more physical or logical blocks of computer instructions, which may be organized, for example, as objects, procedures, or functions. However, the executable files for an identified function need not be physically located together, but may comprise different instructions stored in different locations that, when logically joined together, comprise the function and achieve the purpose described for the function.

[0024] In practice, executable code functionality may include a single instruction or many instructions, and may even be distributed over several different code snippets, between different programs, across several memory devices, and the like. When functionality or portions of functionality are implemented in software, these software portions may be stored on one or more computer-readable storage media and / or computer-executable storage media. Any combination of one or more computer-readable storage media may be utilized. For example, a computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination of the foregoing, but does not include propagating signals. In the context of this document, a computer-readable storage medium and / or computer-executable storage medium may be any tangible and / or non-transitory medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, processor, or device.

[0025] The computer program code for performing the operations of various aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Python, Java, Smalltalk, C++, C#, Objective C, etc., conventional procedural programming languages ​​such as the "C" programming language, scripting programming languages, and / or other similar programming languages. The program code may be executed partially or completely on one or more user computers and / or on a remote computer or server over a data network or the like.

[0026] As used herein, a component includes a tangible, physical, non-transient device. For example, a component may be implemented as: a hardware logic circuit including a custom VLSI circuit, a gate array, or other integrated circuit; an off-the-shelf semiconductor, such as a logic chip, a transistor, or other discrete device; and / or other mechanical or electrical device. A component may also be implemented in a programmable hardware device such as a field programmable gate array, a programmable array logic component, a programmable logic device, or the like. A component may include one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices that are electrically connected to one or more other components via wires of a printed circuit board (PCB), etc. In certain embodiments, each of the functions and / or modules described herein may alternatively be embodied or implemented as a component.

[0027] As used herein, a circuit includes a group of one or more electrical and / or electronic components that provide one or more paths for an electric current. In certain embodiments, a circuit may include a return path for the electric current, making the circuit a closed loop. However, in another embodiment, a group of components that does not include a return path for the electric current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether it is grounded (as a return path for the electric current). In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a group of integrated circuits, a group of non-integrated electrical and / or electronic components with or without an integrated circuit device, and the like. In one embodiment, a circuit may include: a custom VLSI circuit, a gate array, a logic circuit, or other integrated circuit; an off-the-shelf semiconductor, such as a logic chip, a transistor, or other discrete device; and / or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device, such as a field programmable gate array, a programmable array logic unit, a programmable logic device, and the like (e.g., as firmware, a netlist, etc.). A circuit may include one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices in electrical communication with one or more other components via wires on a printed circuit board (PCB), etc. In certain embodiments, each of the functions and / or modules described herein may be embodied or implemented as a circuit.

[0028] References throughout this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment," "in an embodiment," and similar language appearing throughout this specification may, but do not necessarily, all refer to the same embodiment, but rather to "one or more but not all embodiments," unless expressly stated otherwise. The terms "comprises," "comprising," "having," and variations thereof mean "including but not limited to," unless expressly stated otherwise. An enumerated list of items does not mean that any or all of the items are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. The terms "a," "an," and "the" also mean "one or more," unless expressly stated otherwise.

[0029] Furthermore, as used herein, references to reading, writing, storing, buffering, and / or transmitting data may include the entire data, a portion of the data, a data set, and / or a subset of the data. Similarly, references to reading, writing, storing, buffering, and / or transmitting non-host data may include the entire non-host data, a portion of the non-host data, a non-host data set, and / or a subset of the non-host data.

[0030] Finally, as used herein, the terms "or" and "and / or" should be interpreted as inclusive or meaning any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." An exception to this definition occurs only when a combination of elements, functions, steps, or actions are inherently mutually exclusive in some way.

[0031] Aspects of the present disclosure are described below with reference to schematic flow charts and / or schematic block diagrams of the methods, devices, systems, and computer program products according to embodiments of the present disclosure. It should be understood that each frame of the schematic flow charts and / or schematic block diagrams, and the combination of frames in the schematic flow charts and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor or other programmable data processing device of a computer to produce a machine, so that the instructions executed by the processor or other programmable data processing device create a device for implementing the functions and / or actions specified in one or more frames of the schematic flow charts and / or schematic block diagrams.

[0032] It should also be noted that in some alternative embodiments, the functions shown in the blocks may not occur in the order shown in the figures. For example, in fact, two blocks shown in succession may be executed substantially simultaneously, or these blocks may sometimes be executed in the opposite order, depending on the functions involved. Other steps and methods that are equivalent to one or more blocks or portions thereof in function, logic, or effect can be envisioned. Although various arrow types and line types can be used in flow charts and / or block diagrams, it should be understood that these arrow types and line types do not limit the scope of the corresponding embodiments. For example, an arrow can indicate a waiting or monitoring period of unspecified duration between the enumerated steps of the depicted embodiment.

[0033] In the following detailed description, reference is made to the accompanying drawings. The foregoing summary of the invention is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the accompanying drawings and the following detailed description. The description of the elements in each figure may refer to the elements of the preceding figures. Like numbers may refer to like elements in the drawings, including alternative embodiments of like elements.

[0034] Examples of suitable non-volatile memory arrangements in which the systems and methods disclosed herein may be used are in Figures 1A to 1C. That is, the following embodiments disclose non-volatile memory systems and devices and related methods for dynamically managing various host applications (e.g., data flows) based on minimum QoS requirements. Before turning to these and other embodiments, the following paragraphs provide some exemplary non-volatile memory systems, storage devices, and storage modules that can be used with such embodiments. It should be understood that any other suitable embodiments of non-volatile memory systems, devices, and / or storage modules can be used alone or in combination without limitation.

[0035] Now see Figure 1A , shows an exemplary block diagram of a non-volatile memory system 100 according to some embodiments. The non-volatile memory system 100 includes a storage device 120 (or non-volatile storage device) having a controller 102 and non-volatile memory, which may be composed of one or more non-volatile memory devices 104 (also referred to as NV memory, memory, memory die, etc.). In one embodiment, the non-volatile memory device 104 may include a group of non-volatile memory cells formed on a single semiconductor substrate, and associated circuitry (or logic components) for managing the physical operation of those non-volatile memory cells.

[0036] In one embodiment, the controller 102 interacts with the host 112 and transmits a command sequence for a read operation, a program operation, and an erase operation to the non-volatile memory device 104. The controller 102 may take the form of, for example, a processing circuit, a microprocessor or a processor, and a computer-readable medium (e.g., software or firmware) storing computer-readable program code that can be executed by a (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. The controller 102 may be configured with various hardware and / or firmware to perform the various functions described below and shown in the flow chart. In addition, some components shown as being internal or external to the controller 102 may be stored externally or internally, respectively, to the controller, and other components may be used.

[0037] In some embodiments, controller 102 may be a flash memory controller, etc. A flash memory controller may be a device that manages data stored on a flash memory and communicates with a host, such as a computer or electronic device. In addition to the specific functions described herein, a flash memory controller may have functions. For example, a flash memory controller may format the flash memory to ensure proper operation of the memory, identify bad flash memory cells, and allocate spare cells to replace future failed cells. Some of the spare cells may be used to house firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it communicates with the flash memory controller. If the host provides a logical address for the data to be read / written, the flash memory controller may convert the logical address received from the host into a physical address in the flash memory. Note that the host may alternatively provide a physical address. The flash memory controller may also perform various memory management functions, such as, but not limited to, wear leveling (i.e., distributing writes to avoid wearing out specific memory blocks that would otherwise be repeatedly written), garbage collection (i.e., moving only valid data pages to a new block after a block is full, thereby allowing the entire block to be erased and reused), and / or any other similar memory management functions.

[0038] In some embodiments, the non-volatile memory device 104 may include any suitable storage device, medium, or element, including NAND flash memory cells and / or NOR flash memory cells. The memory cells may be in the form of solid-state (e.g., flash) memory cells and may be programmable once, programmable a few times, or programmable multiple times. Additionally, as described above, the memory cells may also be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or use any other memory technology now known or later developed. Additionally, the memory cells may be arranged in a two-dimensional or three-dimensional configuration without limitation.

[0039] The interface between the controller 102 and the non-volatile memory device 104 can be any suitable flash memory interface, such as a double data rate (DDR) interface. In one embodiment, the non-volatile memory system 100 can be a card-based system, such as a secure digital (SD) or micro secure digital (micro-SD) card. In an alternative embodiment, the non-volatile memory system 100 can be part of an embedded memory system.

[0040] In addition, it should be pointed out that if Figure 1AAs shown, the non-volatile memory system 100 includes a single channel between the controller 102 and the non-volatile memory device 104. Although the illustrated embodiment shows a single memory channel, any number of channels may be used without departing from the spirit and scope of the present disclosure. For example, in some NAND memory system architectures, there are 2, 4, 8, or more NAND channels between the controller 102 and the NAND memory devices, based on the capabilities of the controller. Similarly, in any other embodiment described herein, even if a single channel is shown in the figures, there may be a single channel and / or two or more channels between the controller and the memory die.

[0041] In some embodiments, the storage device 120, along with the non-volatile memory device 104 and the controller 102, can be configured to identify zones for optimal parity sharing across zones. For example, as in the following embodiments (e.g., in at least Figures 5A to 5E 、 Figure 6 、 7A to 7D and Figures 8A to 8B As described in more detail in the accompanying drawings, one or more of the controller 102, the non-volatile memory device 104, and the storage device 120 may be configured to: (i) maintain independent parity for all zones during initial zone writes (i.e., during an initial erase state where data is initially written directly to a page or wordline (e.g., typically 4KB-8KB in size)), (ii) track zone write pointers, write frequency, and zones that are written together at the same time, (iii) separate zones that are written together from zones that are written at the same rate (i.e., zones with high correlation) and group them into different groups, (iv) utilize these groups placed across various channels so that zones with higher correlation share parity buffers, and (v) load individual parity buffers that have been XORed for optimal parity sharing across all zones.

[0042] Now see Figure 1B , which shows an exemplary block diagram of a storage module 200 according to some embodiments. According to some embodiments, the storage module 200 includes a storage system 204 having a plurality of storage devices 120. Thus, the storage module 200 may include a storage system similar to Figure 1AIn one embodiment, the storage module 200 may include one or more non-volatile memory systems of the non-volatile memory system 100 in the host 111. In one embodiment, the storage module 200 may include a storage controller 202 that interfaces with the host 111 and the storage system 204, which includes a non-volatile memory system composed of the storage device 120, the non-volatile memory device 104, and the controller 102. The interface between the storage controller 202 and the non-volatile memory system (or storage device 120) may be a bus interface, such as a Serial Advanced Technology Attachment (SATA) or Peripheral Component Interconnect Express (PCIe) interface. In some embodiments, the storage module 200 may be a solid-state drive (SSD), such as found in portable computing devices such as laptop computers and tablet computers.

[0043] Now see Figure 1C , which shows an exemplary block diagram of a hierarchical storage system 210 according to some embodiments. In one embodiment, the hierarchical storage system 210 may include multiple storage controllers 202, each storage controller controlling a corresponding storage system 204. In addition, the hierarchical storage system 210 may be communicatively coupled to one or more hosts 112 (or host systems), which may access the memory within the hierarchical storage system 210 via a bus interface (or the like). In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe), a Fibre Channel over Ethernet (FCoE) interface, or the like. In one embodiment, Figure 1C The illustrated hierarchical storage system 210 may be a rack-mountable mass storage system that is accessible to multiple host computers, such as might be found in a data center or other location where mass storage is required.

[0044] Figure 2 FIG2 shows a schematic block diagram of a computing system 201 having a host computing device 205 and a storage system 224 according to some embodiments. The computing system 201 may include one or more storage devices 120 in the storage system 224, which are communicatively coupled to the host computing device 205 via the controller 102. The host computing device 205 may be similar to the host computing device 205 described above with reference to FIG22. Figures 1A to 1CThe host 112. The host computing device 205 may include a processor 211, a volatile memory 212, and a communication interface 213. The processor 211 may include one or more central processing units, one or more general-purpose processors, one or more dedicated processors, one or more virtual processors (for example, the host computing device 205 may be a virtual machine operating within the host), one or more processor cores, etc. The communication interface 213 may include one or more network interfaces configured to couple the controller 102 of the host computing device 205 and / or the storage device 120 to a network 215 (or communication network), such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless or wired network, etc.

[0045] In some embodiments, the storage device 120 may be disposed in one or more different locations relative to the host computing device 205. In other embodiments, the storage device 120 may be disposed strictly within the storage system 224, wherein the storage system 224 and the host computing device 205 are separate components that communicate via a bus or the like. In one embodiment, the storage device 120 includes one or more non-volatile memory devices (or dies) 104, such as semiconductor devices and / or any other similar integrated circuit devices disposed on one or more PCBs, storage housings, and / or other mechanical and / or electrical support structures. For example, the storage device 120 may include one or more in-line memory module (DIMM) cards, one or more expansion cards and / or daughter cards, an SSD or other hard drive device, and / or may have another memory and / or storage form factor. The storage device 120 may be integrated with and / or mounted on a motherboard of the host computing device 205, mounted in a port and / or slot of the host computing device 205, mounted on a different host computing device 205, and / or on a dedicated storage device on the network 215, communicate with the host computing device 205 via an external bus (e.g., an external hard drive, etc.), etc.

[0046] In further embodiments, the storage device 120 may be provided on a memory bus of the processor 211 (e.g., on the same memory bus as the volatile memory 212, on a different memory bus than the volatile memory 212, in place of the volatile memory 212, etc.). In another embodiment, the storage device 120 may be provided on a peripheral bus of the host computing device 205, such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus (such as, but not limited to, an NVMe interface), a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switch (PCIe-AS) bus, etc. In another embodiment, the storage device 120 may be provided on a network 215, such as an Ethernet network, an Infiniband network, SCSI RDMA over a network, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network, etc.

[0047] The host computing device 205 may also include a computer-readable storage medium 214. The computer-readable storage medium 214 may include executable instructions configured to cause the host computing device 205 (e.g., the processor 211) to perform the steps of one or more methods disclosed herein. Additionally or alternatively, the buffer component 250 may be embodied as one or more computer-readable instructions stored on the computer-readable storage medium 214.

[0048] For some embodiments, the controller 102 (or device driver) may present a logical address space 234 to the host client 216. The logical address space 234 may include a plurality (e.g., a range) of logical addresses. The logical address space 234 may refer to any identifier used to reference a memory resource (e.g., data), including, but not limited to, a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an inode, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a signature, an index entry, a range, an extent, and the like.

[0049] The controller 102 (or driver) of the storage device 120 may maintain metadata 235, such as a logical-to-physical address mapping structure, to map logical addresses of the logical address space 234 to media storage locations on one or more storage devices 120. The controller 102 may be configured to provide storage services to one or more host clients 216. The host clients 216 may include local clients operating on the host computing device 205 and / or remote clients 217 (or remote host clients) accessible via the network 215 and / or the communication interface 213. The host clients 216 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0050] The controller 102 may further be communicatively coupled to one or more storage systems 224, which may include storage devices 120 of different types and configurations, such as, but not limited to, solid-state storage devices, semiconductor storage devices, SAN storage resources, and the like. The one or more storage devices 120 may include one or more corresponding controllers 102 and non-volatile memory channels 222. The controller 102 may provide access to the one or more storage devices 120 via any compatible protocol or interface 233, such as, but not limited to, SATA and PCIe. Metadata 235 may be used to manage and / or track data operations performed via the protocol or interface 233. The logical address space 234 may include a plurality of logical addresses, each corresponding to a corresponding media location of the one or more storage devices 120. The controller 102 may maintain metadata 235, which includes any-to-any mappings between logical addresses and media locations.

[0051] The controller 102 may also include and / or communicate with a storage device interface 239 configured to transmit data, commands, and / or queries to the one or more storage devices 120 via a bus 225, which may include, but is not limited to, a memory bus of the processor 211, a PCI Express or PCIe bus, a Serial Advanced Technology Attachment (ATA) bus, a Parallel ATA bus, a Small Computer System Interface (SCSI), FireWire, Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switch (PCIe-AS) bus, a network 215, Infiniband, SCSI RDMA, etc. The storage device interface 239 may communicate with the one or more storage devices 120 using one or more input / output control (IO-CTL) commands, one or more IO-CTL command extensions, remote direct memory access, etc.

[0052] The communication interface 213 may include one or more network interfaces configured to communicatively couple the host computing device 205 and / or the controller 102 to a network 215 and / or to one or more remote clients 217. The host computing device 205 may communicate with the storage device 120 via a pair of bus interfaces 245 and 255, which may be used to transfer applications with QoS requirements (such as a minimum throughput required by some applications). The controller 102 may be part of and / or communicate with one or more storage devices 120. Additionally, although Figure 2 A single storage device 120 is shown, but computing system 201 and / or storage system 224 are not limited in this regard and may be adapted to incorporate any number of storage devices 120 .

[0053] The storage device 120 may include one or more non-volatile memory devices 104 of a non-volatile memory channel 222, which may include, but are not limited to: ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano-RAM or NRAM), nanocrystal wire-based memory, silicon oxide-based sub-10 nm process memory, graphene memory, silicon oxide nitride oxide (SONOS), programmable metallization cell (PMC), conductive bridging RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, etc. In some embodiments, the one or more non-volatile memory devices 104 of the non-volatile memory channel 222 may include storage class memory (SCM) (e.g., write-in-place memory, etc.).

[0054] Although the non-volatile memory channel 222 may be referred to as a "memory medium," in various embodiments, the non-volatile memory channel 222 may more generally include one or more non-volatile recording media capable of recording data, which may be referred to as non-volatile memory media, non-volatile storage media, etc. Furthermore, in various embodiments, the storage device 120 may include a non-volatile recording device, a non-volatile memory array, a plurality of interconnected storage devices in an array, etc.

[0055] The non-volatile memory channel 222 may include one or more non-volatile memory devices 104, which may include, but are not limited to, chips, packages, planes, dies, etc. The controller 102 may be configured to manage data operations on the non-volatile memory channel 222 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the controller 102 may be configured to store data on and / or read data from the non-volatile memory channel 222, to transfer data to / from the storage device 120, etc.

[0056] The controller 102 may be communicatively coupled to the nonvolatile memory channel 222 via a bus 227. The bus 227 may include an I / O bus for transferring data to / from the nonvolatile memory devices 104. The bus 227 may also include a control bus for transferring addressing and other command and control information to the nonvolatile memory devices 104. In some embodiments, the bus 227 may communicatively couple the nonvolatile memory devices 104 to the controller 102 in parallel. This parallel access may allow the nonvolatile memory devices 104 to be managed as a group, thereby forming a nonvolatile memory array 229. The nonvolatile memory devices 104 may be divided into their respective logical memory units (e.g., logical pages) and / or logical memory partitions (e.g., logical blocks and logical planes). A logical memory unit may be formed by logically combining the physical memory units of each nonvolatile memory device 104 in a nonvolatile memory element.

[0057] In some embodiments, the controller 102 can be organized into blocks of word lines within the non-volatile memory device 104 using the addresses of the word lines such that the word lines are logically organized into a monotonically increasing sequence (e.g., decoding and / or converting the addresses of the word lines into a monotonically increasing sequence, etc.). In yet another embodiment, the word lines of a block within the non-volatile memory device 104 can be physically arranged in a monotonically increasing sequence of word line addresses, where consecutively addressed word lines are also physically adjacent (e.g., as shown below). Figure 4 WL0, WL1, WL2, ... WLN in FIG).

[0058] Controller 102 may include and / or communicate with device drivers executing on host computing device 205. For example, controller 102 and / or such device drivers may provide storage services to host clients 216 via one or more interfaces 233. Likewise, controller 102 and / or such device drivers may also include a storage device interface 239 configured to transmit data, commands, and / or queries to controller 102 via bus 225, as described above.

[0059] Now see Figure 3A , a schematic block diagram of a system 300 illustrates in greater detail exemplary components of the storage device 120 according to some embodiments. The controller 102 may include a front-end module 308 for interacting with a host, a back-end module 310 for interacting with the non-volatile memory device (or die) 104, and various other modules that perform various functions of the non-volatile memory device 100.

[0060] Generally speaking, a module can be hardware or a combination of hardware and software. For example, each module may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware, or a combination thereof. In addition or alternatively, each module may include memory hardware that includes instructions that can be executed by a processor or processor circuit to implement one or more of the features of the module. When any of the one or more modules includes a portion of memory that includes instructions that can be executed by a processor, the module may or may not include a processor. In some examples, each module may be simply a portion of memory that includes instructions that can be executed by a processor to implement the features of the corresponding module, without the module including any other hardware. Because each module includes at least some hardware, each module can be interchangeably referred to as a hardware module even when the included hardware includes software.

[0061] The controller 102 may include a buffer manager / bus controller 314 that manages buffers in random access memory (RAM) 316 and controls internal bus arbitration for communication on an internal communication bus 317 of the controller 102. A read-only memory (ROM) 318 may store and / or access system boot code. Additionally, although Figure 3A 318 are shown as being located separately from the controller 102, but in other embodiments, the RAM 316 and / or ROM 318 may be located within the controller 102. In yet another embodiment, portions of the RAM 316 and / or ROM 318 may be located within the controller 102 and external to the controller 102. Furthermore, in some implementations, the controller 102, RAM 316, and ROM 318 may be located on separate semiconductor devices (or dies).

[0062] Additionally, the front-end module 308 may include a host interface 320 and a physical layer interface 322 that provide an electrical interface with a host or a next-level storage controller. The type of host interface 320 selected may depend on the type of memory being used. Example types of host interface 320 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 320 may generally facilitate the transmission of data, control signals, and timing signals.

[0063] The back-end module 310 may include an error correction controller (ECC) engine 324 that encodes data bytes received from the host and decodes and error corrects data bytes read from the non-volatile memory device 104. As discussed below, the ECC engine 324 may be adjustable, such as generating different amounts of ECC data based on the mode (e.g., generating normal mode ECC data in normal programming mode and generating mixed mode ECC data in mixed mode programming mode, where the mixed mode ECC data is larger than the normal mode ECC data). The back-end module 310 may also include a command sequencer 326 that generates command sequences, such as a program command sequence, a read command sequence, and an erase command sequence, for transmission to the non-volatile memory device 104.

[0064] In addition, the back-end module 310 may include a RAID (Redundant Array of Independent Drives) module 128, which manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the non-volatile memory system 100. In some cases, the RAID module 328 can be part of the ECC engine 324. The memory interface 330 provides command sequences to the non-volatile memory devices 104 and receives status information from the non-volatile memory devices 104. Along with the command sequences and status information, data to be programmed into and read from the non-volatile memory devices 104 can be transmitted via the memory interface 130. In one embodiment, the memory interface 330 can be a double data rate (DDR) interface. The flash control layer 332 can control the overall operation of the back-end module 310.

[0065] Figure 3AAdditional modules of the non-volatile memory system 100 shown in FIG may include a media management layer 338 that performs wear leveling of the memory cells of the non-volatile memory device 104. The non-volatile memory system 100 may also include other discrete components 340, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interact with the controller 102. In alternative embodiments, one or more of the RAID module 328, the media management layer 338, and the buffer management / bus controller 314 are optional components that may not be required in the controller 102.

[0066] See also Figure 3B , a schematic block diagram illustrates in more detail exemplary components of a storage device 120 according to some embodiments. The storage device 120 may be communicatively coupled to a host using a controller 102. The non-volatile memory device 104 may include a non-volatile memory array 342. The non-volatile memory array 342 may include a plurality of non-volatile memory elements or cells, each configured to store one or more data bits. The non-volatile memory elements or cells may be any suitable non-volatile memory cells, including NAND flash memory cells and / or NOR flash memory cells in a two-dimensional configuration and / or a three-dimensional configuration. The memory cells may be in the form of solid-state (e.g., flash) memory cells and may be one-time programmable, several-time programmable, or multiple-time programmable. In addition, as described above, the memory elements or cells may be configured as SLC storing a single data bit per cell, multi-level cell MLC storing multiple data bits per cell, or a combination thereof. For example, in these embodiments, MLC includes TLC, QLC, etc. storing three, four, and more than four bits of data per cell.

[0067] Furthermore, the flash memory cells may include floating gate transistors (FGTs) within the nonvolatile memory array 342, each having a floating gate and a control gate. The floating gate is surrounded by an insulator or insulating material that helps retain charge within the floating gate. The presence or absence of charge within the floating gate may cause a shift in the threshold voltage of the FGT, which is used to distinguish logic levels. In other words, the threshold voltage of each FGT may indicate the data stored in the memory cell. Hereinafter, the terms FGT, memory element, and memory cell may be used interchangeably to refer to the same physical entity.

[0068] For example, SLCs and MLCs may be arranged in a matrix of rows and columns of memory cells in the nonvolatile memory array 342. At the intersections of rows and columns are FGTs (or memory cells). A column of FGTs may be referred to as a string. The FGTs in a string or column may be electrically connected in series, while a row of FGTs may be referred to as a page. The control gates of the FGTs in a page or row may be electrically connected or otherwise coupled together.

[0069] The nonvolatile memory array 342 may also include word lines and bit lines connected to the FGTs. Each page of FGTs is coupled to a word line. Specifically, each word line may be coupled to the control gate of an FGT in the page. Furthermore, each string of FGTs may be coupled to a bit line. Furthermore, a single string may span multiple word lines, and the number of FGTs in a string may be equal to the number of pages in a block.

[0070] In some embodiments, the nonvolatile memory device 104 may include a peripheral circuit 341 having a state machine 352 that provides state information to the controller 102. The nonvolatile memory device 104 also includes a data cache 356 that caches data. The nonvolatile memory device 104 may also include a row address decoder 348 and a column address decoder 350. When reading from or writing data to memory cells in the nonvolatile memory array 342, the row address decoder 348 may decode a row address and select a specific word line in the nonvolatile memory array 342. The column address decoder 350 may decode a column address to select a specific group of bit lines in the nonvolatile memory array 342 to be electrically coupled to the data cache 344.

[0071] The data cache 356 may include multiple sets of data latches 357 for each bit of data in a memory page of the non-volatile memory array 342. Thus, each set of data latches 357 may be page-wide, and multiple sets of data latches 357 may be included in the data cache 356. Additionally, in other embodiments, the controller 102 may be implemented as a single integrated circuit chip and may communicate with one or more different memory layers in the non-volatile memory device 104 via one or more command channels. Note that in other embodiments, the controller executable code for implementing the memory management instructions described herein may be stored in non-volatile flash memory.

[0072] Furthermore, as described herein, the nonvolatile memory array 342 can be arranged in blocks of memory cells, where one block of memory cells is the unit of erase, i.e., the smallest number of memory cells that can be physically erased together. However, to increase parallelism, blocks can be operated in larger metablock (MB) units. One block from each of at least two planes of memory cells can be logically linked together to form a metablock.

[0073] Now see Figure 4 , shows a block diagram illustration of two planes 400 and 402 according to some embodiments. Planes 400 and 402 can be part of a memory structure, etc. For example, planes 400 and 402 can be Figure 1A 、 Figure 2 and Figures 3A to 3B, where the nonvolatile memory device 104 may include planes 400 and 402 in conjunction with a plurality of other planes.

[0074] In some embodiments, planes 400 and 402 can be divided into a large number of blocks 408 and 410 (e.g., blocks 0 to 1023 or other amounts). Each block 408 and 410 includes a plurality of memory cells. In one embodiment, each block 408 and 410 is an erase unit and is therefore sometimes referred to as an erase block. That is, each block contains the minimum number of memory cells that are erased together. Other erase units may also be used. A block may include a set of NAND strings accessed via bit lines (e.g., bit lines BL0-BL69, 623) and word lines (WL0, WL1, WL2, WL3). For example, block 1 shows four memory cells connected in series to form a NAND string. Although four memory cells are depicted as being included in each NAND string, more or less than four memory cells may be used (including, as non-limiting examples, 16, 32, 64, 128, 256 or other number of memory cells). One terminal of the NAND string is connected to the corresponding bit line via a drain select gate (connected to a select gate drain line SGD), and the other terminal is connected to the source line via a source select gate (connected to a select gate source line SGS). Figure 4 69624 bit lines are shown in FIG, but it should be understood that any number of bit lines may be used without limitation. Additionally, as described above, the block may implement non-volatile storage technologies other than NAND flash memory.

[0075] Each block 408 and 410 is typically divided into multiple pages. In one embodiment, a page is the unit of programming. Other programming units may also be used. The data of one or more pages is typically stored in a row of memory cells. For example, the data of one or more pages may be stored in memory cells connected to a common word line. An example of a page may be all the data stored in the memory cells connected to the common word line and in a common block. Another example of a page is a portion (e.g., 1 / 4, 1 / 2, 1 / 3) of the memory cells connected to the common word line and in a common block, or a portion of the bits stored in those memory cells. A page includes user data and overhead data (also referred to as system data). Overhead data typically includes header information and ECC calculated from the user data of the sector. The controller (or other component) calculates the ECC when data is programmed into the array and also checks it when data is read from the array.

[0076] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within the distribution of threshold voltages for erased memory cells, as appropriate. For example, the memory system may use a threshold voltage distribution for the memory cell array when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one bit of data, two bits of data, four bits of data, or five bits of data per memory cell).

[0077] Examples of suitable nonvolatile memory arrangements (or structures) including multi-cell erase blocks and multi-block regions (or logical regions) in which the devices, systems, and associated methods disclosed herein may be used are described in Figures 5A to 5E 、 7A to 7D and Figures 8A to 8B Some embodiments may include a nonvolatile memory system and / or device having a multi-cell erase block array, where the array may be logically partitioned into multiple multi-block regions, and the blocks of each region may be physically adjacent.

[0078] Additionally, the following exemplary embodiments described below can use algorithms to identify zones for optimal parity sharing across zones. That is, in these embodiments described below, zones with high correlation are identified to facilitate grouping zones for parity sharing across all zones. In some embodiments, this optimal parity sharing with highly correlated zones facilitates the storage devices and systems described herein to optimize DRAM buffer usage and reduce parity loading and interrupts.

[0079] Now see Figure 5A , shows an exemplary schematic block diagram of a memory structure 500 during an initial zone write according to some embodiments. The memory structure 500 can be implemented to identify zones for optimal parity sharing across zones. The memory structure 500 can be part of a non-volatile memory device and / or system. For example, the memory structure 500 can be a RAM or the like (e.g., DRAM). Additionally, Figures 5A to 5E The memory structure 500 in may be (or be similar to) the memory structure 500 described above in Figures 1A to 1C 、 Figure 2 、 Figures 3A to 3B and Figure 4 A portion of one or more of the storage devices, systems, and / or modules described in.

[0080] In some embodiments, the memory structure 500 includes a plurality of physical blocks 520 (in Figure 5A ), a plurality of corresponding regions 510 (shown as B0-B1 in Figure 5A, multiple parity buffers 550 (shown as Z1-Z8 in Figure 5A 8) and metablocks 560-561. Additionally, the memory structure 500 may include a die 530 (shown in FIG. Figure 5A The dies are positioned adjacent to each other and their corresponding channels 540 (shown as D0-D3 in FIG. Figure 5A In addition, the memory structure 500 may have a configuration in which one physical block 520 is directly mapped to one corresponding zone 510. For example, a host or the like may implement a zone size approximately equal to one physical block size 520. Figures 5A to 5E One region size may be arranged to be equal to one physical block die size, but it should be understood that any other suitable configuration of memory structure 500, such as different sizes, numbers, locations, etc., may be used without limitation.

[0081] In addition, if Figure 5A As shown, the memory structure 500 can be configured to keep the parity buffer 550 independent of all zones 510 during an initial zone write (i.e., writing a few pages or word lines). In some embodiments, the parity buffer 550 can be kept independent of all zones 510 at the beginning of a write sequence (i.e., the independent parity buffer is composed of Figure 5A However, in other embodiments, based on the base NAND used, if a corresponding region 510 has multiple die 530 within its corresponding block 520, the parity buffer 550 may be able to be shared with other planes / pages / wordlines or other die 530.

[0082] Now see Figure 5B , shows an exemplary schematic block diagram of a memory structure 500 identifying different zone groups according to some embodiments. Embodiments of the memory structure 500 may be configured to track write command attributes of all zones 510 being written, including but not limited to zone write pointers, write frequency, zones written together most of the time, initial write data, etc. Now, based on these zone writes on different blocks 520, possible zone groups 551-552 may be initiated for all zones 510 based on the tracked write command attributes and any other expected / observed write dependencies (e.g., in Figure 5B The possible region candidates are shown in the same pattern in FIG. 1 ). For example, Figure 5B As shown, most of the zones 510 are written at different rates, so that the attributes being tracked may not be as common as other attributes. Figure 5B Only two possible banks are shown in FIG. 5 , but memory structure 500 may utilize fewer or more than two possible banks as desired.

[0083] Now see Figure 5C , shows an exemplary schematic block diagram of a memory structure 500 for separating and grouping regions with high correlation according to some embodiments. Embodiments of the memory structure 500 can be configured to separate regions with high correlation and then group them together into different region groups 515 and 525. For example, regions with high correlation include, but are not limited to, regions that are written together and regions that are written at the same rate. In addition, as Figure 5C As shown, the memory structure 500 has eight zones separated and grouped into two different zone groups 515 and 525. For example, the first separated zone group 515 includes zones Z1, Z5, Z9, and Z13, and the second separated zone group 525 includes zones Z2, Z6, Z11, and Z16. In some embodiments, the first zone group 525 and the second zone group 525 have been grouped together after combining various zone write commands, how zone writes combine with other zone writes, and zones with similar properties when opened.

[0084] Now see Figures 5D to 5E , shows an exemplary schematic block diagram of a memory structure 500 according to some embodiments. Embodiments of the memory structure 500 can be configured to utilize banks 535 and 545 placed across various channels 540 such that banks with higher correlation share parity buffers 550. Additionally, embodiments of the memory structure 500 can be configured to load individual parity buffers 550 and perform an XOR operation on the loaded parity buffers for sharing parity across bank groups 551-552, where the newly shared parity buffers 580 and 590 are now sequenced and shared across different banks 550 (i.e., the shared parity buffers 580 and 590 are composed of Figure 5E In these embodiments, the above information is used in conjunction with the physical location of the zone 550 to form zone groups, and their respective parity buffers are XORed to obtain the resulting parity buffers 580 and 590, as shown in FIG. Figure 5E As shown. In addition, these compressed parity buffers (P'x) can now be cached in DRAM, and the parity interrupts and loads are substantially minimized by having partition groups. As described above, this shared parity across zones results in optimized DRAM buffer usage and reduced parity loads and interrupts, which ultimately provides optimal device performance.

[0085] Now see Figure 6 , shows a high-level flow diagram of an exemplary process 600 for identifying regions for optimal parity sharing across all regions, according to some embodiments. Figure 6 The process 600 in FIG. Figures 5A to 5E For example, process 600 may be configured to use the Figures 5A to 5E The memory structure 500 described in or any other memory device and system described herein may be used to identify regions for optimal parity sharing across regions.

[0086] First, at block 610, process 600 maintains independent parity for all zones during initial zone writes (i.e., writing to a few pages or word lines). At block 620, process 600 tracks zone write pointers, write frequency, and zones that are written together most of the time. At block 630, process 600 separates zones with high correlation (i.e., zones written together and zones written at the same rate) and groups the separated zones into different zone groups. At block 640, process 600 utilizes zone groups placed across various channels so that zones with high correlation to the zone group share corresponding parity buffers. Finally, at block 650, process 600 loads the individual parity buffers and XORs the loaded parity buffers for cross-zone parity sharing.

[0087] Now see 7A to 7D , shows an exemplary schematic block diagram of a memory structure 700 according to some embodiments. The memory structure 700 can be implemented to identify regions for optimal parity sharing across regions while also reducing the RAM time for any parity P1 generation. The memory structure 700 can be substantially similar to the one described above in Figures 5A to 5E Thus, the regions, blocks, channels, dies, metablocks, and parity buffers of the memory structure 700 may be substantially similar to Figures 5A to 5E The components of the memory structure 500 are used.

[0088] like Figure 7D As shown, the memory structure 700 is configured to similarly identify regions for optimal parity sharing across regions by identifying regions with high correlation and grouping them together as shared parity region groups 751-752, similar to Figure 5E Configuration shown. However, in some embodiments, the memory structure 700 has some similar host write workloads from other zones 753, but the most frequent parity buffers 750 required are P1 and P2, which are cached in DRAM, and parity interrupts and loads are kept to a minimum. In this case, occasional accesses to other zones 753 are managed by loading the parity buffers in temporary locations and not evicting the older parity buffers 750P1 and P2. In other words, parity buffers 750P1 and P2 are not loaded into the cache until they are released or "evicted" to create new space for new data due to data usage exceeding a data threshold in the cache.

[0089] In addition, if Figure 7D As shown, parity generation in memory structure 700 is delayed, and the buffer needs to stay in DRAM longer. However, by sharing the shared parity buffer 750 with the highly correlated zones 751-752, the probability of the zones being written at the same rate is increased, which helps prevent the parity in RAM from being retained longer than necessary. That is, sharing the parity buffer 750 across the zones 751-752 with higher correlation now results in write pointers being in similar offset regions, and such buffers can be generated quickly and dumped to the SLC cache instead of being retained in DRAM.

[0090] Now see Figures 8A to 8B , shows an exemplary schematic block diagram of a memory structure 800 according to some embodiments. The memory structure 800 can be implemented to identify regions for optimal parity sharing across regions, and / or to utilize such shared parity region groups for efficient cache management. The memory structure 800 can be substantially similar to that described above in Figures 5A to 5E Thus, the regions, blocks, channels, dies, metablocks, and parity buffers of the memory structure 800 may be substantially similar to Figures 5A to 5E The components of the memory structure 500 are used.

[0091] In these embodiments, if the memory structure 800 cannot assign the same parity buffer to all zones in the zone group 851-852 (e.g., due to underlying physical properties, recovery time considerations, etc.), the memory structure 800 still uses it for efficient cache management. For example, because P2 is shared across zones with high correlation, etc., the memory structure 800 can be configured to avoid evicting P2 even when the write operation is not directed to the zone it shares. Therefore, P2 will receive cache preference and will not be evicted. In addition, along with DRAM sharing, the memory structure 800 can also provide similar preference to the internal controller memory SRAM and use the same logic to cache data.

[0092] The information shown and described in detail herein is fully capable of achieving the above-mentioned objects of the present disclosure (the presently preferred embodiments of the present disclosure), and therefore represents the subject matter broadly envisioned by the present disclosure. The scope of the present disclosure fully encompasses other embodiments that may become apparent to those skilled in the art, and therefore will not be subject to any other limitations except those set forth in the appended claims. Unless expressly stated otherwise, any reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". All structural and functional equivalents of the elements of the above-mentioned preferred embodiments and other embodiments that are considered by those of ordinary skill in the art are hereby expressly incorporated by reference and are intended to be covered by the present claims.

[0093] Furthermore, no system or method is required to solve each and every problem sought to be solved by the present disclosure, nor is it required that the present claims encompass solutions to such problems. Furthermore, no element, component, or method step of the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. It will be apparent to those skilled in the art that various changes and modifications may be made in form, materials, workpiece, and manufacturing material details without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A storage device, comprising: one or more memories; as well as One or more controllers configured to: Maintaining independent parity blocks of the first zone under the initial zone write command; tracking a plurality of write command attributes associated with the first region; separating a plurality of second zones from the first zone, wherein the plurality of second zones are initially associated with the first channel; grouping the plurality of second zones into zone groups; as well as The plurality of second zones are reallocated from the zone group across a plurality of channels such that the independent parity blocks are shared with the plurality of second zones of the zone group based on zones having high correlation.

2. The storage device of claim 1, further comprising loading the independent parity blocks through an XOR circuit for sharing across the block groups.

3. The storage device according to claim 1, wherein the plurality of channels consists of the first channel and a second channel. 4 . The memory device of claim 1 , wherein one or more of the first channels associated with the second zone are different from second channels of the second zone. 5 . The storage device of claim 1 , wherein the plurality of write command attributes consists of at least one or more of: a region write pointer, a write frequency, and regions that are written together most of the time. 6 . The memory device of claim 1 , wherein separating the plurality of second regions from the first region is based on the regions having a high correlation.

7. The storage device of claim 6 , wherein the zones having high correlation are comprised of zones written together and zones written at the same rate, and wherein the independent parity blocks are shared with the plurality of second zones of the zone group based on the zones having high correlation rather than zones having high physical proximity.

8. The storage device of claim 1, wherein the zones from the group of zones with higher correlation share the same independent parity block.

9. A method of identifying a region for shared parity in a storage device, the method comprising: Maintaining independent parity blocks of the first zone under the initial zone write command; tracking a plurality of write command attributes associated with the first region; separating a plurality of second zones from the first zone, wherein the plurality of second zones are initially associated with the first channel; grouping the plurality of second zones into zone groups; reallocating the plurality of second zones from the zone group across a plurality of channels, wherein the independent parity blocks are shared by a corresponding plurality of second zones of the zone group; as well as The independent parity blocks are loaded through an XOR circuit to form a loaded parity block for sharing across the block.

10. The method of claim 9, wherein the grouping of the plurality of second regions is based on any of a region write command, regions written in conjunction with other regions, and regions having similar attributes when opened, and wherein the similar attributes include regions having the same first word line. The method of claim 9 , wherein the plurality of channels consists of the first channel and a second channel.

12. The method of claim 9, wherein one or more of the first channels associated with the second zone are different from second channels of the second zone.

13. The method of claim 9, wherein the plurality of write command attributes consists of at least one or more of: region write pointers, write frequency, and regions written with equal timestamps. The method of claim 9 , wherein separating the plurality of second regions from the first region is based on regions having high correlation.

15. The method of claim 13, wherein the areas having high correlation are composed of the areas written together and areas written at the same rate.

16. The method of claim 9, wherein the zones from the group of zones with higher correlation share the same independent parity block.

17. A storage device, comprising: one or more memories; as well as One or more controllers configured such that: Maintaining independent parity blocks of the first zone under the initial zone write command; tracking a plurality of write command attributes associated with the first region; separating a plurality of second zones from the first zone, wherein each second zone of the plurality of second zones is initially associated with a first channel; grouping the plurality of second zones into zone groups; reallocating the plurality of second zones from the zone group across a plurality of channels, wherein the independent parity blocks are shared by corresponding second zones of the zone group; as well as The independent parity blocks are loaded through an XOR circuit to form a loaded parity block that is shared across the block.

18. The memory device of claim 17, wherein the grouping of the plurality of second zones is based on any one of a zone write command, zones written in conjunction with other zones, and zones having similar attributes when opened, wherein the similar attributes include zones having the same first word line.

19. The storage device of claim 17, wherein the plurality of channels consists of the first channel and a second channel.

20. The memory device of claim 17, wherein one or more of the first channels associated with the second zone are different from second channels of the second zone.

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