A method, device, system and medium for verifying functions of modules in an FPGA

Abstract

The application provides a function verification method, device, system and medium of each module in an FPGA, comprising: establishing data streams corresponding to each module respectively according to the characteristics of each module in the FPGA, analyzing the data contained in each data stream, and extracting the configuration data corresponding to each module in the data, and matching the configuration data with each SRAM in the FPGA circuit netlist; when the matching result is consistent, the configuration data is used to configure and simulate each module to complete the function verification of each module. Without integrating modeling according to the size of the SRAM storage unit and the resources of the FPGA, the design and development efficiency is improved, the design verification time is shortened under the premise of ensuring the reliability of the function verification.

Description

Technical Field

[0001] This application relates to the field of programmable logic devices, and in particular to a method, apparatus, system, and medium for verifying the functionality of various modules in an FPGA. Background Technology

[0002] In the design process of FPGA (Field Programmable Gate Array) chips, the functional verification of various modules in the FPGA, such as CLB (Configurable Logic Block), INT (Switch Interconnect Block), and BRAM (Block Random Access Memory), requires writing the corresponding functional data stream into the storage configuration unit of the corresponding SRAM (Static Random Access Memory) of each module.

[0003] Currently, the main way to achieve the above verification process is to integrate and model the SRAM storage cells and FPGA resources during the forward design process of the FPGA, and use the data flow generated by the model to configure and simulate the circuits of the corresponding functional modules in the simulation verification platform. This method requires establishing data connections between the FPGA module models and the SRAM configuration cells, which is time-consuming. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method, apparatus, system and medium for verifying the functionality of various modules in an FPGA.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] In a first aspect, embodiments of this application provide a method for verifying the functionality of various modules in an FPGA, including:

[0007] Based on the characteristics of each module in the FPGA, establish the data flow corresponding to each module;

[0008] Parse the data contained in each data stream and extract the configuration data corresponding to each module from the data;

[0009] The configuration data is matched with each SRAM in the FPGA circuit netlist;

[0010] When the matching results are consistent, the configuration data is used to perform configuration simulation on each module in order to complete the functional verification of each module.

[0011] In one possible implementation, matching the configuration data with each SRAM in the FPGA circuit netlist includes:

[0012] Extract the bit lines corresponding to each SRAM;

[0013] Match the configuration data with the bit lines.

[0014] In one possible implementation, parsing the data contained in each data stream and extracting the configuration data corresponding to each module from the data includes:

[0015] Identify the data corresponding to the frame address register of each data stream;

[0016] Determine the module corresponding to the block type in the data corresponding to the frame address register;

[0017] Extract the configuration data corresponding to each module from the data corresponding to the frame address register.

[0018] In one possible implementation, the method further includes:

[0019] The data stream is compressed.

[0020] Secondly, embodiments of this application provide a functional verification device for various modules in an FPGA, including:

[0021] The establishment unit is used to establish the data flow corresponding to each module according to the characteristics of each module in the FPGA;

[0022] The parsing unit is used to parse the data contained in each data stream and extract the configuration data corresponding to each module from the data;

[0023] A matching unit is used to match the configuration data with each SRAM in the FPGA circuit netlist;

[0024] The simulation unit is used to perform configuration simulation on each module using the configuration data when the matching result is consistent, so as to complete the functional verification of each module.

[0025] In one possible implementation, the matching unit includes:

[0026] The first extraction unit is used to extract the bit lines corresponding to each SRAM;

[0027] A matching subunit is used to match the configuration data with the bit lines.

[0028] In one possible implementation, the parsing unit includes:

[0029] The identification unit is used to identify the data corresponding to the frame address register of each data stream;

[0030] The judgment unit is used to determine the module corresponding to the block type in the data corresponding to the frame address register;

[0031] The second extraction unit is used to extract the configuration data corresponding to each module from the data corresponding to the frame address register.

[0032] In one possible implementation, the device further includes:

[0033] A compression unit is used to compress the data stream.

[0034] Thirdly, embodiments of this application provide a functional verification system for various modules in an FPGA, including:

[0035] Memory, used to store computer programs;

[0036] A processor is used to execute the computer program to implement the steps of the functional verification method for each module in the FPGA as described above.

[0037] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when processed and executed, implements the steps of the functional verification method for each module in the FPGA as described above.

[0038] This application provides a method, apparatus, system, and medium for functional verification of modules in an FPGA. The method includes: establishing data streams corresponding to each module based on their characteristics; parsing the data contained in each data stream and extracting configuration data corresponding to each module; matching the configuration data with each SRAM in the FPGA circuit netlist; and when the matching results are consistent, performing configuration simulation on each module using the configuration data to complete the functional verification of each module. This eliminates the need for integrated modeling based on the size of the SRAM storage units and the resources of the FPGA, improving design and development efficiency and shortening design verification time while ensuring the reliability of functional verification. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This document illustrates a flowchart of a method for verifying the functionality of various modules in an FPGA, as provided in an embodiment of this application.

[0041] Figure 2 A schematic diagram of a functional verification device for various modules in an FPGA provided in an embodiment of this application is shown. Detailed Implementation

[0042] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0044] As described in the background section, during the design of FPGA (Field Programmable Gate Array) chips, the functional verification of various modules in the FPGA, such as CLB (Configurable Logic Block), INT (Switch Interconnect Block), and BRAM (Block Random Access Memory), requires writing the corresponding functional data stream into the storage configuration unit of the corresponding SRAM (Static Random Access Memory) of each module.

[0045] Currently, the main way to achieve the above verification process is to integrate and model the SRAM storage cells and FPGA resources during the forward design process of the FPGA, and use the data flow generated by the model to configure and simulate the circuits of the corresponding functional modules in the simulation verification platform. This method requires establishing data connections between the FPGA module models and the SRAM configuration cells, which is time-consuming.

[0046] To address the aforementioned technical issues, this application provides a method, apparatus, system, and medium for functional verification of modules within an FPGA. The method includes: establishing data streams corresponding to each module based on their characteristics; parsing the data contained in each data stream; extracting configuration data corresponding to each module from the data; matching the configuration data with each SRAM in the FPGA circuit netlist; and when the matching results are consistent, performing configuration simulation on each module using the configuration data to complete the functional verification of each module. This eliminates the need for integrated modeling based on the size of SRAM storage units and FPGA resources, improving design and development efficiency and shortening design verification time while ensuring the reliability of functional verification.

[0047] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0048] Exemplary methods

[0049] See Figure 1 As shown, this figure is a flowchart of a method for verifying the functionality of various modules in an FPGA according to an embodiment of this application, including:

[0050] S101: Based on the characteristics of each module in the FPGA, establish the data stream corresponding to each module.

[0051] In the embodiments of this application, different modules in the FPGA have different functional characteristics. For example, the CLB module is the most basic building block of the FPGA and can implement basic combinational logic and sequential circuits; the BRAM module can be configured as a single-port RAM, dual-port RAM and other common storage structures, which greatly expands the application range and versatility of the FPGA.

[0052] Based on the characteristics of each functional module of the FPGA, Verilog code can be written to develop and obtain the corresponding functional data stream, that is, bit stream data about "0" and "1" that matches the characteristics of each functional module of the FPGA.

[0053] In addition, all switches and corresponding SRAM cells in each functional module can be obtained from the netlist of each functional module of the FPGA, as well as the connection relationship between each functional module and the SRAM, so that the data stream can be written into the SRAM after the data stream and each functional module are matched.

[0054] S102: Parse the data contained in each data stream and extract the configuration data corresponding to each module from the data.

[0055] In this embodiment, the data stream generated by the method in S101 contains many redundant data fields, such as dummy pad word fields and no-op word fields. To improve the efficiency of parsing the data, redundant data such as dummy pad words and no-op words in the data stream can be removed first. Simultaneously, to save storage space, the data stream can be compressed.

[0056] Then, the data stream can be parsed to obtain the type of data contained in the data stream and the data corresponding to the data area in the data stream. Specifically, a data processing platform that simulates the functions of CFG hardware can be built using programming languages ​​such as Python, Tcl, or Perl, and the data stream can be imported into the data processing platform for parsing and processing.

[0057] Specifically, it can identify the data corresponding to the frame address register (FDRI) of each data stream, parse the data of the frame address register, determine the block type corresponding to each module in the data of the frame address register, that is, determine which functional module of the FPGA the Block Type in the frame address register refers to, and then read the row address and column address of this functional module so as to accurately match the configuration data with the SRAM of each functional module in the future.

[0058] Since the matching process only requires matching the configuration data in the stream data with the SRAM, it is possible to further extract the configuration data corresponding to each module from the data in the frame address register.

[0059] S103: Match the configuration data with each SRAM in the FPGA circuit netlist.

[0060] S104: When the matching result is consistent, the configuration data is used to perform configuration simulation on each module to complete the functional verification of each module.

[0061] Specifically, in the embodiments of this application, the SRAM cell symbol name and its corresponding bit line (BL) in the circuit netlist can be extracted and presented in a hierarchical circuit structure. For example, the name can be topsymbol.secongsymbol.xxx.SRAMsymbol.BL.

[0062] Matching the configuration data with the bit lines involves finding the degree of matching between the configuration data and the sorting pattern of the set bit line data. Specifically, it can be finding the part of the configuration data that is consistent with the symbol sorting. If they are consistent, the remaining SRAM symbol names can be sorted according to the sorting pattern of the matching SRAM symbol names so that the data streams corresponding to each functional module of the FPGA can be written into the corresponding SRAM storage configuration unit of each module.

[0063] When the matching results are consistent, the configuration data is used to perform configuration simulation on each module to complete the functional verification of each module. If the simulation runs normally, it means that the matching results are correct. There is no need to integrate and model based on the size of the SRAM storage unit and the FPGA resources, which improves the design and development efficiency. While ensuring the reliability of functional verification, the design verification time is shortened. It realizes a one-to-one correspondence between the data stream file and the SRAM configuration circuit corresponding to each circuit module in the FPGA circuit design simulation platform, eliminating the need for manual comparison and debugging, and saving time and costs.

[0064] This application provides a method for functional verification of modules in an FPGA, including: establishing data streams corresponding to each module based on their characteristics; parsing the data contained in each data stream; extracting configuration data corresponding to each module from the data; matching the configuration data with each SRAM in the FPGA circuit netlist; and when the matching result is consistent, performing configuration simulation on each module using the configuration data to complete the functional verification of each module. This method eliminates the need for integrated modeling based on the size of SRAM storage units and FPGA resources, improving design and development efficiency and shortening design verification time while ensuring the reliability of functional verification.

[0065] Exemplary device

[0066] See Figure 2 The diagram shown is a schematic of a functional verification device for various modules in an FPGA provided in an embodiment of this application, including:

[0067] Establishment unit 201 is used to establish the data stream corresponding to each module according to the characteristics of each module in the FPGA;

[0068] The parsing unit 202 is used to parse the data contained in each data stream and extract the configuration data corresponding to each module from the data;

[0069] Matching unit 203 is used to match the configuration data with each SRAM in the FPGA circuit netlist;

[0070] The simulation unit 204 is used to perform configuration simulation on each module using the configuration data when the matching result is consistent, so as to complete the functional verification of each module.

[0071] In one possible implementation, the matching unit includes:

[0072] The first extraction unit is used to extract the bit lines corresponding to each SRAM;

[0073] A matching subunit is used to match the configuration data with the bit lines.

[0074] In one possible implementation, the parsing unit includes:

[0075] The identification unit is used to identify the data corresponding to the frame address register of each data stream;

[0076] The judgment unit is used to determine the module corresponding to the block type in the data corresponding to the frame address register;

[0077] The second extraction unit is used to extract the configuration data corresponding to each module from the data corresponding to the frame address register.

[0078] In one possible implementation, the device further includes:

[0079] A compression unit is used to compress the data stream.

[0080] This application provides a functional verification device for modules in an FPGA. The method applied to this device includes: establishing data streams corresponding to each module based on their characteristics; parsing the data contained in each data stream; extracting configuration data corresponding to each module from the data; matching the configuration data with each SRAM in the FPGA circuit netlist; and when the matching result is consistent, performing configuration simulation on each module using the configuration data to complete the functional verification of each module. This eliminates the need for integrated modeling based on the size of the SRAM storage units and the resources of the FPGA, improving design and development efficiency and shortening the design verification time while ensuring the reliability of functional verification.

[0081] Based on the above embodiments, this application also provides a functional verification system for various modules in an FPGA, including:

[0082] Memory, used to store computer programs;

[0083] A processor is used to execute the computer program to implement the steps of the functional verification method for each module in the FPGA as described above.

[0084] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program, which, when processed and executed, implements the steps of the functional verification method for each module in the FPGA as described above.

[0085] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0087] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for verifying the functionality of various modules in an FPGA, characterized in that, include: Based on the characteristics of each module in the FPGA, establish the data flow corresponding to each module; Parse the data contained in each data stream and extract the configuration data corresponding to each module from the data; The configuration data is matched with each SRAM in the FPGA circuit netlist; When the matching result is consistent, the configuration data is used to perform configuration simulation on each module in order to complete the functional verification of each module; The step of matching the configuration data with each SRAM in the FPGA circuit netlist includes: Extract the bit lines corresponding to each SRAM; Match the configuration data with the bit lines.

2. The method according to claim 1, characterized in that, The process of parsing the data contained in each data stream and extracting the configuration data corresponding to each module from the data includes: Identify the data corresponding to the frame address register of each data stream; Determine the module corresponding to the block type in the data corresponding to the frame address register; Extract the configuration data corresponding to each module from the data corresponding to the frame address register.

3. The method according to claim 1, characterized in that, The method further includes: The data stream is compressed.

4. A functional verification device for various modules in an FPGA, characterized in that, include: The establishment unit is used to establish the data flow corresponding to each module according to the characteristics of each module in the FPGA; The parsing unit is used to parse the data contained in each data stream and extract the configuration data corresponding to each module from the data; A matching unit is used to match the configuration data with each SRAM in the FPGA circuit netlist; The simulation unit is used to perform configuration simulation on each module using the configuration data when the matching result is consistent, so as to complete the functional verification of each module. The matching unit includes: The first extraction unit is used to extract the bit lines corresponding to each SRAM; A matching subunit is used to match the configuration data with the bit lines.

5. The apparatus according to claim 4, characterized in that, The parsing unit includes: The identification unit is used to identify the data corresponding to the frame address register of each data stream; The judgment unit is used to determine the module corresponding to the block type in the data corresponding to the frame address register; The second extraction unit is used to extract the configuration data corresponding to each module from the data corresponding to the frame address register.

6. The apparatus according to claim 4, characterized in that, The device further includes: A compression unit is used to compress the data stream.

7. A functional verification system for various modules in an FPGA, characterized in that, include: Memory, used to store computer programs; A processor, used to execute the computer program to implement the steps of the functional verification method for each module in the FPGA as described in any one of claims 1-3.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when processed and executed, implements the steps of the functional verification method for each module in the FPGA as described in any one of claims 1-3.

Images