Write Circuit of Memory Device

Abstract

The present disclosure relates to a write circuit of a memory device. A device includes a memory bank, a first pair of write data wirings, a second pair of write data wirings, and a global write circuit. The first pair of write data wirings is connected to a first group in the memory bank. The second pair of write data wirings is connected to a second group in the memory bank. In response to a first clock signal, the global write circuit generates a first global write signal and a first complement global write signal, and the first global write signal and the first complement global write signal are sent to the first group in the memory bank through the first pair of write data wirings. In response to a second clock signal, the global write circuit generates a second global write signal and a second complement global write signal, and the second global write signal and the second complement global write signal are sent to the second group in the memory bank through the second pair of write data wirings.

Description

Technical Field

[0001] The present disclosure generally relates to a write circuit of a memory device. Background Art

[0002] Electronic devices and electronics-based systems require some form of high-speed memory device to store and retrieve information. Random Access Memory (RAM) is commonly used in integrated circuits. Embedded RAM is particularly popular in high-speed communication, image processing, and System-on-Chip (SOC) applications. The RAM includes an array of individual memory cells. A user can perform both read and write operations on the memory cells of the RAM. During a write process, a write driver is used to set the voltage level on a global signal line connected to the memory array in the memory device. Summary of the Invention

[0003] According to an embodiment of the present disclosure, there is provided a memory device, including: a plurality of memory banks; a first pair of write data wirings connected to a first group of the memory banks; a second pair of write data wirings connected to a second group of the memory banks; and a global write circuit configured to receive a first clock signal and a second clock signal, wherein: in response to the first clock signal, the global write circuit generates a first global write signal and a first complement global write signal, and the first global write signal and the first complement global write signal are sent to the first group of the memory banks through the first pair of write data wirings; in response to the second clock signal, the global write circuit generates a second global write signal and a second complement global write signal, and the second global write signal and the second complement global write signal are sent to the second group of the memory banks through the second pair of write data wirings.

[0004] According to another embodiment of the present disclosure, there is provided a memory circuit, including: a control circuit configured to provide a first clock signal, a second clock signal, and a write data signal; a first global write driver coupled to a first pair of write data wirings, wherein the first global write driver is configured to generate a first global write signal and a first complement global write signal according to the write data signal in response to the first clock signal, and the first global write signal and the first complement global write signal are sent to a first group of a plurality of memory banks through the first pair of write data wirings; and a second global write driver coupled to a second pair of write data wirings, wherein the second global write driver is configured to generate a second global write signal and a second complement global write signal according to the write data signal in response to the second clock signal, and the second global write signal and the second complement global write signal are sent to the second group of the memory banks through the second pair of write data wirings.

[0005] According to another embodiment of the present disclosure, a method for a memory is provided, including: during a first writing process of a first group among a plurality of memory banks, providing a first clock signal to trigger a first global write driver to generate a first global write signal and a first complement global write signal according to a write data signal, and sending the first global write signal and the first complement global write signal to the memory banks in the first group through a first pair of write data wirings; and during a second writing process of a second group among the memory banks, providing a second clock signal to trigger a second global write driver to generate a second global write signal and a second complement global write signal according to the write data signal, and sending the second global write signal and the second complement global write signal to the memory banks in the second group through a second pair of write data wirings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or reduced.

[0007] Figure 1 is a schematic diagram showing a memory device according to various embodiments of the present disclosure.

[0008] Figure 2 is a schematic diagram showing Figure 1 the circuit structures of a global write circuit, a control circuit, and data latches in accordance with various embodiments of the present disclosure.

[0009] Figure 3 is a schematic diagram showing, in accordance with various embodiments of the present disclosure, Figure 1 the signal waveforms of related signals generated in a memory device.

[0010] Figure 4 is a schematic diagram showing a memory device according to various embodiments of the present disclosure.

[0011] Figure 5 is a schematic diagram showing a memory device according to various embodiments of the present disclosure.

[0012] Figure 6 is a schematic diagram showing a memory device according to various embodiments of the present disclosure.

[0013] Figure 7 is a flowchart showing a method according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and not restrictive. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0015] The terms used in this specification generally have their ordinary meanings in the art and in the particular context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of the present disclosure or any exemplary term. Similarly, the present disclosure is not limited to the various embodiments given in this specification.

[0016] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] As used herein, the terms "comprise", "include", "have", "contain", "involve", etc. should be understood as open-ended, i.e., meaning including but not limited to.

[0018] References to "one embodiment", "an embodiment", or "some embodiments" throughout this specification mean that a particular feature, structure, implementation, or characteristic described in connection with the (one or more) embodiments is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" used in various places throughout this specification do not necessarily all refer to the same embodiment. Further, in one or more embodiments, the particular features, structures, implementations, or characteristics may be combined in any suitable manner.

[0019] Figure 1 is a schematic diagram showing a memory device 100 according to various embodiments of the present disclosure. In Figure 1In the illustrated embodiment, the memory device 100 includes a plurality of memory banks BK1 to BK4, and each of the memory banks BK1 to BK4 can be accessed individually. For illustrative purposes, these four memory banks BK1 to BK4 in the memory device 100 are shown, but the present disclosure is not limited to the four memory banks BK1 to BK4. For example, the memory device 100 may include two, three, four, or more different memory banks.

[0020] In some embodiments, each of the memory banks BK1 to BK4 includes a memory array that includes a number of bit cells BC arranged in a plurality of rows and columns. As shown in the memory array CA1 of the memory bank BK1, these bit cells BC in the same column are connected to the same bit line and the same complementary bit line. For example, the bit cells BC in the first column are connected to the bit line BL1 and the complementary bit line BLB1, and the bit cells BC in the nth column are connected to the bit line BLn and the complementary bit line BLBn. Similarly, as shown in the memory array CA2 of the memory bank BK2, these bit cells BC in the same column are connected to the same bit line and the same complementary bit line. In some embodiments, the memory banks BK3 and BK4 also include structures similar to those of the memory banks BK1 and BK2. For the sake of brevity, the internal structures of the memory banks BK3 and BK4 are not fully shown in Figure 1 the figure.

[0021] As Figure 1 shown, the memory device 100 includes a global write circuit 120, a control circuit 140, data latches 160, a first pair of write data wirings W1a to W1b, and a second pair of write data wirings W2a to W2b. The control circuit 140 is configured to provide a clock signal CKD1, another clock signal CKD2, and a write data signal WD.

[0022] Based on the clock signal CKD1, the clock signal CKD2, and the write data signal WD provided by the control circuit 140, the global write circuit 120 is configured to generate two signals selected from a global write signal GW1, a complementary global write signal GWB1, another global write signal GW2, and another complementary global write signal GWB2 to perform a write process with respect to one of the memory banks BK1 to BK4. As Figure 1 shown, the memory banks BK1 to BK4 are arranged at different physical positions with respect to the global write circuit 120 in the memory device 100. As Figure 1As shown, memory banks BK1 to BK4 can be divided into two groups G1 and G2. Memory banks BK1 and BK2 in the first group G1 are relatively closer to the global write circuit 120, and memory banks BK3 and BK4 in the second group G2 are relatively farther from the global write circuit 120. In some embodiments, memory banks BK1 and BK2 in the first group G1 are connected to a first pair of write data wirings W1a and W1b, and memory banks BK3 and BK4 in the second group G2 are connected to a second pair of write data wirings W2a and W2b.

[0023] In some embodiments, the global write circuit 120 is capable of generating a global write signal GW1 and a complement global write signal GWB1, which are sent to memory banks BK1 and BK2 in the first group G1 through the first pair of write data wirings W1a to W1b. On the other hand, the global write circuit 120 is also capable of generating a global write signal GW2 and a complement global write signal GWB2, which are sent to memory banks BK3 and BK4 in the second group G2 through the second pair of write data wirings W2a to W2b.

[0024] In some embodiments, during a single write process, only one of the memory banks BK1 to BK4 is accessed by the memory device 100. In other words, the global write circuit 120 generates two of the four write-related signals (e.g., global write signal GW1, complement global write signal GWB1, global write signal GW2, and complement global write signal GWB2).

[0025] In the example, when the memory device 100 is configured to perform a write process on a bit cell BC in a memory bank BK1 (or BK2) in the first group G1, the global write circuit 120 can generate a global write signal GW1 and a complementary global write signal GWB1, which are sent to the memory bank BK1 (or BK2) in the first group G1 through the first pair of write data wirings W1a~W1b. In some embodiments, the local write driver 181 in the memory bank BK1 (or BK2) can generate a complementary local write signal LWB1 according to the global write signal GW1, and another local write driver 182 in the memory bank BK1 (or BK2) can generate a local write signal LW1 according to the complementary global write signal GW1B. If the write target is in the memory bank BK1, one selection circuit YS in the memory bank BK1 is activated to transfer the local write signal LW1 to one of the bit lines BL1~BLn in the memory bank BK1, and another selection circuit YS in the memory bank BK1 is activated to transfer the complementary local write signal LW1B to one of the complementary bit lines BLB1~BLBn in the memory bank BK1. If the write target is in the memory bank BK2, one selection circuit YS in the memory bank BK2 is activated to transfer the local write signal LW1 to one of the bit lines BL1~BLn in the memory bank BK2, and another selection circuit YS in the memory bank BK2 is activated to transfer the complementary local write signal LW1B to one of the complementary bit lines BLB1~BLBn in the memory bank BK2.

[0026] On the other hand, when the memory device 100 is configured to perform a write process on a bit cell BC in a memory bank BK3 (or BK4) in the second group G2, the global write circuit 120 can generate a global write signal GW2 and a complementary global write signal GWB2, which are sent to the memory bank BK3 (or BK4) in the second group G2 through the second pair of write data wirings W2a~W2b. Similar to the foregoing embodiments regarding the global write signal GW1 and the complementary global write signal GWB1 in the memory bank BK1 / BK2, the global write signal GW2 and the complementary global write signal GWB2 are converted into a complementary local write signal LW2B and a local write signal LW2 by the local write drivers 183 and 184 in the memory bank BK3 (or BK4). The complementary local write signal LW2B and the local write signal LW2 are transferred to the bit line or the complementary bit line ( Figure 1 not shown in the figure).

[0027] In some cases, if all the memory banks in the memory device (e.g., Figure 1In the memory device 100 in the illustrated embodiment, the memory banks BK1 to BK4 are driven by the same pair of write data wirings with the same pair of global write signals and complementary global write signals, a heavy resistive-capacitive (RC) load is formed on the pair of write data wirings, and the global write signals and the complementary global write signals suffer different levels of distortion when these signals reach different memory banks. For example, for a memory bank (such as Figure 1 the memory bank BK4 in the illustrated embodiment), the global write signals and the complementary local write signals may be severely distorted, and the memory bank may not correspondingly generate an operable pair of local write signals and complementary local write signals, so the write process for this memory bank may fail.

[0028] Compared with the foregoing case where all the memory banks in the memory device are driven by the same pair of write data wirings, Figure 1 the memory banks BK1 to BK4 of the memory device 100 in the schematically illustrated embodiment are divided into at least two groups G1 and G2. The memory banks BK1 and BK2 in the first group G1 are driven by a pair of global write signals GW1 and complementary global write signal GWB1 through a first pair of write data wirings W1a and W1b. The memory banks BK3 and BK4 in the second group G2 are driven by a pair of global write signals GW2 and complementary global write signal GWB2 through a second pair of write data wirings W2a and W2b. In other words, the memory device 100 includes separate multiple pairs of write data wirings (and separate multiple pairs of global write signals and complementary global write signals) for the memory banks in different groups G1 and G2. Therefore, the resistive-capacitive (RC) load on each pair of write data wirings is reduced. In this case, the write speed for the memory banks in the memory device 100 can be increased.

[0029] In some embodiments, compared with the write data wirings connected to all the memory banks, the capacitance on the write data wirings W1a and W1b connected to the memory banks BK1 and BK2 in the first group G1 can be reduced by about 50% because there is no need for the write data wirings W1a and W1b to extend far to reach the memory banks BK3 and BK4. In some embodiments, compared with the write data wirings connected to all the memory banks, the capacitance on the write data wirings W2a and W2b connected to the memory banks BK3 and BK4 in the second group G2 can be reduced by about 10% because there is no need for the write data wirings W2a and W2b to be connected to the memory banks B1 and B2 in the first group G1 on the way to reach the memory banks BK3 and BK4 in the second group G2.

[0030] In some embodiments, the control circuit 140 provides a clock signal CKD1, a clock signal CKD2, and a write data signal WD to control the global write circuit 120 during the execution of a write process. More details regarding how the global write circuit 120 responds to the clock signal CKD1, the clock signal CKD2, and the write data signal WD will be discussed in the following paragraphs.

[0031] Figure 2 is a schematic diagram showing the circuit structures of the Figure 1 global write circuit 120, the control circuit 140, and the data latch 160 in accordance with various embodiments of the present disclosure. Figure 3 is a signal waveform showing the relevant signals generated in the Figure 1 memory device 100 in accordance with various embodiments of the present disclosure. Relative to the Figure 1 embodiments, Figure 2 and Figure 3 the same elements in are labeled with the same reference numerals for easy understanding.

[0032] As Figure 2 shown, in some embodiments, the control circuit 140 provides a clock signal CKD1, a clock signal CKD2, and a write data signal WD. As Figure 3 shown by the time period M2 in, when the write target is in the memory bank BK1 or BK2 in the first group G1, the control circuit 140 provides an oscillating clock signal CKD1 (i.e., varying between a high level and a low level) and a suspended clock signal CKD2 (i.e., fixed at the low level). On the other hand, as Figure 3 shown by the time period M3 in, when the write target is in the memory bank BK3 or BK4 in the second group G2, the control circuit 140 provides an oscillating clock signal CKD2 (i.e., varying between a high level and a low level) and a suspended clock signal CKD1 (i.e., fixed at the low level).

[0033] The write data signal WD provided by the control circuit 140 defines the bit data to be written to the target bit cell. When the write data signal WD is logic "1", the corresponding global write signal GW1 (refer to the Figure 3 time period M2b in) is charged to a high level, or the corresponding global write signal GW2 (refer to the Figure 3 time period M3b in) is charged to a high level. When the write data signal WD is logic "0", the corresponding complementary global write signal GWB1 (refer to the Figure 3 time period M2a in) is charged to a high level, or the corresponding global write signal GWB2 (refer to the Figure 3 time period M3a in) is charged to a high level.

[0034] In as Figure 2In some of the illustrated embodiments, the memory device 100 further includes a NOR logic gate 170 and an inverter 171. The NOR logic gate 170 and the inverter 171 are coupled between the control circuit 140 and the data latch 160. The NOR logic gate 170 is configured to generate a clock signal CKnor based on a clock signal CKD1 and a clock signal CKD2. The inverter 171 is configured to invert the clock signal CKnor into another clock signal CKor. The clock signals CKnor and CKor are used to trigger the data latch 160. The relationship among the clock signal CKD1, the clock signal CKD2, the clock signal CKnor, and the clock signal CKor is shown in Table 1 below.

[0035] Clock signal CKD1 CKD2 CKnor CKor Voltage level L L H L Voltage level L H L H Voltage level H L L H

[0036] Table 1

[0037] As Figure 2 illustrated, in some embodiments, the data latch 160 includes eight transistors T1 to T8 and an inverter 161. The transistors T1 to T4 are serially coupled between a positive system power supply VDD and ground. The transistors T5 to T8 are serially coupled between the positive system power supply VDD and ground. The gates of transistors T1 and T7 are controlled by the clock signal CKor. The gates of transistors T4 and T6 are controlled by the clock signal CKnor. The gates of transistors T2 and T3 are controlled by a write data signal WD.

[0038] When both the clock signal CKD1 and the clock signal CKD2 are at the "L" level, the clock signal CKor at "L" turns on the transistor T1, and the clock signal CKnor at "H" turns on the transistor T4, such that the write data signal WD is introduced into the data latch 160 and stored as an inverted write signal WDBin. In Figure 2 the illustrated embodiment, the transistors T2 and T3 together function as an inverter, such that the voltage level of the inverted write signal WDBin is in the opposite logic with respect to the voltage level of the write data signal WD. At the same time, the transistor T6 is turned off by the clock signal CKnor at "H", and the transistor T7 is turned off by the clock signal CKor at "L", such that the latched write signal DX at the output terminal of the data latch 160 does not feedback to affect the inverted write signal WDBin stored in the data latch 160.

[0039] When one of the clock signals CKD1 and CKD2 is at the “H” level, the clock signal CKnor at the “L” level turns on the transistor T6, and the clock signal CKor at the “H” level turns on the transistor T7. In this case, the inverted write signal WDBin is inverted by the inverter 161 and output as the latch write signal DX to the global write circuit 120. The latch write signal DX is fed back to the transistors T5 and T8 to strengthen the inverted write signal WDBin stored in the data latch 160. At the same time, the transistor T1 is turned off by the clock signal CKor at the “H” level, and the transistor T4 is turned off by the clock signal CKnor at the “L” level, so that the write data signal WD at the input terminal of the data latch 160 is not introduced into the data latch 160 and does not affect the inverted write signal WDBin.

[0040] In some embodiments, the voltage level of the latch write signal DX has the same logic as the voltage level of the write data signal WD. The voltage level of the inverted write signal WDBin is in the opposite logic with respect to the voltage levels of the write data signal WD and the latch write signal DX.

[0041] In some embodiments, as Figure 2 schematically shown, the clock signal CKD1 provided by the control circuit 140 is delayed by two cascaded inverters as the delayed clock signal CKD1d, which is sent to the global write circuit 120 to control the first gating circuit 123 in the global write circuit 120. Similarly, the clock signal CKD2 provided by the control circuit 140 is also delayed by two cascaded inverters as another delayed clock signal CKD2d, which is transmitted to the global write circuit 120 to control the second gating circuit 124 in the global write circuit 120.

[0042] However, the present disclosure is not limited thereto. In some other embodiments, the clock signals CKD1 and CKD2 can be directly sent to the global write circuit 120 to control the first gating circuit 123 and the second gating circuit 124 in the global write circuit 120 without delay. Or in still other embodiments, the clock signals CKD1 and CKD2 can be delayed by more than two cascaded inverters before being sent to the global write circuit 120. The delay chain on the clock signals CKD1 and CKD2 depends on the configuration of the timing synchronization among the write data signal WD, the clock signal CKD1, and the clock signal CKD2 in the actual application.

[0043] As Figure 2Schematically shown, in some embodiments, the global write circuit 120 includes a first global write driver 121, a second global write driver 122, a first gating circuit 123, a second gating circuit 124, and an inverter 125. The inverter 125 is configured to generate an inverted latch write signal DXB, which has a logic opposite to that of the latch write signal DX.

[0044] In some embodiments, the first global write driver 121 is coupled between the data latch 160 and the first pair of write data wirings W1a and W1b. The first global write driver 121 is configured to generate a global write signal GW1 and a complementary global write signal GWB1 according to the latch write signal DX stored in the data latch 160. The first global write driver 121 includes four inverters 121a to 121d. The inverters 121a and 121b are coupled between the data latch 160 and the write data wiring W1a to receive the latch write signal DX and generate the global write signal GW1 accordingly. The inverters 121c and 121d are coupled between the inverter 125 and the write data wiring W1b to receive the inverted latch write signal DXB and generate the global write signal GW1B accordingly.

[0045] As Figure 2 Schematically shown, the first gating circuit 123 is coupled to the first global write driver 121. During the write process to one of the memory banks BK1 to BK2 in the first group G1, as Figure 3 shown in the time period M2 in, the clock signal CKD1 oscillates between a high level and a ground level. When the clock signal CKD1 oscillates to the high level, the corresponding delayed clock signal CKD1d turns on the transistor T9, which connects the negative power supply terminal of the inverters 121a and 121b to the ground level, and the corresponding delayed clock signal CKD1d turns off the transistors T10 and T11 in the first gating circuit 123. During the write process to one of the memory banks BK1 to BK2 in the first group G1, the latch write signal DX is transmitted to the write data wiring W1a through the inverters 121a and 121b, and the inverted latch write signal DXB is transmitted to the write data wiring W1b through the inverters 121c and 121d. As Figure 3 shown in the time period M2a in, when the write data signal WD is "L", the global write signal GW1 is fixed at "L", and the complementary global write signal GWB1 oscillates between "H" and "L". As Figure 3 shown in the time period M2b in, when the write data signal WD is "H", the global write signal GW1 oscillates between "H" and "L", and the complementary global write signal GWB1 is fixed at "L".

[0046] In some embodiments, the second global write driver 122 is coupled between the data latch 160 and the second pair of write data wirings W2a and W2b. The second global write driver 122 is configured to generate a global write signal GW2 and a complementary global write signal GWB2 according to the latched write signal DX stored in the data latch 160. The second global write driver 122 includes four inverters 122a to 122d. The inverters 122a and 122b are coupled between the data latch 160 and the write data wiring W2a for receiving the latched write signal DX and generating the global write signal GW2 accordingly. The inverters 122c and 122d are coupled between the inverter 125 and the write data wiring W2b for receiving the inverted latched write signal DXB and generating the global write signal GW2B accordingly.

[0047] As Figure 2 schematically shown, the second gating circuit 124 is coupled to the second global write driver 122. During the write process to one of the memory banks BK3 to BK4 in the second group G2, as Figure 3 shown by the time period M3 in, the clock signal CKD2 oscillates between a high level and a ground level. When the clock signal CKD2 oscillates to the high level, the corresponding delayed clock signal CKD2d turns on the transistor T12, which connects the negative power supply terminals of the inverters 122a and 122b to the ground level, and the corresponding delayed clock signal CKD2d turns off the transistors T13 and T14 in the second gating circuit 124. During the write process to one of the memory banks BK3 to BK4 in the second group G2, the latched write signal DX is transmitted to the write data wiring W2a through the inverters 122a and 122b, and the inverted latched write signal DXB is transmitted to the write data wiring W2b through the inverters 122c and 122d. As Figure 3 shown by the time period M3a in, when the write data signal WD is "L", the global write signal GW2 is fixed at "L", and the complementary global write signal GWB2 oscillates between "H" and "L". As Figure 3 shown by the time period M3b in, when the write data signal WD is "H", the global write signal GW2 oscillates between "H" and "L", and the complementary global write signal GWB2 is fixed at "L".

[0048] Note that during the write process to one of the memory banks BK1 to BK2 in the first group G1, refer to Figure 3During the time period M2, the clock signal CKD2 is fixed at "L", causing the transistor T12 in the second gating circuit 124 to turn off, disconnecting the negative power supply terminals of the inverters 122a and 122b from the ground level, and the transistors T13 and T14 in the second gating circuit 124 to turn on, pulling up the voltage levels on the nodes N3 and N4 to the positive system power supply VDD. In this case, referring to Figure 2 and Figure 3 , during the time period M2, the second gating circuit 124 is configured to disable the second global write driver 122 (by disconnecting the negative power supply terminals of the inverters 122a and 122b from the ground level) and maintain the second pair of write data wirings W2a and W2b at the ground level (by fixing the voltage levels on the nodes N3 and N4 to the positive system power supply VDD). In other words, when a write process is performed on one of the memory banks BK1 - BK2 in the first group G1, the second gating circuit 124 is activated to gate the second global write driver 122 corresponding to the memory banks BK3 - BK4 in the second group G2.

[0049] On the other hand, during the write process for one of the memory banks BK3 - BK4 in the second group G2, referring to Figure 3 during the time period M3, the clock signal CKD1 is fixed at "L", causing the transistor T9 in the first gating circuit 123 to turn off, disconnecting the negative power supply terminals of the inverters 121a and 121b from the ground level, and the transistors T10 and T11 in the first gating circuit 123 to turn on, pulling up the voltage levels on the nodes N1 and N2 to the positive system power supply VDD. In this case, referring to Figure 2 and Figure 3 , during the time period M3, the first gating circuit 123 is configured to disable the first global write driver 121 (by disconnecting the negative power supply terminals of the inverters 121a and 121b from the ground level) and maintain the first pair of write data wirings W1a and W1b at the ground level (by fixing the voltage levels on the nodes N1 and N2 to the positive system power supply VDD). In other words, when a write process is performed on one of the memory banks BK3 - BK4 in the second group G2, the first gating circuit 123 is activated to gate the first global write driver 121 corresponding to the memory banks BK1 - BK2 in the first group G1.

[0050] Based on the foregoing embodiments, the first global write driver 121 and the second global write driver 122 act in response to the same write data signal WD from the control circuit 140. As Figure 2As shown, the first global write driver 121 and the second global write driver 122 receive the same latched write signal DX from the same data latch 160. In some embodiments, the first global write driver 121 and the second global write driver 122 are activated separately in response to different clock signals. The first global write driver 121 is activated in response to the delayed clock signal CKD1d, and the second global write driver 122 is activated in response to the delayed clock signal CKD2d.

[0051] Referring to the time period M1 in Figure 2 and Figure 3 when there is no writing process to any of the memory banks BK1 - BK4 in the two groups, the control circuit 140 can provide the clock signals CKD1 and CKD2 both fixed to "L" such that both the first gating circuit 123 and the second gating circuit 124 are activated to fix the global write signals GW1 / GW2 and the complement global write signals GW1B / GW2B to "L".

[0052] In Figure 1 the foregoing embodiment shown, the memory device 100 includes four memory banks BK1 - BK4 in two groups G1 and G2. The first group G1 including two memory banks BK1 and BK2 shares the same pair of write data wirings W1a and W1b. The second group G2 including two memory banks BK3 and BK4 shares the same pair of write data wirings W2a and W2b. However, the present disclosure is not limited thereto.

[0053] In some embodiments, the first group G1 may include N memory banks, and the second group G2 may include another N memory banks. N is a positive integer greater than or equal to 2. For example, there may be 2, 3, 4, or more memory banks in each of the first group G1 and the second group G2.

[0054] Further referring to Figure 4 , Figure 4 is a schematic diagram showing a memory device 200 according to various embodiments of the present disclosure. Corresponding elements to Figure 1 in the embodiment are labeled with the same reference numerals for easy understanding. Figure 4

[0055] In Figure 4 the embodiment schematically shown, the memory device 200 includes a plurality of memory banks BK1 - BK3, and each of the memory banks BK1 - BK3 can be accessed separately. For illustrative purposes, these three memory banks BK1 - BK3 in the memory device 200 are shown. Figure 4 The internal structure of each of the memory banks BK1 - BK3 in Figure 1The internal structure of each memory bank BK1 to BK4 therein, and reference may be made to the embodiments discussed with respect to the memory bank BK1 or BK2 in the memory device 100 of Figure 1 The memory device 100 of

[0056] In some embodiments, each of the memory banks BK1 to BK3 includes a memory array that includes a plurality of bit cells arranged in a plurality of rows and columns ( Figure 4 Not shown, reference may be made to Figure 1 ). For the sake of brevity, Figure 4 The internal structure of the memory banks BK1 to BK3 is not fully shown.

[0057] As Figure 4 Schematically shown, the memory device 200 includes a global write circuit 220, a control circuit 240, data latches 260, a first pair of write data wirings W1a to W1b, and a second pair of write data wirings W2a to W2b. The control circuit 240 is configured to provide a clock signal CKD1, another clock signal CKD2, and a write data signal WD. Figure 4 The functions and operations of the global write circuit 220, the control circuit 240, and the data latches 260 in the memory device 200 of Figure 1 Are similar to those of the global write circuit 120, the control circuit 140, and the data latches 160 in the memory device 100 of

[0058] Based on the clock signal CKD1, the clock signal CKD2, and the write data signal WD provided by the control circuit 240, the global write circuit 220 is configured to generate two signals selected from a global write signal GW1, a complement global write signal GWB1, another global write signal GW2, and another complement global write signal GWB2, so as to perform a write process with respect to one of the memory banks BK1 to BK3. As Figure 4 Shown, the memory banks BK1 to BK3 are arranged at different physical positions with respect to the global write circuit 220 in the memory device 200. As Figure 4 Schematically shown, the memory banks BK1 to BK3 can be divided into two groups G1 and G2. The memory banks BK1 and BK2 in the first group G1 are relatively closer to the global write circuit 220, and the memory bank BK3 in the second group G2 is relatively farther from the global write circuit 220. In some embodiments, the memory banks BK1 and BK2 in the first group G1 are connected to the first pair of write data wirings W1a and W1b, and the memory bank BK3 in the second group G2 is connected to the second pair of write data wirings W2a and W2b.

[0059] In some embodiments, the memory device 200 includes three memory banks BK1 to BK3 that are divided into two groups G1 and G2. In an embodiment, groups G1 and G2 do not have an equal number of memory banks because the total number of memory banks BK1 to BK3 is odd. In Figure 4 the illustrated embodiment, two memory banks BK1 and BK2 that are closer to the global write circuit 220 are classified as the first group G1, and one memory bank BK3 that is farther from the global write circuit 220 is classified as the second group G2. In this case, the capacitance on the write data wirings W1a and W1b (which have a shorter length and are connected to two memory banks) tends to be more balanced with the write data wirings W2a and W2b (which have a longer length and are connected to one memory bank).

[0060] In some other embodiments, memory bank BK1 can be classified as the first group G1, and two memory banks BK2 and BK3 that are farther from the global write circuit 220 can be classified as the second group G2. In this case, compared with linking all memory banks BK1 to BK3 to the same pair of write data wirings, the resistance-capacitance (RC) load on each pair of write data wirings (e.g., W1a / W1b and W2a / W2b) can still be reduced. In this case, the write speed to the memory banks in the memory device 200 can be increased.

[0061] Further referring to Figure 5 , Figure 5 is a schematic diagram showing a memory device 300 according to various embodiments of the present disclosure. With respect to the embodiments of Figure 1 and Figure 4 , the same elements in Figure 5 are labeled with the same reference numerals for easy understanding.

[0062] In Figure 5 the embodiment schematically shown, the memory device 300 includes a plurality of memory banks BK1 to BK5, and each memory bank BK1 to BK5 can be accessed individually. For illustrative purposes, these five memory banks BK1 to BK5 in the memory device 300 are shown. Figure 5 The internal structure of each memory bank BK1 to BK5 in Figure 1 is similar to the internal structure of each memory bank BK1 to BK4 in Figure 1 , and the embodiments discussed with respect to the memory banks BK1 or BK2 in the memory device 100 of

[0063] In some embodiments, each memory bank BK1 to BK5 includes a memory array that includes a number of bit cells ( Figure 5 not shown, reference may be made to Figure 1 ) arranged in a plurality of rows and columns. For the sake of brevity,Figure 5 The internal structures of memory banks BK1 to BK5 are not fully shown.

[0064] As Figure 5 Schematically shown, the memory device 300 includes a global write circuit 320, a control circuit 340, data latches 360, a first pair of write data wirings W1a to W1b, and a second pair of write data wirings W2a to W2b. The control circuit 340 is configured to provide a clock signal CKD1, another clock signal CKD2, and a write data signal WD. Figure 5 The functions and operations of the global write circuit 320, the control circuit 340, and the data latches 360 in the memory device 300 of Figure 1 are similar to those of the global write circuit 120, the control circuit 140, and the data latches 160 in the memory device 100 of the foregoing embodiments.

[0065] Based on the clock signal CKD1, the clock signal CKD2, and the write data signal WD provided by the control circuit 340, the global write circuit 320 is configured to generate two signals selected from a global write signal GW1, a complement global write signal GWB1, another global write signal GW2, and another complement global write signal GWB2 to perform a write process with respect to one of the memory banks BK1 to BK5. As Figure 5 shown, the memory banks BK1 to BK5 are arranged at different physical positions with respect to the global write circuit 320 in the memory device 300. As Figure 5 Schematically shown, the memory banks BK1 to BK5 can be divided into two groups G1 and G2. The memory banks BK1 to BK3 in the first group G1 are relatively closer to the global write circuit 320, and the memory banks BK4 to BK5 in the second group G2 are relatively farther from the global write circuit 320. In some embodiments, the memory banks BK1 to BK3 in the first group G1 are connected to the first pair of write data wirings W1a and W1b, and the memory banks BK4 to BK5 in the second group G2 are connected to the second pair of write data wirings W2a and W2b.

[0066] In some embodiments, the memory device 300 includes five memory banks BK1 to BK5 that are divided into two groups G1 and G2. In some other embodiments, the groups G1 and G2 do not have an equal number of memory banks because the total number of memory banks BK1 to BK5 is odd. In Figure 5In the illustrated embodiment, three memory banks BK1 to BK3 closer to the global write circuit 320 are classified as a first group G1, and two memory banks BK4 to BK5 farther from the global write circuit 320 are classified as a second group G2. In this case, the capacitance on the write data wirings W1a and W1b (having a shorter length and connected to three memory banks) tends to be more balanced with the write data wirings W2a and W2b (having a longer length and connected to two memory banks).

[0067] In this case, compared with linking all the memory banks BK1 to BK5 to the same pair of write data wirings, the resistance-capacitance (RC) load on each pair of write data wirings (e.g., W1a / W1b and W2a / W2b) can be reduced. In this case, the write speed to the memory banks in the memory device 300 can be increased.

[0068] Based on Figure 4 and Figure 5 the illustrated embodiment, when there are a total of 2M + 1 memory banks in one memory device, M + 1 memory banks closer to the global write circuit can be divided into one group (e.g., Figure 4 or Figure 5 the first group G1 in Figure 4 or Figure 5 ), and the other M memory banks farther from the global write circuit can be divided into another group (e.g., Figure 4 or Figure 5 the second group G2 in

[0069] In Figures 1 to 5 the foregoing embodiment, the memory banks are divided into two groups. However, the present disclosure is not limited to dividing the memory banks into two groups. Further referring to Figure 6 , Figure 6 is a schematic diagram showing a memory device 400 according to various embodiments of the present disclosure. With respect to Figure 1 , Figure 4 and Figure 5 the embodiment, Figure 6 the same elements in

[0070] In Figure 6 the schematically illustrated embodiment, the memory device 400 includes a plurality of memory banks BK1 to BK6, and each of the memory banks BK1 to BK6 can be accessed individually. Figure 6 The internal structure of each of the memory banks BK1 to BK6 in Figure 1 is similar to the internal structure of each of the memory banks BK1 to BK4 in Figure 1The embodiments discussed for memory banks BK1 or BK2 in the memory device 100.

[0071] In some embodiments, each of memory banks BK1 to BK6 includes a memory array that includes a plurality of bit cells arranged in a plurality of rows and columns (as shown in the embodiments of Figure 1 ). For the sake of brevity, Figure 6 the internal structures of memory banks BK1 to BK6 are not fully shown.

[0072] As Figure 6 schematically shown, the memory device 400 includes a global write circuit 420, a control circuit 440, data latches 460, a first pair of write data wirings W1a to W1b, a second pair of write data wirings W2a to W2b, and a third pair of write data wirings W3a to W3b. The control circuit 440 is configured to provide a clock signal CKD1, another clock signal CKD2, yet another clock signal CKD3, and a write data signal WD. Figure 6 The functions and operations of the global write circuit 420, the control circuit 440, and the data latches 460 in the memory device 400 of Figure 1 are similar to those of the global write circuit 120, the control circuit 140, and the data latches 160 in the memory device 100 of the foregoing embodiments.

[0073] Based on the clock signal CKD1, the clock signal CKD2, the clock signal CKD3, and the write data signal WD provided by the control circuit 440, the global write circuit 420 is configured to generate two signals selected from a global write signal GW1, a complementary global write signal GWB1, another global write signal GW2, another complementary global write signal GWB2, yet another global write signal GW3, and yet another complementary global write signal GWB3, so as to perform a write process with respect to one of the memory banks BK1 to BK6. As Figure 6 shown, the memory banks BK1 to BK6 are arranged at different physical positions with respect to the global write circuit 420 in the memory device 400. As Figure 6Schematically shown, memory banks BK1 to BK6 can be divided into three groups G1 to G3. Memory banks BK1 and BK2 in the first group G1 are relatively closer to the global write circuit 420; memory banks BK3 and BK4 in the second group G2 are relatively farther from the global write circuit 420; memory banks BK5 and BK6 in the third group G3 are the farthest from the global write circuit 420. In some embodiments, memory banks BK1 and BK2 in the first group G1 are connected to a first pair of write data wirings W1a and W1b; memory banks BK3 and BK4 in the second group G2 are connected to a second pair of write data wirings W2a and W2b; memory banks BK5 and BK6 in the third group G3 are connected to a third pair of write data wirings W3a and W3b.

[0074] The global write circuit 420 is configured to receive clock signals CKD1 to CKD3 from the control circuit 440. In response to the clock signal CKD1, the global write circuit 420 generates a global write signal GW1 and a complementary global write signal GWB1, which are sent to the first group G1 through the first pair of write data wirings W1a and W1b, and at the same time the global write signals GW2 to GW3 and the complementary global write signals GWB2 to GWB3 are fixed at the ground level. In response to the clock signal CKD2, the global write circuit 420 generates another global write signal GW2 and a complementary global write signal GWB2, which are sent to the second group G2 through the second pair of write data wirings W2a and W2b, and at the same time the global write signals GW1 and GW3 and the complementary global write signals GWB1 and GWB3 are fixed at the ground level. In response to the clock signal CKD3, the global write circuit 420 generates another global write signal GW3 and a complementary global write signal GWB3, which are sent to the third group G3 through the third pair of write data wirings W3a and W3b, and at the same time the global write signals GW1 to GW2 and the complementary global write signals GWB1 to GWB2 are fixed at the ground level. Figure 6 For the detailed structure in the global write circuit 420, reference can be made to Figure 2 the global write circuit 120 shown. The difference between the global write circuit 420 and the global write circuit 120 is that the global write circuit 420 includes three groups of global write drivers and three groups of gating circuits for generating the global write signals GW1 to GW3 and the complementary global write signals GWB1 to GWB3 respectively.

[0075] In this case, compared with linking all memory banks BK1 to BK6 to the same pair of write data wirings, the resistance-capacitance (RC) load on each pair of write data wirings (such as W1a / W1b, W2a / W2b, and W3a / W3b) can be reduced. In this case, the write speed to the memory banks in the memory device 400 can be increased.

[0076] AsFigure 6 For the memory device 400 shown, when the memory device 400 includes more memory banks (e.g., memory banks BK1 - BK6), these memory banks can be divided into more groups. In some other embodiments, the memory device may include two groups, three groups, four groups, or more groups of memory banks, and each of the foregoing groups may include one, two, three, or more memory banks. The global write circuit is configured to provide different groups of global write signals and complementary global write signals for different groups respectively.

[0077] Further referring to Figure 7 , Figure 7 is a flowchart showing a method 500 according to various embodiments of the present disclosure. The method 500 can be used for Figures 1 to 6 the memory devices 100 - 400 of the foregoing embodiments shown. For the sake of brevity, in the following paragraphs, together with Figures 1 to 3 the memory device 100 of the embodiment shown, the method 500 in Figure 7 is discussed.

[0078] The control circuit 140 performs operation S510 to determine the target location of the write process. For example, the target location may include a memory bank identifier, a row address, and a column address. The memory bank identifier indicates in which one of the memory banks BK1 - BK4 the target bit cell of the write process is located. If the write process is intended to write a bit cell in one of the memory banks BK1 - BK2 in the first group G1, then operations S520 and S530 are performed. On the other hand, if the write process is intended to write a bit cell in one of the memory banks BK3 - BK4 in the second group G2, then operations S540 and S550 are performed.

[0079] In operation S520, during the write process of writing one of the memory banks BK1 - BK2 in the first group G1, the control circuit 140 provides an oscillating clock signal CKD1 to trigger the first global write driver 121 in the global write driver 120 to generate a global write signal GW1 and a complementary global write signal GW1B according to the write data signal WD. When the clock signal CKD1 oscillates, the first gating circuit 123 in the global write driver 120 is configured to enable the first global write driver 121 in the global write driver 120 to generate the global write signal GW1 and the complementary global write signal GWB1. More details about generating the global write signal GW1 and the complementary global write signal GW1B are discussed in the embodiment of the global write driver 120 regarding Figure 2 and the embodiment of the time period M2 regarding Figure 3 , and these details are not elaborated herein.

[0080] In operation S530, during the write process of writing one of memory banks BK1 to BK2 in the first group G1, the control circuit 140 pauses the oscillation of the clock signal CKD2 (for example, the clock signal CKD2 is fixed at the ground level) so as to disable the second global write driver 122 through the second gating circuit 124. In this case, the voltage levels on the second pair of write data wirings W2a and W2b connected to the second global write driver 122 are maintained at the ground level.

[0081] In operation S540, during the write process of writing one of memory banks BK3 to BK4 in the second group G2, the control circuit 140 provides the oscillating clock signal CKD2 to trigger the second global write driver 122 in the global write driver 120 to generate the global write signal GW2 and the complementary global write signal GW2B according to the write data signal WD. When the clock signal CKD2 oscillates, the second gating circuit 124 in the global write driver 120 is configured to enable the second global write driver 122 in the global write driver 120 to generate the global write signal GW2 and the complementary global write signal GWB2. More details about generating the global write signal GW2 and the complementary global write signal GW2B are discussed in the embodiment of the global write driver 120 regarding Figure 2 and in the embodiment of the time period M3 regarding Figure 3 and these details are not elaborated herein.

[0082] In operation S550, during the write process of writing one of memory banks BK3 to BK4 in the second group G2, the control circuit 140 pauses the oscillation of the clock signal CKD1 (for example, the clock signal CKD1 is fixed at the ground level) so as to disable the first global write driver 121 through the first gating circuit 123. In this case, the voltage levels on the first pair of write data wirings W1a and W1b connected to the first global write driver 121 are maintained at the ground level.

[0083] In some embodiments, a device includes a plurality of memory banks, a first pair of write data wirings, a second pair of write data wirings, and a global write circuit. The first pair of write data wirings is connected to a first group in the memory banks. The second pair of write data wirings is connected to a second group in the memory banks. The global write circuit is configured to receive a first clock signal and a second clock signal. In response to the first clock signal, the global write circuit generates a first global write signal and a first complementary global write signal, and the first global write signal and the first complementary global write signal are sent to the first group in the memory banks through the first pair of write data wirings. In response to the second clock signal, the global write circuit generates a second global write signal and a second complementary global write signal, and the second global write signal and the second complementary global write signal are sent to the second group in the memory banks through the second pair of write data wirings.

[0084] In some embodiments, the device further includes a control circuit and a data latch. The control circuit is configured to provide a first clock signal, a second clock signal, and a write data signal to a global write circuit. The data latch is coupled between the control circuit and the global write circuit, and the data latch is configured to store the write data signal.

[0085] In some embodiments, the global write circuit includes a first global write driver and a second global write driver. The first global write driver is coupled between the data latch and a first pair of write data wirings. The first global write driver is configured to generate a first global write signal and a first complement global write signal based on the write data signal stored in the data latch. The second global write driver is coupled between the data latch and a second pair of write data wirings. The second global write driver is configured to generate a second global write signal and a second complement global write signal based on the write data signal stored in the data latch.

[0086] In some embodiments, the global write circuit further includes a first gating circuit and a second gating circuit. The first gating circuit is coupled to the first global write driver. In response to the first clock signal being suspended from oscillating, the first gating circuit is configured to disable the first global write driver and maintain the first pair of write data wirings at a ground level. The second gating circuit is coupled to the second global write driver. In response to the second clock signal being suspended from oscillating, the second gating circuit is configured to disable the second global write driver and maintain the second pair of write data wirings at a ground level.

[0087] In some embodiments, in response to the first clock signal oscillating, the first gating circuit is configured to cause the first global write driver to generate the first global write signal and the first complement global write signal. In response to the second clock signal oscillating, the second gating circuit is configured to cause the second global write driver to generate the second global write signal and the second complement global write signal.

[0088] In some embodiments, during a first write process to one memory bank in a first group in a memory bank, the control circuit provides an oscillating first clock signal and a suspended second clock signal. During a second write process to one memory bank in a second group in the memory bank, the control circuit provides a suspended first clock signal and an oscillating second clock signal.

[0089] In some embodiments, the device further includes a NOR logic gate, coupled between the control circuit and the data latch. The NOR logic gate is configured to generate a third clock signal based on the first clock signal and the second clock signal. The third clock signal is configured to trigger the data latch.

[0090] In some embodiments, a first group of memory banks in a memory bank array includes N memory banks disposed relatively adjacent to a global write circuit. A second group of memory banks in the memory bank array includes N other memory banks disposed relatively far from the global write circuit, where N is a positive integer greater than 1.

[0091] In some embodiments, a first group of memory banks in a memory bank array includes M + 1 memory banks disposed relatively adjacent to a global write circuit. A second group of memory banks in the memory bank array includes M other memory banks disposed relatively far from the global write circuit, where M is a positive integer greater than 1.

[0092] In some embodiments, the device further includes a third group of memory banks in the memory bank array and a third pair of write data wirings. The third pair of write data wirings is connected to the third group of memory banks in the memory bank array. The global write circuit is further configured to receive a third clock signal. In response to the third clock signal, the global write circuit generates a third global write signal and a third complement global write signal, and the third global write signal and the third complement global write signal are sent to the third group of memory banks in the memory bank array through the third pair of write data wirings.

[0093] In some embodiments, a circuit includes a control circuit, a first global write driver, and a second global write driver. The control circuit is configured to provide a first clock signal, a second clock signal, and a write data signal. The first global write driver is coupled to a first pair of write data wirings. The first global write driver is configured to generate a first global write signal and a first complement global write signal according to the write data signal in response to the first clock signal. The first global write signal and the first complement global write signal are sent to a first group of a plurality of memory banks through the first pair of write data wirings. The second global write driver is coupled to a second pair of write data wirings. The second global write driver is configured to generate a second global write signal and a second complement global write signal according to the write data signal in response to the second clock signal. The second global write signal and the second complement global write signal are sent to a second group of memory banks through the second pair of write data wirings.

[0094] In some embodiments, the circuit further includes a data latch coupled to the control circuit. The data latch is configured to store the write data signal. The first global write driver is configured to generate the first global write signal and the first complement global write signal according to the write data signal stored in the data latch. The second global write driver is configured to generate the second global write signal and the second complement global write signal according to the write data signal stored in the data latch.

[0095] In some embodiments, the circuit further includes a NOR logic gate coupled between the control circuit and the data latch. The NOR logic gate is configured to generate a third clock signal based on a first clock signal and a second clock signal. The third clock signal is configured to trigger the data latch.

[0096] In some embodiments, the circuit further includes a first gating circuit and a second gating circuit. The first gating circuit is coupled to a first global write driver. In response to the first clock signal being suspended from oscillating, the first gating circuit is configured to disable the first global write driver and maintain a first pair of write data wirings at a ground level. The second gating circuit is coupled to a second global write driver. In response to the second clock signal being suspended from oscillating, the second gating circuit is configured to disable the second global write driver and maintain a second pair of write data wirings at a ground level.

[0097] In some embodiments, in response to the first clock signal oscillating, the first gating circuit is configured to cause the first global write driver to generate a first global write signal and a first complement global write signal. In response to the second clock signal oscillating, the second gating circuit is configured to cause the second global write driver to generate a second global write signal and a second complement global write signal.

[0098] In some embodiments, during a first write process to one memory bank in a first group of memory banks, the control circuit provides an oscillating first clock signal and a suspended second clock signal. During a second write process to one memory bank in a second group of memory banks, the control circuit provides a suspended first clock signal and an oscillating second clock signal.

[0099] In some embodiments, a method includes the following steps. During a first write process to a first group of a plurality of memory banks, a first clock signal is provided to trigger a first global write driver to generate a first global write signal and a first complement global write signal based on a write data signal. The first global write signal and the first complement global write signal are sent to the memory banks in the first group through a first pair of write data wirings. During a second write process to a second group of memory banks, a second clock signal is provided to trigger a second global write driver to generate a second global write signal and a second complement global write signal based on the write data signal. The second global write signal and the second complement global write signal are sent to the memory banks in the second group through a second pair of write data wirings.

[0100] In some embodiments, during the first write process, the first clock signal is provided oscillating, and the second clock signal is suspended from oscillating. During the second write process, the first clock signal is suspended from oscillating, and the second clock signal is provided oscillating.

[0101] In some embodiments, the method further comprises the following steps. During a first write process, a second global write driver is disabled. During a second write process, a first global write driver is disabled.

[0102] In some embodiments, the method further comprises the following steps. During a first write process, a second pair of write data wirings is maintained at a ground level. During a second write process, a first pair of write data wirings is maintained at a ground level.

[0103] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0104] Example 1 is a memory device, comprising: a plurality of memory banks; a first pair of write data wirings connected to a first group among the memory banks; a second pair of write data wirings connected to a second group among the memory banks; and a global write circuit configured to receive a first clock signal and a second clock signal, wherein: in response to the first clock signal, the global write circuit generates a first global write signal and a first complementary global write signal, and the first global write signal and the first complementary global write signal are sent to the first group among the memory banks through the first pair of write data wirings; in response to the second clock signal, the global write circuit generates a second global write signal and a second complementary global write signal, and the second global write signal and the second complementary global write signal are sent to the second group among the memory banks through the second pair of write data wirings.

[0105] Example 2 is the device according to Example 1, further comprising: a control circuit configured to provide the first clock signal, the second clock signal, and a write data signal to the global write circuit; and a data latch coupled between the control circuit and the global write circuit, the data latch being configured to store the write data signal.

[0106] Example 3 is the device described in Example 2, wherein the global write circuit includes: a first global write driver coupled between the data latch and the first pair of write data wirings, wherein the first global write driver is configured to generate the first global write signal and the first complementary global write signal based on the write data signal stored in the data latch; and a second global write driver coupled between the data latch and the second pair of write data wirings, wherein the second global write driver is configured to generate the second global write signal and the second complementary global write signal based on the write data signal stored in the data latch.

[0107] Example 4 is the device described in Example 3, wherein the global write circuit further includes: a first gating circuit coupled to the first global write driver, in response to the first clock signal being suspended from oscillating, the first gating circuit is configured to disable the first global write driver and maintain the first pair of write data wirings at a ground level; and a second gating circuit coupled to the second global write driver, in response to the second clock signal being suspended from oscillating, the second gating circuit is configured to disable the second global write driver and maintain the second pair of write data wirings at a ground level.

[0108] Example 5 is the device described in Example 4, wherein: in response to the first clock signal oscillating, the first gating circuit is configured to cause the first global write driver to generate the first global write signal and the first complementary global write signal; and in response to the second clock signal oscillating, the second gating circuit is configured to cause the second global write driver to generate the second global write signal and the second complementary global write signal.

[0109] Example 6 is the device described in Example 2, wherein: during a first write process to one memory bank in the first group in the memory bank, the control circuit provides the oscillating first clock signal and the suspended second clock signal, and during a second write process to one memory bank in the second group in the memory bank, the control circuit provides the suspended first clock signal and the oscillating second clock signal.

[0110] Example 7 is the device described in Example 2, further including: a NOR logic gate coupled between the control circuit and the data latch, wherein the NOR logic gate is configured to generate a third clock signal based on the first clock signal and the second clock signal, and the third clock signal is configured to trigger the data latch.

[0111] Example 8 is the device described in Example 1, wherein the first group in the memory banks includes N memory banks disposed relatively close to the global write circuit, and the second group in the memory banks includes the other N memory banks disposed relatively far from the global write circuit, and N is a positive integer greater than or equal to 2.

[0112] Example 9 is the device described in Example 1, wherein the first group in the memory banks includes M + 1 memory banks disposed relatively close to the global write circuit, and the second group in the memory banks includes the other M memory banks disposed relatively far from the global write circuit, and M is a positive integer greater than or equal to 1.

[0113] Example 10 is the device described in Example 1, further comprising: a third group in the memory banks; and a third pair of write data wirings connected to the third group in the memory banks, wherein the global write circuit is further configured to receive a third clock signal, and in response to the third clock signal, the global write circuit generates a third global write signal and a third complement global write signal, and the third global write signal and the third complement global write signal are sent to the third group in the memory banks through the third pair of write data wirings.

[0114] Example 11 is a memory circuit, comprising: a control circuit configured to provide a first clock signal, a second clock signal, and a write data signal; a first global write driver coupled to a first pair of write data wirings, wherein the first global write driver is configured to generate a first global write signal and a first complement global write signal according to the write data signal in response to the first clock signal, and the first global write signal and the first complement global write signal are sent to a first group in a plurality of memory banks through the first pair of write data wirings; and a second global write driver coupled to a second pair of write data wirings, wherein the second global write driver is configured to generate a second global write signal and a second complement global write signal according to the write data signal in response to the second clock signal, and the second global write signal and the second complement global write signal are sent to the second group in the memory banks through the second pair of write data wirings.

[0115] Example 12 is the circuit described in Example 11, further comprising: a data latch coupled to the control circuit, the data latch being configured to store the write data signal, wherein the first global write driver is configured to generate the first global write signal and the first complement global write signal according to the write data signal stored in the data latch, and the second global write driver is configured to generate the second global write signal and the second complement global write signal according to the write data signal stored in the data latch.

[0116] Example 13 is the circuit described in Example 12, further comprising: a NOR logic gate, coupled between the control circuit and the data latch, wherein the NOR logic gate is configured to generate a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is configured to trigger the data latch.

[0117] Example 14 is the circuit described in Example 11, further comprising: a first gating circuit, coupled to the first global write driver, and suspended from oscillating in response to the first clock signal, the first gating circuit being configured to disable the first global write driver and maintain the first pair of write data wirings at a ground level; and a second gating circuit, coupled to the second global write driver, and suspended from oscillating in response to the second clock signal, the second gating circuit being configured to disable the second global write driver and maintain the second pair of write data wirings at a ground level.

[0118] Example 15 is the circuit described in Example 14, wherein: in response to the first clock signal oscillating, the first gating circuit is configured to cause the first global write driver to generate the first global write signal and the first complement global write signal, and in response to the second clock signal oscillating, the second gating circuit is configured to cause the second global write driver to generate the second global write signal and the second complement global write signal.

[0119] Example 16 is the circuit described in Example 11, wherein: during a first write process to one memory bank in the first group in the memory bank, the control circuit provides the oscillating first clock signal and the suspended second clock signal, and during a second write process to one memory bank in the second group in the memory bank, the control circuit provides the suspended first clock signal and the oscillating second clock signal.

[0120] Example 17 is a method for a memory, comprising; during a first write process to a first group of a plurality of memory banks, providing a first clock signal to trigger a first global write driver to generate a first global write signal and a first complement global write signal according to a write data signal, the first global write signal and the first complement global write signal being sent to the memory banks in the first group through a first pair of write data wirings; and during a second write process to a second group of the memory banks, providing a second clock signal to trigger a second global write driver to generate a second global write signal and a second complement global write signal according to the write data signal, the second global write signal and the second complement global write signal being sent to the memory banks in the second group through a second pair of write data wirings.

[0121] Example 18 is the method described in Example 17, wherein: during the first writing process, the first clock signal is oscillated and provided, and the second clock signal is suspended from oscillating; and during the second writing process, the first clock signal is suspended from oscillating, and the second clock signal is oscillated and provided.

[0122] Example 19 is the method described in Example 17, further comprising: disabling the second global write driver during the first writing process; and disabling the first global write driver during the second writing process.

[0123] Example 20 is the method described in Example 17, further comprising: maintaining the second pair of write data wirings at a ground level during the first writing process; and maintaining the first pair of write data wirings at a ground level during the second writing process.

Claims

1. A memory device, comprising: a plurality of memory banks; a first pair of write data wirings connected to a first group of the memory banks; a second pair of write data wirings connected to a second group of the memory banks; and a global write circuit configured to receive a first clock signal and a second clock signal, wherein: in response to the first clock signal, the global write circuit generates a first global write signal and a first complement global write signal, and the first global write signal and the first complement global write signal are sent to the first group of the memory banks through the first pair of write data wirings; in response to the second clock signal, the global write circuit generates a second global write signal and a second complement global write signal, and the second global write signal and the second complement global write signal are sent to the second group of the memory banks through the second pair of write data wirings.

2. The device according to claim 1, further comprising: a control circuit configured to provide the first clock signal, the second clock signal, and a write data signal to the global write circuit; and a data latch coupled between the control circuit and the global write circuit, the data latch being configured to store the write data signal.

3. The device according to claim 2, wherein The global write circuit includes: a first global write driver coupled between the data latch and the first pair of write data wirings, wherein the first global write driver is configured to generate the first global write signal and the first complement global write signal according to the write data signal stored in the data latch; and a second global write driver coupled between the data latch and the second pair of write data wirings, wherein the second global write driver is configured to generate the second global write signal and the second complement global write signal according to the write data signal stored in the data latch.

4. The device according to claim 3, wherein, The global write circuit further includes: a first gating circuit coupled to the first global write driver and suspended from oscillating in response to the first clock signal, the first gating circuit being configured to disable the first global write driver and maintain the first pair of write data wirings at a ground level; and a second gating circuit coupled to the second global write driver and suspended from oscillating in response to the second clock signal, the second gating circuit being configured to disable the second global write driver and maintain the second pair of write data wirings at a ground level.

5. The device according to claim 4, wherein: in response to the first clock signal oscillating, the first gating circuit is configured to cause the first global write driver to generate the first global write signal and the first complement global write signal; and in response to the second clock signal oscillating, the second gating circuit is configured to cause the second global write driver to generate the second global write signal and the second complement global write signal.

6. The device according to claim 2, wherein: During a first write process to one memory bank in a first group of the memory banks, the control circuit provides the oscillating first clock signal and the suspended second clock signal, and during a second write process to one memory bank in a second group of the memory banks, the control circuit provides the suspended first clock signal and the oscillating second clock signal.

7. The device according to claim 2, further comprising: A NOR logic gate, coupled between the control circuit and the data latch, wherein the NOR logic gate is configured to generate a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is configured to trigger the data latch.

8. The device according to claim 1, wherein The first group of the memory banks includes N memory banks relatively close to the global write circuit, and the second group of the memory banks includes the other N memory banks relatively far from the global write circuit, where N is a positive integer greater than or equal to 2.

9. The device according to claim 1, wherein, The first group of the memory banks includes M + 1 memory banks relatively close to the global write circuit, and the second group of the memory banks includes the other M memory banks relatively far from the global write circuit, where M is a positive integer greater than or equal to 1.

10. The device according to claim 1, further comprising: A third group of the memory banks: and A third pair of write data wirings, connected to the third group of the memory banks, wherein the global write circuit is further configured to receive a third clock signal, and in response to the third clock signal, the global write circuit generates a third global write signal and a third complement global write signal, and the third global write signal and the third complement global write signal are sent to the third group of the memory banks through the third pair of write data wirings.

11. A memory circuit, comprising: A control circuit, configured to provide a first clock signal, a second clock signal, and a write data signal; A first global write driver, coupled to a first pair of write data wirings, wherein the first global write driver is configured to generate a first global write signal and a first complement global write signal according to the write data signal in response to the first clock signal, and the first global write signal and the first complement global write signal are sent to a first group of a plurality of memory banks through the first pair of write data wirings; and A second global write driver, coupled to a second pair of write data wirings, wherein the second global write driver is configured to generate a second global write signal and a second complement global write signal according to the write data signal in response to the second clock signal, and the second global write signal and the second complement global write signal are sent to the second group of the memory banks through the second pair of write data wirings.

12. The circuit according to claim 11, further comprising: A data latch, coupled to the control circuit, and the data latch is configured to store the write data signal. Wherein, the first global write driver is configured to generate the first global write signal and the first complementary global write signal according to the write data signal stored in the data latch, and the second global write driver is configured to generate the second global write signal and the second complementary global write signal according to the write data signal stored in the data latch.

13. The circuit according to claim 12, further comprising: A NOR logic gate, coupled between the control circuit and the data latch, wherein the NOR logic gate is configured to generate a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is configured to trigger the data latch.

14. The circuit according to claim 11, further comprising: A first gating circuit, coupled to the first global write driver, and suspended from oscillating in response to the first clock signal. The first gating circuit is configured to disable the first global write driver and maintain the first pair of write data wirings at a ground level; And A second gating circuit, coupled to the second global write driver, and suspended from oscillating in response to the second clock signal. The second gating circuit is configured to disable the second global write driver and maintain the second pair of write data wirings at a ground level.

15. The circuit according to claim 14, wherein: In response to the first clock signal oscillating, the first gating circuit is configured to cause the first global write driver to generate the first global write signal and the first complementary global write signal, and In response to the second clock signal oscillating, the second gating circuit is configured to cause the second global write driver to generate the second global write signal and the second complementary global write signal.

16. The circuit according to claim 11, wherein: During a first write process to one memory bank in a first group of the memory banks, the control circuit provides the oscillating first clock signal and the suspended second clock signal, and During a second write process to one memory bank in a second group of the memory banks, the control circuit provides the suspended first clock signal and the oscillating second clock signal.

17. A method for a memory, comprising; During a first write process to a first group of a plurality of memory banks, providing a first clock signal to trigger a first global write driver to generate a first global write signal and a first complementary global write signal according to a write data signal, and the first global write signal and the first complementary global write signal are sent to the memory banks in the first group through a first pair of write data wirings; and During a second write process of the second group in the memory bank, a second clock signal is provided to trigger a second global write driver to generate a second global write signal and a second complementary global write signal according to the write data signal, and the second global write signal and the second complementary global write signal are sent to the memory bank in the second group through a second pair of write data wirings.

18. The method according to claim 17, wherein: during the first write process, the first clock signal is oscillated and provided, and the second clock signal is suspended from oscillating, and during the second write process, the first clock signal is suspended from oscillating, and the second clock signal is oscillated and provided.

19. The method according to claim 17, further comprising: disabling the second global write driver during the first write process; and disabling the first global write driver during the second write process.

20. The method according to claim 17, further comprising: maintaining the second pair of write data wirings at a ground level during the first write process; and maintaining the first pair of write data wirings at a ground level during the second write process.

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