Three-dimensional phase change memory and manufacturing method thereof

Abstract

The present invention provides a three-dimensional phase change memory and a manufacturing method thereof, which enables each layer of phase change memory cells and the first wiring (i.e., word line or bit line) required therefor to be separately manufactured, and further utilizes the replacement of sacrificial layers and the limiting effect of dielectric sidewalls to manufacture phase change memory cells in electrical contact with the bottom electrode and the first contact, so that the shape and size of the phase change memory cells are no longer completely dependent on the overlap at the intersection of the word line and the bit line, which is conducive to achieving a smaller memory size and a higher storage density, and can improve the parasitic effects introduced by the word line and the bit line, and reduce the programming current and power supply requirements of the phase change memory. In addition, the contact plugs for leading the word line outward and the contact plugs for leading the bit line outward can be arranged at the periphery of the array formed by the phase change memory cells, thereby being conducive to further miniaturization of the overall size of the phase change memory and further improvement of the storage density.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a three-dimensional phase change memory and a manufacturing method thereof. Background Art

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, program algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit, and three-dimensional (3D) memory architectures have emerged to solve the density limitation problem in planar memory cells.

[0003] The current mainstream three-dimensional phase change memory (3D Phase Change Memory, 3D PCM) architecture may include a single-layer phase change memory cell (PCM cell), two-layer stacked phase change memory cells or four-layer stacked phase change memory cells, and each layer of phase change memory cells is generally self-aligned and formed at the intersection of mutually perpendicular word lines (WL) and bit lines (BL). Its shape and size are completely dependent on the overlap at the intersection of the word lines and bit lines, so it generally presents a vertical square column as a whole.

[0004] Although the above-mentioned three-dimensional phase change memory architecture can break through the density limitation of planar phase change memory, since the shape and size of its phase change memory unit are completely dependent on the overlap at the intersection of the word line and the bit line, it is in the shape of a vertical square column, which is not conducive to further miniaturization of the device size. This has also become one of the technical problems that technical personnel in this field need to solve urgently. Summary of the invention

[0005] The object of the present invention is to provide a three-dimensional phase change memory and a method for manufacturing the same, which can be beneficial to realizing a memory device with a smaller size and a higher storage density.

[0006] To achieve the above object, the present invention provides a method for manufacturing a three-dimensional phase change memory, which comprises the following steps:

[0007] A first interlayer dielectric layer is formed by using a first wiring process, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts located on each of the first wirings are formed in the first interlayer dielectric layer, wherein the first wirings are bit lines or word lines;

[0008] forming a stacked layer on the first interlayer dielectric layer and the first contact, the stacked layer comprising a bottom electrode layer and a sacrificial layer stacked above the bottom electrode layer;

[0009] Performing corresponding photolithography and etching on the stacked layers until the bottom electrode layer is patterned to form a plurality of stacked bodies spaced apart from each other;

[0010] forming a gap-filling layer in the gap between adjacent stacked bodies, wherein the gap-filling layer exposes the top surface of the sacrificial layer;

[0011] Removing the sacrificial layer to form an opening, and further forming a dielectric sidewall on the sidewall of the opening;

[0012] A phase change memory layer is deposited on the opening, the dielectric sidewalls and the surface of the gap filling layer.

[0013] Optionally, the step of forming a first interlayer dielectric layer, a first wiring and a first contact by using a first wiring process includes:

[0014] Forming a first dielectric layer on a substrate, and performing photolithography and etching on the first dielectric layer to form a plurality of first grooves extending along a first direction;

[0015] forming a first wiring filled in each first trench;

[0016] Covering the first dielectric layer and the first wiring with a second dielectric layer, and performing photolithography and etching on the second dielectric layer to form a plurality of first contact holes on each of the first wirings, wherein the first dielectric layer and the second dielectric layer constitute the first interlayer dielectric layer;

[0017] A first contact is formed to fill each first contact hole.

[0018] Optionally, the stacked layer is subjected to corresponding photolithography and etching along the first direction until the bottom electrode layer is patterned to form a plurality of stacked bodies that are spaced apart from each other and extend along the first direction;

[0019] After depositing a phase change memory layer on the opening, the dielectric sidewalls and the surface of the gap filling layer, the manufacturing method further includes:

[0020] Performing corresponding photolithography and etching on the phase change memory layer and the remaining stacked body along a second direction intersecting the first direction until the bottom electrode layer is patterned again, so as to form a plurality of mutually spaced phase change memory cells by double pattern exposure technology, wherein the bottom electrode layer of each phase change memory cell is aligned with and electrically contacts the corresponding first contact;

[0021] forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer fills the gaps between adjacent phase change memory cells and buries the top surface of the phase change memory layer of each phase change memory cell therein;

[0022] A second wiring process is used to form a required second contact in the second interlayer dielectric layer, and a plurality of second wirings extending along the second direction are formed on the second interlayer dielectric layer, each of the second contacts is aligned with and contacts the phase change memory layer of the corresponding phase change memory unit, and each of the second wirings is electrically connected to the corresponding phase change memory unit through the corresponding second contact, wherein when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

[0023] Optionally, after depositing the phase change memory layer on the surface of the opening, the dielectric sidewalls and the gap filling layer, and before or after performing corresponding photolithography and etching on the phase change memory layer and the remaining stack along the second direction to form a plurality of mutually spaced phase change memory units, the top surface of the phase change memory layer is flattened until the top surface of the gap filling layer is exposed.

[0024] Optionally, the stacked layer is subjected to corresponding photolithography and etching along the first direction until the bottom electrode layer is patterned to form a plurality of stacked bodies that are spaced apart from each other and extend along the first direction;

[0025] After depositing a phase change memory layer on the opening, the dielectric sidewalls and the surface of the gap filling layer, the manufacturing method further includes:

[0026] Planarizing the top surface of the phase-change memory layer until the top surface of the gap-filling layer is exposed;

[0027] Depositing a top electrode layer and a second wiring layer sequentially on the phase change memory layer and the gap filling layer;

[0028] The second wiring layer, the top electrode layer, the phase change memory layer and the remaining stack are subjected to corresponding photolithography and etching along the second direction until the bottom electrode layer is patterned again, so as to form a plurality of mutually spaced phase change memory cells and a plurality of top electrode lines and second wirings extending along the second direction through a double pattern exposure technique, wherein the bottom electrode layer of each phase change memory cell is aligned with and electrically contacts the corresponding first contact, and each second wiring is electrically connected to a plurality of the phase change memory cells through the top electrode line aligned thereunder, wherein when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

[0029] Optionally, the step of performing corresponding photolithography and etching on the stacked layer until the bottom electrode layer is patterned to form a plurality of stacked bodies spaced apart from each other comprises:

[0030] Performing corresponding photolithography and etching on the sacrificial layer by using a single exposure technique or a multiple pattern exposure technique to form a pattern for defining each phase change memory unit in the sacrificial layer;

[0031] Using the sacrificial layer as a mask, the bottom electrode layer is etched to form a stack corresponding to each of the phase change memory cells, with gaps between adjacent stacks. The bottom electrode layer in each of the stacks is aligned with and electrically contacted with the corresponding first contact to serve as the bottom electrode of the phase change memory cell to be formed.

[0032] Optionally, after depositing a phase change memory layer on the opening, the dielectric sidewalls and the surface of the gap filling layer, the manufacturing method further includes:

[0033] Planarizing the top surface of the phase-change memory layer until the top surface of the gap-filling layer is exposed to form a plurality of phase-change memory units spaced apart from each other;

[0034] A second interlayer dielectric layer is formed on the phase-change memory layer and the gap-filling layer by a second wiring process, and a required second contact is formed in the second interlayer dielectric layer, and a plurality of second wirings extending along the second direction are formed on the second interlayer dielectric layer, each of the second contacts is aligned with and contacts the phase-change memory layer of the corresponding phase-change memory unit, and each of the second wirings is electrically connected to the corresponding phase-change memory unit through the corresponding second contact, wherein when the first wiring is a bit line, the second wiring is a word line, and when the first wiring is a word line, the second wiring is a bit line.

[0035] Optionally, before forming a gap filling layer in the gap between adjacent stacked bodies, an interface protection layer is first formed on the sidewalls of the stacked bodies.

[0036] Optionally, the first interlayer dielectric layer and the first wiring are formed on a substrate, the substrate having a storage area and a peripheral area located outside the storage area, the first wiring extends from the storage area to the peripheral area, and the manufacturing method further includes: while performing the first wiring process in the storage area, a corresponding electrical connection structure is also formed in the peripheral area.

[0037] Based on the same inventive concept, the present invention also provides a three-dimensional phase change memory, which includes:

[0038] A first interlayer dielectric layer, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts located on each of the first wirings are formed in the first interlayer dielectric layer;

[0039] A plurality of phase change memory cells spaced apart from each other are formed on the first interlayer dielectric layer, and each of the phase change memory cells comprises a bottom electrode layer and a phase change memory layer stacked in sequence, the bottom electrode layer is aligned with and electrically contacted with the corresponding first contact, a dielectric sidewall is formed on the sidewall of the phase change memory layer, and a structure composed of the dielectric sidewall and the phase change memory layer is aligned with the bottom electrode layer;

[0040] A gap filling layer, filling the gap between adjacent phase change memory cells;

[0041] a plurality of second wirings extending along a second direction intersecting the first direction, the second wirings being formed above the phase-change memory unit and the gap-filling layer, and each of the second wirings being electrically connected to a corresponding phase-change memory unit through a corresponding second contact or a top electrode line extending along the second direction;

[0042] The first wiring is a bit line and the second wiring is a word line, or the first wiring is a word line and the second wiring is a bit line.

[0043] Optionally, the three-dimensional phase change memory also includes a substrate, the first interlayer dielectric layer and the first wiring are formed on the substrate, the substrate has a storage area and a peripheral area located outside the storage area, and an electrical connection structure formed together with the first wiring and the first contact is formed in the peripheral area.

[0044] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0045] 1. A first wiring process is used to first form a first wiring used as a bit line or a word line and a first contact on the first wiring on a substrate, and then a phase change memory cell in electrical contact with a bottom electrode and the first contact is manufactured by replacing a sacrificial layer and limiting the effect of a dielectric sidewall. The manufacturing method makes it possible for the patterning of the bit line and the phase change memory cell to have no correlation as in the existing double patterning technology, so that the shape and size of the phase change memory cell no longer completely depend on the overlap at the intersection of the word line and the bit line, and the dielectric sidewall can be used to limit the line width of the phase change memory layer of the phase change memory cell, so that a smaller phase change memory cell size can be achieved, which is conducive to further miniaturization of the overall size of the phase change memory and further improvement of the storage density.

[0046] 2. The shielding and protection function of the sacrificial layer is used to first etch the selection layer, and then the sacrificial layer is replaced by the phase change storage layer, so that the phase change storage layer and the selection layer are no longer etched together at least along the word line or bit line direction, thereby improving the cross contamination problem between the phase change storage layer and the selection layer, and ensuring the performance of each of the phase change storage layer and the selection layer.

[0047] 3. The bit lines, phase change memory cells and word lines can be manufactured separately, so the corresponding single exposure technology (or single patterning technology) can be used to manufacture the bit lines, phase change memory cells and word lines respectively. This can avoid the process complexity and cost brought about by the use of double patterning technology to manufacture word lines and bit lines in the prior art, thereby achieving the effect of simplifying the process steps and reducing costs.

[0048] 4. After patterning the stacked layer along the first direction into a stacked body, the second wiring layer, the top electrode layer, the phase change memory layer and the remaining stacked body are patterned along the second direction together, which can further simplify the process complexity and cost of manufacturing the second wiring (ie, word line or bit line).

[0049] 5. Since the second wiring (for example, the word line) can be electrically contacted with the top electrode of the phase change memory cell through the second contact, and the first wiring (for example, the bit line) can be electrically contacted with the bottom electrode of the phase change memory cell through the first contact, the parasitic effects caused by the word line and the bit line (including parasitic resistance R, parasitic capacitance C, and RC delay effect, etc.) can be reduced, and the crosstalk problem between adjacent memory cells can be improved, thereby reducing the programming current and power requirements of the phase change memory.

[0050] 6. A peripheral area can also be set up, and the electrical connection structures (contacts, contact plugs) used to lead the first wiring and the second wiring outward are arranged at the periphery of the array formed by the phase change memory unit (i.e., the storage area), which can avoid the problem of word line contact plugs and bit line contact plugs occupying the storage area in the prior art, thereby facilitating further miniaturization of the overall size of the phase change memory and further improving the storage density.

[0051] 7. The first wiring process and the second wiring process can be respectively the manufacturing processes of two layers of metal lines in the multi-layer metal interconnection process in the peripheral area, thereby embedding the manufacturing of the phase change memory into the manufacturing process of the peripheral integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figures 1A to 1C It is a schematic cross-sectional view of a device structure in an existing method for manufacturing a three-dimensional phase change memory.

[0053] Figure 2 The diagram is a distribution diagram of word lines, bit lines and contact holes in an existing three-dimensional phase change memory.

[0054] Figure 3 The flowchart is a method for manufacturing a three-dimensional phase change memory provided by one embodiment of the present invention.

[0055] 4A to 4HIt is a schematic diagram of the cross-sectional structure of a device in the method for manufacturing a three-dimensional phase change memory according to the first embodiment of the present invention.

[0056] Figure 5 FIG. 1 is a schematic top view of the structure of a method for manufacturing a three-dimensional phase change memory according to the first embodiment of the present invention.

[0057] Figure 6 FIG. 1 is a schematic top view of a method for manufacturing a three-dimensional phase change memory according to a second embodiment of the present invention.

[0058] Figure 7 FIG. 4 is a schematic diagram of a cross-sectional structure of a device in a method for manufacturing a three-dimensional phase change memory according to a second embodiment of the present invention.

[0059] Figure 8 for Figure 6 Schematic diagram of the distribution of word lines, bit lines and contact holes in a three-dimensional phase change memory.

[0060] Fig. 9 and Fig.10 They are respectively a schematic cross-sectional structure diagram and a schematic top view structure diagram of a device in a method for manufacturing a three-dimensional phase change memory according to a fourth embodiment of the present invention.

[0061] Fig.11 FIG. 4 is a schematic top view of a method for manufacturing a three-dimensional phase change memory according to a fifth embodiment of the present invention.

[0062] Fig.12 FIG. 4 is a schematic diagram of a cross-sectional structure of a device in a method for manufacturing a three-dimensional phase change memory according to a sixth embodiment of the present invention.

[0063] Wherein, the accompanying drawings are marked as follows:

[0064] 100-substrate; 101-first interlayer dielectric layer; 1011-first dielectric layer; 1012-second dielectric layer; 102-first wiring; 102'-first layer word line peripheral circuit wiring (i.e., a layer of metal wiring in the multi-layer metal interconnection structure in the peripheral area); 103-first contact; 103'-peripheral contact; 104-lower structure layer of phase change memory cell; 1041-bottom electrode layer; 1042-selection layer; 1043-middle electrode layer; 105-sacrificial layer; 106-gap; 107-interface protection layer; 1071-first interface layer; 1072-second interface layer; 1073-third interface layer; 108-gap filling layer; 109-opening; 110-dielectric sidewall; 111-phase change memory layer; 112-second interlayer dielectric layer; 113-second contact; 113'-peripheral contact; 114-second wiring; 114'-second layer word line peripheral circuit wiring (i.e., another layer of metal wiring in the multi-layer metal interconnect structure in the peripheral area); 115-top electrode line; 115'-peripheral wiring; cell-phase change memory cell; WL-word line; BBL-bottom layer bit line; TBL-top layer bit line; CT1-second contact plug (i.e., bit line contact plug connected to BBL); CT2-first contact plug (i.e., word line contact plug connected to WL); CT3-third contact plug (i.e., bit line contact plug connected to TBL). DETAILED DESCRIPTION

[0065] Please refer to Figures 1A to 1C In the existing manufacturing method of the three-dimensional phase change memory, when forming each layer of phase change memory cell and the bit line BL and word line WL electrically connected thereto, a double patterning technique (also called double pattern exposure technique) is usually required to be used for manufacturing. The double patterning technique requires the pattern of the word line WL and the pattern of the bit line BL to overlap twice in order to define the pattern of the phase change memory cell at the intersection of the word line WL and the bit line BL.

[0066] For example, when manufacturing the bottom phase-change memory cell cell and the word line WL electrically connected thereto and the bottom bit line BL, it is usually necessary to first perform photolithography and etching on the stacked layer deposited for manufacturing the bottom phase-change memory cell and the bottom bit line layer, and implement the first patterning to form a plurality of bit lines BL extending along the horizontal direction Y and divide the stacked layer into a plurality of bottom stacks extending along the horizontal direction Y in parallel lines, with gaps between adjacent bottom stacks, as shown in FIG. 1A ; after the gaps are filled and the word line layer is deposited, photolithography and etching are performed on the word line layer and the bottom stack, and the second patterning is implemented to form a plurality of word lines WL extending along the horizontal direction X, and at the same time Figure 1AThe stacked body of the bottom layer extending in the Y direction is divided in the X direction, thereby forming a phase change memory cell cell located at the intersection of the word line WL and the bottom bit line BL, as shown in FIG. Figure 1B shown.

[0067] When needed Figure 1B When further manufacturing the top-layer phase-change memory cell cell and the top-layer bit line BL electrically connected thereto based on the structure, it is also necessary to adopt a double patterning technique to implement the process. Specifically, it is necessary to firstly perform a first patterning on the stacked layer deposited for manufacturing the top-layer phase-change memory cell to form a plurality of top-layer stacked bodies extending in parallel lines along the horizontal direction X. After gap filling and deposition of the top-layer bit line layer, a second patterning is performed on the top-layer bit line layer and the top-layer stacked body to form the top-layer bit line BL extending along the Y direction. At the same time, the top-layer stacked body extending along the X direction is divided along the Y direction, thereby forming a phase-change memory cell cell located at the intersection of the word line WL and the top-layer bit line BL. Figure 1C shown.

[0068] If the architecture of the three-dimensional phase change memory includes four layers of stacked phase change memory cells, the sequential structure of bit line-phase change memory cell-word line-phase change memory cell can be repeatedly manufactured along the Z direction according to the above method.

[0069] In addition, please refer to Figure 2 In the existing three-dimensional phase change memory architecture, a word line contact plug (also called contact or contact point in some embodiments, i.e., a contact point) is usually used to lead the word line WL outward. Figure 2 CT1 in the bottom), a bit line contact plug (i.e. Figure 2 CT2 in the top layer) and the bit line contact plug (ie, Figure 2 CT3 in the figure are all arranged in an array formed by phase change memory cells.

[0070] The inventors have found that the existing three-dimensional phase change memory and its manufacturing method have the following disadvantages: (1) Since the manufacturing of each layer of phase change memory cell and its electrically connected bit line BL and word line WL requires the use of double patterning technology, the shape and size of the phase change memory cell are completely dependent on the overlap at the intersection of the word line and the bit line, which is not conducive to achieving a smaller memory size and a higher storage density; (2) The process is complex and costly, and the reduction of parasitic effects (including parasitic resistance R, parasitic capacitance C and RC delay effect, etc.) introduced by the word line WL and the bit line BL is limited; (3) Due to the word line contact plug and The bit line contact plugs are arranged in the array formed by the phase change memory cells, thus occupying the area of ​​the storage area of ​​the phase change memory, limiting the further reduction of the overall size and density of the phase change memory; (4) when the deposited stacked layers for making the phase change memory cells include a bottom electrode layer, an on-state layer (OTS) intermediate electrode layer, a phase change memory layer and a top electrode layer from bottom to top, in the double patterning technology, when the stacked layers are etched along the Y direction and the stacked body is further etched along the X direction, the phase change memory layer and the on-state layer are usually etched together, which easily causes cross contamination between the phase change memory layer and the on-state layer, affecting the performance of each of the phase change memory layer and the on-state layer.

[0071] Based on this, the present invention provides a three-dimensional phase change memory and a manufacturing method thereof, so that each layer of phase change memory unit and the first wiring (i.e., word line or bit line) required by it are separately manufactured, and further utilize the replacement of the sacrificial layer and the limiting effect of the dielectric sidewall to manufacture the phase change memory unit in which the bottom electrode is electrically in contact with the first contact, so that the shape and size of the phase change memory unit no longer completely depend on the overlap at the intersection of the word line and the bit line, which is conducive to achieving a smaller memory size and a higher storage density, and can improve the parasitic effects introduced by the word line and the bit line, and reduce the programming current and power supply requirements of the phase change memory. Further, when the word line, the bit line and the phase change memory unit are all implemented by a single exposure technology, the process complexity and cost brought by the use of double patterning technology to manufacture the word line and the bit line in the prior art can be further avoided. In addition, the contact plug (contact, which can also be called an electrical connection structure) used to lead the word line outward and the contact plug used to lead the bit line outward can be arranged at the periphery of the array formed by the phase change memory unit, thereby being conducive to further miniaturization of the overall size of the phase change memory and further improvement of the storage density.

[0072] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0073] First embodiment

[0074] Please refer to Figure 3 This embodiment provides a method for manufacturing a three-dimensional phase change memory, which includes the following steps:

[0075] S1, forming a first interlayer dielectric layer by using a first wiring process, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts located on each of the first wirings are formed in the first interlayer dielectric layer, wherein the first wirings are bit lines or word lines;

[0076] S2, forming a stacked layer on the first interlayer dielectric layer and the first contact, the stacked layer comprising a bottom electrode layer and a sacrificial layer stacked above the bottom electrode layer;

[0077] S3, performing corresponding photolithography and etching on the stacked layer until the bottom electrode layer is patterned to form a plurality of stacked bodies spaced apart from each other;

[0078] S4, forming a gap-filling layer in the gap between adjacent stacked bodies, wherein the gap-filling layer exposes the top surface of the sacrificial layer;

[0079] S5, removing the sacrificial layer to form an opening, and further forming a dielectric sidewall on the sidewall of the opening;

[0080] S6, depositing a phase change memory layer on the surface of the opening, the dielectric sidewalls and the gap filling layer.

[0081] First, please refer to Figure 4A As shown, in step S1, a substrate 100 is first provided, and then a first interlayer dielectric layer 101, a plurality of first wirings 102 extending along a first direction Y, and a plurality of first contacts 103 located on each first wiring 102 can be formed on the substrate 100 by a first wiring process.

[0082] The substrate 100 may be a wafer material that has been processed through a series of integrated circuit manufacturing processes. The wafer material may be selected from at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compounds. The wafer material may also be a multi-layer structure or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeO). The substrate 100 may have formed active or passive electronic components such as MOS transistors, diodes, resistors, etc., may also have a device isolation structure, etc., and may further form a multi-layer metal interconnect structure, etc. When the three-dimensional phase change memory to be formed has two layers of stacked or four layers of stacked or more layers of stacked phase change memory cells, the substrate 100 may also have completed the manufacture of some layers of phase change memory cells and their electrically connected word lines and / or bit lines.

[0083] When the first wiring 102 is used as a bit line, the first contact 103 on each first wiring 102 is used to make a column of phase change memory cells. When the first wiring 102 is used as a word line, the first contact 103 on each first wiring 102 is used to make a row of phase change memory cells.

[0084] The following takes the example that the first wiring 102 is used as a bit line and the second wiring formed subsequently is used as a word line to describe in detail the process of step S1 and the subsequent steps S2 to S4.

[0085] As an example, in step S1, the process of forming the first interlayer dielectric layer 101, the first wiring 102 and the first contact 103 includes:

[0086] First, a first dielectric layer 1011 is formed on the substrate 100 by a suitable process such as chemical vapor deposition and spin coating. The material of the first dielectric layer 1011 includes a combination of any one or more suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric. Preferably, the first dielectric layer 1011 is a low-k dielectric with a dielectric constant k less than 3, so as to reduce the parasitic effect introduced by the first wiring.

[0087] Next, the first dielectric layer 1011 is photolithographically etched using a bit line mask to form a plurality of first trenches extending along the first direction Y (not shown).

[0088] Then, each of the first trenches is filled with a conductive material by a suitable process such as chemical vapor deposition, sputtering deposition, electroplating, chemical plating, metal silicide manufacturing, doped polysilicon deposition, etc., and the filled conductive material is further subjected to chemical mechanical polishing (CMP), and the polishing stops at the top surface of the first dielectric layer 1011 to form a first wiring 102 filled in each of the first trenches. Thus, the material of the first wiring 102 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, metal silicide, etc.

[0089] Next, by chemical vapor deposition, spin coating or other suitable processes, the second dielectric layer 1012 is covered on the first dielectric layer 1011 and the first wiring 102, and the second dielectric layer 1012 and the first dielectric layer 1011 form the first interlayer dielectric layer 101. The material of the second dielectric layer 1012 can be the same as or different from that of the first dielectric layer 1011.

[0090] Afterwards, the contact hole array can be photolithographically and etched on the second dielectric layer 1012 with the aid of a corresponding mask capable of defining the contact hole array, so as to form a plurality of first contact holes (not shown) on each first wiring 102 that can expose the top surface of the corresponding position of the first wiring 102. When the size and shape of the phase change memory cell to be formed are substantially the same as those of the first contact 103 to be formed, the mask capable of defining the contact hole array is the mask for manufacturing the phase change memory cell array.

[0091] Then, conductive material is filled into each first contact hole by chemical vapor deposition, sputtering deposition, electroplating, chemical plating, metal silicide manufacturing, doped polysilicon deposition, and other suitable processes, and the filled conductive material is further subjected to chemical mechanical polishing (CMP), and the polishing stops at the top surface of the second dielectric layer 1012 to form the first contact 103 filled in each first contact hole. The material of the first contact 103 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, doped polysilicon, metal silicide, and the like. The material of the first contact 103 may be the same as or different from the material of the first wiring 102, for example, the first wiring 102 is copper and the first contact 103 is tungsten. The phase change memory cells subsequently connected to the same first wiring 102 through the first contact 103 constitute a column of phase change memory cells.

[0092] Of course, the first wiring process may not be limited to the above example. In another example of the present embodiment, the process of forming the first interlayer dielectric layer 101, the first wiring 102 and the first contact 103 by the first wiring process may include first forming a plurality of first wirings 102 separated from each other and extending along the first direction Y on the substrate 100 by a metal lift-off process, wherein the metal lift-off process is to first form a patterned photoresist layer on the substrate 100, then cover the patterned photoresist layer and the gaps therebetween with a metal layer, and then lift off the patterned photoresist layer. The metal layer filled in the gap of the patterned photoresist layer is the first wiring 102, and the metal layer outside the gap is removed as the photoresist layer is stripped; then, the first interlayer dielectric layer 101 is covered in the gap of the first wiring 102 and on the top surface of the first wiring 102, and the first interlayer dielectric layer 101 can fill the gap of the first wiring 102, and then holes are punched in the first interlayer dielectric layer 101 at the corresponding positions of the first wiring 102 to form first contact holes arranged in an array, and the first contact holes expose the top surface of the first wiring 102, and then the first contacts 103 filled in the first contact holes are further formed according to the method of the above example.

[0093] Optionally, the first wiring process may be a copper wiring process (eg, a copper interconnection process or a rewiring process using copper wires, etc.).

[0094] The first wiring 102 can be realized by only a single exposure technology (single patterning technique, also known as single patterning technology, single photolithography technology, etc.), without the need for double patterning technology, with fewer process steps and lower cost.

[0095] Please continue to refer to Figure 4AIn step S2, a bottom electrode layer 1041, a gate layer 1042, an intermediate electrode layer 1043 and a sacrificial layer 105 may be sequentially covered on the first interlayer dielectric layer 101 and the first contact 103 by a suitable process such as chemical vapor deposition, physical vapor deposition or atomic layer deposition to form a stacked layer. The materials of the bottom electrode layer 1041 and the intermediate electrode layer 1043 may be the same or different, and may be selected from one or more of C, Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu and Ni. The gate layer 1042 may include an Ovonic Threshold Switch (OTS) material. The material of the sacrificial layer 105 may be an inorganic insulating layer of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, may be an organic insulating layer including polyvinyl phenol, polyimide or siloxane, may be a single layer, or may be a composite structure formed by stacking multiple layers. For example, the sacrificial layer 105 includes an organic material layer (not shown) and a hard mask layer (not shown) stacked from bottom to top. Among them, the bottom electrode layer 1041, the gating layer 1042, and the intermediate electrode layer 1043 are used to form the lower structure layer 104 of the phase change memory unit. In other embodiments of the present invention, the gating layer 1042 and the intermediate electrode layer 1043 may also be omitted.

[0096] In this embodiment, the stacked layer needs to be processed by double pattern exposure technology to form the final required phase change memory unit. In this step S3, only the first pattern exposure in the double pattern exposure technology is performed on the stacked layer, and after step S6, the second pattern exposure in the double pattern exposure technology is performed on the stacked layer.

[0097] Specifically, please refer to Figure 4B In step S3, according to the size of the phase change memory unit to be formed, the stacked layers are subjected to corresponding photolithography and etching along the first direction Y until the bottom electrode layer 1041 is patterned to form a plurality of stacked bodies (not marked) spaced apart from each other and extending along the first direction Y. At this time, the gaps 106 between adjacent stacked bodies are grooves extending along the first direction Y. The line width of the stacked body may be less than, equal to, or greater than the line width of the first wiring 102. In this step, the sacrificial layer 105 may be subjected to corresponding photolithography and etching to form a corresponding pattern in the sacrificial layer 105, and then the lower structure layer 104 formed by the intermediate electrode layer 1043 to the bottom electrode layer 1041 is etched using the sacrificial layer 105 as a mask to form the desired stacked body.

[0098] Please refer to Figure 4C and Figure 4DIn step S4, first, an interface protection layer 107 is formed on the side wall of the stack by a suitable method such as a deposition method or a plasma reaction method; then, a gap filling layer 108 is deposited in the gap 106 between adjacent stacks and on the top surface of the sacrificial layer 105 by a suitable material deposition process such as chemical vapor deposition and high aspect ratio vapor deposition. The deposited gap filling layer 108 can fill the gap 106 or seal the gap 106 into a structure with an air gap (the air gap can reduce parasitic capacitance); then, the top of the gap filling layer 108 is chemically mechanically polished until the top surface of the sacrificial layer 105 of each stack is exposed. The material of the interface protection layer 107 can be selected from at least one of silicon oxide, silicon nitride, and silicon oxynitride. The interface protection layer 107 can improve the adhesion between the subsequent gap filling layer and the side wall of the intermediate electrode layer 1043 to the bottom electrode layer 1041 of the stack, and block the diffusion of elements between the intermediate electrode layer 1043 to the bottom electrode layer 1041 and the gap filling layer formed subsequently, prevent the material composition of each film layer from changing, and ensure the performance of the device. In this embodiment, the interface protection layer 107 has a first interface layer 1071, a second interface layer 1072 and a third interface layer 1073 stacked sequentially on the side wall surface of each stack. The material of the first interface layer 1071 and the third interface layer 1073 can be the same, and the material of the second interface layer 1072 is different from that of the first interface layer 1071. The material of the gap filling layer 108 includes, for example, one or more combinations of silicon oxide, tetraethyl orthosilicate, low-k dielectrics (including organic or inorganic porous materials), etc.

[0099] Please refer to Figure 4E In step S5, first, the sacrificial layer 105 can be removed by any suitable process such as wet etching or dry etching to form an opening 109, in which case the opening 109 is a strip-shaped groove extending along the first direction; then, a dielectric material is deposited on the inner surface of the opening 109, the top surface of the interface protection layer 107, and the top surface of the gap filling layer 108 by a suitable deposition process, and further, the dielectric material on the bottom surface of the opening 109, the top surface of the interface protection layer 107, and the top surface of the gap filling layer 108 is etched and removed by a suitable sidewall etching process, thereby forming a dielectric sidewall 110 on the sidewall of the opening 109. The material of the dielectric sidewall 110 can be at least one of titanium nitride, tantalum nitride, silicon nitride, silicon oxynitride, etc., and can be a single-layer film or a multi-layer film stacked structure. Among them, on the one hand, the dielectric sidewall 110 can block the elements in the phase change storage layer subsequently filled in the opening 109 from diffusing outward and block external elements from diffusing into the phase change storage layer, and on the other hand, it also needs to have a suitable thickness to ensure that the line width of the phase change storage layer in the phase change storage unit finally formed meets the requirements.

[0100] Please refer to Figure 4F In step S6, a phase change memory layer 111 may be deposited on the surfaces of the opening 109, the dielectric sidewall 110, the interface protection layer 107, and the gap filling layer 108 by a suitable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal organic chemical vapor deposition (MOCVD). The deposition thickness of the phase change memory layer 111 is at least enough to fill the opening 109. The material of the phase change memory layer 111 may be any suitable phase change material, for example, may include at least one of Ge-Sb-Te based phase change material (also known as GST), Ge-Te based phase change material, Ge-Sb based phase change material, Si-Sb-Te based phase change material, Sb-Te based phase change material, Sb based phase change material, etc., and may be a combination of two phase change materials, a combination of three phase change materials, or a combination of more phase change materials. Among them, the Ge-Sb-Te based phase change material is composed of three elements: Ge, Sb and Te, which may include but not limited to Ge3Sb4Te8, Ge2Sb2Te5, Ge2Sb2Te4, GeSb2Te4, etc., and the Ge-Te based phase change material is composed of two elements: Ge and Te. Among them, the Ge-Sb based phase change material is composed of two elements: Ge and Sb, and the Si-Sb-Te based phase change material is composed of three elements: Si-, Sb and Te, which may include but not limited to: Si11Sb57Te32, Si18Sb52Te30, Si24Sb48Te28, etc. Therefore, based on the fact that the phase change material contained in the phase change memory layer 111 can be a single layer or a combination of multiple phase change materials, the present invention does not impose any specific restriction on the number of layers of the phase change memory layer 111, which can be a single layer or multiple layers, such as 2 layers, 3 layers, 4 layers, 5 layers, 6 layers or even more layers. The crystallization temperature and threshold voltage of two adjacent layers of phase change materials can be different. When the phase change materials with different crystallization temperatures and threshold voltages correspond to different pulse voltages or pulse currents for phase change, under a pulse voltage or pulse current of a specific magnitude, the phase change materials of all layers of the phase change memory layer 111 may be in a low resistance state, or the phase change materials of all layers of the phase change memory layer 111 may be in a high resistance state, or the phase change materials of some layers may be in a low resistance state, while the phase change materials of other layers may be in a high resistance state.

[0101] The method for manufacturing a three-dimensional phase change memory of this embodiment, after step S6, further includes the following steps:

[0102] S7 (not shown), please refer to Figure 4G, the phase change memory layer 111 and the remaining stack (i.e., the lower structure layer 104 formed by the intermediate electrode layer 1043, the gating layer 1042 and the bottom electrode layer 1041) are subjected to corresponding photolithography and etching along a second direction X intersecting with the first direction Y, until the bottom electrode layer 1041 is patterned again, thereby achieving the purpose of forming a plurality of mutually spaced phase change memory units by double pattern exposure technology, wherein the bottom electrode layer 1041 of each phase change memory unit is aligned with and electrically contacted with the corresponding first contact 103.

[0103] S8 (not shown), please refer to Figure 4H , a second interlayer dielectric layer 112 is formed by a second wiring process, and a required second contact 113 is formed in the second interlayer dielectric layer 112, and a plurality of second wirings 114 extending along the second direction X are formed on the second interlayer dielectric layer 112. The second interlayer dielectric layer covers the film layers such as the phase change memory layer 111, the gap filling layer 108, and the interface protection layer 107, and fills the gaps (not shown) between adjacent phase change memory cells, and buries the top surface of the phase change memory layer 111 of each phase change memory cell. The second interlayer dielectric layer 112 may include a combination of any one or more suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric, and the material used to fill the gaps between adjacent phase change memory cells is preferably a low-k dielectric with a dielectric constant k less than 3, so as to reduce the parasitic effects introduced by the second wiring formed subsequently. The second interlayer dielectric layer 112 may be a single-layer film layer or a multi-layer film layer. The second interlayer dielectric layer 112 includes another interface protection layer (not shown, the material of which can be the same as the interface protection layer 107) covering the sidewalls of each phase change memory cell, another gap filling layer (not shown, the material of which can be the same as the gap filling layer 108) filling the gap between adjacent phase change memory cells, and a metal interlayer dielectric layer (not shown, the material of which can be the same as the first interlayer dielectric layer 101) covering the device surface including the other gap filling layer. Each second contact 113 is aligned with and in contact with the phase change memory layer 111 of the corresponding phase change memory cell, and each second wiring 114 is electrically connected to the corresponding phase change memory cell through the corresponding second contact 113, wherein when the first wiring 102 is a bit line, the second wiring 114 is a word line, and each second wiring 114 is electrically connected to a plurality of second contacts 113 arranged in a row along the second direction X, that is, the phase change memory cells connected to the same second wiring 114 through the second contact 113 constitute a row of phase change memory cells. When the first wiring 102 is a word line, the second wiring 114 is a bit line.

[0104] In this embodiment, the second wiring process can be implemented by a single exposure technology (single patterning technique, also known as single patterning technology, single photolithography technology, etc.), without the need for double patterning technology, with fewer process steps and lower cost.

[0105] In this embodiment, the second wiring 114 and the first wiring 102 intersect vertically, the contact array formed by the second contact 113 and the contact array formed by the first contact 103 are aligned, and the cross-sections of the second contact 113, the first contact 103 and the phase change memory unit along the XY plane are all circular, and the radii of the cross-sectional circles of the second contact 113 and the first contact 103 are smaller than the cross-sectional circle of the phase change memory unit, that is, the sizes of the second contact 113 and the first contact 103 are smaller than the size of the phase change memory unit.

[0106] from Figure 5 It can be seen that, due to the etching along the first direction in step S3 and the etching along the second direction in step S8 in this embodiment, the phase change memory cell finally formed is a rectangular (or square) column, but its length and width can be smaller than the line width of the first wiring and the line width of the second wiring, respectively, so it is possible to manufacture a smaller-sized phase change memory cell compared to the prior art. And in this embodiment, the second contact 113 serves as the top electrode of the phase change memory cell cell to realize the electrical connection between the phase change memory cell cell and the second wiring 114.

[0107] As an example, see Figure 4H The process of implementing the second wiring process in step S8 includes:

[0108] First, another interface protection layer (not shown) is formed on the sidewalls of the phase change memory unit.

[0109] Then, another gap-filling layer is filled in the gaps between adjacent phase-change memory cells, and the other gap-filling layer is planarized to the top surface of the phase-change memory layer 111 .

[0110] Afterwards, the intermetallic dielectric layer is covered on the gap filling layer 108, another gap filling layer, and the phase change memory layer 111, and the intermetallic dielectric layer can be photolithographically and etched with the help of a corresponding mask that can be used to define the contact hole lattice, so as to form a plurality of second contact holes (not shown) in the intermetallic dielectric layer. The mask can be the same mask as the mask used to form the first contact in step S1, so as to reduce the mask cost and improve the alignment accuracy of the first contact and the second contact to be formed. The other interface protection layer, the other gap filling layer, and the intermetallic dielectric layer constitute the second interlayer dielectric layer 112.

[0111] Then, each second contact hole is filled with a conductive material by a suitable process such as chemical vapor deposition, sputtering deposition, electroplating, chemical plating, metal silicide manufacturing, doped polysilicon deposition, etc., and the filled conductive material is further subjected to chemical mechanical polishing (CMP), and the polishing stops at the top surface of the intermetallic dielectric layer to form a second contact 113 filled in each second contact hole. The material of the second contact 113 may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, doped polysilicon, metal silicide, etc.

[0112] Afterwards, a plurality of second wirings 114 extending along the second direction X may be formed on the intermetallic dielectric layer by a method similar to forming the first dielectric layer 1011 on the substrate 100 and forming the first wirings 102 in the first dielectric layer 1011 .

[0113] It should be noted that, in another example of the present embodiment, the second wiring process may include a process of forming the second contact 113 through a contact hole process and a process of forming the second wiring 114 through a metal stripping process. For details, reference may be made to the description of another embodiment of the first wiring process above, which will not be repeated here. In another example of the present embodiment, the second wiring process may also be a dual-damascene damascene process, the process of which includes: first etching a groove in the intermetallic dielectric layer for forming the second wiring 114 and further etching a second contact hole in the intermetallic dielectric layer at the bottom of the groove to expose the top surface of the corresponding phase change storage layer, and then filling the second contact hole and the groove together to form the second contact 113 and the second wiring 114 together.

[0114] Optionally, after step S6 and before step S7, or after step S7 and before step S8, the top surface of the phase change memory layer 111 is planarized by a process such as chemical mechanical polishing (CMP) until the top surface of the gap filling layer 108 is exposed, so as to provide a flat process surface for the subsequent second wiring process. After the top surface planarization of the phase change memory layer 111 is completed, the structure of the combination of the dielectric sidewall 110 and the phase change memory layer 111 is aligned with the bottom electrode layer 1041.

[0115] It should be understood that the above embodiment only shows the manufacture of one layer of phase change memory cells and word lines and bit lines electrically connected thereto. When the architecture of the three-dimensional phase change memory to be manufactured by the present invention includes two layers of stacked phase change memory cells, a corresponding contact array can be manufactured above the second wiring according to the manufacturing method in the above embodiment, and then an upper phase change memory cell can be manufactured above the contact array. Then, another contact array and a third wiring electrically connected to the other contact array can be manufactured on the upper phase change memory cell. The second wiring and the third wiring intersect, and the third wiring can be parallel to the first wiring. Alternatively, a layer of lower phase change memory cells and a fourth wiring electrically connected thereto can be manufactured below the first wiring according to the manufacturing method in the above embodiment, and the fourth wiring is connected to the electrode at the bottom of the lower phase change memory cell through the corresponding contact in the one contact array, and the first wiring is connected to the electrode at the top of the lower phase change memory cell through the corresponding contact in the other contact array, and the fourth wiring intersects with the first wiring, and the fourth wiring can be parallel to the second wiring.

[0116] Therefore, when the architecture of the three-dimensional phase change memory to be manufactured in the present invention includes three, four or more layers of phase change memory cells stacked along the Z direction which is perpendicular to both the X and Y directions, the sequential structure of wiring-contact-phase change memory cell-contact-wiring... in the above embodiment can be repeated along the Z direction until the manufacture of all layers of phase change memory cells and their electrically connected word lines and bit lines is completed.

[0117] The manufacturing method of the three-dimensional phase change memory of the present embodiment adopts a first wiring process to first form a first wiring used as a bit line or a word line and a first contact on the first wiring on a substrate, and then utilizes the replacement of a sacrificial layer and the limiting effect of a dielectric sidewall to manufacture a phase change memory unit in which a bottom electrode is in electrical contact with the first contact, and then further utilizes a second wiring process to manufacture a second wiring and a second contact. The manufacturing method makes it possible for the patterning of the bit line, the word line and the phase change memory unit to have no correlation as in the existing double patterning technology, so that the shape and size of the phase change memory unit no longer completely depend on the overlap at the intersection of the word line and the bit line, and the dielectric sidewall can be used to limit the line width of the phase change memory layer of the phase change memory unit, so that a smaller phase change memory unit size can be achieved, which can be conducive to further miniaturization of the overall size of the phase change memory and further improvement of the storage density. And because the second wiring (for example, the word line) can be electrically contacted with the top electrode of the phase change memory cell through the second contact, and the first wiring (for example, the bit line) can be electrically contacted with the bottom electrode of the phase change memory cell through the first contact, it is possible to reduce the parasitic effects caused by the word line and the bit line (including parasitic resistance R, parasitic capacitance C, and RC delay effect, etc.), improve the crosstalk problem between adjacent memory cells, and thereby reduce the programming current and power requirements of the phase change memory.

[0118] In addition, since the film layers such as the selection layer 1042 are first etched along the Y direction under the protection of the sacrificial layer, and then the sacrificial layer 105 is replaced by the phase change storage layer 111, compared with the double pattern exposure technology in the prior art, the solution of this embodiment reduces the process of etching the phase change storage layer 111 and the selection layer 1042 together at one time, thereby improving the cross-contamination problem between the phase change storage layer and the selection layer, and ensuring the performance of each of the phase change storage layer and the selection layer.

[0119] Second embodiment

[0120] Please refer to Figure 3 , 4A to 4H as well as Figure 6 This embodiment also provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6 and step S8. The method for manufacturing a three-dimensional phase change memory in this embodiment is different from that in the first embodiment in that, in step S3, the stacked layer formed by the bottom electrode layer 1041 to the sacrificial layer 105 is patterned by a single exposure technique or a multiple pattern exposure technique to directly form an island-shaped stacked body corresponding to each phase change memory unit, thereby omitting the execution of step S7 after step S6.

[0121] Specifically, in step S3, when a single exposure technique (single patterning technique, also known as single patterning processing technology, single photolithography technology, etc.) is adopted, the sacrificial layer 105 can be photolithographically processed and etched once with the help of a mask having patterns corresponding to each phase change memory unit, so as to form a pattern for defining each phase change memory unit in the sacrificial layer 105. When a multiple pattern exposure technology is used, the multiple pattern exposure technology can be a lithography-etching-lithography-etching (Litho-Etch-Litho-Etch, LELE) technology, which splits an original layer of lithography patterns into two or more masks to achieve the superposition of pattern density in the sacrificial layer 105; the multiple pattern exposure technology can also be a lithography-curing-lithography-etching (Litho-Freeze-Litho-Etch, LFLE) technology, which uses two lithography steps and one etching step to double the pattern density in the sacrificial layer 105; the multiple pattern exposure technology can also be a self-aligned double patterning (Self Aligned Double Patterning, SADP) technology, which forms an axial pattern through a single lithography and etching process, and then forms a sidewall pattern on the sidewall through atomic layer deposition and etching processes, removes the axial layer (i.e., the sacrificial layer), and forms a sacrificial layer 105 pattern in the form of a sidewall with a half size (pitch). Therefore, no matter what kind of photolithography technology is used in step S3 of this embodiment, it is ultimately necessary to first use corresponding photolithography and etching processes to pattern the sacrificial layer 105, and make the pattern in the sacrificial layer 105 correspond to the phase change memory unit and the array formed by it, and the size and shape of each pattern meet the manufacturing requirements of the size and shape of each phase change memory unit, and then use the sacrificial layer 105 as a mask to etch the lower structure layer 104 from the intermediate electrode layer 1043 to the bottom electrode layer 1041 to form an island-shaped stack corresponding to each phase change memory unit, and there is a gap between adjacent stacks. The bottom electrode layer in each stack is aligned with and electrically contacts the corresponding first contact to serve as the bottom electrode of the phase change memory unit to be formed. Among them, when a single exposure technology is used to form a pattern for defining each phase change memory unit in the sacrificial layer 105, compared with the double pattern exposure technology or the multiple pattern exposure processing technology, the process steps are few and the cost is low, but the limit size of the phase change memory unit formed is limited by the limit size of the single exposure technology.

[0122] After step S6, the top surface of the phase-change memory layer 111 is planarized until the top surface of the gap-filling layer 108 is exposed; then, step S8 is performed to form a second interlayer dielectric layer 112 on the phase-change memory layer 111 and the gap-filling layer 108 by a second wiring process, and to form a required second contact 113 in the second interlayer dielectric layer 112, and to form a plurality of second wirings 114 extending along the second direction X on the second interlayer dielectric layer 112, each second contact 113 is aligned with and contacts the phase-change memory layer 111 of the corresponding phase-change memory unit, and each second wiring 114 is electrically connected to the corresponding phase-change memory unit through the corresponding second contact 113, wherein when the first wiring 102 is a bit line, the second wiring 114 is a word line, and when the first wiring 102 is a word line, the second wiring 114 is a bit line.

[0123] It should be understood that steps S1 to S2, steps S4 to S6 and step S8 of this embodiment are the same as those of the first embodiment, and reference may be made to the corresponding descriptions above, which will not be repeated here.

[0124] Please refer to Figure 6 Since the intermediate electrode layer to the bottom electrode layer are directly etched into an island structure corresponding to the phase-change memory cell in step S3 of this embodiment, the phase-change memory cell finally formed can be a cylinder, and its diameter is smaller than the line width of the first wiring 102 and the line width of the second wiring 114, respectively, so that the manufacture of a smaller-sized phase-change memory cell can be achieved compared with the first embodiment. Moreover, the bit line, phase-change memory cell and word line are all made separately and can all be made using a single patterning process technology, thereby avoiding the process complexity and cost caused by using double patterning technology to make word lines, phase-change memory cells and bit lines in the prior art, thereby achieving the effect of simplifying process steps and reducing costs.

[0125] In addition, since the intermediate electrode layer to the bottom electrode layer are directly etched into an island structure corresponding to the phase change memory unit in step S3 of the present embodiment, the etching of the phase change memory layer 111 and the selection layer 1042 can be completely separated and no longer etched together, thereby more effectively improving the cross-contamination problem between the phase change memory layer and the selection layer, thereby ensuring the performance of each of the phase change memory layer and the selection layer.

[0126] Third embodiment

[0127] Please refer to Figure 3 , 4A to 4H as well as Figures 5 to 8This embodiment provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6, and also includes step S7 or steps S7-S8. Compared with the first embodiment and the second embodiment, the difference is that the substrate 100 provided in step S1 has a storage area I and a peripheral area II, the storage area I is mainly used to form a phase change memory array to store data, and the peripheral area II is mainly used to form a peripheral circuit to realize the functional control of the operation (reading operation, writing operation, etc.) of the phase change memory array. The first wiring process in step S1 and the second wiring process in step S8 of this embodiment are not implemented separately from the manufacturing process of the electrical connection structure for realizing the electrical connection between the peripheral circuit and the word line or the bit line of the peripheral area II, but are embedded in the manufacturing process of the electrical connection structure for realizing the electrical connection between the peripheral circuit and the word line or the bit line of the peripheral area II.

[0128] Specifically, please refer to Figure 7 and Figure 8 In the manufacturing method of the three-dimensional memory provided in this embodiment, the substrate 100 provided in step S1 has a storage area I and a peripheral area II located outside the storage area I, and the required peripheral circuit (not shown) has been formed in the substrate of the peripheral area II, and the peripheral circuit is used to realize the functional control of the operation (read operation, write operation, etc.) of the phase change memory unit. The manufacturing method of this embodiment also includes: forming a multi-layer metal interconnection structure above the substrate 100 in the peripheral area II through a multi-layer metal interconnection process, wherein the first wiring process in step S1 is a formation process of a certain layer of metal wiring in the multi-layer metal interconnection process, and the second wiring process in step S8 is a formation process of another layer of metal wiring in the multi-layer metal interconnection process, so that the first wiring 102 and a layer of metal wiring in the multi-layer metal interconnection structure are the same layer of metal, and the second wiring 114 and another layer of metal wiring in the multi-layer metal interconnection structure are the same layer of metal. At this time, the manufacturing of the phase change memory can be embedded in the manufacturing process of the peripheral integrated circuit. When the multi-layer metal interconnection process is a copper interconnection process, the first wiring 102 and the second wiring 114 may both be copper, and the first contact 102 and the second contact 113 may both be tungsten plugs.

[0129] As an example, in step S1 of the present embodiment, while forming the first wiring 102 as the bit line in the storage area I by the first wiring process, the first layer of word line peripheral circuit wiring 102' is formed in the peripheral area II, and while forming the first contact 103 in the storage area I, the peripheral contact 103' located on the first layer of word line peripheral circuit wiring 102' and electrically contacting the first layer of word line peripheral circuit wiring 102' is formed in the peripheral area II; in step S8, the first wiring 102 is formed in the storage area I by the second wiring process. While forming the second contact 113 in the storage area, a peripheral contact 113' is also formed in the peripheral area II, which is located on the peripheral contact 103' and electrically in contact with the peripheral contact 103'. While forming the second wiring 114 in the storage area I, a second layer of word line peripheral circuit wiring 114' is also formed in the peripheral area II, which is located on the peripheral contact 113' and electrically in contact with the peripheral contact 113'. Thus, the peripheral contacts 103' and 113' form a word line contact plug (i.e., a second contact plug), and the first layer of word line peripheral circuit wiring 102', the peripheral contacts 103' and 113', and the second layer of word line peripheral circuit wiring 114' are connected in sequence to form an electrical connection structure for electrically connecting the second wiring (i.e., word line) 114 and the corresponding peripheral circuit in the peripheral area II.

[0130] It should be understood that the first-layer word line peripheral circuit wiring 102' is electrically isolated from the first wiring 102, and the second-layer word line peripheral circuit wiring 114' can be integrated with the second wiring 114, that is, the second-layer word line peripheral circuit wiring 114' is the part of the second wiring 114 extending into the peripheral area II, the second-layer word line peripheral circuit wiring 114' can also be separated from the second wiring 114, and the second-layer word line peripheral circuit wiring 114' can also be electrically connected to the second wiring 114 only through a subsequent wiring process or a metal interconnection process.

[0131] Similarly, when the first wiring 102 is led outward from the top surface of the peripheral region II, in step S1, the first wiring 102 is formed as a bit line in the memory region I by the first wiring process. A first layer of bit line peripheral circuit wiring (not shown) is formed in the peripheral region II, and while the first contact 103 is formed in the storage region I, a first peripheral contact (not shown) located on the first layer of bit line peripheral circuit wiring and electrically in contact with the first layer of bit line peripheral circuit wiring is also formed in the peripheral region II; in step S8, while the second contact 113 is formed in the storage region I through a second wiring process, a second peripheral contact (not shown) located on the first peripheral contact and electrically in contact with the first peripheral contact is also formed in the peripheral region II, and while the second wiring 114 is formed in the storage region I, a second layer of bit line peripheral circuit wiring (not shown) located on the second peripheral contact and electrically in contact with the second peripheral contact is also formed in the peripheral region II, thereby, the first peripheral contact and the second peripheral contact form a bit line contact plug (i.e., a first contact plug), and the first layer of bit line peripheral circuit wiring, the first peripheral contact and the second peripheral contact, and the second layer of bit line peripheral wiring are sequentially connected to form an electrical connection structure for electrically connecting the first wiring (i.e., word line) 102 and the corresponding peripheral circuit in the peripheral region II.

[0132] It should also be understood that the second layer of bit line peripheral circuit wiring is electrically insulated and isolated from the second wiring 114. The first layer of bit line peripheral circuit wiring can be integrated with the first wiring 102, that is, the first layer of bit line peripheral circuit wiring is the part of the first wiring 102 extending into the peripheral area II, and the first layer of bit line peripheral circuit wiring can also be electrically insulated and isolated from the first wiring 102. The first layer of word line peripheral circuit wiring can only be electrically connected to the first wiring 102 through a subsequent wiring process or a metal interconnection process, that is, the electrical connection is achieved through an electrical connection structure including the second layer of bit line peripheral circuit wiring.

[0133] That is to say, in this embodiment, the substrate 100 has a storage area I and a peripheral area II located outside the storage area I, and the first wiring 102 and the second wiring 114 both extend from the storage area I to the peripheral area II, and the manufacturing method of this embodiment also includes: while performing the first wiring process and the second wiring process in the storage area I respectively, a corresponding electrical connection structure is also formed together in the peripheral area II, so that while the second contact 113 is manufactured in the storage area I, the first contact plug (contact) and the second contact plug (contact) are manufactured in the peripheral area II, so that the second wiring 114 extending into the peripheral area II is electrically connected to the second contact plug, and the first wiring 102 extending into the peripheral area II is electrically connected to the first contact plug.

[0134] It should be understood that steps S1 to S2, steps S4 to S6 and step S8 (or steps S7 to S8) of this embodiment are the same as those of the first embodiment or the second embodiment, and reference may be made to the corresponding descriptions above, which will not be repeated here.

[0135] Please refer to Figure 8 The manufacturing method of the three-dimensional phase change memory of this embodiment can arrange the contact plugs required for the word line and the bit line in the peripheral area II, that is, the second contact plug CT1 required for the second wiring 114, the first contact plug CT2 required for the first wiring 102, and the third contact plug CT3 required for the third wiring (for example, the top-layer bit line TBL) are all arranged in the peripheral area II, which can avoid the problem of word line contact plugs and bit line contact plugs occupying the storage area in the prior art, thereby being conducive to further miniaturization of the overall size of the phase change memory and further improvement of the storage density.

[0136] In some examples of the present embodiment, the peripheral circuits of the peripheral area II are some digital, analog and / or mixed signal circuits pre-formed in the substrate for phase change memory array operations. These signal circuits include control logic elements, data buffers, decoders (also called decoders), drivers and read-write circuits, etc. These peripheral circuits need to be ultimately electrically connected to the word lines and bit lines through electrical connection structures such as a multi-layer metal interconnect structure formed in the substrate and a contact plug formed in the peripheral area II and located on the periphery of the storage area.

[0137] Fourth embodiment

[0138] Please refer to Figure 3 , FIG. 4A to FIG. 4G as well as Figures 9 and 10This embodiment also provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6 and step S7. The method for manufacturing a three-dimensional phase change memory in this embodiment is different from that in the first embodiment in that after executing step S6 and before executing step S7, the top surface of the phase change memory layer 111 deposited in step S6 is firstly flattened until the top surface of the gap filling layer 108 is exposed, and then the top electrode layer and the second wiring layer are sequentially deposited on the phase change memory layer 111 and the gap filling layer 108. When executing step S7, the second wiring layer, the top electrode layer, the phase change memory layer 111 and the remaining stack (i.e., the lower structure layer 104 formed by the middle electrode layer 1043 to the bottom electrode layer 1041) are subjected to corresponding photolithography and etching along the second direction X until the bottom electrode layer 1041 is patterned again, so as to form a plurality of mutually spaced phase change memory cells and a plurality of top electrode lines 115 and second wirings 114 extending along the second direction X by double patterning technology, the bottom electrode layer 1041 of each phase change memory cell is aligned with and electrically contacts the corresponding first contact 103, and each second wiring 114 is electrically connected to a plurality of phase change memory cells (i.e., the phase change memory cells in the same row) through the top electrode line 115 aligned thereunder, wherein when the first wiring 102 is a bit line, the second wiring 114 is a word line, and when the first wiring 102 is a word line, the second wiring 114 is a bit line.

[0139] The material of the top electrode line 115 may be the same as or different from the material of the middle electrode layer 1043 or the bottom electrode layer 1041. As an example, the materials of the top electrode line 115, the middle electrode layer 1043 and the bottom electrode layer 1041 are all amorphous carbon.

[0140] It should be understood that steps S1 to S6 of this embodiment are the same as those of the first embodiment, and reference may be made to the corresponding descriptions above, which will not be repeated here.

[0141] from Fig.10It can be seen that, since the patterning process of the stacked layer along the first direction in this embodiment is not performed together with the manufacture of the first wiring, and the patterning process along the second direction is performed together with the manufacture of the second wiring, a key dimension (such as width) of the formed phase change memory cell is limited by the line width of the second wiring, but its other key dimension (such as length) can be flexibly designed as needed, and the shape and size of the phase change memory cell are no longer completely dependent on the overlap at the intersection of the word line and the bit line, and the dielectric sidewall can be used to limit the line width of the phase change memory layer of the phase change memory cell, so that a smaller phase change memory cell size can be achieved, which can be beneficial to further miniaturization of the overall size of the phase change memory and further improvement of the storage density. Moreover, in the manufacturing method of the three-dimensional phase change memory of this embodiment, after step S6, the second wiring layer, the top electrode layer, the phase change memory layer and the remaining stacked body are patterned together along the second direction, which can further simplify the process complexity and cost of manufacturing the second wiring (word line or bit line).

[0142] Fifth embodiment

[0143] Please refer to Figure 3 , FIG. 4A to FIG. 4G as well as Fig. 9 , Fig.11 This embodiment also provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6 and step S7. The manufacturing method of the three-dimensional phase change memory of the present embodiment is different from that of the second embodiment in that, after executing step S6, the top surface of the phase change memory layer 111 deposited in step S6 is firstly flattened until the top surface of the gap filling layer 108 is exposed, and then the top electrode layer and the second wiring layer are sequentially deposited on the phase change memory layer 111 and the gap filling layer 108, and then the second wiring layer and the top electrode layer are correspondingly photolithographically and etched along the second direction X to form a plurality of top electrode lines 115 and second wirings 114 extending along the second direction X, the bottom electrode layer 1041 of each phase change memory cell is aligned with and electrically contacts the corresponding first contact 103, and each second wiring 114 is electrically connected to a plurality of phase change memory cells (i.e., phase change memory cells in the same row) through the top electrode line 115 aligned thereunder, wherein when the first wiring 102 is a bit line, the second wiring 114 is a word line, and when the first wiring 102 is a word line, the second wiring 114 is a bit line.

[0144] It should be understood that steps S1 to S6 of this embodiment are the same as those of the first embodiment, and reference may be made to the corresponding descriptions above, which will not be repeated here.

[0145] from Fig.11It can be seen that, since the patterning process of the phase change memory unit in this embodiment is not related to the first wiring and the second wiring, a smaller-sized phase change memory unit can be realized compared to the solution of the fourth embodiment, for example, the phase change memory unit is cylindrical, which is conducive to further miniaturization of the overall size of the phase change memory and further improvement of the storage density. Moreover, in the manufacturing method of the three-dimensional phase change memory of this embodiment, the second wiring is simultaneously connected to a row of phase change memory units through the top electrode line, which is conducive to improving the control ability of the second wiring to a row of phase change memory units compared to the solution of the second embodiment, and simplifying the complexity and cost of the manufacturing process of electrically connecting the second wiring to a row of phase change memory units.

[0146] Sixth embodiment

[0147] Please refer to Figure 3 , FIG. 4A to FIG. 4G as well as Fig.12 , this embodiment provides a method for manufacturing a three-dimensional phase change memory, which also includes steps S1 to S6 and step S7. Compared with the fourth embodiment and the fifth embodiment, the difference is that the substrate 100 provided in step S1 has a storage area I and a peripheral area II, the storage area I is mainly used to form a phase change memory array to store data, and the peripheral area II is mainly used to form a peripheral circuit to realize the functional control of the operation (read operation, write operation, etc.) of the phase change memory array. The first wiring process in step S1 of this embodiment is also embedded in the manufacturing process of the electrical connection structure (for example, a multi-layer metal interconnection process) for realizing the electrical connection between the peripheral circuit and the word line or the bit line of the peripheral area II, and before depositing the top electrode layer and the second wiring layer, the peripheral contact 113' will be formed in the peripheral area II by the manufacturing process of the electrical connection structure, and the top electrode line 115 and the second wiring 114 will be formed in the storage area I. At the same time, two layers of peripheral wiring (i.e. Fig.12 115' and 114').

[0148] The peripheral contacts 113' and two layers of peripheral wiring (i.e. Fig.12 The process of forming the peripheral contacts 113' and the second layer word line peripheral circuit wiring 114' in the third embodiment is similar to the process of forming the peripheral contacts 113' and the second layer word line peripheral circuit wiring 114' in the third embodiment, and can be referred to above, so it will not be described in detail here.

[0149] Please further combine Figure 8The manufacturing method of the three-dimensional phase change memory of this embodiment can also arrange the electrical connection structures such as contact plugs required for word lines and bit lines in the peripheral area II, that is, the second contact plug CT1 required for the second wiring 114, the first contact plug CT2 required for the first wiring 102, and the third contact plug CT3 required for the third wiring (for example, the top-layer bit line TBL) are all arranged in the peripheral area II, which can avoid the problem of word line contact plugs and bit line contact plugs occupying the storage area in the prior art, thereby facilitating further miniaturization of the overall size of the phase change memory and further improving the storage density.

[0150] Seventh embodiment

[0151] Based on the same inventive concept, this embodiment also provides a three-dimensional phase change memory, which is preferably manufactured using the manufacturing method of the three-dimensional phase change memory of any embodiment of the present invention described above. Of course, those skilled in the art can also use corresponding process steps to replace the corresponding process steps in the manufacturing method of the three-dimensional phase change memory of the present invention to manufacture the same structure.

[0152] Please refer to Figures 3 to 12 , the three-dimensional phase change memory of this embodiment includes:

[0153] A first interlayer dielectric layer 101, in which a plurality of first wirings 102 extending along a first direction Y and a plurality of first contacts 103 located on each first wiring 102 are formed;

[0154] A plurality of mutually spaced phase change memory cells are formed on the first interlayer dielectric layer 101, and each phase change memory cell comprises a bottom electrode layer 1041 and a phase change memory layer 111 stacked in sequence, the bottom electrode layer 1041 is aligned with and electrically contacts the corresponding first contact 103, a dielectric sidewall 110 is formed on the sidewall of the phase change memory layer 111, and the structure of the combination of the dielectric sidewall 110 and the phase change memory layer 111 is aligned with the bottom electrode layer 1041;

[0155] A gap filling layer 108 is used to fill the gap between adjacent phase change memory cells;

[0156] A plurality of second wirings 114 extending along a second direction X intersecting the first direction Y, the second wirings 114 being formed above the phase-change memory cell and the gap-filling layer 108, and each second wiring 114 being electrically connected to a corresponding phase-change memory cell through a corresponding second contact 113 or a top electrode line 115 extending along the second direction X;

[0157] Here, the first wiring 102 is a bit line and the second wiring 114 is a word line, or the first wiring 102 is a word line and the second wiring 114 is a bit line.

[0158] Optionally, the materials of the first wiring 102 and the second wiring 114 respectively include at least one of Cu, Al, Pt, Au, and Ag, and the materials of the second contact 113 and the first contact 103 respectively include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, and metal silicide.

[0159] Optionally, the three-dimensional phase change memory of the present embodiment further includes a substrate 100, a first interlayer dielectric layer 101 and a first wiring 102 are formed on the substrate 100, the substrate 100 has a storage area I and a peripheral area II located outside the storage area I, and an electrical connection structure (i.e., Figure 6 and Fig.12 102', 103').

[0160] It should be understood that the three-dimensional phase change memory of this embodiment may further include other film layers, and the specific structures of these film layers may refer to the description of the corresponding film layers in the above method for manufacturing the three-dimensional phase change memory, which will not be repeated here.

[0161] The three-dimensional phase change memory provided in this embodiment has a phase change memory cell whose shape and size no longer completely depend on the overlap at the intersection of the word line and the bit line, which is conducive to achieving a smaller device size and a higher storage density, improving the parasitic effects introduced by the word line and the bit line, and reducing the programming current and power requirements of the phase change memory.

[0162] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0163] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0164] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0165] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the present invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have a logical "or" definition, rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiment of the present invention may include performing the selected task manually, automatically, or in combination.

[0166] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional phase change memory, characterized in that: include: A first interlayer dielectric layer is formed by using a first wiring process, wherein a plurality of first wirings extending along a first direction and a plurality of first contacts located on each of the first wirings are formed in the first interlayer dielectric layer, wherein the first wirings are bit lines or word lines; forming a stacked layer on the first interlayer dielectric layer and the first contact, the stacked layer comprising a bottom electrode layer and a sacrificial layer stacked above the bottom electrode layer; Performing corresponding photolithography and etching on the stacked layers until the bottom electrode layer is patterned to form a plurality of stacked bodies spaced apart from each other; forming a gap-filling layer in the gaps between adjacent stacked bodies, wherein the gap-filling layer exposes the top surface of the sacrificial layer; Removing the sacrificial layer to form an opening, and further forming a dielectric sidewall on the sidewall of the opening; Depositing a phase change memory layer on the surface of the opening, the dielectric sidewall and the gap filling layer, thereby forming a plurality of phase change memory units spaced apart from each other, each of the phase change memory units having a bottom electrode layer and a phase change memory layer stacked in sequence, the bottom electrode layer in the phase change memory unit being aligned with and electrically contacting the corresponding first contact, and the structure of the combination of the dielectric sidewall and the phase change memory layer in the phase change memory unit being aligned with the bottom electrode layer; A plurality of second wirings extending along a second direction intersecting the first direction are formed, the second wirings are formed above the phase change memory unit and the gap filling layer, and each of the second wirings is electrically connected to the corresponding phase change memory unit through a corresponding second contact or a top electrode line extending along the second direction, wherein the first wiring is a bit line and the second wiring is a word line, or the first wiring is a word line and the second wiring is a bit line.

2. The manufacturing method according to claim 1, characterized in that: The steps of forming a first interlayer dielectric layer, a first wiring and a first contact by using a first wiring process include: Forming a first dielectric layer on a substrate, and performing photolithography and etching on the first dielectric layer to form a plurality of first grooves extending along a first direction; forming a first wiring filled in each first trench; Covering the first dielectric layer and the first wiring with a second dielectric layer, and performing photolithography and etching on the second dielectric layer to form a plurality of first contact holes on each of the first wirings, the first dielectric layer and the second dielectric layer forming the first interlayer dielectric layer; A first contact is formed to fill each first contact hole.

3. The manufacturing method according to claim 1, characterized in that: Performing corresponding photolithography and etching on the stacked layer along the first direction until the bottom electrode layer is patterned to form a plurality of stacked bodies that are spaced apart from each other and extend along the first direction; After depositing a phase change memory layer on the opening, the dielectric sidewalls and the surface of the gap filling layer, the manufacturing method further includes: Performing corresponding photolithography and etching on the phase change memory layer and the remaining stacked body along a second direction intersecting the first direction until the bottom electrode layer is patterned again, so as to form a plurality of mutually spaced phase change memory cells by double pattern exposure technology, wherein the bottom electrode layer of each phase change memory cell is aligned with and electrically contacts the corresponding first contact; forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer fills the gaps between adjacent phase change memory cells and buries the top surface of the phase change memory layer of each phase change memory cell therein; A second wiring process is used to form the required second contacts in the second interlayer dielectric layer, and a plurality of second wirings extending along the second direction are formed on the second interlayer dielectric layer, each of the second contacts is aligned with and contacts the phase change memory layer of the corresponding phase change memory unit, and each of the second wirings is electrically connected to the corresponding phase change memory unit through the corresponding second contact.

4. The manufacturing method according to claim 3, characterized in that: After depositing the phase change memory layer on the surface of the opening, the dielectric sidewalls and the gap filling layer, and before or after performing corresponding photolithography and etching on the phase change memory layer and the remaining stack along the second direction to form a plurality of mutually spaced phase change memory units, the top surface of the phase change memory layer is flattened until the top surface of the gap filling layer is exposed.

5. The manufacturing method according to claim 1, characterized in that: Performing corresponding photolithography and etching on the stacked layer along the first direction until the bottom electrode layer is patterned to form a plurality of stacked bodies that are spaced apart from each other and extend along the first direction; After depositing a phase change memory layer on the opening, the dielectric sidewalls and the surface of the gap filling layer, the manufacturing method further includes: Planarizing the top surface of the phase-change memory layer until the top surface of the gap-filling layer is exposed; Depositing a top electrode layer and a second wiring layer sequentially on the phase change memory layer and the gap filling layer; The second wiring layer, the top electrode layer, the phase change memory layer and the remaining stack are subjected to corresponding photolithography and etching along the second direction until the bottom electrode layer is patterned again, so as to form a plurality of mutually spaced phase change memory units and a plurality of top electrode lines and second wirings extending along the second direction through a double pattern exposure technique, wherein the bottom electrode layer of each phase change memory unit is aligned with and electrically contacted with the corresponding first contact, and each second wiring is electrically connected to a plurality of the phase change memory units through the top electrode line aligned thereunder.

6. The manufacturing method according to claim 1, characterized in that: The step of performing corresponding photolithography and etching on the stacked layer until the bottom electrode layer is patterned to form a plurality of stacked bodies spaced apart from each other comprises: Performing corresponding photolithography and etching on the sacrificial layer by using a single exposure technique or a multiple pattern exposure technique to form a pattern for defining each phase change memory unit in the sacrificial layer; Using the sacrificial layer as a mask, the bottom electrode layer is etched to form a stack corresponding to each of the phase change memory cells, with gaps between adjacent stacks. The bottom electrode layer in each of the stacks is aligned with and electrically contacted with the corresponding first contact to serve as the bottom electrode of the phase change memory cell to be formed.

7. The manufacturing method according to claim 6, characterized in that: After depositing a phase change memory layer on the opening, the dielectric sidewalls and the surface of the gap filling layer, the manufacturing method further includes: Planarizing the top surface of the phase-change memory layer until the top surface of the gap-filling layer is exposed to form a plurality of phase-change memory units spaced apart from each other; A second interlayer dielectric layer is formed on the phase change memory layer and the gap filling layer by using a second wiring process, and a required second contact is formed in the second interlayer dielectric layer, and a plurality of second wirings extending along the second direction are formed on the second interlayer dielectric layer, each of the second contacts is aligned with and contacts the phase change memory layer of the corresponding phase change memory unit, and each of the second wirings is electrically connected to the corresponding phase change memory unit through the corresponding second contact.

8. The manufacturing method according to any one of claims 1 to 7, characterized in that: Before forming a gap filling layer in the gap between adjacent stacked bodies, an interface protection layer is first formed on the sidewalls of the stacked bodies.

9. The manufacturing method according to any one of claims 1 to 7, characterized in that: The first interlayer dielectric layer and the first wiring are formed on a substrate, the substrate has a storage area and a peripheral area located outside the storage area, the first wiring extends from the storage area to the peripheral area, and the manufacturing method further includes: while performing the first wiring process in the storage area, a corresponding electrical connection structure is also formed in the peripheral area.

10. A three-dimensional phase change memory, characterized in that: include: A first interlayer dielectric layer, in which a plurality of first wirings extending along a first direction and a plurality of first contacts located on each of the first wirings are formed; A plurality of phase change memory cells spaced apart from each other are formed on the first interlayer dielectric layer, and each of the phase change memory cells comprises a bottom electrode layer and a phase change memory layer stacked in sequence, the bottom electrode layer is aligned with and electrically contacted with the corresponding first contact, a dielectric sidewall is formed on the sidewall of the phase change memory layer, and a structure composed of the dielectric sidewall and the phase change memory layer is aligned with the bottom electrode layer; A gap filling layer, filling the gap between adjacent phase change memory cells; a plurality of second wirings extending along a second direction intersecting the first direction, the second wirings being formed above the phase-change memory unit and the gap-filling layer, and each of the second wirings being electrically connected to a corresponding phase-change memory unit through a corresponding second contact or a top electrode line extending along the second direction; The first wiring is a bit line and the second wiring is a word line, or the first wiring is a word line and the second wiring is a bit line.

11. The three-dimensional phase change memory according to claim 10, characterized in that: The three-dimensional phase change memory also includes a substrate, the first interlayer dielectric layer and the first wiring are formed on the substrate, the substrate has a storage area and a peripheral area located outside the storage area, and an electrical connection structure formed together with the first wiring and the first contact is formed in the peripheral area.

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