Capacity acquisition method, device, electronic device and readable storage medium

Abstract

The present application discloses a capacity acquisition method, which is applied to an electronic device, wherein the electronic device includes a processor and a memory, wherein the processor and the memory are connected, and the method includes: obtaining the data to be processed by the processor; determining the capacity requirement of the processor based on the data to be processed; and determining the storage space of the memory based on the capacity requirement, wherein the storage space is used to store the data to be processed. Since the capacity requirement of the processor when processing the data to be processed is variable, if a memory with a smaller storage space is set for the processor, it will not be able to meet the capacity requirement of the processor, affecting the processor performance; if a memory with a larger storage space is set for the processor, the power consumption of the electronic device will increase, reducing the energy consumption ratio. The present application determines the storage space size based on the capacity requirement of the data to be processed, which can not only meet the capacity requirement of the processor, but also avoid wasting storage space and reduce power consumption.

Description

Technical Field

[0001] The present application relates to the field of bandwidth calculation technology, and more specifically, to a capacity acquisition method, device, electronic device, computer-readable medium, and product. Background Art

[0002] With the advancement of electronic information technology, people are using an increasing number of electronic devices. The processors in these devices often have varying capacity requirements when processing tasks. However, the current ability to adapt to these varying processor capacity requirements is insufficient, resulting in low processor efficiency. Summary of the Invention

[0003] The present application proposes a capacity acquisition method, device, electronic device, computer-readable medium, and product.

[0004] In a first aspect, an embodiment of the present application provides a capacity acquisition method, which is applied to an electronic device, wherein the electronic device includes a processor and a memory, and the processor and the memory are connected. The method includes: obtaining data to be processed by the processor; determining the capacity requirement of the processor based on the data to be processed; and determining the storage space of the memory based on the capacity requirement, wherein the storage space is used to store the data to be processed.

[0005] In a second aspect, embodiments of the present application further provide a capacity acquisition device, applied to an electronic device, the electronic device including a processor and a memory, the processor and the memory being connected, the device comprising: an acquisition unit, a first determination unit, and a second determination unit. The acquisition unit is configured to acquire data to be processed by the processor; the first determination unit is configured to determine the capacity requirement of the processor based on the data to be processed; and the second determination unit is configured to determine the storage space of the memory based on the capacity requirement.

[0006] In a third aspect, an embodiment of the present application further provides an electronic device comprising: one or more processors; a memory; the one or more processors are used to execute the above method; the one or more processors are neural network processors, and the memory comprises a double rate synchronous dynamic random access memory and a static random access memory; the static random access memory is connected to the neural network processor and the double rate synchronous dynamic random access memory, respectively; the static random access memory is used to store data to be processed; the double rate synchronous dynamic random access memory is used to provide the data to be processed.

[0007] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0008] In a fifth aspect, an embodiment of the present application further provides a computer program product, comprising a computer program / instruction, which implements the above method when executed by a processor.

[0009] The capacity acquisition method, device, electronic device, computer-readable medium and product provided by the present application first obtain the data to be processed by the processor; then, based on the data to be processed, the capacity requirement of the processor is determined; and then, based on the capacity requirement, the storage space of the memory is determined. Since the capacity requirement of the processor when processing the data to be processed is variable, if a memory with a smaller storage space is set for the processor, it will not be able to meet the capacity requirement of the processor, affecting the processor performance; if a memory with a larger storage space is set for the processor, the power consumption of the electronic device will increase and the energy consumption ratio will be reduced. By determining the storage space size based on the capacity requirement of the data to be processed, the present application can meet the capacity requirement of the processor without wasting storage space, thereby reducing the overall power consumption of the electronic device.

[0010] Other features and advantages of the embodiments of the present application will be described in the following description and, in part, will become apparent from the description or be understood by practicing the embodiments of the present application. The objectives and other advantages of the embodiments of the present application can be achieved and obtained through the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A schematic diagram of bandwidth requirements for reading data is shown;

[0013] Figure 2 A schematic diagram of bandwidth requirements for writing data is shown;

[0014] Figure 3 A schematic diagram of meeting processor capacity requirements is shown;

[0015] Figure 4 Another schematic diagram for meeting processor capacity requirements is shown;

[0016] Figure 5 Another schematic diagram of meeting processor capacity requirements is shown;

[0017] Figure 6A diagram showing a scenario of applying the capacity acquisition method provided in an embodiment of the present application is shown;

[0018] Figure 7 A flow chart of a method for acquiring capacity provided by an embodiment of the present application is shown;

[0019] Figure 8 A flow chart of a method for acquiring capacity provided in another embodiment of the present application is shown;

[0020] Figure 9 Shown Figure 8 An implementation diagram of step S830;

[0021] Figure 10 A schematic diagram of a first bandwidth provided by an embodiment of the present application is shown;

[0022] Figure 11 A schematic diagram showing another first bandwidth provided by an embodiment of the present application is shown;

[0023] Figure 12 A flow chart of a capacity acquisition method provided by another embodiment of the present application is shown;

[0024] Figure 13 Show Figure 12 An implementation diagram of step S1230;

[0025] Figure 14 A schematic diagram showing an average bandwidth provided by an embodiment of the present application is shown;

[0026] Figure 15 A flow chart of a capacity acquisition method provided in another embodiment of the present application is shown;

[0027] Figure 16 A schematic diagram of a third bandwidth provided by an embodiment of the present application is shown;

[0028] Figure 17 Shown Figure 15 An implementation diagram of step S1550;

[0029] Figure 18 A unit block diagram of a capacity acquisition device provided in an embodiment of the present application is shown;

[0030] Figure 19 A schematic diagram of an electronic device provided in an embodiment of the present application is shown;

[0031] Figure 20 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown;

[0032] Figure 21The structural block diagram of the computer program product provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0034] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0035] With the rapid development of information technology and semiconductor technology, processors are required to process ever-increasing amounts of data. The data bandwidth required by processors fluctuates depending on the tasks they handle. Therefore, it's crucial to rationally allocate memory space to ensure the bandwidth required by processors and maintain processor efficiency.

[0036] See also Figure 1 , Figure 1 A schematic diagram showing the bandwidth requirements for reading data when the processor is processing a task. Figure 1 The horizontal axis is time, the vertical axis is bandwidth, and the curve is the read bandwidth of the processor when processing the task to be processed. It can be seen that the processor's read bandwidth requirement is larger at the beginning of the task processing and smaller in the later stages. Figure 2 , Figure 2 A schematic diagram showing the write data bandwidth requirement when the processor processes a task. Figure 2 The horizontal axis is time, the vertical axis is bandwidth, and the curve is the write bandwidth of the processor when processing the pending task. It can be seen that the write bandwidth of the processor is small at the beginning of processing the task, and is larger in the later stages.

[0037] To meet the data bandwidth requirements of the processor, see Figure 3By using a larger capacity Double Data Rate SDRAM (DDR), the processor can communicate directly with the DDR, thereby enabling the processor to achieve faster data read and write operations. Figure 3 and Figure 4 , Figure 4 exist Figure 3 A smaller static random access memory (SRAM) is added to the processor and the double-speed synchronous dynamic random access memory (DDR), respectively. The SRAM is located between the processor and the double-speed synchronous dynamic random access memory (DDR), which is different from the Figure 3 In the embodiment shown in FIG, the processor communicates directly with the static random access memory SRAM. The static random access memory SRAM can read the data of the double data rate synchronous dynamic random access memory DDR into the static random access memory SRAM in advance, or store the data generated by the processor in the static random access memory SRAM, and then transfer it to the double data rate synchronous dynamic random access memory DDR when the static random access memory SRAM capacity is insufficient. Please refer to Figure 3 and Figure 5 , Figure 5 exist Figure 3 On the basis of the MCU, a larger static random access memory (SRAM) and a digital signal processing (DSP) are added. The static random access memory SRAM is connected to the processor, the digital signal processing chip and the double data rate synchronous dynamic random access memory DDR. Figure 4 In the embodiment shown in the figure, the capacity of the static random access memory SRAM is relatively large, and the processor and the digital signal processing chip DSP share the static random access memory SRAM. Specifically, the digital signal processor DSP can generate data and send it to the processor via the static random access memory SRAM. After the processor completes the processing, the digital signal processor DSP then post-processes the data.

[0038] However, the inventors found in their research that due to the large data delay between the DDR and the processor and the high power consumption, when only the DDR is used for communication, the performance of the processor will be affected. Figure 3In one embodiment shown, all data transmissions are based on double-data-rate synchronous dynamic random access memory (DDR). However, the access rate of the double-data-rate synchronous dynamic random access memory (DDR) is relatively low, which may cause a loss in processor performance. Figure 4 In one embodiment shown, since the capacity of the static random access memory (SRAM) is small and the bandwidth required by the processor fluctuates with the task, when the processor is in the peak read bandwidth period, the capacity of the static random access memory (SRAM) is insufficient, and the processor needs to wait for data to be read from the double data rate synchronous dynamic random access memory (DDR) to the static random access memory (SRAM); during the peak write bandwidth period, it is necessary to wait until the data is written from the static random access memory (SRAM) to the double data rate synchronous dynamic random access memory (DDR), resulting in reduced processor performance. Figure 5 In one embodiment shown, the use of a larger capacity data slave static random access memory SRAM can meet the data bandwidth requirements of the processor, but the use of a larger capacity data slave static random access memory SRAM will increase the power consumption of the device and reduce the energy efficiency of the system.

[0039] Therefore, in order to overcome the above-mentioned defects, the embodiments of the present application provide a capacity acquisition method, device, electronic device, computer-readable medium and product, which first obtains the data to be processed by the processor; then, based on the data to be processed, determines the capacity requirement of the processor; and then determines the storage space of the memory according to the capacity requirement. Since the capacity requirement of the processor when processing the data to be processed is variable, if a memory with a smaller storage space is set for the processor, it will not be able to meet the capacity requirement of the processor, affecting the performance of the processor; if a memory with a larger storage space is set for the processor, the power consumption of the electronic device will increase and the energy consumption ratio will be reduced. By determining the storage space size based on the capacity requirement of the data to be processed, the present application can meet the capacity requirement of the processor without wasting storage space, thereby reducing the overall power consumption of the electronic device.

[0040] See also Figure 6 , Figure 6 The present invention illustrates an application scenario of the capacity acquisition method provided in an embodiment of the present invention. The capacity acquisition method can be applied to an electronic device 600, which includes a processor 610, a memory 620, and a capacity acquisition module 630. The capacity acquisition module 630 is connected to the processor 610 and the memory 620, respectively. The processor 610 is connected to the memory 620.

[0041] For some embodiments, the processor 610 can process the pending task by operations such as reading or writing data, wherein the pending task can be issued by the electronic device 600, or issued by an operating system installed on the electronic device 600, or issued by an application installed on the operating system. For different pending tasks, the processor 610 requires different data bandwidths, wherein the data bandwidth can be provided by the memory 620, that is, the processor 610 can perform operations such as reading or writing data through the memory 620. Specifically, the processor can be a computer CPU core, a mobile phone CPU core, a field programmable gate array (FPGA) circuit, a graphics processor core, a neural network processor (NPU), an optical processor, a quantum processor, etc. For one embodiment provided in the present application, the processor is a neural network processor NPU.

[0042] The memory 620 is a storage component made of semiconductor materials. The access rate of the memory 620 is generally greater than that of the external storage device, but the capacity is generally smaller than that of the external storage device, wherein the external storage device can be a mechanical hard disk, a solid-state drive, a USB flash drive or a flash memory card, etc. In some embodiments, during operation, the memory 620 can transfer relevant data from the external storage device to the processor 610, and the processor communicates directly with the memory 620, thereby reducing the waiting time of the processor 610 due to the low access rate of the external memory and improving the efficiency of the processor 610 in processing pending tasks. In one embodiment provided in the present application, the memory 620 may include static random access memory (SRAM) and double data rate synchronous dynamic random access memory (DDR).

[0043] The capacity acquisition module 630 is used to allocate storage space to the memory 620, and the storage space meets the capacity requirements. For some embodiments, the capacity acquisition module 630 can also be used to transfer data between storage elements with different storage speeds in the memory 620. For example, if the memory 620 includes static random access memory (SRAM) and double-speed synchronous dynamic random access memory (DDR), since the access rate of the static random access memory (SRAM) is greater than the access rate of the double-speed synchronous dynamic random access memory (DDR), the capacity acquisition module 630 can be connected to the static random access memory (SRAM) and the double-speed synchronous dynamic random access memory (DDR) respectively to realize data transmission between the static random access memory (SRAM) and the double-speed synchronous dynamic random access memory (DDR). For some embodiments, the capacity acquisition module 630 can be direct memory access (DMA).

[0044] See also Figure 7 , Figure 7 A capacity acquisition method provided in an embodiment of the present application is shown. This method can be applied to the electronic device 600 in the aforementioned embodiment. The electronic device 600 includes a processor 610, a memory 620, and a capacity acquisition module 630. The capacity acquisition module 630 is connected to the processor 610 and the memory 620, respectively. The processor 610 is connected to the memory 620. Specifically, the method includes steps S710 to S730.

[0045] Step S710: Obtain data to be processed by the processor.

[0046] For some embodiments, the processor may be a neural network processor NPU, and the data to be processed may include information about the object to be processed and a processing model. The information about the object to be processed may include the type of the object to be processed, the size of the object to be processed, the format of the object to be processed, and other information about the object to be processed. For example, if the data to be processed is an image file, the type of the object to be processed may be obtained as an image, the size of the object to be processed is 2MB, the format of the object to be processed is Portable Network Graphics (PNG), and other information about the object to be processed may include that the resolution of the object is 1920x1080. The processing model may be reasonably selected based on the type of object that the neural network processor NPU needs to process. For example, if the object to be processed is an image, an image processing model may be selected; if the object to be processed is music, a music processing model may be selected; and if the object to be processed is a video, a video processing model may be selected. MB stands for megabytes.

[0047] It should be noted that the processing model can be reasonably selected according to the type of processing object, and is not limited in this application.

[0048] Step S720: Determine the capacity requirement of the processor based on the data to be processed.

[0049] For some embodiments, since the capacity requirements of the processor are different when processing different pending tasks, it is necessary to obtain the capacity requirements of the processor through the pending data. For example, if there are two pending tasks, namely pending task A and pending task B, the pending object information corresponding to pending task A includes: the type of the pending object is image, the size of the pending object is 2MB, the format of the pending object is portable network graphic PNG, and other information of the pending object may include that the resolution of the object is 1920x1080; the pending object information corresponding to pending task B includes: the type of the pending object is image, the size of the pending object is 5MB, the format of the pending object is portable network graphic PNG, and other information of the pending object may include that the resolution of the object is 3840x2160. It is easy to know that the capacity requirements required by the processor to process pending tasks A and B are different. Furthermore, the capacity requirement for processing pending task A should be less than the capacity requirement for processing pending task B.

[0050] Furthermore, in some implementations, the time the processor spends processing pending tasks can be divided into multiple time segments, and the capacity requirement corresponding to each time segment is then calculated. The highest capacity requirement among all time segments is then calculated and used as the processor's capacity requirement. A detailed description of this method can be found in the subsequent examples.

[0051] Step S730: Based on the capacity requirement, determine the storage space of the memory, where the storage space is used to store the data to be processed.

[0052] For some implementation methods, the capacity requirement can be sufficient to store the data to be processed, that is, the capacity requirement can be used as storage space of the memory to store the data to be processed.

[0053] Furthermore, for some embodiments, the capacity requirement may include read capacity, that is, the capacity required for the processor to read data when processing the task to be processed. In this case, the read capacity can be used as the storage space of the memory to store the data to be processed. For other embodiments, the capacity requirement may also include write capacity, that is, the capacity required for the processor to write data when processing the task to be processed. In this case, the write capacity can be used as the storage space of the memory to store the data to be processed. For some other embodiments, the capacity requirement may also include read capacity and write capacity, that is, the capacity required for the processor to read data when processing the task to be processed and the capacity required to write data. In this case, the sum of the values ​​of the read capacity and the write capacity can be used as the storage space of the memory to store the data to be processed.

[0054] For example, in some implementations, if the read capacity is A and the write capacity is B, and if the capacity requirement is represented by C, the capacity requirement can be represented by C=A+B, and the capacity requirement is used as the storage space of the memory.

[0055] For other embodiments, the capacity requirement can be formed by adding the numerical sum of the read capacity and the write capacity, plus a smaller capacity, so that even if a calculation error occurs, the capacity requirement still leaves a certain margin for data communication with the processor. For example, if the read capacity is A and the write capacity is B, if C represents the capacity requirement and E represents the smaller capacity, then the capacity requirement can be expressed as C=A+B+E, and the capacity requirement is used as the storage space of the memory. Furthermore, the smaller capacity can be a fixed value, such as E=1MB; the smaller capacity can also be a certain ratio of the arithmetic sum of the read capacity and the write capacity, such as 1%, that is, E=(A+B) / 100.

[0056] In some embodiments, during some time periods, the memory space may be larger than the processor's capacity requirements. In this case, the excess memory space may be put into a low-power mode, thereby reducing the overall power consumption of the electronic device and improving the energy efficiency of the electronic device.

[0057] For example, if the storage space of the memory is A and the capacity requirement of the processor is B, the storage space A = 10MB. When in a certain time segment, the capacity requirement of the processor B = 8MB. At this time, 8BM is less than 10MB, then the excess storage space can be obtained as AB = 10-8 = 2MB, that is, at this time, the 2MB storage space can be put into low power mode.

[0058] For other implementations, the excess storage space can be allocated to other tasks to achieve dynamic task allocation and improve the overall task processing capability of the electronic device. The method for determining and obtaining the excess storage space is similar to the above method and will not be repeated here.

[0059] The capacity acquisition method, device, electronic device, computer-readable medium and product provided by the present application first obtain the data to be processed by the processor; then, based on the data to be processed, the capacity requirement of the processor is determined; and then, based on the capacity requirement, the storage space of the memory is determined. Since the capacity requirement of the processor when processing the data to be processed is variable, if a memory with a smaller storage space is set for the processor, it will not be able to meet the capacity requirement of the processor, affecting the performance of the processor; if a memory with a larger storage space is set for the processor, the power consumption of the electronic device will increase and the energy consumption ratio will be reduced. By determining the storage space size based on the capacity requirement of the data to be processed, the present application can meet the capacity requirement of the processor without wasting storage space, thus saving power consumption.

[0060] See also Figure 8 , Figure 8 A capacity acquisition method provided in an embodiment of the present application is shown. This method can be applied to the electronic device 600 in the aforementioned embodiment. The electronic device 600 includes a processor 610, a memory 620, and a capacity acquisition module 630. The capacity acquisition module 630 is connected to the processor 610 and the memory 620, respectively. The processor 610 is connected to the memory 620. Specifically, the method includes steps S810 to S850.

[0061] Step S810: Acquire data to be processed by the processor.

[0062] Among them, S810 has been described in detail in the above embodiment and will not be repeated here.

[0063] Step S820: Based on the data to be processed, determine the average capacity, where the average capacity is used to represent the average value of the data processing amount corresponding to all time segments.

[0064] In some embodiments, there are multiple data items to be processed, each corresponding to a time segment. Based on the data items to be processed, an average capacity can be determined. The average capacity represents the average of the data processing volume corresponding to all time segments. The average capacity can be determined based on the average bandwidth and the time segment corresponding to the average bandwidth. For detailed methods, please refer to the subsequent embodiments.

[0065] Step S830: Based on each of the time segments and the to-be-processed data corresponding to the time segment, determine a first capacity corresponding to each of the time segments.

[0066] For some implementations, a first capacity can be determined. Specifically, a capacity can be determined by combining the data to be processed corresponding to each time segment and the time segment, and combining each capacity determined in this way to form the first capacity. Figure 9 , Figure 9 An implementation of step S830 is shown. Figure 9 Including step S831.

[0067] Step S831: Integrate the data to be processed in each of the time segments to obtain a second integration result, and use the second integration result as the first capacity corresponding to each of the time segments.

[0068] Further, for some implementations, if the current task is to read data, you can refer to Figure 1, at this time, the bandwidth requirement of the data to be processed is larger at the beginning of the processing task, and smaller in the later stages. At this time, a second integral result can be obtained based on the integral of the data to be processed in each of the time segments. For example, see Figure 10 , Figure 10 An implementation of step S831 is shown. Figure 10 This is a two-dimensional coordinate system built with time as the horizontal axis and bandwidth as the vertical axis. The curve represents the bandwidth required for the data to be processed at different time intervals. This curve can be represented by B(t). The data capacity required for the data to be processed can be calculated by taking the definite integral of the bandwidth required for the data to be processed over the corresponding time interval. Specifically, the data capacity can be obtained using the following formula:

[0069]

[0070] Among them, t m is the start time corresponding to the time segment, t n is the deadline corresponding to the time segment, t x and t x-1 is the time differential, t x The bandwidth required for the data to be processed corresponding to the time differential, N represents the bandwidth of the data to be processed at t m to t n The data capacity required in a time slice.

[0071] For further information, please refer to Figure 10 , Figure 10 There are five time segments, namely t0 to t1, t1 to t2, t2 to t3, t3 to t4, t4 and t5. Specifically, the data capacity corresponding to the time segment t0 to t1 of the data to be processed can be N1; the data capacity corresponding to the time segment t1 to t2 of the data to be processed can be N2; the data capacity corresponding to the time segment t2 to t3 of the data to be processed can be N3; the data capacity corresponding to the time segment t3 to t4 of the data to be processed can be N4; the data capacity corresponding to the time segment t4 to t5 of the data to be processed can be N5. Then we can get the data capacity corresponding to the time segment t4 to t5 of the data to be processed by the above definite integral formula.

[0072]

[0073] Furthermore, the acquisition method of N2, N3, N4 and N5 is similar to that of N1, and will not be repeated here. The data capacity corresponding to each acquired time segment is combined to obtain the first capacity, that is, the first capacity includes N1, N2, N3, N4 and N5.

[0074] Furthermore, for other implementations, if the current task is to write data, you can refer to Figure 2 , the capacity requirement of the data to be processed is smaller at the beginning of the processing task and larger in the later stages. At this time, a second integral result can be obtained based on the integral of the data to be processed in each of the time segments. For example, see Figure 11 , Figure 11 Another implementation of step S831 is shown. Figure 11 A two-dimensional coordinate system is established with time as the horizontal axis and bandwidth as the vertical axis. The curve represents the bandwidth required for the data to be processed at different time segments, which can be represented by B(t). Similarly, the data capacity required for the data to be processed can be calculated by taking the definite integral of the bandwidth required for the data to be processed over the corresponding time segments. For details, please refer to the integral formula for calculating the data capacity N in the above embodiment.

[0075] For further information, please refer to Figure 11 , Figure 11 There are five time segments, namely t0 to t1, t1 to t2, t2 to t3, t3 to t4, t4 and t5. Specifically, the data capacity corresponding to the time segment t0 to t1 of the data to be processed can be N1; the data capacity corresponding to the time segment t1 to t2 of the data to be processed can be N2; the data capacity corresponding to the time segment t2 to t3 of the data to be processed can be N3; the data capacity corresponding to the time segment t3 to t4 of the data to be processed can be N4; the data capacity corresponding to the time segment t4 to t5 of the data to be processed can be N5. Then we can get the data capacity corresponding to the time segment t4 to t5 of the data to be processed by the above definite integral formula.

[0076]

[0077] Furthermore, the acquisition method of N2, N3, N4 and N5 is similar to that of N1, and will not be repeated here. The data capacity corresponding to each acquired time segment is combined to obtain the first capacity, that is, the first capacity includes N1, N2, N3, N4 and N5.

[0078] Step S840: Determine the capacity requirement based on the first capacity and the average capacity.

[0079] In some implementations, the arithmetic difference between each first capacity and each corresponding average capacity can be calculated, and then the arithmetic sum of each second capacity and the second capacity before the time segment corresponding to the second capacity can be calculated to obtain the third capacity corresponding to the time segment; finally, the maximum value of the third capacities is used as the capacity requirement. In this way, the capacity requirement of the processor to process the pending tasks can be met while the storage space of the memory can be controlled as much as possible without wasting storage space, thus controlling the overall power consumption of the electronic device and improving the processing capability of the processor. For the specific method of determining the capacity requirement, please refer to the subsequent implementation methods.

[0080] Step S850: Based on the capacity requirement, determine the storage space of the memory, where the storage space is used to store the data to be processed.

[0081] Among them, step S850 has been described in detail in the above embodiment and will not be repeated here.

[0082] See also Figure 12 , Figure 12 A capacity acquisition method provided in an embodiment of the present application is shown. This method can be applied to the electronic device 600 in the aforementioned embodiment. The electronic device 600 includes a processor 610, a memory 620, and a capacity acquisition module 630. The capacity acquisition module 630 is connected to the processor 610 and the memory 620, respectively. The processor 610 is connected to the memory 620. Specifically, the method includes steps S1210 to S1260.

[0083] Step S1210: Obtain data to be processed by the processor.

[0084] Among them, step S1210 has been described in detail in the above embodiment and will not be repeated here.

[0085] Step S1220: determining an average bandwidth based on the data to be processed, where the average bandwidth is used to characterize the data processing amount per unit time of the processor within a specified time period consisting of all time segments.

[0086] In some embodiments, an average bandwidth may be determined based on the data to be processed, where the average bandwidth represents the amount of data processed per unit time by the processor within a specified time period consisting of all time segments. The specified time period may include multiple time segments, for example, five, and the time period consisting of the five time segments constitutes the specified time period.

[0087] Furthermore, in some embodiments, the specified time period may be the time it takes for the processor to process the data to be processed. The average bandwidth may be calculated by dividing the size of the object in the data to be processed by the specified time period. For example, if the size of the object in the data to be processed is 10 MB and the specified time period is 1 second, the average bandwidth may be 10 MB / 1 second = 10 MB / s, where s represents the time unit in seconds.

[0088] Step S1230: Based on the average bandwidth and each of the time segments, determine the average capacity corresponding to each of the time segments.

[0089] For some implementations, the average capacity corresponding to each time segment can be determined based on the average bandwidth and each time segment. Specifically, the average capacity corresponding to each time segment can be determined by calculating the definite integral of the average bandwidth corresponding to each time segment. The average capacity corresponding to each time segment can also be obtained by directly multiplying the average bandwidth and the corresponding time segment. Figure 13 , Figure 13 An implementation of step S1230 is shown. Figure 13 Including step S1231.

[0090] Step S1231: Integrate the average bandwidth in each of the time segments to obtain a first integration result, and use the first integration result as the average capacity corresponding to each of the time segments.

[0091] See also Figure 14 , Figure 14 It is a two-dimensional coordinate system based on time as the horizontal axis and bandwidth as the vertical axis. The horizontal line represents the average bandwidth, which can be represented by B(t). The average bandwidth corresponds to multiple time segments. Specifically, Figure 14 There are five time segments, namely t0 to t1, t1 to t2, t2 to t3, t3 to t4, and t4 and t5. The average capacity of the data to be processed in the time segment t0 to t1 can be M1; the average capacity of the data to be processed in the time segment t1 to t2 can be M2; the average capacity of the data to be processed in the time segment t2 to t3 can be M3; the average capacity of the data to be processed in the time segment t3 to t4 can be M4; and the average capacity of the data to be processed in the time segment t4 to t5 can be M5. The definite integral formula for calculating data capacity in the above embodiment can be used to obtain:

[0092]

[0093] Furthermore, the acquisition method of M2, M3, M4 and M5 is similar to that of M1, and will not be repeated here. Among them, the first integration result is M1, M2, M3, M4 and M5, and the first integration result is used as the average capacity corresponding to each time segment.

[0094] Step S1240: Based on each of the time segments and the to-be-processed data corresponding to the time segment, determine a first capacity corresponding to each of the time segments.

[0095] Step S1250: Determine the capacity requirement based on the first capacity and the average capacity.

[0096] Step S1260: Based on the capacity requirement, determine the storage space of the memory, where the storage space is used to store the data to be processed.

[0097] Among them, steps S1240 to S1260 have been described in detail in the above embodiments and will not be repeated here.

[0098] See also Figure 15 , Figure 15 A capacity acquisition method provided in an embodiment of the present application is shown. This method can be applied to the electronic device 600 in the aforementioned embodiment. The electronic device 600 includes a processor 610, a memory 620, and a capacity acquisition module 630. The capacity acquisition module 630 is connected to the processor 610 and the memory 620, respectively. The processor 610 is connected to the memory 620. Specifically, the method includes steps S1510 to S1560.

[0099] Step S1510: Obtain data to be processed by the processor.

[0100] Step S1520: Based on the data to be processed, determine the average capacity, where the average capacity is used to represent the average value of the data processing amount corresponding to all time segments.

[0101] Step S1530: Based on each of the time segments and the to-be-processed data corresponding to the time segment, determine a first capacity corresponding to each of the time segments.

[0102] Among them, steps S1510 to S1530 have been described in detail in the above embodiments and will not be repeated here.

[0103] Step S1540: Calculate the arithmetic difference between each of the first capacities and each of the corresponding average capacities to determine the second capacity, wherein the time segment corresponding to each of the first capacities is the same as the time segment corresponding to each of the average capacities.

[0104] For some embodiments, the arithmetic difference between the first capacity and the average capacity corresponding to each time segment obtained through the above steps can be calculated to obtain the second capacity. For example, if the average capacity corresponding to the time segment is M, the first capacity is N, and S represents the second capacity, then the second capacity can be expressed as S=NM. The second capacity can represent the amount by which the capacity requirement of the processor when processing the task to be processed in the time segment exceeds or is less than the average capacity. It is easy to understand that the time segment corresponding to each of the first capacities is the same as the time segment corresponding to each of the average capacities.

[0105] For example, see Figure 16 , Figure 16 An implementation of step S1540 is shown. Figure 16 The 2D coordinate system is established based on time as the horizontal axis and bandwidth as the vertical axis. The horizontal line represents the average bandwidth, and the curve represents the bandwidth required for the data to be processed corresponding to different time segments. The graph formed by the horizontal line and the curve is the second capacity. The second capacity corresponds to different time segments and can be calculated from the first capacity corresponding to each time segment and the average capacity. Specifically, Figure 16 There are five time segments: t0 to t1, t1 to t2, t2 to t3, t3 to t4, and t4 to t5. The first capacity corresponding to the time segment t0 to t1 can be N1, the average capacity M1, and the second capacity S1; the first capacity corresponding to the time segment t1 to t2 can be N2, the average capacity M2, and the second capacity S2; the first capacity corresponding to the time segment t2 to t3 can be N3, the average capacity M3, and the second capacity S3; the first capacity corresponding to the time segment t3 to t4 can be N4, the average capacity M4, and the second capacity S4; and the first capacity corresponding to the time segment t4 to t5 can be N5, the average capacity M5, and the second capacity S5. In this case, we can conclude that S1 = N1 - M1. The methods for calculating S2, S3, S4, and S5 are similar to those for S1. The calculated S1, S2, S3, S4, and S5 are the second capacities.

[0106] It should be noted that the second capacity corresponding to each time segment can be a positive number, that is, the first capacity corresponding to the time segment is greater than the average capacity; the second capacity corresponding to each time segment can be a negative number, that is, the first capacity corresponding to the time segment is less than the average capacity; the second capacity corresponding to each time segment can be 0, that is, the first capacity corresponding to the time segment is equal to the average capacity.

[0107] Step S1550: Determine the capacity requirement based on each of the second capacities.

[0108] For some implementations, the capacity requirement can be determined based on the second capacity obtained in the above steps. Figure 17 , Figure 17 An implementation of step S1550 is shown. Figure 17 Includes step S1551 and step S1552.

[0109] Step 1551: Calculate the arithmetic sum of each second capacity and the second capacity before the time segment corresponding to the second capacity, and use the sum as the third capacity corresponding to the time segment.

[0110] Step 1552: Use the maximum value of the third capacities as the capacity requirement.

[0111] In some implementations, the relationship between the processor's capacity requirement and average bandwidth can be determined using the second capacities corresponding to different time segments. Specifically, when the second capacity corresponding to the time segment is a negative number, it indicates that the capacity requirement is less than the average bandwidth; when the second capacity corresponding to the time segment is a positive number, it indicates that the capacity requirement is greater than the average bandwidth; and when the second capacity corresponding to the time segment is 0, it indicates that the capacity requirement is equal to the average bandwidth.

[0112] Furthermore, in some embodiments, for any time segment, the arithmetic sum of the second capacities corresponding to the time segment and the time segment before the time segment can be calculated, and the value of the arithmetic sum is the third capacity, which can represent the capacity requirement of the processor in the time segment. Specifically, if the second capacity corresponding to the time segment t0 to t1 is S1, and the second capacity corresponding to the time segment t0 to t1 is S2, then the capacity requirement of the processor in the time segment t1 to t2 can be represented by S1, and the capacity requirement of the processor in the time segment t1 to t2 can be represented by S1+S2, that is, the third capacity corresponding to the time segment t0 to t1 is S1, and the third capacity corresponding to the time segment t0 to t1 is S1+S2.

[0113] Furthermore, for some implementations, the maximum value of the third capacity corresponding to each time segment can be used as the capacity requirement. This satisfies the maximum capacity requirement of the processor when processing the task to be processed without causing capacity waste, thereby improving the work efficiency of the processor while minimizing the overall power consumption of the electronic device. For details, please continue to refer to Figure 16 ,by Figure 16 As an example, we can explain it in detail. Figure 16The second capacity corresponding to the time segment from t0 to t1 is S1; the second capacity corresponding to the time segment from t1 to t2 is S2; the second capacity corresponding to the time segment from t2 to t3 is S3; the second capacity corresponding to the time segment from t3 to t4 is S4; and the second capacity corresponding to the time segment from t4 to t5 is S5. Then the third capacity corresponding to each time segment can be obtained, specifically, the third capacity corresponding to the time segment from t0 to t1 is S1; the third capacity corresponding to the time segment from t1 to t2 is S1+S2; the third capacity corresponding to the time segment from t2 to t3 is S1+S2+S3; the third capacity corresponding to the time segment from t3 to t4 is S1+S2+S3+S4; and the third capacity corresponding to the time segment from t4 to t5 is S1+S2+S3+S4+S5. At this time, the maximum value of the third capacities can be obtained as the capacity demand, that is: max S1…S5 (S1, S1+S2, S1+S2+S3, …), where max is the function for finding the maximum value.

[0114] For some embodiments, when the pending task being processed by the processor requires reading, the capacity requirement may be the read capacity. In this case, the read capacity may be WS. The method for calculating the read capacity is similar to the method for calculating the capacity requirement described above and will not be described in detail here. That is, if there are 5 time segments, WS = max S1…S5 (S1,S1+S2,S1+S2+S3,…).

[0115] For other embodiments, when the pending task being processed by the processor requires writing, the capacity requirement may be the write capacity. In this case, the read capacity may be RS. The method for obtaining the read capacity is similar to the method for obtaining the capacity requirement described above, and will not be described in detail here. That is, if there are 5 time segments, RS = max S1…S5 (S1,S1+S2,S1+S2+S3,…).

[0116] Furthermore, the arithmetic sum of the read capacity WS and the write capacity RS may be calculated as the capacity requirement to ensure that the requirement of the processor to process the task to be processed is met.

[0117] For other implementation methods, the third capacity corresponding to each time segment can also be used as the capacity demand, and the capacity demand can be adjusted for each time segment, so that a larger capacity demand can be provided only when the third capacity is the largest, and the processor can be satisfied with processing tasks with minimal capacity resource improvement.

[0118] Step S1560: Based on the capacity requirement, determine the storage space of the memory, where the storage space is used to store the data to be processed.

[0119] Among them, step S1560 has been described in detail in the above embodiment and will not be repeated here.

[0120] The capacity acquisition method, device, electronic device, computer-readable medium and product provided by the present application first obtain the data to be processed by the processor; then, based on the data to be processed, determine the average bandwidth and the first capacity, determine the second capacity based on the average bandwidth and the first capacity, and then determine the third capacity from the second capacity, and take the maximum value of the third capacity as the capacity requirement; then, determine the storage space of the memory based on the capacity requirement. Since the capacity requirement of the processor when processing the data to be processed is variable, if a memory with a smaller storage space is set for the processor, it will not be able to meet the capacity requirement of the processor, affecting the performance of the processor; if a memory with a larger storage space is set for the processor, the power consumption of the electronic device will increase, reducing the energy efficiency ratio. The present application comprehensively determines the storage space size of the memory by obtaining the average bandwidth, the first capacity, the second capacity and the third capacity, so that the storage space can meet the capacity requirement of the processor without causing waste, saving power consumption and improving the overall energy efficiency ratio of the electronic device.

[0121] See also Figure 18 , which shows a structural block diagram of a capacity acquisition device 1800 provided in an embodiment of the present application, which is applied to an electronic device, the electronic device includes a processor and a memory, the processor and the memory are connected, and the device may include: an acquisition unit 1810, a first determination unit 1820 and a second determination unit 1830.

[0122] The acquisition unit 1810 is used to obtain the data to be processed by the processor.

[0123] The first determining unit 1820 is configured to determine the capacity requirement of the processor based on the data to be processed.

[0124] Furthermore, the first determination unit 1820 is also used to determine the average capacity based on the data to be processed, and the average capacity is used to characterize the average value of the data processing amount corresponding to all time segments; based on each of the time segments and the data to be processed corresponding to the time segment, determine the first capacity corresponding to each of the time segments; based on the first capacity and the average capacity, determine the capacity requirement.

[0125] Furthermore, the first determination unit 1820 is also used to determine the average bandwidth based on the data to be processed, and the average bandwidth is used to characterize the data processing volume per unit time of the processor within a specified time period composed of all time segments; based on the average bandwidth and each of the time segments, determine the average capacity corresponding to each of the time segments.

[0126] Furthermore, the first determining unit 1820 is further configured to obtain a first integration result by integrating the average bandwidth in each of the time segments, and the first integration result is used as the average capacity corresponding to each of the time segments.

[0127] Furthermore, the first determining unit 1820 is further configured to obtain a second integration result by integrating the data to be processed in each of the time segments, and the second integration result is used as the first capacity corresponding to each of the time segments.

[0128] Furthermore, the first determination unit 1820 is also used to calculate the arithmetic difference between each of the first capacities and each of the corresponding average capacities to determine the second capacity, wherein the time segment corresponding to each of the first capacities is the same as the time segment corresponding to each of the average capacities; and determine the capacity requirement based on each of the second capacities.

[0129] Furthermore, the first determining unit 1820 is further configured to calculate the arithmetic sum of each second capacity and the second capacity before the time segment corresponding to the second capacity as a third capacity corresponding to the time segment; and determine the capacity requirement based on the third capacity.

[0130] Furthermore, the first determining unit 1820 is further configured to use a maximum value of the third capacities as the capacity requirement.

[0131] The second determining unit 1830 is configured to determine the storage space of the memory based on the capacity requirement.

[0132] Furthermore, the second determining unit 1830 is further configured to use the sum of the read capacity and the write capacity as the storage space of the memory.

[0133] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0134] In several embodiments provided in this application, the coupling between units may be electrical, mechanical or other forms of coupling.

[0135] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0136] Please refer to Figure 19, which shows a block diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 1900 can be an electronic device capable of running applications, such as a smartphone, tablet computer, or server. The electronic device 1900 in the present application may include one or more of the following components: a processor 1910 and a memory 1920, wherein the one or more processors are used in the above-mentioned method.

[0137] Processor 1910 may include one or more processing cores and is a neural network processor (NPU). Processor 1910 utilizes various interfaces and circuits to connect various components within electronic device 1900. Processor 1910 executes instructions, programs, code sets, or instruction sets stored in memory 1920 and accesses data stored in memory 1920 to perform various functions of electronic device 1900 and process data.

[0138] Memory 1920 may include double data rate synchronous dynamic random access memory (DDR) and static random access memory (SRAM). Optionally, memory 1920 may also include external memory, which may be a mechanical hard disk, solid-state drive, USB flash drive, flash memory card, etc. Memory 1920 may be used to store instructions, programs, codes, code sets, or instruction sets. Memory 1920 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the various method embodiments described below, etc. The data storage area may also store data created by electronic device 1900 during use.

[0139] Please refer to Figure 20 , which shows a block diagram of a computer-readable storage medium provided in an embodiment of the present application. The computer-readable medium 2000 stores program code, which can be called by a processor to execute the method described in the above method embodiment.

[0140] The computer-readable storage medium 2000 can be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 2000 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 2000 has storage space for program code 2010 for executing any of the method steps in the above method. These program codes can be read from or written to one or more computer program products. The program code 2010 can be compressed, for example, in an appropriate form.

[0141] As an embodiment, the readable storage medium 2000 may include a double data rate synchronous dynamic random access memory (DDR) and a static random access memory (SRAM). Optionally, the readable storage medium may also include an external memory. Applications are stored in the external memory. When the processor 1910 needs to execute a pending task, the double data rate synchronous dynamic random access memory (DDR) may retrieve part of the application and the data corresponding to the application from the external memory. The static random access memory (SRAM) then retrieves the data most likely to be used by the processor 1910 through the double data rate synchronous dynamic random access memory (DDR) and directly provides it to the processor 1910 for processing. The data written by the processor 1910 is temporarily stored in the static random access memory (SRAM), and then the static random access memory (SRAM) transfers the data to the double data rate synchronous dynamic random access memory (DDR). Optionally, the double data rate synchronous dynamic random access memory (DDR) may also transfer the data to the external memory.

[0142] Please refer to Figure 21 , which shows a structural block diagram 2100 of a computer program product provided by an embodiment of the present application. The computer program product 2100 includes a computer program / instruction 2110, which implements the steps of the above method when executed by a processor.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A capacity acquisition method, characterized in that: Applied to an electronic device, the electronic device includes a processor and a memory, the processor and the memory are connected, and the method includes: Acquire data to be processed by the processor, where the data to be processed corresponds to a task to be processed, there are multiple data to be processed, and each data to be processed corresponds to a time segment; Determine an average capacity based on the data to be processed, where the average capacity is used to represent an average value of data processing amounts corresponding to all time segments; Determine a first capacity corresponding to each time segment based on each time segment and the to-be-processed data corresponding to the time segment; Calculating the arithmetic difference between each of the first capacities and each of the corresponding average capacities to determine a second capacity, wherein the time segment corresponding to each of the first capacities is the same as the time segment corresponding to each of the average capacities; Calculate the arithmetic sum of each second capacity and the second capacity before the time segment corresponding to the second capacity as the third capacity corresponding to the time segment; Taking the maximum value of the third capacities as the capacity demand; Based on the capacity requirement, a storage space of the memory is determined, where the storage space is used to store the data to be processed.

2. The method according to claim 1, characterized in that The determining the average capacity based on the data to be processed includes: Determine an average bandwidth based on the data to be processed, where the average bandwidth is used to characterize the amount of data processed per unit time by the processor within a specified time period consisting of all time segments; Based on the average bandwidth and each of the time segments, an average capacity corresponding to each of the time segments is determined.

3. The method according to claim 2, characterized in that The determining, based on the average bandwidth and each of the time segments, an average capacity corresponding to each of the time segments includes: The average bandwidth is integrated in each of the time segments to obtain a first integration result, and the first integration result is used as the average capacity corresponding to each of the time segments.

4. The method according to claim 1, wherein The determining, based on each of the time segments and the to-be-processed data corresponding to the time segment, a first capacity corresponding to each of the time segments includes: The data to be processed is integrated in each of the time segments to obtain a second integration result, and the second integration result is used as the first capacity corresponding to each of the time segments.

5. The method according to claim 1, wherein The capacity requirement includes a read capacity and a write capacity. Determining the storage space of the memory based on the capacity requirement includes: The sum of the read capacity and the write capacity is used as the storage space of the memory.

6. A capacity acquisition device, characterized in that: Applied to an electronic device, the electronic device includes a processor and a memory, the processor and the memory are connected, and the device includes: an acquiring unit, configured to acquire data to be processed by the processor, wherein the data to be processed corresponds to a task to be processed, and there are multiple data to be processed, each of which corresponds to a time segment; A first determining unit is configured to determine an average capacity based on the data to be processed, wherein the average capacity is used to represent the average value of the data processing amount corresponding to all time segments; determine a first capacity corresponding to each time segment based on each time segment and the data to be processed corresponding to the time segment; calculate an arithmetic difference between each first capacity and each corresponding average capacity to determine a second capacity, wherein the time segment corresponding to each first capacity is the same as the time segment corresponding to each average capacity; calculate an arithmetic sum between each second capacity and the second capacity before the time segment corresponding to the second capacity as a third capacity corresponding to the time segment; and determine a maximum value among the third capacities as the capacity requirement; The second determining unit is configured to determine a storage space of the memory based on the capacity requirement.

7. An electronic device, characterized in that: include: one or more processors; Memory; the one or more processors are configured to execute the method according to any one of claims 1 to 5; The one or more processors are neural network processors, and the memory includes a double data rate synchronous dynamic random access memory and a static random access memory; The static random access memory is connected to the neural network processor and the double rate synchronous dynamic random access memory respectively; The static random access memory is used to store data to be processed; The double rate synchronous dynamic random access memory is used to provide the data to be processed.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program code, which can be called by a processor to execute the method according to any one of claims 1 to 5.

9. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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