A heterogeneous multi-chip fan-out plastic packaging heat dissipation structure and preparation method

Abstract

The present invention relates to a heterogeneous multi-chip fan-out plastic package heat dissipation structure and a preparation method, wherein the heat dissipation structure is manufactured using a wafer-level plastic packaging process, and heat dissipation grooves of different sizes, depths, and densities are manufactured on a plastic package body, and metal is filled as a heat dissipation structure, so that the heat dissipation structure contacts the back of the chip to form a direct heat dissipation channel, reduce thermal resistance, and expand the heat dissipation area, which can effectively improve the heat dissipation efficiency and improve the chip packaging reliability. This method is different from the traditional heat conduction heat dissipation method of using a heat sink to mount on the back of the plastic package body. This structure adopts a direct contact heat dissipation method, which has higher heat dissipation efficiency; at the same time, it is also different from the contact heat dissipation method of thinning all chips in the plastic package body to the back of the chip leaking out, and then mounting a heat sink, and this method effectively avoids the risk of defects that may occur during the chip thinning process, and improves the packaging yield.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a heterogeneous multi-chip fan-out type plastic packaging heat dissipation structure and a preparation method thereof. Background Art

[0002] The new generation of high-density chip plastic packaging technology integrates chips of different materials, functions, sizes and thicknesses to achieve complete system functions in a tiny packaging structure. At the same time, the significant increase in assembly density will inevitably cause a sharp increase in the heat flux density of the micro-assembly system. Generally speaking, for every 10°C increase in the temperature of electronic products, the reliability may be reduced to half of the original; and when the temperature rises from 75°C to 125°C, the reliability becomes 20% of the original. Therefore, how to solve the heat dissipation problem caused by high-density components has become the primary challenge facing high-performance assembly systems. The traditional heat dissipation method is to mount a cold plate or heat sink on the back of the plastic package, but there is still a certain thickness of plastic package material in the middle, and the heat is dissipated by indirect heat conduction, which has low heat dissipation efficiency. Another improvement to the heat dissipation method for the plastic package is to thin all chips of different sizes and thicknesses to the same height, expose the back of the chip, and mount a heat sink on its back. Although the heat dissipation method is improved from conduction heat dissipation to contact heat dissipation, for chips of different thicknesses thinned to the same height (this height is determined by the chip with the smallest thickness in the system), the thinning process makes the stress of each chip in the plastic package more concentrated, resulting in a sharp increase in the risk of potential chip edge collapse, corner breakage or cracking, making it difficult to guarantee the chip packaging yield. Summary of the invention

[0003] To this end, the technical problem to be solved by the present invention is to overcome the problems of heterogeneous multi-chips in the prior art: the back patch of the plastic packaging material relies on heat conduction, resulting in low heat dissipation efficiency; and the method of mounting the heat sink after the chip is thinned as a whole results in low chip packaging yield, thereby providing a high-density heterogeneous multi-chip fan-out plastic packaging heat dissipation structure and preparation method.

[0004] In order to solve the above technical problems, a heterogeneous multi-chip fan-out plastic package heat dissipation structure of the present invention comprises:

[0005] After the heterogeneous multi-chip and the Dummy chip are bonded by thermal conductive adhesive, they are face-down mounted and encapsulated by plastic packaging material; heat dissipation grooves of different sizes, depths and densities are opened on the surface and inside of the Dummy chip through a series of processes on the back of the plastic packaging material, and metal materials are filled inside the heat dissipation grooves. The heat dissipation grooves are connected to the thermal conductive adhesive, and the thermal conductive adhesive is connected to the back of the heterogeneous multi-chip;

[0006] The rewiring and UBM layer is manufactured on the front side of the plastic encapsulation material, connected to the pad of the heterogeneous multi-chip, and has an electrical interconnection function, and is wrapped by polyimide;

[0007] Solder balls are manufactured on the surface of the rewiring and UBM layers.

[0008] Optionally, the heterogeneous multi-chip and the Dummy chip are bonded together by thermally conductive adhesive and then mounted on a temporary carrier according to coordinates. After being integrally encapsulated by a plastic encapsulation material, high-density integration of chips of different sizes and thicknesses can be achieved, and the front sides of all chips are on the same plane.

[0009] Optionally, the heat sink on the back of the plastic packaging material is made by reconstructing a wafer thinning process, a photolithography process and a dry etching process, so that heat sinks of different sizes, depths and densities can be cut on the surface and inside of the Dummy chip. The size and density of the heat sink are adjustable. The heat sink remains connected to the thermal conductive adhesive, and the thermal conductive adhesive is connected to the back of the real chip.

[0010] Optionally, the metal material filling in the heat dissipation groove on the back of the plastic packaging material is completed by a wafer-level sputtering process and a wafer-level electroplating process, and the metal material includes copper, aluminum and titanium-tungsten alloy.

[0011] Optionally, the rewiring and UBM layer are completed through a wafer-level rewiring process and maintain contact with the pad of the heterogeneous multi-chip, and the materials include polyimide and copper.

[0012] Optionally, the solder balls are completed by wafer-level ball planting or single-chip stencil ball planting process, and are kept in contact with the rewiring and UBM layers, and the materials include tin-lead, tin-silver and tin-silver-copper.

[0013] Another aspect of the present application provides a heterogeneous multi-chip fan-out plastic package heat dissipation structure, comprising:

[0014] Step S11: providing a glass wafer, a temporary bonding film, a heterogeneous multi-chip, and a resin molding compound, and attaching a temporary bonding film to the glass wafer to form a temporary bonding carrier for packaging;

[0015] Step S12: By controlling the thickness of the Dummy chip, the Dummy chip is bonded to the back of the real chip using thermal conductive adhesive so that all chips have the same thickness;

[0016] Step S13: After the Dummy chip is bonded to the back of the real chip by thermally conductive adhesive through the chip loading equipment to form an integrated whole, the center of each chip is sucked by the device nozzle according to the coordinate requirements of each heterogeneous multi-chip in the chip loading file, and the front PAD of each chip is mounted on the temporary bonding film according to the coordinates, completing the chip loading step;

[0017] Step S14: using a wafer-level molding process to pot the mounted heterogeneous multi-chip with a resin molding compound, and curing and reconstructing the compound to form a resin wafer;

[0018] Step S15: After temporarily bonding and protecting the front side of the resin wafer, the back side of the resin wafer is thinned to expose the dummy chip on the back side of each real chip;

[0019] Step S16: After the thinned wafer backside is coated with glue, exposed and developed, the Dummy chip area is opened and the other parts are protected by photoresist;

[0020] Step S17: performing a dry etching process on the reconstructed wafer after the photolithography process is completed, grooving the surface and interior of the Dummy chip, and completing the grooving of heat dissipation grooves of different sizes, depths, and densities on the back of the plastic packaging material;

[0021] Step S18: completing the metal material filling of the groove on the back of the plastic packaging material through sputtering and electroplating processes;

[0022] Step S19: using chemical mechanical polishing to thin the back of the reconstructed plastic package wafer to expose the heat dissipation groove pattern;

[0023] Step S20: temporarily bonding the back side of the resin wafer, performing a wafer-level rewiring process on the front side of the resin wafer, and using PI glue and a wafer-level multi-layer rewiring process to sequentially implement UBM and RDL multi-layer interconnect metal rewiring;

[0024] Step S21: using a wafer-level ball implantation process to implant balls at the UBM of the reconstructed resin wafer; and then dicing the reconstructed resin wafer to form a final package.

[0025] Optionally, the grooving on the surface and inside of the Dummy chip can be completed by a silicon dry etching process to form heat dissipation grooves of different sizes, depths, and densities, and directly connected to the real chip through thermal conductive adhesive.

[0026] Optionally, filling the heat dissipation slot with metal material by electroplating includes the electroplating metal material covering the entire back side of the plastic packaging material and completely filling the heat dissipation slot.

[0027] The present invention provides a high-density heterogeneous multi-chip fan-out plastic package heat dissipation structure and a preparation method thereof. The wafer-level plastic package manufacturing process is used. Heat dissipation grooves of different sizes, depths and densities are manufactured on the back of the plastic package material through a wafer-level thinning process, a photolithography process and a silicon dry etching process and are filled with metal as a heat dissipation structure. This heat dissipation structure does not require uniform thinning of heterogeneous multi-chips of different thicknesses to the same thickness before mounting a heat sink. This structure satisfies the requirement that heat dissipation grooves of different sizes, depths and densities can be slotted inside the same plastic package body. After the heat dissipation grooves are filled with metal material, they are in contact with the back of the chip to form a direct heat dissipation channel with low thermal resistance and expanded heat dissipation area, thereby effectively increasing the heat dissipation efficiency of the chip wrapped by the organic plastic package material and improving the chip packaging reliability.

[0028] The above technical scheme of the present invention has the following advantages over the prior art: 1) By controlling the thickness of the Dummy chip, the Dummy chip and the real chip are bonded together by thermal conductive adhesive to achieve consistent thickness of all chips. After being encapsulated by plastic packaging material, the problem of grooving the heat dissipation groove on the back of the plastic packaging body of heterogeneous multi-chips of different sizes and thicknesses is effectively solved through wafer-level thinning process, photolithography process and silicon dry etching process, thereby avoiding various defects of the real chip during the thinning process and effectively improving the plastic packaging yield; 2) The metal material is covered on the entire back of the plastic packaging material by electroplating process and the heat dissipation groove is completely filled to ensure the metal filling coverage and density in the heat dissipation groove; 3) The heat dissipation method in which the bottom of the heat dissipation groove is in direct contact with the back of the chip is adopted, which greatly improves the thermal conduction efficiency of the chip, forms a direct heat dissipation channel, increases the heat dissipation efficiency, and improves the packaging reliability of the heterogeneous multi-chip plastic packaging body. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of a high-density heterogeneous multi-chip fan-out plastic package heat dissipation structure provided by the present invention;

[0031] Figure 2 It is a flow chart of a method for preparing a high-density heterogeneous multi-chip fan-out plastic packaging heat dissipation structure provided by the present invention;

[0032] Figure 3 is a schematic diagram of a temporarily bonded carrier;

[0033] Figure 4 Schematic diagram of the real chip and the dummy chip being bonded together with thermal conductive adhesive to maintain the same thickness;

[0034] Figure 5 It is a schematic diagram of chip mounting according to coordinates after bonding;

[0035] Figure 6 It is a schematic diagram of wafer-level injection molding;

[0036] Figure 7 This is a schematic diagram of the thinned resin wafer leaking out of the back of the Dummy chip;

[0037] Figure 8 It is a schematic diagram of applying glue before silicon-based dry etching;

[0038] Fig. 9 This is a schematic diagram of manufacturing heat sinks by dry etching of silicon on the back of a resin wafer;

[0039] Fig.10 This is a schematic diagram of the metal material filling of the heat dissipation slot on the back of the resin wafer;

[0040] Fig.11 It is a schematic diagram of the pattern of the heat dissipation slots leaking out of the electroplated metal layer on the back of the thinned resin wafer;

[0041] Fig.12 It is a schematic diagram of the front side rewiring and UBM fabrication of the resin wafer;

[0042] Fig.13 It is a schematic diagram of wafer-level ball implantation.

[0043] As shown in the figure: 101, glass wafer, 102, temporary bonding film, 103, Dummy chip, 104, thermal conductive adhesive, 105, heterogeneous multi-chip, 106, plastic packaging material, 107, photoresist, 108, heat sink, 109, metal material, 110, rewiring, 111, UBM, 112, solder ball. DETAILED DESCRIPTION

[0044] This embodiment provides a heterogeneous multi-chip fan-out plastic packaging heat dissipation structure, the structure of which is as follows Figure 1 As shown, it includes a Dummy chip 103, a thermal conductive adhesive 104, a heterogeneous multi-chip 105, a plastic encapsulation material 106, a photoresist 107, heat dissipation grooves 108 of different sizes and depths, a metal material 109, an RDL 110, a UBM 111 and a solder ball 112. The heterogeneous multi-chip 105 is bonded to the Dummy chip 103 by the thermal conductive adhesive 104, and then Face Down mounted and encapsulated by the plastic encapsulation material 106; heat dissipation grooves 108 of different sizes, depths and densities are opened on the surface and inside of the Dummy chip through a series of processes on the back of the plastic encapsulation material, and the metal material 109 is filled inside the heat dissipation grooves 108, and the heat dissipation grooves 108 are connected to the thermal conductive adhesive 104, and the thermal conductive adhesive 104 is connected to the back of the heterogeneous multi-chip 105; and the wiring 110 is connected to the UBM Layer 111 is manufactured on the front side of the molding compound 106 , is connected to the pad of the heterogeneous multi-chip 105 , and has an electrical interconnection function, and is wrapped by polyimide 107 ; solder balls 112 are manufactured on the surface of the rewiring 110 and the UBM 111 layer.

[0045] The heterogeneous multi-chip 105 and the dummy chip 103 are bonded together by the thermal conductive adhesive 104 and mounted on a temporary carrier according to coordinates. After being integrally encapsulated by the plastic encapsulation material 106, high-density integration of chips of different sizes and thicknesses can be achieved, and the front sides of all chips are on the same plane.

[0046] The heat dissipation groove 108 on the back of the plastic packaging material is manufactured by reconstructing the wafer thinning process, the photolithography process and the dry etching process, and can realize the grooves 108 of different sizes, depths and densities on the surface and inside of the Dummy chip 103. The size and density of the heat dissipation groove are adjustable. The heat dissipation groove 108 maintains connection with the thermal conductive adhesive 104, and the thermal conductive adhesive 104 is connected to the back of the real chip 105.

[0047] The metal material 109 is filled in the heat dissipation grooves 108 of different sizes and depths through an electroplating process. The metal material is preferably copper, and aluminum or titanium-tungsten alloy can also be selected, and the filled metal material 109 is kept in contact with the back side of the heterogeneous multi-chip 105.

[0048] The metal material 109 is filled in the heat dissipation groove 108 on the back of the plastic packaging material through a wafer-level sputtering process and a wafer-level electroplating process, and the metal material includes copper, aluminum and titanium-tungsten alloy.

[0049] The rewiring 110 and UBM 111 layers are completed through a wafer-level rewiring process and maintain contact with the pads of the heterogeneous multi-chip 105. The materials include polyimide 107 and copper.

[0050] The solder balls 112 are made by wafer-level ball planting or single-chip stencil ball planting process to keep in contact with the redistribution 110 and the UBM 111 layer. The materials include tin-lead, tin-silver, and tin-silver-copper.

[0051] The heat dissipation structure provided by the embodiment of the present invention is manufactured using a wafer-level plastic packaging process. By manufacturing heat dissipation grooves of different sizes, depths, and densities on the plastic package, and filling metal as a heat dissipation structure, the heat dissipation structure is in contact with the back of the chip to form a direct heat dissipation channel, reduce thermal resistance, and expand the heat dissipation area, which can effectively improve the heat dissipation efficiency and improve the chip packaging reliability. This method is different from the traditional heat conduction heat dissipation method of using a heat sink to mount on the back of the plastic package. This structure adopts a direct contact heat dissipation method with higher heat dissipation efficiency; at the same time, it is also different from the contact heat dissipation method of thinning all chips in the plastic package to the back of the chip (the thinning thickness is determined by the chip with the smallest thickness in the system), and then mounting a heat sink. This structure can groove the back of chips of different sizes and thicknesses in the plastic package, without thinning the back of the real chip, greatly reducing various defects that are prone to occur in the thinning process of the chip, ensuring the packaging yield, and at the same time, the groove size and density of this method are adjustable, which can achieve larger size and higher density grooves, and higher heat dissipation efficiency.

[0052] In one implementation of the present application, a preparation method is provided, the process of which is as follows: Figure 2 As shown, the following steps are included:

[0053] Step S11, providing a glass wafer, a temporary bonding film, a heterogeneous multi-chip, and a resin molding compound, and attaching a temporary bonding film to the glass wafer to form a temporary bonding carrier for packaging;

[0054] Step S12, by controlling the thickness of the Dummy chip, the Dummy chip is bonded to the back of the real chip using thermal conductive adhesive so that all chips have the same thickness;

[0055] Step S13, using the chip loading equipment, according to the chip coordinate requirements in the chip loading file, the center of each chip is sucked by the device nozzle, and the front PAD of each chip is mounted on the temporary bonding film according to the coordinates, thus completing the chip loading step;

[0056] Step S14: using a wafer-level plastic encapsulation process to encapsulate the mounted heterogeneous multi-chip with a resin plastic encapsulation material, and curing and reconstructing the material to form a resin wafer;

[0057] Step S15, attaching a temporary bonding film to the front side of the resin wafer to perform front bonding protection, and then thinning the back side of the resin wafer. The thinning thickness is determined by the difference between the overall thickness of the plastic packaging material and the thickness of the chip, and the back side of the Dummy chip is exposed;

[0058] Step S16, coating the back of the thinned wafer with glue, exposing and developing, so that the Dummy chip area is opened and the other parts are protected by photoresist;

[0059] Step S17, performing a dry etching process on the reconstructed wafer after the photolithography process is completed, controlling the process parameters of the dry etching, etching the Dummy chips of different sizes and thicknesses on the back of each chip, and performing grooves of different sizes, depths, and densities on the surface and inside of the Dummy chip;

[0060] Step S18, completing the metal material filling of the groove on the back of the plastic packaging material through sputtering and electroplating processes;

[0061] Step S19, using chemical mechanical polishing (CMP) to thin the back of the reconstructed plastic package wafer to expose the heat dissipation groove pattern;

[0062] Step S20, temporarily bonding the back side of the resin wafer, performing a wafer-level rewiring process on the front side of the resin wafer, and using PI glue and a wafer-level multi-layer rewiring process to sequentially prepare RDL and UBM;

[0063] Step S21 , using a wafer-level ball planting process to plant balls at the UBM of the reconstructed resin wafer; and then dicing the reconstructed resin wafer to form a final single package.

[0064] First, a glass wafer 101 with a thickness of 700 μm is provided, and a temporary bonding film 102 is attached to the front side of the glass wafer 101 to form a temporary bonding carrier. Figure 3 shown.

[0065] By controlling the thickness of the Dummy chip 103, the Dummy chip is bonded to the back of the real chip 105 using the thermal conductive adhesive 104, so that the thickness of all chips is consistent. Figure 4 shown.

[0066] Through the chip loading equipment, all chips with the same thickness are placed according to the chip coordinate requirements in the chip loading file, and the center of each chip is sucked by the device nozzle, and the front PAD of each chip is mounted on the temporary bonding film 102 according to the coordinates, completing the chip loading steps, such as Figure 5 shown.

[0067] The wafer-level molding process is used to pot the mounted heterogeneous multi-chip with a resin molding material 106, and the resin wafer is solidified and reconstructed to form a resin wafer. Figure 6 shown.

[0068] Furthermore, a glass wafer 101, a heterogeneous multi-chip 105, a temporary bonding film 102, and a resin molding compound 106 are provided, and a temporary bonding carrier for packaging is formed by attaching the temporary bonding film to the glass wafer; the thickness of the glass wafer 101 is not less than 300 μm, and the adhesion of the temporary bonding film 102 is greater than 0.196 N / 20 mm.

[0069] A temporary bonding film 102 is attached to the front of the resin wafer for temporary bonding protection, and then the back of the resin wafer is thinned. The thinning thickness is determined by the difference between the overall thickness of the plastic packaging material and the thickness of the chip, and the back of the Dummy chip 103 is exposed. Figure 7 shown.

[0070] After the thinned wafer backside is coated with glue, exposed and developed, the Dummy chip area is opened, and the other parts are protected by the photoresist 107. Figure 8 shown.

[0071] After the photolithography process is completed, the reconstructed wafer is subjected to a dry etching process, and the process parameters of the dry etching are controlled to etch the Dummy chips 103 of different sizes and thicknesses on the back of each chip, and to complete the grooves 108 of different sizes, depths, and densities on the back of each real chip, and directly connect them with the real chip through thermal conductive glue, such as Fig. 9 shown.

[0072] Filling the heat dissipation slot with metal material by electroplating includes the electroplating metal material covering the entire back side of the plastic packaging material and completely filling the heat dissipation slot.

[0073] Through the sputtering and electroplating process, the metal material 109 filling of the groove on the back of the plastic packaging material is completed. Fig.10 shown.

[0074] The back of the reconstructed plastic package wafer is thinned by chemical mechanical polishing (CMP) to expose the heat sink pattern 108, such as Fig.11 shown.

[0075] A temporary bonding film 102 is attached to the back of the resin wafer, and a wafer-level rewiring process is performed on the front of the resin wafer. The RDL 110 and the UBM 111 are prepared in sequence using PI glue and a wafer-level multi-layer rewiring process. Fig.12 shown.

[0076] Furthermore, the wafer-level multi-layer rewiring process is a wiring process in which metal layers and passivation layers overlap multiple times; the number of rewiring layers is at least 1 metal layer; the thickness of the passivation layer is greater than the formed metal layer, and the passivation layer covers the metal layer; the thickness of the metal layer is not less than 1μm, and the thickness of the passivation layer is not less than 3μm.

[0077] By using the wafer-level ball implantation process, solder balls 112 are implanted at the UBM 111 of the reconstructed resin wafer; and then the reconstructed resin wafer is diced to form a final single package body, such as Fig.13 shown.

[0078] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A method for preparing a heterogeneous multi-chip fan-out plastic packaging heat dissipation structure, characterized in that: include: Step S11: providing a glass wafer, a temporary bonding film, a heterogeneous multi-chip, and a resin molding compound, and attaching a temporary bonding film to the glass wafer to form a temporary bonding carrier for packaging; Step S12: By controlling the thickness of the Dummy chip, the Dummy chip is bonded to the back of the real chip using thermal conductive adhesive so that all chips have the same thickness; Step S13: After the Dummy chip is bonded to the back of the real chip by thermally conductive adhesive through the chip loading equipment to form an integrated whole, the center of each chip is sucked by the device nozzle according to the coordinate requirements of each heterogeneous multi-chip in the chip loading file, and the front PAD of each chip is mounted on the temporary bonding film according to the coordinates, completing the chip loading step; Step S14: using a wafer-level molding process to pot the mounted heterogeneous multi-chip with a resin molding compound, and curing and reconstructing the compound to form a resin wafer; Step S15: After temporarily bonding and protecting the front side of the resin wafer, the back side of the resin wafer is thinned to expose the dummy chip on the back side of each real chip; Step S16: After the thinned wafer backside is coated with glue, exposed and developed, the Dummy chip area is opened and the other parts are protected by photoresist; Step S17: performing a dry etching process on the reconstructed wafer after the photolithography process is completed, grooving the surface and interior of the Dummy chip, and completing the grooving of heat dissipation grooves of different sizes, depths, and densities on the back of the plastic packaging material; Step S18: completing the metal material filling of the groove on the back of the plastic packaging material through sputtering and electroplating processes; Step S19: using chemical mechanical polishing to thin the back of the reconstructed plastic package wafer to expose the heat dissipation groove pattern; Step S20: temporarily bonding the back side of the resin wafer, performing a wafer-level rewiring process on the front side of the resin wafer, and using PI glue and a wafer-level multi-layer rewiring process to sequentially implement UBM and RDL multi-layer interconnect metal rewiring; Step S21: using a wafer-level ball implantation process to implant balls at the UBM of the reconstructed resin wafer; and then dicing the reconstructed resin wafer to form a final package.

2. The method for preparing a heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 1, characterized in that: The grooves on the surface and inside of the Dummy chip can be completed by a silicon dry etching process to form heat dissipation grooves of different sizes, depths, and densities, and are directly connected to the real chip through thermal conductive adhesive.

3. The method for preparing a heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 1, characterized in that: Filling the heat dissipation slot with metal material by electroplating includes the electroplating metal material covering the entire back side of the plastic packaging material and completely filling the heat dissipation slot.

4. A heterogeneous multi-chip fan-out plastic packaging heat dissipation structure, characterized in that: The heat dissipation structure is made based on claim 1, comprising: After the heterogeneous multi-chip 105 and the Dummy chip 103 are bonded by the thermal conductive adhesive 104, they are face-down mounted and encapsulated by the plastic packaging material 106; heat dissipation grooves 108 of different sizes, depths, and densities are opened on the surface and inside of the Dummy chip through a series of processes on the back of the plastic packaging material, and the heat dissipation grooves 108 are filled with metal materials 109. The heat dissipation grooves 108 are connected to the thermal conductive adhesive 104, and the thermal conductive adhesive 104 is connected to the back of the heterogeneous multi-chip 105; The rewiring 110 and UBM 111 layers are manufactured on the front side of the molding compound 106, connected to the pads of the heterogeneous multi-chip 105, and have an electrical interconnection function, and are wrapped by polyimide 107; Solder balls 112 are fabricated on the surface of the redistribution 110 and UBM 111 layers.

5. The heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 4, characterized in that: The heterogeneous multi-chip 105 and the dummy chip 103 are bonded together by the thermal conductive adhesive 104 and mounted on a temporary carrier according to coordinates. After being integrally encapsulated by the plastic encapsulation material 106, high-density integration of chips of different sizes and thicknesses can be achieved, and the front sides of all chips are on the same plane.

6. The heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 4, characterized in that: The heat dissipation groove 108 on the back of the plastic packaging material is manufactured by reconstructing the wafer thinning process, the photolithography process and the dry etching process, and can realize the grooves 108 of different sizes, depths and densities on the surface and inside of the Dummy chip 103. The size and density of the heat dissipation groove are adjustable. The heat dissipation groove 108 maintains connection with the thermal conductive adhesive 104, and the thermal conductive adhesive 104 is connected to the back of the real chip 105.

7. The heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 4, characterized in that: The metal material 109 is filled in the heat dissipation groove 108 on the back of the plastic packaging material through a wafer-level sputtering process and a wafer-level electroplating process, and the metal material includes copper, aluminum and titanium-tungsten alloy.

8. The heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 4, characterized in that: The rewiring 110 and UBM 111 layers are completed through a wafer-level rewiring process and maintain contact with the pads of the heterogeneous multi-chip 105. The materials include polyimide 107 and copper.

9. The heterogeneous multi-chip fan-out plastic package heat dissipation structure according to claim 4, characterized in that: The solder balls 112 are made by wafer-level ball planting or single-chip stencil ball planting process to keep in contact with the redistribution 110 and the UBM 111 layer. The materials include tin-lead, tin-silver, and tin-silver-copper.

Images