A new ESD protection device under PD-SOI integrated circuit process

Abstract

The present application relates to the field of semiconductor technology, and specifically to a new ESD protection device under PD-SOI integrated circuit technology, which forms a side additional structure through proper doping and structure design under PD-SOI integrated circuit technology, the side additional structure is in a lateral direction perpendicular to the radial direction, thereby providing an additional embedded parasitic structure for the traditional PNPN thyristor structure, and constituting a new ESD protection device; comprising semiconductor substrate one, semiconductor substrate two, insulator medium one, insulator medium two, insulator-on-semiconductor base one, insulator-on-semiconductor base two, polysilicon one and polysilicon two on the insulator-on-semiconductor base; the polysilicon one is divided into radial polysilicon and side polysilicon according to different directions, the radial polysilicon and the side polysilicon are electrically connected, the side polysilicon is narrowed on one side, and the wide part and the narrow part have chamfers; the semiconductor substrate one and the semiconductor substrate two can be silicon substrates.

Description

TECHNICAL FIELD

[0001] The present application relates to the design of integrated circuit ESD protection reliability in the field of semiconductor technology, in particular to a new ESD protection device under a PD-SOI integrated circuit process. BACKGROUND

[0002] With the continuous development of integrated circuit power consumption and performance, SOI (Silicon on Insolution) technology has extremely low parasitic capacitance, while providing dynamic voltage regulation function, which has obvious advantages in low-voltage low-power consumption, memory, radio frequency, large-scale SoC and radiation resistance applications, and has great practical application value in the fields of Internet of Things, consumer electronics, mobile Internet and aerospace. In the process of increasingly advancing SOI technology application, electrostatic reliability is a great challenge. Compared with bulk silicon technology, SOI structure has obvious disadvantages in heat dissipation difficulty and uneven heat distribution. At the same time, due to the use of complex structures such as fully depleted silicon film and high-k metal gate, the effect of traditional ESD protection means in SOI is rapidly deteriorated, the ESD protection capability is greatly reduced, and the electrostatic design complexity is greatly increased.

[0003] PD-SOI (Partially Depleted SOI) has a thicker silicon film than FD-SOI (Fully Depleted SOI) process, has an effective source-drain implant bottom surface, and can form a controllable silicon or silicon-like single unit structure as an ESD protection device. Controllable silicon has good discharge current capacity, but it also has the following defects: first, the holding voltage is too small, and once subjected to ESD impact, the ESD protection device will be turned on and cannot be turned off, or the latch will be burned out; second, the turn-on voltage is large, and once the turn-on voltage of the ESD protection device exceeds the damage voltage of the protected unit, the protected unit will be burned out before the ESD protection device is turned on. In advanced processes below 28nm, the ESD design window limiting the turn-on voltage and holding voltage has been greatly reduced, and traditional methods are increasingly difficult to meet the needs of ESD protection under advanced processes. SUMMARY

[0004] In view of the problems mentioned in the background art, the purpose of the present application is to provide a new ESD protection device under a PD-SOI integrated circuit process, which forms a side edge additional structure by proper doping and structure design under a PD-SOI integrated circuit process, and the side edge additional structure is in a lateral direction perpendicular to the radial direction, thereby providing an additional embedded parasitic structure for the traditional PNPN controllable silicon structure, forming a new ESD protection device.

[0005] The technical problem is solved by the following technical solution: a new ESD protection device under a PD-SOI integrated circuit process, comprising a semiconductor substrate one, a semiconductor substrate two, an insulator medium one, an insulator medium two, an insulator-on-semiconductor substrate one, an insulator-on-semiconductor substrate two, a polysilicon one and a polysilicon two on the insulator-on-semiconductor substrate; the polysilicon one is divided into radial polysilicon and side polysilicon according to different directions, the radial polysilicon and the side polysilicon are electrically connected, the side polysilicon is narrowed on one side, and the wide part and the narrow part have chamfers; the semiconductor substrate one and the semiconductor substrate two can be silicon substrates; the insulator medium one and the insulator medium two can be SiO2 insulators, the insulator-on-semiconductor substrate one and the insulator-on-semiconductor substrate two are active regions, the thicknesses are the same as the standard device silicon film thicknesses of the protected circuits,

[0006] The first semiconductor type can be formed by doping, and the first semiconductor type can be bottom doping of the insulator-on-semiconductor substrate one and the insulator-on-semiconductor substrate two or diffusion-formed well region doping;

[0007] The second semiconductor type can be formed by doping, and the second semiconductor type can be well region doping; the doping concentrations of the first semiconductor type heavy doping one, the first semiconductor type heavy doping two and the first semiconductor type heavy doping three and the second semiconductor type heavy doping one and the second semiconductor type heavy doping two are much higher than the doping in the first semiconductor type and the doping in the second semiconductor type, and form an ohmic contact with no Schottky barrier with a metal or a metal silicide, and also serve as electrodes of a parasitic ESD discharge mechanism.

[0008] Preferably, the first semiconductor type heavy doping one, the first semiconductor type heavy doping two and the first semiconductor type heavy doping three and the second semiconductor type heavy doping one and the second semiconductor type heavy doping two are self-aligned formed by the polysilicon one.

[0009] Preferably, the first semiconductor type heavy doping one, the first semiconductor type heavy doping two and the first semiconductor type heavy doping three and the second semiconductor type heavy doping one and the second semiconductor type heavy doping two are formed by pattern transfer of the polysilicon one; and the chamfers of the wide part and the narrow part of the first semiconductor type heavy doping three are formed by pattern transfer of the chamfers.

[0010] Preferably, the doping of the first semiconductor type heavy doping one, the doping of the second semiconductor type and the doping in the first semiconductor type in the main direction constitute a parasitic PNP-BJT one, and the doping of the second semiconductor type, the doping of the first semiconductor type and the first semiconductor type heavy doping two in the main direction constitute a parasitic NPN-BJT.

[0011] As preferred, the first semiconductor type heavy doping one, the second semiconductor type doping, and the first semiconductor type heavy doping three constitute a parasitic PNP-BJT two; the anode electrode is formed by the first semiconductor type heavy doping one and the second semiconductor type heavy doping one, and the internal resistance from the second semiconductor type heavy doping one to the first semiconductor type heavy doping one constitutes a parasitic resistance one, and the internal resistance from the second semiconductor type heavy doping one to the first semiconductor type heavy doping three constitutes a parasitic resistance two.

[0012] As preferred, the first semiconductor type heavy doping two, the second semiconductor type heavy doping two, and the cathode electrode are formed by the second semiconductor type heavy doping two, and the internal resistance from the second semiconductor type heavy doping two to the first semiconductor type heavy doping two constitutes a parasitic resistance two.

[0013] As preferred, the parasitic PNP-BJT one, the parasitic NPN-BJT, and the parasitic PNP-BJT two are nested to form a PNPN thyristor type ESD protection device.

[0014] As preferred, the parasitic PNP-BJT two is a parasitic device formed in the lateral direction, and the current direction is inconsistent with the parasitic PNP-BJT one and the parasitic NPN-BJT.

[0015] In summary, the present application mainly has the following beneficial effects:

[0016] Under the PD-SOI integrated circuit process, a side additional structure is formed by proper doping and structural design, and the side additional structure is in the lateral direction perpendicular to the radial direction, thereby providing an additional embedded parasitic mechanism for the traditional PNPN thyristor structure, and constituting a new type of ESD protection device.

[0017] On the one hand, the new type of ESD protection device has a side additional structure in the lateral direction perpendicular to the radial direction, the flowing area for discharging static charges is larger, the burnout current is higher, and the ESD protection capability is better;

[0018] On the other hand, when the PNPN structure of the new type of ESD protection device enters a back-through state, the side additional structure of the new type of ESD protection device extracts part of the carriers that should enter the PNP transmitter, weakens the back-through effect of the PNPN structure, and can overcome the problem of too small holding voltage of the thyristor type ESD protection device; and thirdly, the opening of the new type of ESD protection device is determined by the breakdown of the side additional structure in the lateral direction perpendicular to the radial direction, so that the opening voltage of the entire ESD protection device is changed from the gradual change of the well region avalanche breakdown to the tunneling breakdown of the side additional structure, not only effectively reduces the trigger voltage of the entire ESD protection device, but also is more controllable, and can better meet the increasingly small ESD protection window requirements under deep nanometer and micrometer processes. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a three-dimensional structure schematic diagram of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application;

[0020] Figure 2 is a top view, front view, left view and right view structure schematic diagram of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application;

[0021] Figure 3 is a top view, front view, back view, left view and right view schematic diagram of active area doping of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application;

[0022] Figure 4 is an electrical equivalent circuit schematic diagram of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application;

[0023] Figure 5 is an electrostatic charge discharge curve schematic diagram of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application;

[0024] Figure 6 is a mask plate preparation schematic diagram of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application;

[0025] Figure 7 is a three-dimensional structure schematic diagram of a protection unit composed of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application when applied;

[0026] Figure 8 is a top view, front view / back view, left view / right view structure schematic diagram of a protection unit composed of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application when applied;

[0027] Figure 9 is a top view schematic diagram of active area doping of a protection unit composed of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application when applied;

[0028] Figure 10 is a mask plate preparation schematic diagram of a protection unit composed of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiment of the present application when applied.

[0029] BRIEF DESCRIPTION OF DRAWINGS: 101, semiconductor substrate one; 201, semiconductor substrate two; 102, insulator medium one; 202, insulator medium two; 103, SOI substrate one; 203, SOI substrate two; 104, polysilicon one; 204, polysilicon two; 111, radial polysilicon; 112, side polysilicon; 113, chamfer; 301, first semiconductor type; 302, second semiconductor type; 3031, first semiconductor type heavily doped one; 3032, first semiconductor type heavily doped two; 3033, first semiconductor type heavily doped three; 3041, second semiconductor type heavily doped one; 3042, second semiconductor type heavily doped two; 401, parasitic PNP-BJT one; 402, parasitic resistance one; 403, parasitic NPN-BJT; 404, parasitic resistance two; 405, parasitic PNP-BJT two; 406, parasitic resistance two; 501, zero point; 502, trigger point one; 503, sustain point; 504, thermal burnout point one; 505, trigger point two; 506, sustain point; 507, thermal burnout point two; 701, semiconductor substrate three; 801, semiconductor substrate four; 702, insulator medium three; 802, insulator medium four; 703, SOI substrate three; 803, SOI substrate four; 704, polysilicon three; 804, polysilicon four; 711, radial polysilicon two; 712, side polysilicon two; 713, chamfer two; 901, first semiconductor type moderately doped; 902, second semiconductor type moderately doped; 9031, first semiconductor type heavily doped four; 9032, first semiconductor type heavily doped five; 9033, first semiconductor type heavily doped six; 9041, second semiconductor type heavily doped three; 9042, second semiconductor type heavily doped four. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] Figure 1 is a three-dimensional structure schematic diagram of a new ESD protection device under a PD-SOI integrated circuit process provided by the embodiments of the present application; Figure 2 is a top view, front view, left view and right view structure schematic diagram of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiments of the present application, which is used to conveniently and clearly illustrate Figure 1 the structural details.

[0032] The embodiment structurally includes a semiconductor substrate 101, a semiconductor substrate 201, an insulating dielectric 102, an insulating dielectric 202, a semiconductor-on-insulator matrix 103, a semiconductor-on-insulator matrix 203, and polysilicon 104 and polysilicon 204 on the semiconductor-on-insulator matrix. For example... Figure 1 As shown, polysilicon 104 is divided into radial polysilicon 111 and side polysilicon 112 according to different directions. Radial polysilicon 111 and side polysilicon 112 are electrically connected and are, but not limited to, fabricated in a single piece. Side polysilicon 112 narrows on the right side as shown in the figure, and it is suggested that the wide and narrow parts have chamfers 113. This embodiment aims to be compatible with standard silicon-based PD-SOI integrated circuit processes. Since it is a standard silicon-based process, semiconductor substrate 101 and semiconductor substrate 201 in this embodiment are, but not limited to, silicon substrates, and the doping concentration is determined according to the channel back-side doping concentration of standard silicon-based PD-SOI integrated circuits. Insulator dielectric 102 and insulator dielectric 202 are, but not limited to, SiO2 insulators, and are prepared by, but not limited to, oxygen implantation isolation (SIMOX), bonding method, and SmartCurt method. Semiconductor-on-insulator substrate 103 and semiconductor-on-insulator substrate 203 are the main active regions of this device. They are, but are not limited to, silicon film layers of standard silicon-based PD-SOI integrated circuit technology. The thickness of these layers is determined by the standard silicon-based PD-SOI integrated circuit technology, and the thickness of the silicon film of the protected circuit is determined by the standard silicon-based PD-SOI integrated circuit technology.

[0033] Figure 3 These are schematic diagrams of the top, front, rear, left, and right views of the active region doping of the novel ESD protection device under the PD-SOI integrated circuit process provided in the embodiments of the present invention.

[0034] In addition to the structural design, the novel ESD protection device under the PD-SOI integrated circuit process provided in this embodiment of the invention also includes appropriate doping to form the aforementioned function. As described above, the semiconductor-on-insulator matrix 103 and the semiconductor-on-insulator matrix 203 are the main active regions of this device; therefore, this embodiment only shows the doping schematic in polysilicon 104 and polysilicon 204.

[0035] The doping in the first semiconductor type 301 is, but not limited to, the bottom doping of the SOI substrate 103, the SOI substrate 203, or the diffusion formed well region; the doping in the second semiconductor type 302 is, but not limited to, the diffusion formed well region. The doping concentration of the first semiconductor type heavy doping 3031, the first semiconductor type heavy doping 3032, the first semiconductor type heavy doping 3033, and the second semiconductor type heavy doping 3041, the second semiconductor type heavy doping 3042 is much higher than that of the first semiconductor type heavy doping 3031 and the first semiconductor type heavy doping 3032, which forms the Schottky barrier free ohmic contact with the metal or the metal silicide, and is also the electrode of the parasitic ESD discharge mechanism. The patterns of the first semiconductor type heavy doping 3031, the first semiconductor type heavy doping 3032, the first semiconductor type heavy doping 3033, and the second semiconductor type heavy doping 3041, the second semiconductor type heavy doping 3042 are, but not limited to, the self-alignment of the polysilicon 104, which helps to reduce the surface damage of the discharge path surface, and avoid the current concentration at the defects under large current and the early burnout. Through the pattern transfer of the polysilicon 104, the first semiconductor type heavy doping 3031, the first semiconductor type heavy doping 3032, the first semiconductor type heavy doping 3033, and the second semiconductor type heavy doping 3041, the second semiconductor type heavy doping 3042 are formed as shown in the figure; through the pattern transfer of the polysilicon chamfer 113, the chamfer of the wide and narrow parts of the lower first semiconductor type heavy doping 3033 is formed as shown in the top view. The chamfer formed suggestively can avoid the electric field concentration formed by the sharp angle shape under high voltage, and thus avoid the accidental breakdown caused by uncontrollable high field strength.

[0036] Figure 4 is the electrical equivalent circuit schematic diagram of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the application.

[0037] Reference Figure 3The back view, the first semiconductor type heavy doping one 3031, the second semiconductor type 302 doping and the first semiconductor type 301 doping constitute a parasitic PNP-BJT one 401 in the main direction, the second semiconductor type 302 doping, the first semiconductor type 301 doping, the first semiconductor type heavy doping two 3032 constitute a parasitic NPN-BJT 403 in the main direction. The first semiconductor type heavy doping one 3031, the second semiconductor type 302 doping, the first semiconductor type heavy doping three 3033 constitute a parasitic PNP-BJT two 405 in the side direction; the first semiconductor type heavy doping one 3031 and the second semiconductor type heavy doping one 3041 form an anode electrode, the internal resistance of the second semiconductor type heavy doping one 3041 to the first semiconductor type heavy doping one 3031 constitutes a parasitic resistance one 402, and the internal resistance of the second semiconductor type heavy doping one 3041 to the first semiconductor type heavy doping three 3033 constitutes a parasitic resistance two 406. The first semiconductor type heavy doping two 3032, the second semiconductor type heavy doping two 3042, and the second semiconductor type heavy doping two 3042 form a cathode electrode, and the internal resistance of the second semiconductor type heavy doping two 3042 to the first semiconductor type heavy doping two 3032 constitutes a parasitic resistance two 404. The parasitic PNP-BJT one 401, the parasitic NPN-BJT 403, and the parasitic PNP-BJT two 405 are nested to form a PNPN silicon-controlled ESD protection device. The parasitic PNP-BJT two 405 is a parasitic device formed in the side direction, and the current direction is inconsistent with the parasitic PNP-BJT one 401 and the parasitic NPN-BJT 403.

[0038] Figure 5 It is an electrostatic charge discharge curve schematic diagram of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the application.

[0039] The electrostatic charge discharge curve of the conventional silicon-controlled ESD protection device starts from zero point 501, as the voltage increases, the gradual junction reverse bias between the first semiconductor type and the second semiconductor type well region increases, until avalanche breakdown occurs at the trigger point one 502, and enters the back-through region; when the PNP and NPN BJT latch is stable, the maintenance point 503 of the back-through region is reached, the minimum voltage and the maintenance voltage of the secondary state are reached; as the voltage continues to rise, the charge continues to be discharged, until the local current density reaches a certain degree, the heat accumulation causes the temperature to rise sharply, and irreversible thermal burnout occurs, reaching the thermal burnout point one 504. The conventional silicon-controlled ESD protection device has a small maintenance voltage and a large opening voltage, which is difficult to meet the ESD protection requirements under the advanced process of the PD-SOI process.

[0040] The static charge discharge curve of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the present application also starts from zero point 501, and as the voltage increases, the voltage between the first semiconductor type heavily doped one 3031 and the first semiconductor type heavily doped three 3033 also increases while the gradual reverse bias of the junction between the well regions of the first semiconductor type and the second semiconductor type increases. In the avalanche breakdown between the well regions and the tunneling breakdown of the first semiconductor type heavily doped one 3031 and the first semiconductor type heavily doped three 3033, once one of them occurs, the back-through region is entered. The width of the side poly 112 is controlled, that is, the distance between the first semiconductor type heavily doped one 3031 and the first semiconductor type heavily doped three 3033 is controlled, and then the tunneling breakdown voltage of the first semiconductor type heavily doped one 3031 and the first semiconductor type heavily doped three 3033 is controlled, so that the function of effectively controlling and reducing the opening voltage of the ESD protection device is achieved. Generally, the tunneling breakdown of the first semiconductor type heavily doped one 3031 and the first semiconductor type heavily doped three 3033 is obviously smaller than the avalanche breakdown between the well regions, so the device disclosed in the present patent can be triggered at a lower trigger point two 505.

[0041] When the PNP and NPN BJT latch is stable, the maintenance point 506 of the back-through region is reached. When the PNPN structure formed by the parasitic PNP-BJT one 401, the parasitic NPN-BJT 403 and the parasitic PNP-BJT two 405 of the new ESD protection device enters the back-through state, the parasitic PNP-BJT two 405 of the side additional structure extracts part of the carriers that should enter the parasitic PNP-BJT one 401, and weakens the back-through effect of the PNPN structure, so that the function of effectively improving the maintenance voltage of the ESD protection device is achieved, and the maintenance point 506 is higher than the maintenance point 503 of the traditional silicon controlled rectifier type ESD protection device.

[0042] As the voltage continues to rise and the charge is discharged, the local current density is further improved. In addition to the main direction current, the device disclosed in the present patent also has part of the current shunted in the side direction due to the existence of the parasitic PNP-BJT two 405 of the side structure, and the area through which the static charge is discharged is larger. Therefore, when irreversible thermal burnout occurs at the same local current density, the total current that can be discharged is larger, and the thermal burnout point two 507 is higher than the thermal burnout point one 504 of the traditional silicon controlled rectifier type ESD protection device.

[0043] Figure 6 The figure is a mask preparation schematic diagram of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the present application.

[0044] Fabricating the novel ESD protection device using the PD-SOI integrated circuit process provided in this embodiment of the invention requires no additional cost. The process flow is the same as the standard PD-SOI process, differing only in the pattern design. In this embodiment, assuming that the first type of semiconductor well region is formed by underdoping of semiconductor-on-insulator substrate 103 and semiconductor-on-insulator substrate 203, the well region of the second type of semiconductor is formed as follows... Figure 6 The mask shown in Figure A is formed. This embodiment does not exclude the possibility of forming a first-type semiconductor well region by underdoping the semiconductor substrate 103 and semiconductor substrate 203 on an insulator, and instead using an additional mask to form a second-type semiconductor well region. Polysilicon 104 and polysilicon 204 on the semiconductor substrate are as follows... Figure 6 The mask shown in B is formed to utilize self-aligned implantation of polysilicon 104 and polysilicon 204 to form various heavily doped materials. First semiconductor type heavy doping one 3031, first semiconductor type heavy doping two 3032, and first semiconductor type heavy doping three 3033 are formed through... Figure 6 The photomask shown in C is formed through a single injection annealing process. The pattern ratio of this photomask can be used without a forced ratio. Figure 6 B is wider to achieve self-alignment of polysilicon type 104 and polysilicon type 204. Second semiconductor type heavily doped type 3041 and second semiconductor type heavily doped type 3042 are achieved through, for example... Figure 6 The photomask shown in D is formed through a single injection annealing process. The pattern on this photomask can be, but is not required to be, exactly the same. Figure 6 B is wider to enable self-alignment of polysilicon-104 and polysilicon-204.

[0045] Figure 7 This is a three-dimensional structural diagram of the protection unit formed when the novel ESD protection device under the PD-SOI integrated circuit process provided in this embodiment of the invention is applied. The protection unit consists of... Figure 1 The basic structure shown is symmetrically composed and has good symmetry. It is a recommended composition form for the application of the device disclosed in this invention. Figure 8 These are top, front / rear, left / right views of the protection unit formed by the novel ESD protection device under the PD-SOI integrated circuit technology provided in the embodiments of the present invention, used to facilitate and clearly illustrate the application. Figure 1 Structural details.

[0046] The embodiment structurally includes semiconductor substrate 3 701, semiconductor substrate 4 801, insulating dielectric 3 702, insulating dielectric 4 802, semiconductor-on-insulator matrix 3 703, semiconductor-on-insulator matrix 4 803, and polysilicon 3 704 and polysilicon 4 804 on the semiconductor-on-insulator matrix. For example... Figure 1As shown, the polysilicon three 704 is divided into the radial polysilicon two 711 and the lateral polysilicon two 712 according to different directions, and the radial polysilicon two 711 and the lateral polysilicon two 712 are electrically connected, which are but not limited to one-time integrated preparation. The lateral polysilicon two 712 is narrowed at the right side as shown, and the wide part and the narrow part are provided with the chamfer two 713. The embodiment is compatible with the standard silicon-based PD-SOI integrated circuit process, and thus the semiconductor substrate three 701 and the semiconductor substrate four 801 are but not limited to silicon substrates, and the doping concentration is determined according to the channel bottom back doping concentration of the standard silicon-based PD-SOI integrated circuit. The insulator medium three 702 and the insulator medium four 802 are but not limited to SiO2 insulators, which are prepared by but not limited to SIMOX, bonding method and SmartCurt method. The polysilicon three 704 and the polysilicon four 804 on the semiconductor-on-insulator substrate are the main active areas of the device, which are but not limited to the silicon film layer of the standard silicon-based PD-SOI integrated circuit process, and the thickness is determined by the standard silicon-based PD-SOI integrated circuit process.

[0047] Figure 9 Figure 1 is a top view of the active area doping of the protection unit of the application of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the application;

[0048] In addition to the structural design, the features of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the application also include suitable doping to form the functions. As described above, the semiconductor-on-insulator substrate three 703 and the semiconductor-on-insulator substrate four 803 are the main active areas of the device, and thus the embodiment only shows the doping of the polysilicon three 704 and the polysilicon four 804.

[0049] The first semiconductor type doping 901 is but not limited to the bottom doping of the SOI substrate three 703 and the SOI substrate four 803, or the diffusion formed well region doping; the second semiconductor type doping 902 is but not limited to the diffusion formed well region doping. The first semiconductor type heavy doping one 9031, the first semiconductor type heavy doping two 9032, the first semiconductor type heavy doping three 9033, the second semiconductor type heavy doping one 9041 and the second semiconductor type heavy doping two 9042 have a doping concentration much higher than the first semiconductor type doping 901 and the second semiconductor type doping 902, form the ohmic contact with metal or metal silicide without Schottky barrier, and are also the electrodes of the parasitic ESD discharge mechanism. The patterns of the first semiconductor type heavy doping one 9031, the first semiconductor type heavy doping two 9032, the first semiconductor type heavy doping three 9033, the second semiconductor type heavy doping one 9041 and the second semiconductor type heavy doping two 9042 are but not limited to the self-alignment of the polysilicon three 704. The self-alignment technology of the polysilicon three 704 helps to reduce the surface damage of the discharge path surface, and avoid the current concentration at the defects under large current and the early burnout. The first semiconductor type heavy doping one 9031, the first semiconductor type heavy doping two 9032, the first semiconductor type heavy doping three 9033, the second semiconductor type heavy doping one 9041 and the second semiconductor type heavy doping two 9042 are formed by the pattern transfer of the polysilicon three 704; the chamfer of the lower side of the first semiconductor type heavy doping three 9033 is formed by the pattern transfer of the polysilicon chamfer 113. The suggested chamfer can avoid the electric field concentration of the sharp corner shape under high voltage, and avoid the accidental breakdown caused by uncontrollable high field strength.

[0050] Figure 10 It is a preparation mask plate schematic diagram of the protection unit of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the application;

[0051] The preparation of the new ESD protection device under the PD-SOI integrated circuit process provided by the embodiment of the application does not need additional cost, and the process flow is the same as the standard PD-SOI process, and only the pattern design is different from the standard PD-SOI circuit. In the case of the default SOI substrate three 703 and the SOI substrate four 803 bottom doping forming the first type semiconductor well region, the well region of the second type semiconductor is formed by the mask plate shown in A. The embodiment does not exclude the case of the SOI substrate three 703 and the SOI substrate four 803 bottom doping forming the first type semiconductor well region, and forming the well region of the second type semiconductor by an additional mask plate. The polysilicon three 704 and the polysilicon four 804 on the SOI substrate are Figure 6 A. The embodiment does not exclude the case of the SOI substrate three 703 and the SOI substrate four 803 bottom doping forming the first type semiconductor well region, and forming the well region of the second type semiconductor by an additional mask plate. The polysilicon three 704 and the polysilicon four 804 on the SOI substrate areFigure 6 B shown mask formation, in order to form a variety of heavy doping by self-alignment implantation of polysilicon three 704, polysilicon four 804. First semiconductor type heavy doping four 9031, first semiconductor type heavy doping five 9032, first semiconductor type heavy doping six 9033 by as Figure 6 C shown mask formation through one-time implantation annealing, the pattern of the mask is wider than can be but not forced than Figure 6 B, to achieve self-alignment of polysilicon three 704, polysilicon four 804. Second semiconductor type heavy doping three 9041, first semiconductor type heavy doping five 9032 by as Figure 6 D shown mask formation through one-time implantation annealing, the pattern of the mask is wider than can be but not forced than Figure 6 B, to achieve self-alignment of polysilicon three 704, polysilicon four 804.

[0052] It needs to be emphasized that, by using the opposite type to discharge the static negative charge, the method is also within the protection scope of the present application.

[0053] The embodiments of the present application are described, for those skilled in the art, it can be understood that in the absence of departing from the principles and spirit of the present application can be made to these embodiments of a variety of changes, modifications, substitutions and variations, the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A novel ESD protection device under PD-SOI integrated circuit process, characterized in that, The semiconductor substrate one (101), the semiconductor substrate two (201), the insulator medium one (102), the insulator medium two (202), the insulator-on-semiconductor substrate one (103), the insulator-on-semiconductor substrate two (203), the polysilicon one (104) and the polysilicon two (204) on the insulator-on-semiconductor substrate; the polysilicon one (104) is divided into radial polysilicon (111) and side edge polysilicon (112) according to different directions, the radial polysilicon (111) and the side edge polysilicon (112) are electrically connected, the side edge polysilicon (112) is narrowed on one side, and the wide part and the narrow part have a chamfer (113); the semiconductor substrate one (101) and the semiconductor substrate two (201) are silicon substrates; the insulator medium one (102) and the insulator medium two (202) are SiO2 insulators, the insulator-on-semiconductor substrate one (103) and the insulator-on-semiconductor substrate two (203) are active regions, The first semiconductor type (301) is formed by doping, the first semiconductor type (301) is bottom doping of the insulator-on-semiconductor substrate one (103) and the insulator-on-semiconductor substrate two (203), or is well region doping formed by diffusion; The second semiconductor type (302) is formed by doping, the second semiconductor type (302) is well region doping; the doping concentration of the first semiconductor type heavy doping one (3031), the first semiconductor type heavy doping two (3032) and the first semiconductor type heavy doping three (3033) and the second semiconductor type heavy doping one (3041) and the second semiconductor type heavy doping two (3042) is much higher than that of the first semiconductor type (301) and the second semiconductor type (302), and forms ohmic contact with metal or metal silicide without Schottky barrier, and is also an electrode of a parasitic ESD discharge mechanism; The first semiconductor type heavy doping one (3031), the first semiconductor type heavy doping two (3032) and the first semiconductor type heavy doping three (3033) and the second semiconductor type heavy doping one (3041) and the second semiconductor type heavy doping two (3042) are self-aligned formed by the polysilicon one (104); The first semiconductor type heavy doping one (3031), the first semiconductor type heavy doping two (3032) and the first semiconductor type heavy doping three (3033) and the second semiconductor type heavy doping one (3041) and the second semiconductor type heavy doping two (3042) are formed by pattern transfer of the polysilicon one (104); and the chamfer of the first semiconductor type heavy doping three (3033) is formed by pattern transfer of the chamfer (113). The doping of the first semiconductor type (301), the doping of the second semiconductor type (302) and the first semiconductor type heavy doping one (3031) in the main direction constitute a parasitic PNP-BJT one (401), the doping of the second semiconductor type (302), the doping of the first semiconductor type (301) and the first semiconductor type heavy doping two (3032) in the main direction constitute a parasitic NPN-BJT (403); The first semiconductor type heavy doping one (3031), the doping of the second semiconductor type (302) and the first semiconductor type heavy doping three (3033) in the side direction constitute a parasitic PNP-BJT two (405); the anode electrode is formed by the first semiconductor type heavy doping one (3031) and the second semiconductor type heavy doping one (3041), the internal resistance from the second semiconductor type heavy doping one (3041) to the first semiconductor type heavy doping one (3031) constitutes a parasitic resistance one (402), and the internal resistance from the second semiconductor type heavy doping one (3041) to the first semiconductor type heavy doping three (3033) constitutes a parasitic resistance two (406); The first semiconductor type heavy doping two (3032), the second semiconductor type heavy doping two (3042) and the cathode electrode formed by the second semiconductor type heavy doping two (3042) constitute a parasitic resistance two (404).

2. The novel ESD protection device under PD-SOI integrated circuit process according to claim 1, wherein, The parasitic PNP-BJT one (401), the parasitic NPN-BJT (403) and the parasitic PNP-BJT two (405) are nested to form a PNPN thyristor type ESD protection device.

3. The new ESD protection device under PD-SOI integrated circuit process according to claim 2, characterized in that, The parasitic PNP-BJT two (405) is a parasitic device formed in the side direction, and the current direction is inconsistent with the parasitic PNP-BJT one (401) and the parasitic NPN-BJT (403).

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