A display backplane, a preparation method thereof, and a display device

Abstract

An embodiment of the present disclosure provides a display backplane, including a substrate, on which a plurality of pixel circuits, a plurality of bonding electrodes, and a plurality of bonding connection lines respectively corresponding to and connected to the bonding electrodes are provided; the plurality of bonding electrodes and the plurality of bonding connection lines are respectively located on two opposite surfaces of the substrate, and the plurality of pixel circuits and the plurality of bonding connection lines are located on the same side of the substrate; one end of the plurality of bonding connection lines is connected to the bonding electrodes through first vias formed in the substrate; the other ends of at least some of the plurality of bonding connection lines are connected to the pixel circuits; at least one of the plurality of bonding electrodes and the plurality of bonding connection lines does not overlap with the positive projection of the pixel circuit on the substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure belong to the technical field of displays, and particularly relate to a display backplane, a preparation method thereof, and a display device. Background Art

[0002] In recent years, full-screen and borderless seamless displays have become important development directions for high-end mobile displays; in order to achieve full-screen and borderless seamless displays, it is necessary to conduct signals between the front and back of the substrate. Currently, the substrate mainly includes a glass substrate and a polyimide (PI) substrate; in order to realize signal conduction between the front and back, it is usually necessary to drill holes in the substrate. Since the glass substrate cannot achieve flexible display, PI drilling is a better implementation method for full-screen and borderless seamless displays. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display backplane, a preparation method thereof, and a display device.

[0004] In a first aspect, embodiments of the present disclosure provide a display backplane, including a substrate, on which a plurality of pixel circuits, a plurality of bonding electrodes, and a plurality of bonding connection lines respectively corresponding to and connected to the bonding electrodes are provided; the plurality of bonding electrodes and the plurality of bonding connection lines are respectively located on two opposite surfaces of the substrate, and the plurality of pixel circuits and the plurality of bonding connection lines are located on the same side of the substrate; one end of each of the plurality of bonding connection lines is connected to the bonding electrode through a first via hole formed in the substrate; the other end of at least some of the plurality of bonding connection lines is connected to the pixel circuit;

[0005] At least one of the plurality of bonding electrodes and the plurality of bonding connection lines does not coincide with the positive projection of the pixel circuit on the substrate.

[0006] In some embodiments, the display backplane further includes a plurality of dummy circuits provided on the substrate, and at least one of the plurality of bonding electrodes and the plurality of bonding connection lines partially overlaps with at least one of the plurality of dummy circuits in the positive projection on the substrate.

[0007] In some embodiments, the circuit structure of the dummy circuit is the same as that of the pixel circuit.

[0008] In some embodiments, the display backplane includes a plurality of light-emitting elements arranged in a uniform array, and the plurality of pixel circuits are respectively connected to the light-emitting elements in one-to-one correspondence; in the pixel circuit array, adjacent n rows of pixel circuits form a pixel circuit group; where n is an integer and 2 ≤ n ≤ 5;

[0009] The pitch in the column direction along the pixel circuits between two adjacent rows of the light-emitting elements is M, and for any two adjacent rows of pixel circuits within the pixel circuit group, the pitch S satisfies: 0 < S ≤ M;

[0010] The length of the bonding electrode in the column direction along the pixel circuits is L, and the pitch T between two adjacent pixel circuit groups satisfies: M < T ≤ (2·p + 1)·M, where p = [L / M].

[0011] In some embodiments, the multiple dummy circuits are arranged in a uniform array, and n adjacent rows of the dummy circuits form a dummy circuit group, where n is an integer and 2 ≤ n ≤ 5;

[0012] Within the dummy circuit group, the pitch G between any two adjacent rows of the dummy circuits satisfies: 0 < G ≤ M.

[0013] In some embodiments, the pitch H between the dummy circuit group and the adjacent pixel circuit group satisfies: M < H ≤ 2M; the pitch X between multiple dummy circuit groups satisfies: M < X ≤ 2M.

[0014] In some embodiments, the orthographic projection of the first via on the substrate is located within the orthographic projection area of the end of the bonding electrode on the substrate.

[0015] In some embodiments, there are multiple first vias, and the multiple first vias are respectively arranged at both ends of the bonding electrode, and the first vias are arranged in sequence along the length direction of the bonding electrode.

[0016] In some embodiments, the first via includes N, N is an even number, N / 2 first vias are correspondingly arranged at one end of the bonding electrode, and the other N / 2 first vias are correspondingly arranged at the other end of the bonding electrode.

[0017] In some embodiments, the pixel circuit is located on the side of the bonding connection line away from the substrate, and a first insulating layer is further arranged between the pixel circuit and the bonding connection line, and a second via is formed in the first insulating layer, and the pixel circuit is connected to the bonding connection line through the second via.

[0018] In some embodiments, a shift register is further included, the shift register is arranged on the side of the bonding connection line away from the substrate, and the orthographic projection of the shift register on the substrate is at least partially located within the orthographic projection of the bonding electrode that provides signals for it on the substrate;

[0019] One end of the shift register is connected to the bonding electrode through the bonding connection line, and the other end is connected to the pixel circuit.

[0020] In some embodiments, the shift register is disposed on the same layer as the pixel circuit, and the shift register is located in the region between two adjacent columns of the pixel circuits;

[0021] The first insulating layer further extends between the shift register and the bonding connection line, and a third via hole is further formed in the first insulating layer. The shift register is connected to the bonding connection line through the third via hole so as to be connected to the bonding electrode through the bonding connection line.

[0022] In some embodiments, a data selection circuit is further included. A positive projection of the data selection circuit on the substrate overlaps with a positive projection of the bonding connection line on the substrate. One end of the data selection circuit is connected to the bonding electrode through the bonding connection line, and the other end is connected to a data line;

[0023] The data line is configured to connect the pixel circuit and the data selection circuit.

[0024] In some embodiments, the data selection circuit is located on a side of the bonding connection line away from the substrate. The data selection circuit is disposed on the same layer as the pixel circuit, and the data selection circuit is staggered from the pixel circuit and the shift register;

[0025] The first insulating layer further extends between the data selection circuit and the bonding connection line, and a fourth via hole is formed in the first insulating layer. The data selection circuit is connected to the bonding connection line through the fourth via hole so as to be connected to the bonding electrode through the bonding connection line.

[0026] In some embodiments, the plurality of bonding electrodes are arranged in a row direction in which the pixel circuits are arranged, and a length direction of the plurality of bonding electrodes is parallel to a column direction in which the pixel circuits are arranged;

[0027] The data selection circuit has a strip shape, and a length direction of the data selection circuit is parallel to the row direction in which the pixel circuits are arranged.

[0028] In some embodiments, there are a plurality of data selection circuits. The plurality of data selection circuits are parallel to each other and are sequentially arranged along a column direction in which the pixel circuits are arranged.

[0029] In some embodiments, the pixel circuit includes at least a capacitor and a thin film transistor which are electrically connected.

[0030] In a second aspect, an embodiment of the present disclosure further provides a display device, including the above-mentioned display backplane.

[0031] In a third aspect, embodiments of the present disclosure further provide a method for manufacturing a display backplane, including sequentially manufacturing a plurality of bonding electrodes, a substrate and a first via hole therein, a plurality of bonding connection lines, and a plurality of pixel circuits on a substrate; the plurality of bonding electrodes are in one-to-one correspondence with and connected to the plurality of bonding connection lines; the plurality of bonding electrodes and the plurality of bonding connection lines are respectively located on two opposite surfaces of the substrate, and the plurality of pixel circuits and the plurality of bonding connection lines are located on the same side of the substrate; one end of the plurality of bonding connection lines is connected to the bonding electrodes through the first via hole; the other ends of at least some of the plurality of bonding connection lines are connected to the pixel circuits;

[0032] At least one of the plurality of bonding electrodes and the plurality of bonding connection lines does not overlap with the positive projection of the pixel circuit on the substrate.

[0033] In some embodiments, it further includes the step of peeling the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation to the present disclosure. By describing the detailed exemplary embodiments with reference to the drawings, the above and other features and advantages will become more apparent to those skilled in the art. In the drawings:

[0035] Figure 1 is a schematic diagram of the signal line architecture of a display panel in the related art;

[0036] Figure 2 is a schematic diagram of the signal line architecture in a PI-drilled borderless substrate in the related art;

[0037] Figure 3 is a schematic diagram of the overlap between the fan-out wiring and the transistor active layer in a PI-drilled borderless substrate in the related art;

[0038] Figure 4 is a schematic diagram of the layout of the driving circuit and the fan-out wiring in a PI-drilled borderless substrate in the related art;

[0039] Figure 5 is caused by Figure 4 the layout of the driving circuit and the fan-out wiring in the display panel shows uneven brightness;

[0040] Figure 6 is a top view schematic diagram of the signal line architecture of a display backplane in an embodiment of the present disclosure;

[0041] Figure 7 is a schematic diagram of the layout of pixel circuits in a traditional display backplane;

[0042] Figure 8 Schematic diagram of the arrangement of pixel circuits in the display backplane according to an embodiment of the present disclosure;

[0043] Figure 9 Schematic diagram of the positional relationship between the first vias opened in the substrate and the bonding electrodes according to an embodiment of the present disclosure;

[0044] Figure 10 Schematic diagram of the overlap between the bonding connection lines and the transistor active layer in the display backplane according to an embodiment of the present disclosure;

[0045] Figure 11 Structural diagram of a pixel circuit according to an embodiment of the present disclosure;

[0046] Figure 12 Structural diagram of a shift register according to an embodiment of the present disclosure;

[0047] Figure 13 Schematic diagram of the on / off selection of the connection data lines by two data selection circuits according to an embodiment of the present disclosure;

[0048] Figure 14 Top view schematic diagram of the signal line architecture of the display backplane according to another embodiment of the present disclosure.

[0049] Wherein the reference numerals are:

[0050] 1. Bonding area; 2. Bonding wiring area; 3. Display area; 4. Shift register; 5. Bonding electrode; 6. Bonding connection line; 7. Pixel circuit; 70 / 70' / 70''. Pixel circuit group; 8. Pixel; 9. First via; 91. Side; 10. Data selection circuit; 11. Signal line; 12. dummy circuit; 120. Dummy circuit group; 13. Fan-out wiring; 130. Fan-out wiring area; 100. Brightness non-uniform area; 14. Driving circuit; 15. Data line; 16. Transistor; 160. First gate; 161. Second gate; 162. Active layer; 163. Source; 164. Drain; 17. Substrate; 171. First side; 172. Second side; 18. Relay line; 19. Recess; 20. Insulating layer; 21. Additional insulating layer; 210. Passivation layer; 211. Barrier layer; 212. Buffer layer; 22. First gate insulating layer; 23. Second gate insulating layer; 24. Interlayer dielectric layer; 25. Light-emitting element; 26. First planarization layer; 27. Second planarization layer; 28. Second passivation layer; 29. First contact pad; 30. Second contact pad; 31. Substrate through hole; 32. Third passivation layer; 33. Fifth via; 34. Sixth via. Detailed implementation manners

[0051] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display backplane, a method for manufacturing the same, and a display device provided by the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] In the following, the embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. However, the disclosed embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0053] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications to the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be restrictive.

[0054] In the related art, the signal traces are all disposed on one surface of the display substrate, such as Figure 1 as shown, the signal lines 11 (such as data lines, power lines, etc.) in the display area 3 are connected to the bonding electrodes 5 through the fan-out traces 13 in the non-display area of the display substrate. In the module process, the bonding electrodes 5 are electrically connected to the driving chips (ICs) through flexible printed circuits (FPCs) or chip on film (COF).

[0055] The related art provides an implementation manner of a narrow-bezel display substrate, such as Figure 2 and Figure 3As shown, the display substrate includes a substrate 17, a bonding electrode 5 disposed on the second side 172 of the substrate 17, and a fan-out trace 13, a driving circuit, and other metal layers sequentially disposed on the first side 171 of the substrate 17. Each sub-pixel corresponds to a driving circuit, and the driving circuits are arranged in an array uniformly. Each driving circuit includes at least one transistor 16. Among them, the first side 171 and the second side 172 are opposite two surfaces of the substrate 17. The transistor 16 includes a first gate 160, a second gate 161, an active layer 162, a source electrode 163 electrically connected to the active layer 162, and a drain electrode 164 electrically connected to the active layer 162; the fan-out trace 13, the conductive film layer in the transistor 16, and other metal layers are separated by an insulating layer. The bonding electrode 5 is disposed in the display area 3. The signal line 11 runs through the source-drain metal layer in the transistor (TFT) or other metal layers above the source-drain metal layer (generally a low-resistance metal such as a Ti / Al / Ti stack, Cu, etc.), and is overlapped with the fan-out trace 13 through a via hole in the insulating layer located at the edge of the display substrate. The fan-out trace 13 is connected to the bonding electrode 5 located in the display area 3 through a substrate via hole 31 in the display area 3 that overlaps with the orthographic projection of the bonding electrode 5. The bonding electrode 5 is connected to a driving chip or other signal sources through a flexible circuit board or a flip chip film, so as to transmit the electrical signals emitted by the peripheral circuit signal sources such as the driving chip or the power supply to the electrical devices in the display substrate. Among them, the material of the substrate 17 can be a flexible material such as polyimide, or a rigid material such as glass or quartz.

[0056] For a high-resolution display panel, limited by the number of output data signal channels of the driving chip, a data selection circuit is usually used to expand the number of data signal channels to solve the problem of mismatch between the number of output data signal channels of the driving chip and the number of signal lines of the display panel. In the related art, as Figure 2 , the data selection circuit 10 is also disposed at the edge of the display panel, and the data selection circuit 10 is connected to the fan-out trace 13 through a sixth via hole 34 in the insulating layer located at the edge of the display substrate.

[0057] In the borderless substrate provided by the related art, as Figure 3 and Figure 4As shown, the fan-out routing 13 needs to connect the bonding electrode 5 in the middle of the display area 3 and the data selection circuit located at the edge of the display substrate. When the routing distance is large and there are many signal channels, the fan-out routings 13 are densely arranged and overlap with the positive projection area of the active layer 162 of the transistor 16 in the driving circuit 14 in the display area 3 (low-temperature polysilicon or semiconductor oxide materials can be used). Taking the substrate of the low-temperature polysilicon transistor active layer 162 as an example, the fan-out routing 13 is located in the display area 3 and is separated from the low-temperature polysilicon active layer 162 by a buffer layer 212 and a barrier layer 211 (with a total thickness of about 0.9 μm). However, due to the overlap of the positive projection areas, a large coupling effect will still be generated between the two, resulting in uneven brightness during the display of the display panel. In comparison Figure 4 with Figure 5 it can be found that the contour of the uneven brightness area 100 is consistent with that of the fan-out routing area 130. This is mainly because the fan-out routing 13 is located below the active layer 162 of the transistor 16, and their positive projection areas overlap, affecting the crystallization of the polysilicon active layer 162. In addition, the electrical signals on the fan-out routing 13 will also couple to the gate voltage of the transistor 16, resulting in abnormal pixel current magnitudes and affecting the brightness uniformity of the display panel.

[0058] Aiming at the problem that the overlap between the fan-out routing and the active layer or gate of the transistor leads to uneven display brightness of the display panel, the embodiments of the present disclosure provide a display backplane, a manufacturing method thereof, and a display device.

[0059] The embodiments of the present disclosure provide a display backplane, as Figure 6 shown. The display backplane includes a substrate, on which a plurality of pixel circuits 7, a plurality of bonding electrodes 5, and a plurality of bonding connection lines 6 corresponding to and connected to the bonding electrodes 5 one by one are provided; the plurality of bonding electrodes 5 and the plurality of bonding connection lines 6 are respectively located on two opposite surfaces of the substrate, and the plurality of pixel circuits 7 and the plurality of bonding connection lines 6 are located on the same side of the substrate; one end of the plurality of bonding connection lines 6 is connected to the bonding electrode 5 through a first via hole formed in the substrate; at least some of the other ends of the plurality of bonding connection lines 6 are connected to the pixel circuit 7; at least one of the plurality of bonding electrodes 5 and the plurality of bonding connection lines 6 does not overlap with the pixel circuit 7 in the positive projection on the substrate.

[0060] In some embodiments, the display backplane includes a bonding area 1, a bonding routing area 2, and a display area 3. The bonding area 1 and the bonding routing area 2 are adjacent, and the bonding area 1 and the bonding routing area 2 are located in the display area 3; the bonding electrode 5 is located in the bonding area 1; the bonding connection line 6 is located in the bonding routing area 2; the pixel circuit 7 is located in the area of the display area 3 other than the bonding area 1 and the bonding routing area 2. The substrate can adopt a polyimide material to achieve flexible display.

[0061] Among them, the display area 3 refers to the area on the display backplane where images are actually displayed. The pixel circuit 7 is a circuit for driving the light-emitting elements to emit light, and the light-emitting elements can be micro inorganic light-emitting diodes or organic light-emitting diodes. The bonding electrode 5 is used to bond the peripheral circuit. One end of the bonding connection line 6 is connected to the bonding electrode 5, and the other end is connected to the pixel circuit 7, so that signals provided by the peripheral circuit (including driving signals, power supply signals, control signals, clock signals, etc.) can be provided to the pixel circuit 7, so that the pixel circuit 7 drives the sub-pixels to display. The pixel circuit 7 is a circuit formed by connecting electronic components such as capacitors and multiple transistors. By arranging the bonding area 1 and the bonding wiring area 2 within the display area 3, a display panel using this display backplane can achieve a full-screen or borderless display.

[0062] By making at least one of the multiple bonding electrodes 5 and the multiple bonding connection lines 6 not coincide with the positive projection of the pixel circuit 7 on the substrate, it is possible to avoid the overlap between the bonding electrodes 5 and the bonding connection lines 6 and the active layer, gate, etc. of the transistors in the pixel circuit 7, thereby avoiding the coupling effect between the bonding electrodes 5 and the bonding connection lines 6 and the conductive layer of the transistors, and further avoiding the influence of the coupling effect on the light-emitting brightness of the display panel, ensuring the uniformity of the display brightness of the display panel.

[0063] Such as Figure 7 FIG. shows a display panel in a related art, where the light-emitting elements 25 are arranged in an equidistant array on the display panel, and the pixel circuits 7 are connected to the light-emitting elements 25 in a one-to-one correspondence and are also arranged in a uniform array. The distance M between any two adjacent rows of light-emitting elements 25 is equal; the distance Z between any two adjacent rows of pixel circuits 7 is equal. The arrangement of the light-emitting elements 25 on the display backplane provided in the embodiments of the present invention is the same as the arrangement of the light-emitting elements 25 on the display backplane in the related art, that is, the light-emitting elements 25 are arranged in an equidistant array in the display area 3, but the arrangement of the pixel circuits 7 in the display backplane in this embodiment is different from that in the related art.

[0064] In some embodiments, the bonding electrode 5 is arranged in the bonding area 1 within the display area 3. The length L of the bonding electrode in the Y direction is approximately p times the distance M between adjacent rows of light-emitting elements 25 in the Y direction (i.e., p = [L / M], p > 1). In order to avoid the overlap between the area where the bonding electrode 5 is located and the pixel circuit rows and affect the display, it is necessary to move the pixel circuit rows that overlap with the bonding electrode 5. Specifically, p pixel circuit rows need to be moved.

[0065] Specifically, such as Figure 8As shown, the length L of the bonding electrode 5 in the Y direction is approximately twice the pitch M of the adjacent row of light-emitting elements 25 in the Y direction (i.e., p = 2), and there is an overlap with the partial light-emitting elements located in the 7th row and the 8th row. Therefore, the two pixel circuit rows that should have been arranged between the light-emitting elements in the 7th row and the 8th row need to be moved and arranged respectively above the light-emitting elements in the 5th row and below the light-emitting elements in the 10th row for example. The pixel circuit row above the light-emitting elements in the 5th row and the two adjacent pixel circuit rows closest to it form a pixel circuit group 70'; similarly, the pixel circuit row below the light-emitting elements in the 10th row and the two adjacent pixel circuit rows closest to it form a pixel circuit group.

[0066] In some embodiments, as Figure 8 shown, the display backplane includes a plurality of light-emitting elements 25 arranged in a uniform array, and the pitch M between adjacent rows of light-emitting elements 25. A plurality of pixel circuits 7 are connected to the light-emitting elements 25 in one-to-one correspondence; in the pixel circuit array, adjacent n rows of pixel circuits 7 form a pixel circuit group 70 / 70', where n is an integer and 2 ≤ n ≤ 5. Within a pixel circuit group 70, the pitch S between any adjacent two rows of pixel circuits 7 satisfies: 0 < S ≤ M. That is, for the case where two rows of pixel circuits 7 are sandwiched between adjacent rows of light-emitting elements 25, the pitch S1 of these two rows of pixel circuits 7 is significantly smaller than the pitch M between adjacent rows of light-emitting elements 25; and for the pixel circuit rows arranged on both sides of the same row of light-emitting elements 25 respectively, the pitch S2 between them is also smaller than the pitch M between adjacent rows of light-emitting elements 25. The pitch T between two adjacent pixel circuit groups satisfies: M < T ≤ (2·p + 1)·M, that is, for the pitch T1 between the pixel circuit group 70 and the pixel circuit group 70", M < T1 ≤ 2M; for the pitch T2 between the pixel circuit group 70 and the pixel circuit group 70', M < T2 ≤ 2M; for the pitch T3 between two adjacent pixel circuit groups 70', it satisfies M < T3 ≤ 5M.

[0067] That is to say, in the pixel circuit array, the pitch between any adjacent n rows of pixel circuits 7 can be equal or unequal; and / or, the pitch between any adjacent pixel circuit groups 70 can be equal or unequal. Within any pixel circuit group 70, the number of rows of pixel circuits 7 can be equal or unequal. The interconnected pixel circuits 7 and the light-emitting elements 25 form a sub-pixel, and three adjacent sub-pixels along the row direction of the light-emitting element array form a pixel 8.

[0068] All the pixel circuits 7 in the area of the display backplane provided by the embodiment of the present application, which is located in the display area 3 and outside the bonding area 1 and the bonding wiring area 2, are arranged according to the arrangement manner of the spacing S between any two adjacent rows of pixel circuits 7 and the spacing T between adjacent pixel circuit groups 70 as described above. In this way, on the one hand, compared with the pixel circuits 7 arranged uniformly in the related art, the spacing S between two adjacent rows of pixel circuits 7 within the same pixel circuit group 70 is smaller, while the spacing T between adjacent pixel circuit groups 70 is larger. As a result, compared with Figure 8 the pixel circuits 7 that should be arranged in the bonding area 1 and the bonding wiring area 2 in the traditional pixel circuit arrangement in the related art are grouped and arranged in the area outside the bonding area 1 and the bonding wiring area 2 to realize the normal driving of the light-emitting elements 25 normally arranged in the bonding area 1 and the bonding wiring area 2; on the other hand, in this embodiment, the arrangement of the light-emitting elements 25 is kept uniform, thereby ensuring the display uniformity of the display backplane.

[0069] In addition, it is also necessary to redesign the connection relationship between the relevant row of light-emitting elements and the pixel circuits to ensure that the connection line between the pixel circuit 7 and the light-emitting element 25 has a short path and avoid the influence of the too long connection line between the pixel circuit 7 and the light-emitting element 25 on the brightness uniformity of the light-emitting element 25. In some embodiments, as Figure 8 shown, specifically, the row of pixel circuits above the fifth row of light-emitting elements is in one-to-one correspondence and electrically connected with the fifth row of light-emitting elements, the row of pixel circuits below the fifth row of light-emitting elements and close to the fifth row of light-emitting elements is in one-to-one correspondence and electrically connected with the sixth row of light-emitting elements, the row of pixel circuits below the fifth row of light-emitting elements and close to the sixth row of light-emitting elements is in one-to-one correspondence and electrically connected with the seventh row of light-emitting elements, the row of pixel circuits below the ninth row of light-emitting elements and close to the ninth row of light-emitting elements is in one-to-one correspondence and electrically connected with the eighth row of light-emitting elements, the row of pixel circuits below the ninth row of light-emitting elements and close to the tenth row of light-emitting elements is in one-to-one correspondence and electrically connected with the ninth row of light-emitting elements, and the row of pixel circuits below the tenth row of light-emitting elements is in one-to-one correspondence and electrically connected with the tenth row of light-emitting elements. For other areas of the display area, two rows of pixel circuits corresponding to two connected light-emitting elements form a pixel circuit group 70. The two rows of pixel circuits 7 belonging to a pixel circuit group 70 are arranged between the two rows of light-emitting elements 25 corresponding to their connection, that is, the spacing S between the two rows of pixel circuits 7 belonging to a pixel circuit group 70 is less than the spacing M between two adjacent rows of light-emitting elements 25 (closely arranged); while the spacing T between two adjacent pixel circuit groups 70 is greater than the spacing M between two adjacent rows of light-emitting elements 25.

[0070] It can be understood that the spacing between the structure A and the structure B described in the embodiment of the present application refers to the distance between the centers of the structure A and the structure B along a certain direction; for two structures with the same shape and size, the spacing between them can also be the distance between the same sides.

[0071] In some embodiments, with the center line along the X direction of the bonding electrode 5 as the axis of symmetry, the pixel circuit rows located on the upper and lower sides of the bonding electrode 5 along the column direction of the light-emitting element array are symmetrically arranged.

[0072] In some embodiments, when moving an even number of pixel circuits, the situation of setting a single row of pixel circuits will not occur.

[0073] In some embodiments, as Figure 9 shown, the orthographic projection of the first via 9 on the substrate is located within the orthographic projection area of the end of the bonding electrode 5 on the substrate. Among them, the first via 9 is formed in the substrate and is used to connect the bonding electrode 5 and the bonding connection line 6. By making the orthographic projection of the first via 9 on the substrate located within the orthographic projection area of the end of the bonding electrode 5 on the substrate, on the one hand, the wiring length of the bonding connection line 6 can be reduced to reduce the resistance of the bonding connection line 6 and reduce the attenuation of the transmitted signal on the bonding connection line 6; on the other hand, the distribution range of the bonding connection line 6 can be reduced, which is beneficial to avoiding overlapping with the area where the transistor in the pixel circuit is located and ensuring the uniformity of display brightness.

[0074] In some embodiments, a plurality of first vias 9 are respectively arranged at both ends of the bonding electrode 5. Among them, the plurality of first vias 9 arranged at both ends of the same bonding electrode 5 are connected to the same bonding connection line 6. The arrangement of the plurality of first vias 9 can ensure a more reliable connection between the bonding connection line 6 and the bonding electrode 5 and avoid the bonding electrode 5 being disconnected from the bonding connection line 6 under the extrusion effect when bonding the peripheral circuit.

[0075] In some embodiments, N first vias 9 are correspondingly arranged with the same bonding electrode 5, N is an even number, N / 2 first vias 9 are correspondingly arranged at one end of the bonding electrode 5, and the other N / 2 first vias 9 are correspondingly arranged at the other end of the bonding electrode 5. Among them, the N first vias 9 are arranged in sequence along the length direction of the bonding electrode 5. If N is 4, two are arranged at one end of the bonding electrode 5 and the other two are arranged at the other end of the bonding electrode 5.

[0076] In some embodiments, 2≤N≤8. The length range of the bonding electrode 5 is 0.5 - 1.5 mm. The opening diameter range of the first via 9 is 20 - 50 μm.

[0077] In some embodiments, the pixel circuit 7 is located on the side of the bonding connection line 6 away from the substrate, and a first insulating layer is further provided between the pixel circuit 7 and the bonding connection line 6. A second via is formed in the first insulating layer, and the pixel circuit 7 and the bonding connection line 6 are connected through the second via. Among them, the pixel circuit includes a plurality of device structures such as transistors, capacitors, and resistors. The transistor includes multiple film layers such as an active layer, a gate, a gate insulating layer, a source, and a drain. The first insulating layer may include a plurality of sub-insulating layers, and is not limited to only one insulating layer. The second via formed in the first insulating layer may include a plurality of sub-vias, and the plurality of sub-vias are respectively formed in different sub-insulating layers. The plurality of sub-vias may form nested vias with corresponding positions, or may form vias with staggered positions, as long as it is ensured that each conductive film layer in the pixel circuit 7 can be connected to the corresponding bonding electrode 5 through the corresponding bonding connection line 6.

[0078] In this embodiment, as Figure 10 shown, a plurality of transistors 16 in the pixel circuit are located on the first side 171 of the substrate 17 and are respectively located in a plurality of sub-pixels 8. In some embodiments, a corresponding one of the plurality of transistors 16 is selected from the group consisting of a top-gate structure transistor and a bottom-gate structure transistor. For example, a corresponding one of the plurality of transistors 16 includes a first gate 160, a second gate 161, an active layer 162, a source 163 electrically connected to the active layer 162, and a drain 164 electrically connected to the active layer 162.

[0079] In some embodiments, the surface of the bonding electrode 5 is exposed on the second side 172 of the substrate 17, and the bonding electrode 5 can be connected to the pixel circuit from the second side 172 of the substrate 17. A corresponding one of the plurality of sub-pixels 8 includes a bonding connection line 6, which electrically connects a corresponding one of the plurality of transistors 16 to the bonding electrode 5.

[0080] In some embodiments, the bonding connection line 6 is electrically connected to the signal line 11. In some embodiments, the signal line 11 is selected from the group consisting of a gate line, a data line, a touch signal line, a clock signal line, a high-power voltage line, a low-power voltage line, a common signal line, and a floating signal line. For example, the bonding connection line 6 is electrically connected to the data line, so as to connect a corresponding one of the plurality of transistors 16 to the bonding electrode 5. In some embodiments, the signal line 11 and the bonding connection line 6 are formed in different layers.

[0081] Referring to Figure 10, a corresponding one of the plurality of sub-pixels 8 includes a relay line 18 that connects the bonding connection line 6 to the signal line 11. For example, the bonding connection line 6 connects the bonding electrode 5 to the relay line 18, and the relay line 18 connects the bonding connection line 6 to the signal line 11 (e.g., a data line), so that the bonding connection line 6 electrically connects a corresponding one of the plurality of transistors 16 to the bonding electrode 5. In some embodiments, the signal line 11 and the relay line 18 are formed in different layers. In some embodiments, the relay line 18 and the bonding connection line 6 are formed in different layers.

[0082] In some embodiments, the bonding connection line 6 is electrically connected to the source electrode of a corresponding one of the plurality of transistors 16. In some embodiments, the relay line 18 connects the bonding connection line 6 to the source electrode of a corresponding one of the plurality of transistors 16.

[0083] Referring to Figure 10 , a corresponding one of the plurality of sub-pixels 8 includes a first via 9 that extends through the substrate 17. In some embodiments, the first via 9 exposes a portion of the surface of the bonding electrode 5 that is closer to the bonding connection line 6. In some embodiments, the bonding connection line 6 extends from the first side 171 of the substrate 17 to the second side 172 via the first via 9 to connect to the bonding electrode 5.

[0084] In some embodiments, the display backplane further includes a recess 19 located in the area corresponding to the bonding electrode 5. The recess 19 is located on the second side 172 of the substrate 17, exposing the surface of the bonding electrode 5 that is away from the bonding connection line 6. For example, the recess 19 does not expose any surface of the bonding connection line 6.

[0085] In some embodiments, the display backplane further includes an insulating layer 20, which is located on the second side 172 of the substrate 17. The bonding electrode 5 is located on the side of the insulating layer 20 that is away from the substrate 17. In some embodiments, the first via 9 extends through the substrate 17 and the insulating layer 20 to expose the surface of the bonding electrode 5 that is closer to the bonding connection line 6.

[0086] In some embodiments, the display backplane further includes a plurality of additional insulating layers 21, and each additional insulating layer 21 partially extends into the first vias 9. In some embodiments, each of the plurality of additional insulating layers 21 extends throughout the display area. In some embodiments, the plurality of additional insulating layers 21 includes a passivation layer 210 that extends through the entire display area. For example, the passivation layer 210 extends through the area corresponding to the bonding electrodes 5. In some embodiments, the passivation layer 210 is located on the first side 171 of the substrate 17. In some embodiments, the passivation layer 210 at least partially covers the side surface 91 of the first vias 9. In some embodiments, the plurality of additional insulating layers 21 includes a barrier layer 211 that extends through the entire display area. The barrier layer 211 extends through the area corresponding to the bonding electrodes 5. The barrier layer 211 is located on the side of the passivation layer 210 and the bonding connection lines 6 away from the substrate 17.

[0087] In some embodiments, the plurality of additional insulating layers 21 further includes a buffer layer 212 that extends through the entire display area. The buffer layer 212 is located on the side of the barrier layer 211 away from the substrate 17. In some embodiments, a corresponding one of the plurality of transistors 16 includes an active layer 162, which is located on the side of the buffer layer 212 away from the substrate 17.

[0088] In some embodiments, the display backplane further includes a first gate insulating layer 22 that extends through the entire display area. The first gate insulating layer 22 is located on the side of the buffer layer 212 away from the barrier layer 211. In some embodiments, a corresponding one of the plurality of transistors 16 includes a first gate 160, which is located on the side of the first gate insulating layer 22 away from the active layer 162.

[0089] In some embodiments, the display backplane further includes a second gate insulating layer 23 that extends through the entire display area. The second gate insulating layer 23 is located on the side of the first gate insulating layer 22 away from the buffer layer 212. In some embodiments, a corresponding one of the plurality of transistors 16 includes a second gate 161, which is located on the side of the second gate insulating layer 23 away from the first gate 160.

[0090] In some embodiments, the display backplane further includes an interlayer dielectric layer 24 that extends through the display area. The interlayer dielectric layer 24 is located on the side of the second gate insulating layer 23 away from the first gate insulating layer 22. In some embodiments, the signal lines 11 are located on the side of the interlayer dielectric layer 24 away from the substrate 17.

[0091] In some embodiments, the source 163 of each of the plurality of transistors 16 extends through the first gate insulating layer 22, the second gate insulating layer 23, and the interlayer dielectric layer 24 to connect the active layer 162 to the signal line 11. In some embodiments, the drain 164 of each of the plurality of transistors 16 extends through the first gate insulating layer 22, the second gate insulating layer 23, and the interlayer dielectric layer 24 to connect the active layer 162 to a corresponding one of the plurality of light-emitting elements 25.

[0092] In some embodiments, the source 163 of each of the plurality of transistors 16 extends through the first gate insulating layer 22, the second gate insulating layer 23, and the interlayer dielectric layer 24 to connect to the relay line 18. In some embodiments, the source 163 of each of the plurality of transistors 16 extends through the first gate insulating layer 22, the second gate insulating layer 23, and the interlayer dielectric layer 24 to the bonding connection line 6.

[0093] In some embodiments, the display backplane further includes a first planarization layer 26 on a side of the interlayer dielectric layer 24 away from the second gate insulating layer 23. In some embodiments, the first planarization layer 26 extends through the display area.

[0094] In some embodiments, the display backplane further includes a second planarization layer 27 on a side of the first planarization layer 26 away from the interlayer dielectric layer 24. The second planarization layer 27 extends through the display area.

[0095] In some embodiments, the display backplane further includes: a second passivation layer 28 on a side of the second planarization layer 27 away from the first planarization layer 26; and a first contact pad 29 and a second contact pad 30 on a side of the second passivation layer 28 away from the second planarization layer 27. In some embodiments, the first contact pad 29 is electrically connected to the drain 164 of a corresponding one of the plurality of transistors 16. In some embodiments, the second contact pad 30 is electrically connected to the common signal line. In some embodiments, a third passivation layer 32 on a side of the second passivation layer 28 away from the substrate 17 is further included, which is mainly used for insulating and isolating the first contact pad 29 and the second contact pad 30 and exposing the surfaces of the first contact pad 29 and the second contact pad 30 for connection to the corresponding electrodes of the light-emitting elements.

[0096] For example, each of the plurality of light-emitting elements 25 is a micro light-emitting diode (MicroLED) having a cathode and an anode. The first contact pad 29 and the second contact pad 30 are electrically connected to the cathode and the anode of the micro light-emitting diode respectively through vias formed in the third passivation layer 32.

[0097] In some embodiments, such as Figure 6As shown, the display backplane further includes a shift register 4. The shift register 4 is disposed on the side of the bonding connection line 6 away from the substrate, and the positive projection of the shift register 4 on the substrate is at least partially located within the positive projection of the bonding electrode 5 that provides signals for it; one end of the shift register 4 is connected to the bonding electrode 5 through the bonding connection line 6, and the other end is connected to the pixel circuit 7.

[0098] In some embodiments, the shift register 4 and the pixel circuit 7 are disposed on the same layer. The shift register 4 is located in the region between two adjacent columns of pixel circuits 7. The first insulating layer further extends between the shift register 4 and the bonding connection line 6. A third via is formed in the first insulating layer. The shift register 4 is connected to the bonding connection line 6 through the third via to be connected to the bonding electrode 5 through the bonding connection line 6.

[0099] Among them, the shift register 4 requires signals such as a trigger signal, a clock signal, and a power signal to operate. These signals are generated by the peripheral circuit and then accessed to the shift register 4 through the bonding electrode 5 and the bonding connection line 6. The first insulating layer may include multiple sub-insulating layers, and is not limited to only one insulating layer. The third via formed in the first insulating layer may include multiple sub-vias. The multiple sub-vias are respectively formed in different sub-insulating layers. The multiple sub-vias may form nested vias with corresponding positions, or may form vias with staggered positions, as long as it is ensured that each signal line in the shift register 4 can be connected to the corresponding bonding electrode 5 through the corresponding bonding connection line 6.

[0100] In the related art, the shift register is disposed around the display backplane, resulting in a large wiring area and a long length of the bonding connection line 6 connecting the bonding electrode and the shift register. This not only increases the loss of the electrical signal, but also the overlapping area between the bonding connection line 6 and the transistor conductive film layer in the pixel circuit 7 is large, making the brightness uniformity of the display panel using this display backplane very poor. In this embodiment, the above setting position of the shift register 4 can, on the one hand, reduce the wiring length of the bonding connection line 6 to reduce the resistance of the bonding connection line 6 and reduce the loss of the transmitted signal on the bonding connection line 6; on the other hand, it can reduce the distribution range of the bonding connection line 6, which is beneficial to avoiding the overlap between the bonding connection line 6 and the transistor conductive layer in the pixel circuit 7, ensuring the display brightness uniformity of the display panel using this display backplane.

[0101] In some embodiments, the shift register 4 includes a plurality of cascaded stages, and the plurality of stages are arranged in the column direction Y of the pixel circuits 7. The shift register 4 includes a plurality of transistors, and the pixel circuits 7 include a plurality of transistors. Each film layer (such as the gate, gate insulating layer, active layer, source, and drain) of the transistors in the shift register 4 is provided on the same layer as the corresponding film layer (such as the gate, gate insulating layer, active layer, source, and drain) of the transistors in the pixel circuits 7. The pixel circuits 7 in the same row are connected to the same scan signal line, and each stage in the shift register 4 is respectively connected to each scan signal line.

[0102] In some embodiments, multiple sets of shift registers 4 are provided on the display backplane, and the multiple sets of shift registers 4 are arranged in sequence in the row direction X of the pixel circuits 7. Such an arrangement can facilitate the corresponding connection of each set of shift registers 4 to the bonding electrodes 5 that provide signals for them in sequence, so as to facilitate the peripheral circuit to provide signals for them through the bonding electrodes 5.

[0103] In some embodiments, the pixel circuits in the same row are connected to the same scan signal line, and two sets of shift registers are provided on the display backplane, which are respectively connected to both ends of each scan signal line and output synchronously, so as to achieve bilateral driving of the pixel circuits in each row.

[0104] In some embodiments, the pixel circuits in the same row are connected to the same scan signal line, and two sets of shift registers are provided on the display backplane, a working shift register and a standby shift register; wherein the working shift register is connected to each scan signal line, and the standby shift register corresponds to each scan signal line and is only connected to each scan signal line and enabled when the working shift register fails.

[0105] In some embodiments, the pixel circuits in the same row are connected to the same scan signal line and the same light emission enable signal line, and two sets of shift registers are provided on the display backplane, wherein one set of shift registers is connected to the row scan signal line; the other set of shift registers is connected to the light emission enable signal line.

[0106] In some embodiments, such as Figure 11As shown, the pixel circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first storage capacitor C1, and a light-emitting element D. Among them, the first pole of the first transistor T1 is connected to the initial voltage signal terminal Vint. The second pole of the first transistor T1 is connected to the second pole of the first storage capacitor C1, the first pole of the second transistor T2, and the control pole of the third transistor T3. The control pole of the first transistor T1 is connected to the reset signal terminal Reset. The second pole of the second transistor T2 is connected to the second pole of the third transistor T3 and the first pole of the sixth transistor T6. The control pole of the second transistor T2 is connected to the gate scan signal line Gate. The first pole of the third transistor T3 is connected to the first power supply voltage terminal VDD. The first pole of the fourth transistor T4 is connected to the data line Data. The second pole of the fourth transistor T4 is connected to the second pole of the fifth transistor T5, the second pole of the seventh transistor T7, and the first pole of the first storage capacitor C1. The control pole of the fourth transistor T4 is connected to the gate scan signal line Gate. The first pole of the fifth transistor T5 is connected to the reference voltage signal terminal Vref. The control pole of the fifth transistor T5 is connected to the light-emitting enable signal line EM. The second pole of the sixth transistor T6 is connected to the first pole of the light-emitting element D. The control pole of the sixth transistor T6 is connected to the light-emitting enable signal line EM. The first pole of the seventh transistor T7 is connected to the reference voltage signal terminal Vref. The control pole of the seventh transistor T7 is connected to the reset signal terminal Reset. The second pole of the light-emitting element is connected to the second power supply voltage terminal VSS.

[0107] In some embodiments, the shift register circuit includes a plurality of cascaded shift registers 4, where the structure of each shift register 4 is as Figure 12As shown in the figure. The shift register 4 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second storage capacitor C2, and a third storage capacitor C3. Among them, the first pole of the eighth transistor T8 is connected to the signal input terminal Input. The second end of the eighth transistor T8 is connected to the N1 node. The control pole of the eighth transistor T8 is connected to the first clock signal terminal CLK. The first pole of the ninth transistor T9 is connected to the first clock signal terminal CLK. The second pole of the ninth transistor T9 is connected to the N2 node. The control pole of the ninth transistor T9 is connected to the N1 node. The first pole of the tenth transistor T10 is connected to the low-level signal terminal VGL. The second pole of the tenth transistor T10 is connected to the N2 node. The control pole of the tenth transistor T10 is connected to the first clock signal terminal CLK. The first pole of the eleventh transistor T11 is connected to the high-level signal terminal VGH and the second pole of the third storage capacitor C3. The second pole of the eleventh transistor T11 is connected to the signal output terminal Output. The control pole of the eleventh transistor T11 is connected to the N2 node. The first pole of the third storage capacitor C3 is connected to the N2 node. The first pole of the twelfth transistor T12 is connected to the second clock signal terminal CLKB. The second pole of the twelfth transistor T12 is connected to the second pole of the second storage capacitor C2 and the signal output terminal Output. The control pole of the twelfth transistor T12 is connected to the first pole of the second storage capacitor C2. The first pole of the thirteenth transistor T13 is connected to the high-level signal terminal VGH. The second pole of the thirteenth transistor T13 is connected to the first pole of the fourteenth transistor T14. The control pole of the thirteenth transistor T13 is connected to the N2 node. The second pole of the fourteenth transistor T14 is connected to the N1 node. The control pole of the fourteenth transistor T14 is connected to the second clock signal terminal CLKB. The first pole of the fifteenth transistor T15 is connected to the N1 node. The second pole of the fifteenth transistor T15 is connected to the first pole of the second storage capacitor C2. The control pole of the fifteenth transistor T15 is connected to the low-level terminal VGL.

[0108] In some embodiments, as Figure 6 shown, the display backplane further includes a data selection circuit 10. The orthographic projection of the data selection circuit 10 on the substrate overlaps with the orthographic projection of the bonding connection line 6 on the substrate. One end of the data selection circuit 10 is connected to the bonding electrode 5 through the bonding connection line 6, and the other end is connected to the data line 15; the data line 15 is configured to connect the pixel circuit 7 and the data selection circuit 10. Among them, the data selection circuit 10 is disposed in the display area 3 in a region close to the bonding area 1; on the one hand, it can greatly shorten the wiring length of the bonding connection line 6 to reduce the resistance of the bonding connection line 6 and reduce the loss of the transmitted signal on the bonding connection line 6; on the other hand, it can greatly reduce the distribution range of the bonding connection line 6, which is beneficial to avoiding overlapping with the transistor conductive layer in the pixel circuit 7 and ensuring the display brightness uniformity.

[0109] In some embodiments, the data selection circuit 10 is located on the side of the bonding connection line 6 away from the substrate. The data selection circuit 10 is arranged on the same layer as the pixel circuit 7, and the data selection circuit 10 is staggered from the pixel circuit 7 and the shift register 4; the first insulating layer also extends between the data selection circuit 10 and the bonding connection line 6, and a fourth via is formed in the first insulating layer. The data selection circuit 10 is connected to the bonding connection line 6 through the fourth via to be connected to the bonding electrode 5 through the bonding connection line 6. Wherein, the first insulating layer may include a plurality of sub-insulating layers, and is not limited to only one insulating layer. The fourth via formed in the first insulating layer may include a plurality of sub-vias, and the plurality of sub-vias are respectively formed in different sub-insulating layers. The plurality of sub-vias may form nested vias with corresponding positions, or may form vias with staggered positions, as long as it is ensured that the data selection circuit 10 can be connected to the corresponding bonding electrode 5 through the corresponding bonding connection line 6.

[0110] In some embodiments, the plurality of bonding electrodes 5 are arranged along the row direction X of the pixel circuit 7, and the length direction of the plurality of bonding electrodes 5 is parallel to the column direction Y of the pixel circuit 7; the shape of the data selection circuit 10 includes a strip shape, and the length direction of the data selection circuit 10 is parallel to the row direction X of the pixel circuit 7. Since the arrangement direction of the data lines 15 is along the row direction X of the pixel circuit 7, the length direction of the data selection circuit 10 is parallel to the row direction X of the pixel circuit 7, which is beneficial to the respective selection output ends of the data selection circuit 10 being respectively connected to the respective data lines 15, and the connection lines therebetween will not have too long routing.

[0111] In some embodiments, there are a plurality of data selection circuits 10, and the plurality of data selection circuits 10 are parallel to each other and are arranged in sequence along the column direction Y of the pixel circuit 7. The plurality of data selection circuits 10 are respectively used for the opening and closing selection of different data lines 15. For a display panel with a relatively high resolution, the number of data lines 15 is large. The setting of the plurality of data selection circuits 10 can avoid too many bonding electrodes 5 connected to the data lines 15 occupying too much space, and at the same time can ensure that the opening and closing selection of each data line 15 can be realized through a smaller number of bonding electrodes 5.

[0112] In some embodiments, such as Figure 13As shown, the data selection circuit 10 includes two parts: one of which includes the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18. Among them, the first poles of the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are connected together, and are connected to a source driver (not shown in the figure) through a data voltage introduction line Data1 connected by a bonding electrode 5. The second pole of the sixteenth transistor T16 is connected to the first data line Data11, the second pole of the seventeenth transistor T17 is connected to the second data line Data12, the second pole of the eighteenth transistor T18 is connected to the third data line Data13, and the control poles of the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are respectively connected to different output terminals of a timing controller (not shown in the figure). The other data selection circuit 10 includes the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21. Among them, the first poles of the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 are connected together, and are connected to a source driver (not shown in the figure) through a data voltage introduction line Data2 connected by another bonding electrode 5. The second pole of the nineteenth transistor T19 is connected to the fourth data line Data21, the second pole of the twentieth transistor T20 is connected to the fifth data line Data22, the second pole of the twenty-first transistor T21 is connected to the sixth data line Data23, and the control poles of the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 are respectively connected to different output terminals of a timing controller (not shown in the figure).

[0113] The transistors used in the above examples can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetric, there is no difference between the source and drain.

[0114] In order to distinguish the source and drain of the transistors in the above examples, one pole is called the first pole, the other pole is called the second pole, and the gate is called the control pole. Moreover, according to the characteristics of the transistors, the transistors can be divided into N-type and P-type. When a P-type transistor is used, the first pole is the source of the P-type transistor, the second pole is the drain of the P-type transistor, and when a low level is input to the gate, the source and drain are turned on. When an N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and when a high level is input to the gate, the source and drain are turned on.

[0115] In addition, each transistor in the above pixel driving sub-circuit is described by taking an N-type transistor as an example. It can be imagined that using a P-type transistor to implement it can be easily thought of by those skilled in the art without creative labor. Therefore, it is also within the protection scope of the present disclosure.

[0116] In some embodiments, a sub-pixel includes a pixel circuit 7 and a light-emitting element; the pixel circuits 7 are connected to the light-emitting elements in a one-to-one correspondence; one pixel circuit 7 can drive one light-emitting element to emit light; the pixel circuit 7 includes at least an electrically connected capacitor and a thin-film transistor.

[0117] Based on the above structure of the display backplane, the present embodiment further provides a method for manufacturing the display backplane, including sequentially manufacturing a plurality of bonding electrodes, a substrate and a first via hole therein, a plurality of bonding connection lines, and a plurality of pixel circuits on the substrate; the plurality of bonding electrodes are in one-to-one correspondence and connected to the plurality of bonding connection lines; the plurality of bonding electrodes and the plurality of bonding connection lines are respectively located on two opposite surfaces of the substrate, and the plurality of pixel circuits and the plurality of bonding connection lines are located on the same side of the substrate; one end of the plurality of bonding connection lines is connected to the bonding electrode through the first via hole; the other end of at least some of the plurality of bonding connection lines is connected to the pixel circuit; at least one of the plurality of bonding electrodes and the plurality of bonding connection lines does not coincide with the positive projection of the pixel circuit on the substrate.

[0118] Among them, as Figure 10 for each structural film layer of the display backplane, various suitable materials can be used to manufacture the substrate. Examples of materials suitable for manufacturing the substrate include, but are not limited to, polyimide and polyester, etc.

[0119] Various suitable materials can be used to manufacture the bonding electrodes. Examples of materials suitable for manufacturing the bonding electrodes include, but are not limited to, titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), or an alloy composed of two of these metals.

[0120] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture the insulating layer. For example, the insulating material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable insulating materials include, but are not limited to, polyimide, silicon oxide (SiO y ), silicon nitride (SiN y , such as Si3N4), and silicon oxynitride (SiO x N y ). For example, the insulating layer is made of silicon oxide (SiO2) and is configured to protect the bonding electrode from exposure to air and moisture. Using silicon oxide (SiO2) to form the insulating layer can increase the adhesion between the insulating layer and the substrate.

[0121] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture the passivation layer. For example, the material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable materials include, but are not limited to, polyimide, silicon oxide (SiO y ), silicon nitride (SiN y , for example, Si3N4), and silicon oxynitride (SiOx N y )。

[0122] A variety of suitable materials can be used to fabricate the bonding connection lines. Examples of materials suitable for fabricating the bonding connection lines include, but are not limited to, copper (Cu), aluminum (Al), and combinations of copper and aluminum.

[0123] A variety of suitable conductive electrode materials and a variety of suitable manufacturing methods can be used to fabricate the source and drain. In some embodiments, the conductive electrode material includes a metal material. Examples of suitable metal materials include, but are not limited to, molybdenum, gold, and aluminum.

[0124] A variety of suitable insulating materials and a variety of suitable manufacturing methods can be used to fabricate the buffer layer. For example, the insulating material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of materials suitable for fabricating the buffer layer include, but are not limited to, silicon oxide (SiO x )、silicon nitride (SiN x ) or combinations thereof. In some embodiments, the buffer layer can have a single layer structure or a stacked structure including two or more sub-layers (e.g., a stacked structure including a silicon oxide sub-layer and a silicon nitride sub-layer). In some embodiments, the thickness of the buffer layer is in the range of about 100 nm to about 400 nm. For example, the buffer layer can include a silicon oxide sub-layer with a thickness in the range of about 50 nm to about 100 nm and a silicon nitride sub-layer with a thickness in the range of about 100 nm to about 300 nm.

[0125] A variety of suitable dielectric materials and a variety of suitable manufacturing methods can be used to fabricate the interlayer dielectric layer. For example, the dielectric material can be deposited on the substrate by a plasma enhanced chemical vapor deposition process. Examples of materials suitable for fabricating the interlayer dielectric layer include, but are not limited to, silicon oxide (SiO y )、silicon nitride (SiN y , such as Si3N4), silicon oxynitride (SiO x N y )。

[0126] A variety of suitable materials can be used to fabricate the first contact pad and the second contact pad. In some embodiments, a respective one of the first contact pad and the second contact pad includes two sub-layers. The first sub-layer of the two sub-layers is formed using a metal (including, but not limited to, molybdenum (Mo), titanium (Ti), and combinations of molybdenum (Mo) and titanium (Ti)), and the second sub-layer of the two sub-layers is formed using copper (Cu). In some embodiments, the second sub-layer is formed on a side of the first sub-layer away from the substrate.

[0127] In some embodiments, the method for manufacturing the display backplane further includes a step of peeling the substrate. The substrate is made of glass or quartz. In order to achieve the flexibility of the display backplane, after forming each film layer in the display backplane, the rigid substrate can be peeled off. Since the remaining substrate is a flexible material, the flexible deformation of the display backplane can be achieved.

[0128] Embodiments of the present disclosure further provide a display backplane. As Figure 14 shown, based on the display backplane provided in the above embodiments, the display backplane further includes a plurality of dummy circuits 12 disposed on the substrate, and at least one of the plurality of bonding electrodes 5 and the plurality of bonding connection lines 6 overlaps with at least one of the plurality of dummy circuits 12 in the orthographic projection on the substrate. Among them, the dummy circuit 12 and the bonding connection line 6 are located on the same side of the substrate; the dummy circuit 12 is located in the bonding area and the bonding wiring area, and the circuit structure of the dummy circuit 12 is the same as that of the pixel circuit 7. However, the dummy circuit 12 is not connected to other components in the display backplane, for example, it is not electrically connected to any light-emitting element 25, so that it will not drive the light-emitting element 25 to emit light; that is, it will not affect the normal operation of the display backplane.

[0129] If no pixel circuit is provided in the bonding area and the bonding wiring area, it will make the display backplane significantly different in structure from other areas of the display area in the bonding area and the bonding wiring area, such as different thicknesses at different positions of the backplane, etc. Further, it will also cause uneven light-emitting brightness of the display panel using this display backplane. By providing dummy circuits 12 with the same circuit structure as the pixel circuit 7 in the bonding area and the bonding wiring area, the circuit structure of the bonding area and the bonding wiring area can be made consistent with the circuit structure of other areas of the display area, thereby ensuring the uniformity of the brightness of the display panel using this display backplane.

[0130] In some embodiments, the light-emitting elements 25 in the display area are uniformly arranged in an array, and the pixel circuits 7 of the light-emitting elements 25 located in the bonding area and the bonding wiring area are located outside the bonding area and the bonding wiring area to ensure the normal driving of the light-emitting elements 25 located in the bonding area and the bonding wiring area. With such a setting, it is possible to avoid the coupling effect between the bonding connection line 6 and the bonding electrode 5 and the transistor conductive layer in the pixel circuit 7, thereby avoiding the influence of the coupling effect on the light-emitting brightness of the display panel and ensuring the uniformity of the display brightness of the display panel.

[0131] In some embodiments, the plurality of dummy circuits 12 are arranged in a uniform array, and adjacent n rows of dummy circuits 12 form a dummy circuit group 120, where n is an integer and 2 ≤ n ≤ 5; within the dummy circuit group 120, the distance G between any two adjacent rows of dummy circuits 12 is greater than 0 and less than or equal to the distance M between two adjacent rows of light-emitting elements 25. As Figure 12As shown, within the dummy circuit group 120, the pitch G between any two adjacent rows of dummy circuits 12 satisfies: 0 < G ≤ M. In some embodiments, within the dummy circuit group 120, the number of rows of dummy circuits is equal to the number of rows of pixel circuits within one of the pixel circuit groups 70", both being two rows. The pitch G between two adjacent rows of dummy circuits 12 is equal to the pitch S1 between two adjacent rows of pixel circuits 7 within one of the pixel circuit groups 70". This setting makes the arrangement of the dummy circuits 12 exactly the same as that of the pixel circuits 7, thereby further enabling the circuit structures in the bonding area and the bonding wiring area to be consistent with those in other areas of the display area, and further ensuring the brightness uniformity of the display panel using this display backplane.

[0132] In some embodiments, the pitch H between the dummy circuit group 120 and the adjacent pixel circuit group 70' is greater than the pitch M between two adjacent light-emitting elements 25 and less than or equal to twice the pitch M between two adjacent light-emitting elements 25. That is, the pitch H between the dummy circuit group 120 and the adjacent pixel circuit group 70' satisfies: M < H ≤ 2M. If there are multiple dummy circuit groups 120, the pitch X (not shown in the figure) between adjacent dummy circuit groups 120 satisfies: M < X ≤ 2M. Such a setting makes the arrangement of the dummy circuits 12 and the pixel circuits 7 in the adjacent area between the distribution areas of the dummy circuits 12 and the pixel circuits 7 exactly the same, thereby further enabling the circuit structures in the bonding area and the bonding wiring area to be consistent with those in other areas of the display area, and further ensuring the brightness uniformity of the display panel using this display backplane.

[0133] The other structures of the display backplane and the manufacturing method of the display backplane in this embodiment are the same as those in the above embodiments, and will not be elaborated here.

[0134] The embodiments of the present disclosure also provide a display backplane. Different from the above embodiments, a data selection circuit may not be provided in the display backplane, that is, according to the resolution of the display panel, the number of output data signal channels of the driving chip (IC) is sufficient, and in this case, the data selection circuit may not be provided. In the case where the data selection circuit is not provided, the data lines in the display backplane are connected to the corresponding bonding electrodes through bonding connection lines. Through holes are formed in the insulating layer between the data lines and the bonding connection lines, and the data lines and the bonding connection lines are connected through the through holes. The through holes can be formed in the area of the display area close to the bonding area, so as to shorten the wiring length of the bonding connection lines, reduce the resistance of the bonding connection lines, and reduce the loss of the transmitted signal on the bonding connection lines; the through holes can also be formed in the area of the display area where no pixel circuits are distributed, so as to avoid the overlap of the bonding connection lines and the transistor conductive layer in the pixel circuits and ensure the brightness uniformity of the display.

[0135] In this embodiment, other structures of the display backplane and the manufacturing method of the display backplane are the same as those in the above embodiment, and will not be described in detail here.

[0136] In the display backplane provided in the above embodiment, by arranging the pixel circuit in the area of the display region other than the bonding area and the bonding wiring area, it is possible to avoid the overlap between the bonding electrode and the bonding connection line and the transistor conductive layer (such as the active layer, gate, etc.) in the pixel circuit, thereby avoiding the coupling effect between the bonding electrode and the bonding connection line and the transistor conductive layer, and further avoiding the influence of the coupling effect on the emission brightness of the display panel, and ensuring the uniformity of the display brightness of the display panel; by making the orthographic projection of the first via hole on the substrate located within the orthographic projection area of the end of the bonding electrode on the substrate, on the one hand, it is possible to reduce the wiring length of the bonding connection line connecting the bonding electrode through the first via hole, so as to reduce the resistance of the bonding connection line and reduce the loss of the transmitted signal on the bonding connection line; on the other hand, it can reduce the distribution range of the bonding connection line, which is beneficial to avoiding the overlap with the transistor conductive layer in the pixel circuit and ensuring the uniformity of the display brightness; by making the orthographic projection of the shift register on the substrate at least partially located within the orthographic projection area of the bonding electrode that provides signals for it on the substrate, on the one hand, it is possible to reduce the wiring length of the bonding connection line connecting the shift register and the bonding electrode, so as to reduce the resistance of the bonding connection line and reduce the loss of the transmitted signal on the bonding connection line; on the other hand, it can reduce the distribution range of the bonding connection line, which is beneficial to avoiding the overlap with the transistor conductive layer in the pixel circuit and ensuring the uniformity of the display brightness of the display panel using this display backplane; by arranging the data selection circuit in the area of the display region close to the bonding area, on the one hand, it is possible to greatly shorten the wiring length of the bonding connection line connecting the data selection circuit and the bonding electrode, so as to reduce the resistance of the bonding connection line and reduce the loss of the transmitted signal on the bonding connection line; on the other hand, it can greatly reduce the distribution range of the bonding connection line, which is beneficial to avoiding the overlap with the transistor conductive layer in the pixel circuit and ensuring the uniformity of the display brightness.

[0137] In a second aspect, an embodiment of the present disclosure further provides a display device, including the display backplane in any of the above embodiments.

[0138] By adopting the display backplane in any of the above embodiments, the uniformity of the display brightness of the display device is improved.

[0139] The display device provided in the embodiments of the present disclosure can be any product or component with a display function, such as an OLED panel, an OLED TV, a Micro LED panel, a Micro LED TV, a monitor, a mobile phone, a navigator, etc.

[0140] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A display backplane, comprising a substrate, characterized in that, A plurality of pixel circuits, a plurality of bonding electrodes, and a plurality of bonding connection lines respectively corresponding to and connected to the bonding electrodes are provided on the substrate; the plurality of bonding electrodes and the plurality of bonding connection lines are respectively located on two opposite surfaces of the substrate, and the plurality of pixel circuits and the plurality of bonding connection lines are located on the same side of the substrate; One end of each of the plurality of bonding connection lines is connected to the bonding electrode through a first via hole formed in the substrate; the other ends of at least some of the plurality of bonding connection lines are connected to the pixel circuits; At least one of the plurality of bonding electrodes and the plurality of bonding connection lines does not overlap with the positive projection of the pixel circuit on the substrate; It further includes a plurality of light-emitting elements arranged in a uniform array, and the plurality of pixel circuits are respectively connected to the light-emitting elements in one-to-one correspondence; in the pixel circuit array, adjacent n rows of pixel circuits form a pixel circuit group; wherein, n is an integer, and 2 ≤ n ≤ 5; The pitch in the column direction along the arrangement of the pixel circuits between adjacent two rows of the light-emitting elements is M, and within the pixel circuit group, the pitch S between any adjacent two rows of the pixel circuits satisfies: 0 < S ≤ M; The length of the bonding electrode in the column direction along the arrangement of the pixel circuits is L, and the pitch T between adjacent two pixel circuit groups satisfies: M < T ≤ (2∙p + 1)∙M, where p = [L / M]; 2. The display backplane according to claim 1, wherein It further includes a plurality of dummy circuits provided on the substrate, and at least one of the plurality of bonding electrodes and the plurality of bonding connection lines partially overlaps with at least one of the plurality of dummy circuits in the positive projection on the substrate; 3. The display backplane according to claim 2, wherein The circuit structure of the dummy circuit is the same as that of the pixel circuit; 4. The display backplane according to claim 3, characterized in that The plurality of dummy circuits are arranged in a uniform array, and adjacent n rows of the dummy circuits form a dummy circuit group, wherein, n is an integer, and 2 ≤ n ≤ 5; Within the dummy circuit group, the pitch G between any adjacent two rows of the dummy circuits satisfies: 0 < G ≤ M; 5. The display backplane according to claim 4, wherein The pitch H between the dummy circuit group and the adjacent pixel circuit group satisfies: M < H ≤ 2M; the pitch X between the plurality of dummy circuit groups satisfies: M < X ≤ 2M; 6. The display backplane according to any one of claims 1-5, characterized in that, The positive projection of the first via hole on the substrate is located within the positive projection area of the end of the bonding electrode on the substrate; 7. The display backplane according to claim 6, wherein The first via hole includes a plurality of them, and the plurality of first via holes are respectively correspondingly arranged at both ends of the bonding electrode, and the first via holes are arranged in sequence along the length direction of the bonding electrode; 8. The display backplane according to claim 7, wherein, The first via hole includes N, N is an even number, N / 2 first via holes are correspondingly arranged at one end of the bonding electrode, and the other N / 2 first via holes are correspondingly arranged at the other end of the bonding electrode; 9. The display backplane according to claim 8, wherein The pixel circuit is located on the side of the bonding connection line away from the substrate, and a first insulating layer is further provided between the pixel circuit and the bonding connection line, and a second via hole is formed in the first insulating layer, and the pixel circuit and the bonding connection line are connected through the second via hole; 10. The display backplane according to claim 9, wherein It further includes a shift register which is disposed on a side of the bonding connection line away from the substrate, and a positive projection of the shift register on the substrate is at least partially located within a positive projection of the bonding electrode that provides signals to it on the substrate; One end of the shift register is connected to the bonding electrode through the bonding connection line, and the other end is connected to the pixel circuit.

11. The display backplane according to claim 10, wherein The shift register is disposed on the same layer as the pixel circuit, and the shift register is located in a region between two adjacent columns of the pixel circuits; The first insulating layer further extends between the shift register and the bonding connection line, and a third via hole is further formed in the first insulating layer. The shift register is connected to the bonding connection line through the third via hole so as to be connected to the bonding electrode through the bonding connection line.

12. The display backplane according to claim 11, wherein It further includes a data selection circuit. A positive projection of the data selection circuit on the substrate partially overlaps with a positive projection of the bonding connection line on the substrate. One end of the data selection circuit is connected to the bonding electrode through the bonding connection line, and the other end is connected to a data line; The data line is configured to connect the pixel circuit and the data selection circuit.

13. The display backplane according to claim 12, wherein The data selection circuit is located on a side of the bonding connection line away from the substrate. The data selection circuit is disposed on the same layer as the pixel circuit, and the data selection circuit is staggered from the pixel circuit and the shift register; The first insulating layer further extends between the data selection circuit and the bonding connection line, and a fourth via hole is formed in the first insulating layer. The data selection circuit is connected to the bonding connection line through the fourth via hole so as to be connected to the bonding electrode through the bonding connection line.

14. The display backplane according to claim 13, characterized in that, The multiple bonding electrodes are arranged along a row direction in which the pixel circuits are arranged, and a length direction of the multiple bonding electrodes is parallel to a column direction in which the pixel circuits are arranged; The data selection circuit has a strip shape, and a length direction of the data selection circuit is parallel to the row direction in which the pixel circuits are arranged.

15. The display backplane according to claim 14, wherein There are multiple data selection circuits. The multiple data selection circuits are parallel to each other and are sequentially arranged along the column direction in which the pixel circuits are arranged.

16. The display backplane according to claim 1, wherein The pixel circuit at least includes a capacitor and a thin film transistor which are electrically connected.

17. A display device, characterized in that, It includes the display backplane according to any one of claims 1-16.

18. A method for preparing a display backplane, characterized in that, It includes preparing multiple bonding electrodes, a substrate and first vias therein, multiple bonding connection lines and multiple pixel circuits on the substrate in sequence; the multiple bonding electrodes correspond to and are connected to the multiple bonding connection lines one by one; the multiple bonding electrodes and the multiple bonding connection lines are respectively located on two opposite surfaces of the substrate, and the multiple pixel circuits and the multiple bonding connection lines are located on the same side of the substrate; One end of the multiple bonding connection lines is connected to the bonding electrode through the first via hole; the other ends of at least some of the multiple bonding connection lines are connected to the pixel circuit; At least one of the multiple bonding electrodes and the multiple bonding connection lines does not coincide with a positive projection of the pixel circuit on the substrate; It further includes preparing multiple light-emitting elements; The multiple light-emitting elements are arranged in a uniform array, and the multiple pixel circuits are connected to the light-emitting elements in a one-to-one correspondence; in the pixel circuit array, adjacent n rows of pixel circuits form a pixel circuit group; wherein, n is an integer, and 2 ≤ n ≤ 5; The pitch in the column direction along the arrangement of the pixel circuits between two adjacent rows of the light-emitting elements is M, and within the pixel circuit group, the pitch S between any two adjacent rows of the pixel circuits satisfies: 0 < S ≤ M; The length of the bonding electrode in the column direction along the arrangement of the pixel circuits is L, and the pitch T between two adjacent pixel circuit groups satisfies: M < T ≤ (2∙p + 1)∙M, where p = [L / M].

19. The method for preparing the display backplane according to claim 18, wherein, It further includes the step of peeling the substrate.

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