Display panel, manufacturing method thereof and display device

Abstract

A display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate (100) having a display area (1), a peripheral area (2) and a pad area (5); a first barrier wall (201) located in the peripheral area (2) and surrounding the display area (1); a planarization layer (101) located in the first barrier wall (201), the first barrier wall (201) and the planarization layer (101) having a first groove (3) therebetween, along the extension direction of the edge of a first side (111) of the planarization layer (101), the edge of the first side (111) comprising a first boundary segment (112) and a second boundary segment (113) connected in sequence; an encapsulation layer (102) covering the planarization layer (101); a touch layer (103) on the encapsulation layer (102), the touch layer (103) comprising a touch signal line (1031) and a touch electrode pattern (1032), the touch electrode pattern (1032) being electrically connected to a pad (501) of the pad area (5) through the touch signal line (1031), and the touch signal line (1031) passing through the first boundary segment (112); wherein the encapsulation layer (102) comprises an organic layer (121), the edge of the organic layer (121) being located in the first groove (3), and the distance (L1) between the edge of the organic layer (121) and the first boundary segment (112) of the planarization layer (101) being greater than the distance (L2) between the edge of the organic layer (121) and the second boundary segment (113).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display, and in particular, to a display panel, a manufacturing method thereof and a display device. BACKGROUND

[0002] A touch screen (TSP for short) integrates a display panel and a touch structure, and can realize display and touch functions simultaneously. SUMMARY

[0003] Embodiments of the present disclosure provide a display panel, a manufacturing method thereof and a display device, which can reduce the problem of touch failure. The technical solutions are as follows:

[0004] In one aspect, the present disclosure provides a display panel, comprising:

[0005] a substrate, the substrate having:

[0006] a display area;

[0007] a peripheral area surrounding a periphery of the display area;

[0008] a pad area located on a side of the peripheral area away from the display area;

[0009] a first barrier wall located in the peripheral area and surrounding the periphery of the display area;

[0010] a planarization layer located in the first barrier wall, the first barrier wall and the planarization layer having a first groove therebetween, an edge of a first side of the planarization layer extending in a direction, the edge of the first side including a first boundary segment and a second boundary segment connected in sequence, the first side being located on the same side of the display area as the pad area;

[0011] an encapsulation layer covering the planarization layer;

[0012] a touch layer on the encapsulation layer, the touch layer including a touch signal line and a touch electrode pattern, one end of the touch signal line being electrically connected to the touch electrode pattern, the other end of the touch signal line extending from the display area to the pad area and being electrically connected to a pad of the pad area, and the touch signal line passing through the first boundary segment;

[0013] wherein the encapsulation layer includes an organic layer, an edge of the organic layer on the same side of the display area as the first side of the planarization layer being located in the first groove, and a distance between the edge of the organic layer and the first boundary segment of the planarization layer being greater than a distance between the edge of the organic layer and the second boundary segment.

[0014] In an implementation form of the display panel, the first side of the planarization layer comprises a first section of slope and a second section of slope connected to each other, a bottom edge of the first section of slope is a first section of boundary, and a bottom edge of the second section of slope is a second section of boundary.

[0015] In a direction perpendicular to a bearing surface of the substrate, a height of the first section of slope is greater than a height of the second section of slope, the height of the first section of slope is a distance from a top surface of the first section of slope to a bottom surface of the substrate in the direction perpendicular to the bearing surface of the substrate, and the height of the second section of slope is a distance from a top surface of the second section of slope to the bottom surface of the substrate in the direction perpendicular to the bearing surface of the substrate.

[0016] In an implementation form of the display panel, a distance between an edge of the first barrier wall opposite to the second section of boundary and the second section of boundary is less than a distance between an edge of the first barrier wall opposite to the first section of boundary and the first section of boundary.

[0017] In an implementation form of the display panel, the display panel further comprises a thin film transistor array layer, and the planarization layer is located on the thin film transistor array layer.

[0018] The thin film transistor array layer comprises gate lines and data lines, the gate lines and the data lines extend from the display area to the pad area and pass through the second section of boundary.

[0019] In an implementation form of the display panel, in an extending direction of an edge of the first side, a length of the organic layer between the first section of boundary and the first barrier wall is between 1 millimeter and 3 millimeters.

[0020] In an implementation form of the display panel, a distance between an edge of the organic layer and the first section of boundary is between 50 micrometers and 150 micrometers.

[0021] In an implementation form of the display panel, the first side of the planarization layer comprises two first sections of boundary, and in an extending direction of an edge of the first side, the two first sections of boundary are respectively located on two sides of the second boundary.

[0022] In an implementation form of the display panel, the organic layer between the first section of boundary and the first barrier wall forms a first section of slope, and an angle of a slope angle of the first section of slope is between 1 degree and 35 degrees.

[0023] In an implementation form of the display panel, the planarization layer comprises a first planarization layer and a second planarization layer.

[0024] The display area further comprises a first pixel definition layer located on the second planarization layer.

[0025] The first planarization layer, the second planarization layer and the first pixel defining layer corresponding to the first segment boundary form a second slope near the part of the first barrier wall, and edges of the first planarization layer, the second planarization layer and the first pixel defining layer corresponding to the first segment boundary coincide.

[0026] In an implementation form of the embodiment of the disclosure, an angle of the slope angle of the second slope is between 35 degrees and 55 degrees.

[0027] In an implementation form of the embodiment of the disclosure, a distance between an edge of the first barrier wall opposite to the second segment boundary and the second segment boundary is smaller than a distance between the edge of the first barrier wall opposite to the second segment boundary and an edge of the first pixel defining layer opposite to the second segment boundary.

[0028] In an implementation form of the embodiment of the disclosure, the display panel further comprises a second barrier wall, the second barrier wall is located in the peripheral region and surrounds the first barrier wall;

[0029] The first barrier wall and the second barrier wall have a second groove therebetween, a height of the second barrier wall is greater than a height of the first barrier wall, a distance between a first surface of the planarization layer and a second surface of the first pixel defining layer is greater than the height of the second barrier wall, the height of the first barrier wall is a distance from a top surface of the substrate to the first surface of the planarization layer in a direction perpendicular to a bearing surface of the substrate, the height of the second barrier wall is a distance from the top surface of the substrate to the first surface of the planarization layer in the direction perpendicular to the bearing surface of the substrate, the first surface of the planarization layer is a surface of the planarization layer close to the substrate, and the second surface of the first pixel defining layer is a surface of the first pixel defining layer away from the substrate.

[0030] In an implementation form of the embodiment of the disclosure, the first barrier wall comprises a third planarization layer, a second pixel defining layer and a spacer layer which are sequentially stacked.

[0031] The second barrier wall comprises the third planarization layer, a fourth planarization layer, the second pixel defining layer and the spacer layer which are sequentially stacked.

[0032] The third planarization layer is in the same layer as the first planarization layer, the fourth planarization layer is in the same layer as the second planarization layer, and the second pixel defining layer is in the same layer as the first pixel defining layer.

[0033] In an implementation form of the embodiment of the disclosure, a difference between the height of the second barrier wall and the height of the first barrier wall is between 0.4 microns and 1.0 microns.

[0034] In an implementation form of the display panel according to the present disclosure, the touch electrode pattern comprises a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged in a cross manner, the touch driving electrodes and the touch sensing electrodes are insulated and spaced apart by the touch insulation layer, each of the touch driving electrodes and each of the touch sensing electrodes are connected to one of the touch signal lines.

[0035] In an implementation form of the display panel according to the present disclosure, the encapsulation layer further comprises a first inorganic encapsulation layer and a second inorganic encapsulation layer, the organic layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0036] In an implementation form of the display panel according to the present disclosure, in the display area, the substrate is stacked with a thin film transistor array layer, the planarization layer, a first pixel definition layer, a spacer layer, a light emitting layer, the encapsulation layer and the touch layer.

[0037] In an implementation form of the display panel according to the present disclosure, in the peripheral area, the substrate is stacked with the thin film transistor array layer, a third planarization layer, a fourth planarization layer, a second pixel definition layer, the spacer layer, the encapsulation layer and the touch layer.

[0038] In an implementation form of the display panel according to the present disclosure, the display panel further comprises a polarizer and a cover plate stacked on the touch layer.

[0039] In another aspect, the present disclosure provides a manufacturing method of a display panel, the method comprising:

[0040] forming a first barrier wall, a planarization layer and an encapsulation layer on a substrate, the substrate has a display area, a peripheral area surrounding a periphery of the display area, and a pad area located on a side of the peripheral area away from the display area, the first barrier wall is located in the peripheral area and surrounds the periphery of the display area, the planarization layer is located in the display area, and the first barrier wall and the planarization layer have a first groove therebetween, along an extension direction of an edge of a first side of the planarization layer, the first side comprises a first boundary segment and a second boundary segment connected to each other, and the first side and the pad area are located on the same side of the display area; wherein the encapsulation layer comprises an organic layer, a distance between an edge of the organic layer and the first boundary segment of the planarization layer is greater than a distance between the edge of the organic layer and the second boundary segment.

[0041] Form a touch control layer on the encapsulation layer, the touch control layer comprising a touch control signal line and a touch control electrode pattern, one end of the touch control signal line being electrically connected to the touch control electrode pattern, the other end of the touch control signal line extending from the display area to the pad area and being electrically connected to a pad of the pad area, and the touch control signal line passing through the first boundary.

[0042] In another aspect, the display panel is used in a display device.

[0043] The technical scheme provided by the display panel has the following beneficial effects:

[0044] In the display panel, the first recess is formed between the first barrier and the planarization layer. The touch control signal line passes through the first boundary and the first recess corresponding to the first boundary. The distance between the edge of the organic layer in the encapsulation layer and the first boundary of the planarization layer is greater than the distance between the edge of the organic layer and the second boundary of the planarization layer, that is, the organic layer is arranged in the first recess corresponding to the first boundary, and the material of the organic layer in the first recess corresponding to the first boundary is more, so that the depth of the first recess corresponding to the first boundary is reduced and is less than the exposure depth, which can avoid the touch control material layer in the first recess from being left over during exposure and etching, thereby reducing the phenomenon of touch control failure. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical scheme in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort.

[0046] Figure 1 is a top view of a display panel provided by the embodiments of the present disclosure;

[0047] Figure 2 is Figure 1 is a schematic view of a section of A-A in FIG. 1;

[0048] Figure 3 is Figure 1 is a schematic view of a section of B-B in FIG. 1;

[0049] Figure 4 is a schematic view of a printing pattern provided by the embodiments of the present disclosure;

[0050] Figure 5 is Figure 1 is a schematic view of a section of C-C in FIG. 1;

[0051] Figure 6is a slice schematic diagram in a first groove provided by an embodiment of the present disclosure;

[0052] Figure 7 is Figure 1 is a schematic diagram of a section of D-D in the middle;

[0053] Figure 8 is a print effect diagram of a first side of a display panel provided by an embodiment of the present disclosure;

[0054] Figure 9 is a print effect diagram of a first side of a display panel provided by an embodiment of the present disclosure;

[0055] Figure 10 is a flowchart of manufacturing a display panel provided by an embodiment of the present disclosure;

[0056] Figure 11 is a manufacturing process diagram of a display panel provided by the present disclosure;

[0057] Figure 12 is a manufacturing process diagram of a display panel provided by the present disclosure;

[0058] Figure 13 is a manufacturing process diagram of a display panel provided by the present disclosure;

[0059] Figure 14 is a manufacturing process diagram of a display panel provided by the present disclosure;

[0060] Figure 15 is a manufacturing process diagram of a display panel provided by the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0062] In related art, a display panel has a display area and a peripheral area surrounding the display area, and a first dam is arranged in the peripheral area to surround the display area. A first groove is formed between the boundary of a planarization layer in the display area and the first dam. The touch structure includes a touch electrode in the display area and a touch trace connecting the touch electrode and the driving integrated circuit, and the touch trace extends to the peripheral area through one side edge of the planarization layer.

[0063] In a display panel manufacturing process, a touch material layer is exposed and etched to form touch wires. The first groove at the edge of the planarization layer through which the touch wires pass has a depth greater than the exposure depth, so that the touch material layer in the first groove at this position is prone to residual touch material during exposure and etching. The residual touch material can cause short circuit between the formed touch wires, resulting in touch failure (Touch NG).

[0064] Figure 1 is a top view of a display panel provided by an embodiment of the present disclosure. Referring to Figure 1 , the display panel includes a substrate 100, a first barrier wall 201, a planarization layer 101, and a touch layer 103.

[0065] The substrate 100 has a display area 1, a peripheral area 2 surrounding the four sides of the display area 1, and a pad area 5 located on the side of the peripheral area 2 away from the display area 1. The first barrier wall 201 is located in the peripheral area 2 and surrounds the four sides of the display area 1. The planarization layer 101 is located in the first barrier wall 201, and the first barrier wall 201 and the planarization layer 101 have a first groove 3 therebetween. The edge of the first side 111 of the planarization layer 101 includes a first segment boundary 112 and a second segment boundary 113 connected to each other along the extension direction a of the edge of the first side 111 of the planarization layer 101. The first side 111 and the pad area 5 are located on the same side of the display area 1. The first side 111 of the planarization layer 101 is one of the side edges of the planarization layer 101. The bearing surface of the substrate 100 is the surface of the substrate 100 facing the planarization layer 101. The touch layer 103 includes a touch signal line 1031 and a touch electrode pattern 1032. One end of the touch signal line 1031 is electrically connected to the touch electrode pattern 1032. The other end of the touch signal line 1031 extends from the display area 1 to the pad area 5 and is electrically connected to the pad 501 of the pad area 5. The touch signal line 1031 passes through the first segment boundary 112.

[0066] Figure 2 is a schematic view of the section of A-A in Figure 1 . Referring to Figure 2 , the display panel further includes an encapsulation layer 102. The encapsulation layer 102 covers the planarization layer 101.

[0067] Figure 3 is a schematic view of the section of B-B in Figure 1 . Referring to Figure 3 , the touch layer 103 is on the encapsulation layer 102, and the encapsulation layer 102 includes an organic layer 121. In combination with Figure 1The edge of the organic layer 121 on the same side of the first side 111 of the planarization layer 101 in the display area 1 is located in the first groove 3, and the distance L1 between the edge of the organic layer 121 and the first segment boundary 112 of the planarization layer 101 is greater than the distance L2 between the edge of the organic layer 121 and the second segment boundary 113 of the planarization layer 101.

[0068] In the embodiment of the present disclosure, the peripheral area of the substrate is provided with a first barrier wall surrounding the display area, the planarization layer, the encapsulation layer and the touch layer are arranged in the first barrier wall, and the first groove is formed between the first barrier wall and the planarization layer.

[0069] The edge of the first side of the planarization layer includes the first segment boundary and the second segment boundary connected thereto, the touch signal line passes through the first segment boundary, and the first groove corresponding to the first segment boundary. The distance between the edge of the organic layer in the encapsulation layer and the first segment boundary of the planarization layer is greater than the distance between the edge of the organic layer and the second segment boundary of the planarization layer, that is, the organic layer is arranged in the first groove corresponding to the first segment boundary, and the material of the organic layer in the first groove corresponding to the first segment boundary is more, so that the depth of the first groove corresponding to the first segment of the organic layer is reduced and is less than the exposure depth, which can avoid the touch material layer in the first groove from generating touch material residues during exposure and etching, thereby reducing the phenomenon of touch failure.

[0070] In the embodiment of the present disclosure, the display area 1 is used for displaying a picture, and the display area includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, the first direction and the second direction being perpendicular to each other. The plurality of gate lines and the plurality of data lines cross to define a plurality of pixel regions, each of which is provided with a pixel, and each pixel has an organic light-emitting element, for example, an organic light-emitting diode (English: Organic Light-Emitting Diode, for short: OLED).

[0071] In the embodiment of the present disclosure, the peripheral area 2 is used for arranging a driving integrated circuit (English: Integrated Circuit, for short: IC) and the like. The pad area 5 is located on one side of the peripheral area 2 and is arranged corresponding to the first side 111 of the planarization layer 101. The pad area includes a plurality of pads 501, each of which is electrically connected to a signal line extending from the display area. The pad 501 can be exposed on the surface of the pad area, that is, not covered by any layer, so as to facilitate the electrical connection of the pad 501 to the flexible printed circuit board. The flexible printed circuit board is electrically connected to the controller to transmit signals or power from the controller. For example, the pad 501 is electrically connected to the touch signal line 1031 to realize the mutual communication between the touch signal line 1031 and the flexible printed circuit board.

[0072] In the embodiments of the present disclosure, the touch signal line 1031 is electrically connected with the touch electrode pattern 1032 and the pad 501 of the pad area 5 respectively, the touch signal line 1031 transmits the signal of the touch electrode pattern 1032 to the pad 501, and then to the flexible printed circuit board, so as to realize the touch function of the display panel.

[0073] Optionally, in the embodiments of the present disclosure, the organic layer 121 is an inkjet printing layer. Hereinafter, the inkjet printing layer will be exemplarily described.

[0074] In the embodiments of the present disclosure, the first barrier wall 201 is arranged around the display area 1, and the first barrier wall 201 can block the external water vapor or oxygen from entering the display area 1, so as to avoid affecting the devices in the display area 1 and thus affecting the display effect. Meanwhile, the first barrier wall 201 can also avoid the ink in the inkjet printing layer from overflowing, so as to ensure the packaging effect.

[0075] In the embodiments of the present disclosure, the planarization layer 101 makes the surface of the display area 1 more planar, which on the one hand facilitates packaging, and on the other hand makes the light exit surface of the display panel more planar, so as to ensure the normal emission of light and thus improve the display effect.

[0076] Exemplarily, the planarization layer 101 can be an insulating layer, and the material of the insulating layer can be one or more of polyimide, epoxy resin, acrylic, polyester and the like.

[0077] Again referring to Figure 3 , the planarization layer 101 can include a first planarization layer 114 and a second planarization layer 115, the first planarization layer 114 is located on the substrate 100, and the second planarization layer 115 is located on the first planarization layer 114. Arranging two layers of planarization layers increases the planarization effect and facilitates manufacturing.

[0078] Exemplarily, the first planarization layer and the second planarization layer can be made of the same material or different materials, and the present disclosure does not limit this.

[0079] In the embodiments of the present disclosure, the packaging layer 102 packages the structure between the display panel and the planarization layer 101, so as to facilitate the subsequent manufacturing of the touch signal line.

[0080] As Figure 3 shown, the packaging layer 102 can also include a first inorganic packaging layer 122 and a second inorganic packaging layer 123, and the organic layer 121 is located between the first inorganic packaging layer 122 and the second inorganic packaging layer 123.

[0081] In this implementation manner, the packaging layer 102 is arranged as a stack formed by the first inorganic packaging layer 122, the organic layer 121 and the second inorganic packaging layer 123, so as to ensure the packaging effect.

[0082] For example, the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 123 may be manufactured using a chemical vapor deposition (CVD) technique.

[0083] For example, the first inorganic encapsulating layer 122 and the second inorganic encapsulating layer 123 may be one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, or a stacked layer of multiple layers.

[0084] In the embodiment of the present disclosure, the organic layer 121 is located within the first barrier wall 201 , and the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 123 both cover the display area and the first barrier wall.

[0085] like Figure 1 As shown, the touch electrode pattern 1032 includes a plurality of touch drive electrodes 131 and a plurality of touch sensing electrodes 132. The touch drive electrodes 131 and the touch sensing electrodes 132 are arranged to intersect with each other. The intersections of the touch drive electrodes 131 and the touch sensing electrodes 132 are insulated and separated by a touch insulation layer. Each touch drive electrode 131 and each touch sensing electrode 132 is correspondingly connected to a touch signal line 1031.

[0086] In this implementation, the touch drive electrodes 131 and the touch sensing electrodes 132 are both connected to the pads 501 via touch signal lines 1031. The touch signal lines 1031 transmit the signals of the touch drive electrodes 131 and the touch sensing electrodes 132 to the pads 501, and then to the flexible printed circuit board, thereby realizing the touch function of the display panel.

[0087] The touch driving electrodes 131 and the touch sensing electrodes 132 are separated by a touch insulating layer to prevent short circuits between the electrodes and to prevent the touch function from being affected.

[0088] like Figure 1 and Figure 3 As shown, the touch drive electrodes 131 and touch sensing electrodes 132 are located in the first touch sublayer 133. Each of the touch drive electrodes 131 and the touch sensing electrodes 132 includes multiple electrode blocks. The electrode blocks of one of the touch drive electrodes 131 and the touch sensing electrodes 132 are electrically connected via a connecting block on the same layer. The electrode blocks of the other of the touch drive electrodes 131 and the touch sensing electrodes 132 are connected via a touch bridge 136 on a different layer. The touch bridge 136 is located in the second touch sublayer 134. The first touch sublayer 133 and the second touch sublayer 134 are insulated and disconnected by a touch insulating sublayer 135.

[0089] In other implementations, the touch control bridge 136 is located in the first touch control sub-layer 133, and the touch control driving electrode 131 and the touch control sensing electrode 132 are located in the second touch control sub-layer 134. That is, the touch control bridge 136 is closer to the substrate 100.

[0090] Exemplarily, the first touch control sub-layer 133 can be a metal layer or an Indium Tin Oxide (ITO) layer, to ensure the conductivity of the touch control driving electrode 131 and the touch control sensing electrode 132, and to enable the transmission of an electrical signal.

[0091] Exemplarily, the second touch control sub-layer 134 can be a metal layer or an Indium Tin Oxide layer, to ensure the conductivity of the touch control bridge 136, and to enable the transmission of an electrical signal.

[0092] In the embodiments of the present disclosure, the materials of the first touch control sub-layer 133 and the second touch control sub-layer 134 can be different or the same, and the present disclosure does not limit this.

[0093] Exemplarily, the touch control insulating sub-layer 135 can be a stack layer formed by one or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, to ensure the insulation effect of the touch control insulating sub-layer.

[0094] Again referring to Figure 3 The display panel further includes a Thin Film Transistor (TFT) array layer 104, and the planarization layer 101 is located on the TFT array layer 104.

[0095] The TFT array layer 104 includes a gate line (not shown in the figure) and a data line (not shown in the figure), and the data line is located in a Source Drain (SD) layer in the TFT array layer 104. The gate line and the data line extend from the display area 1 to the pad area 5 and pass through the second segment boundary 113. The gate line is electrically connected to a gate of the TFT and a driving integrated circuit, the driving integrated circuit controls the switching of the TFT through the gate line and the gate, the data line is electrically connected to a source of the TFT and the driving integrated circuit, and the driving integrated circuit controls the voltage of the TFT through the data line and the source.

[0096] In the embodiments of the present disclosure, the gate of the thin film transistor is connected with the driving integrated circuit through the gate line, the driving integrated circuit provides the driving signal to the gate of the thin film transistor through the gate line, and the gate line can be arranged along the edge of the display area and extend from the display area 1 to the pad area 5. One of the source-drain electrodes of the thin film transistor is connected with the data line, and the source-drain electrode is connected with the driving integrated circuit through the data line. The driving integrated circuit writes the data signal to the data signal line through the data line, so that the display panel displays an image. The gate line and the data line extend from the second segment boundary 113 of the first side to the pad area 5, so that the gate line, the data line and the touch signal line are more uniformly distributed on the first side, and the wiring is arranged conveniently.

[0097] Referring again to Figure 2 , the first side 111 of the planarization layer 101 includes a first segment slope 112a and a second segment slope 113a connected with each other, the bottom edge of the first segment slope 112a is a first segment boundary 112, and the bottom edge of the second segment slope 113a is a second segment boundary 113. In the direction b perpendicular to the bearing surface of the substrate 100, the height of the first segment slope 112a is greater than the height of the second segment slope 113a. The height of the first segment slope 112a is the distance from the top surface of the first segment slope 112a to the bottom surface of the substrate 100 in the direction perpendicular to the bearing surface of the substrate 100, and the height of the second segment slope 113a is the distance from the top surface of the second segment slope 113a to the bottom surface of the substrate 100 in the direction perpendicular to the bearing surface of the substrate 100. The bottom edge of the first segment slope 112a is the edge of the first segment slope 112a on the first surface of the planarization layer 101, the bottom edge of the second segment slope 113a is the edge of the second segment slope 113a on the first surface of the planarization layer 101, and the first surface of the planarization layer 101 is the surface thereof facing the substrate.

[0098] In this implementation, the touch signal line 1031 extends from the display area 1 to the pad area 5 through the first segment slope 112a, that is, the touch signal line 1031 extends from the planarization layer with a higher height to the pad area 5, that is, the touch signal line 1031 passes through the first segment slope 112a. In the related art, due to the higher height of the first segment slope 112a, the depth of the first groove 3 corresponding to the first segment slope 112a is deeper, greater than the exposure depth, and the touch material layer in the first groove 3 will produce touch material residues in the subsequent exposure and etching. In the embodiments of the present disclosure, the organic layer 121 is arranged in the first groove 3 corresponding to the first segment slope 112a, the depth of the first groove 3 is reduced and is less than the exposure depth, so that the touch material layer in the first groove 3 can avoid producing touch material residues in the exposure and etching, thereby reducing the phenomenon of touch failure.

[0099] In the embodiments of the present disclosure, the height of the planarization layer corresponding to the first segment boundary 112 (i.e., the height of the aforementioned first segment slope 112a) is greater than the height of the planarization layer corresponding to the second segment boundary 113 (i.e., the height of the aforementioned second segment slope 113a). In the related art, when printing ink, the ink is more likely to flow from the second segment boundary 113 into the first groove 3. Since the height of the planarization layer corresponding to the first segment boundary 112 is higher, the ink is less likely to flow from the first segment boundary 112, resulting in no ink being printed in the first groove 3 corresponding to the first segment boundary 112. The scheme provided by the present disclosure expands the range of the organic layer 121, and performs over-expansion printing at the first groove 3, i.e., when printing ink, the printing range is expanded into the first groove 3, and the expanded position corresponds to the first segment boundary 112 and is adjacent to the second segment boundary 113. By using such a special-shaped printing, the ink is directly printed into the first groove 3, thereby reducing the depth of the first groove 3 corresponding to the first segment boundary 112.

[0100] For example, the height of the planarization layer corresponding to the first segment boundary 112 can be between 4.5 microns and 5 microns, for example, the height of the planarization layer corresponding to the first segment boundary 112 can be 4.89 microns.

[0101] For example, the height of the planarization layer corresponding to the second segment boundary 113 can be between 3.5 microns and 4 microns, for example, the height of the planarization layer corresponding to the second segment boundary 113 can be 3.79 microns.

[0102] Again referring to Figure 1 The distance between the edge of the first barrier wall 201 opposite to the second segment boundary 113 and the second segment boundary 113 is less than the distance between the edge of the first barrier wall 201 opposite to the first segment boundary 112 and the first segment boundary 112. The edge of the first barrier wall 201 opposite to the second segment boundary 113 and the edge of the first barrier wall 201 opposite to the first segment boundary 112 both refer to the edge of the first barrier wall 201 on the same side of the first side 111 as the display area and facing the display area.

[0103] In the embodiments of the present disclosure, the second segment boundary 113 protrudes towards the first barrier wall 201 relative to the first segment boundary 112, i.e., the planarization layer 101 has a protruding portion towards the first barrier wall, and the second segment slope 113a is arranged on the protruding portion. Through the protruding portion of the planarization layer 101, the gate line and the data line can be wrapped during packaging, so as to ensure that the gate line and the data line will not be damaged in subsequent manufacturing processes.

[0104] For example, the orthogonal projection of the outwardly protruding second segment slope 113a on the bearing surface of the substrate 100 is a rectangle.

[0105] In this implementation, the slope angle of the first segment slope 112a is greater than the slope angle of the second segment slope 113a.

[0106] In other implementations, the distance between the first segment boundary 112 and the first barrier 201 and the distance between the second segment boundary 113 and the first barrier 201 can be equal, i.e. the first segment boundary 112 and the second segment boundary 113 are located on the same straight line.

[0107] In an implementation of the embodiment of the present disclosure, the length of the organic layer 121 between any one of the first segment boundaries 112 and the first barrier 201 in the extension direction a of the edge of the first side 111 is between 1 mm and 3 mm.

[0108] In this implementation, by limiting the length of the organic layer 121 between the first segment boundary 112 and the first barrier 201, the organic layer 121 is arranged below the touch signal line, which avoids the generation of touch material residues when etching the touch material layer, thereby reducing the phenomenon of touch failure.

[0109] In an implementation of the embodiment of the present disclosure, the distance between the edge of the organic layer 121 and the first segment boundary 112 is between 50 μm and 150 μm.

[0110] In this implementation, the organic layer 121 corresponding to the first segment boundary 112 is located in the first groove 3, and the distance between the edge of the organic layer 121 and the first segment boundary 112 is limited, so that the area of the organic layer 121 in the first groove 3 corresponding to the first segment boundary 112 is large, the slope formed by the organic layer 121 is gentle, the difference is reduced, and etching of the touch layer is facilitated.

[0111] Again referring to Figure 1 and Figure 2 , the first side 111 of the planarization layer 101 includes two first segment boundaries 112, and the two first segment boundaries 112 are respectively located on the two sides of the second segment boundary 113 in the extension direction a of the edge of the first side 111.

[0112] In this implementation, two first segment boundaries 112 are arranged and distributed on the two sides of the second segment boundary 113, i.e. the two first segment boundaries 112 are respectively located on the two sides of the edge of the first side 111 of the planarization layer 101, so that the touch signal line can extend from the two first segment boundaries 112 on the two sides to the connection with the bonding pad 501 in the bonding pad area 5, which on the one hand facilitates the manufacture of the touch signal line, and on the other hand ensures that the lengths of the touch signal lines on the two sides of the display panel are equivalent, so that the resistances of the touch signal lines are relatively small, and the sizes of the touch signals at different positions of the display panel are avoided to be different, which affects the touch effect.

[0113] In the process of inkjet printing, the printing area can be defined according to a computer aided design (CAD) drawing, and the inkjet printing area can be flexibly adjusted according to the actual flow effect of the ink, so that the process can be improved in time, and the cost is low compared with directly changing the mask of the planarization layer.

[0114] In an implementation manner of the embodiment of the present disclosure, the ink coverage of the edge of the planarization layer can be monitored in time through automated optical inspection (AOI) in the process of printing the ink, and the corresponding area coverage can be adjusted in time according to the monitoring result, so as to ensure the yield of the display panel.

[0115] Figure 4 is a schematic diagram of printing a pattern provided by the embodiment of the present disclosure. Referring to Figure 4 , the organic layer is printed outwardly, and the outward printing is performed only at positions corresponding to the first section boundary 112, that is, the two highlighted parts in the figure, so as to avoid that the range of the organic layer is too large to cause ink overflow. Since the height of the planarization layer corresponding to the first section boundary 112 is relatively high, if the range of the organic layer is too large, the amount of ink will be large, and more ink will flow into the first groove 3 corresponding to the second section boundary 113, so that the ink overflows from the first dam, resulting in packaging failure.

[0116] As shown in Figure 4 , the outward printing area is two rectangles, and the two rectangles are respectively arranged corresponding to the two first section boundaries 112. Since the ink has fluidity, the ink will flow outwardly to the printed pattern, and finally form the boundary of the organic layer 121 as shown in Figure 1 .

[0117] The present disclosure only performs special-shaped printing on the part where the touch material residue is prone to occur, so that the ink can overflow the planarization layer without affecting the stopping position of the ink in other areas, thereby significantly reducing the difference of the climbing area (that is, the first slope 6), and further improving the problem of touch material residue at the position.

[0118] Figure 5 is a schematic diagram of the section of the C-C plane in Figure 1 . Referring to Figure 5 , in the extension direction a of the edge of the first side 111, the part of the first section boundary 112 close to the first dam 201 is not provided with outward printing, so that the boundary of the organic layer 121 in this area is closer to the boundary of the display area 1.

[0119] Figure 6 is a schematic diagram of a slice in the first groove provided by the embodiment of the present disclosure. Referring toFigure 6 The organic layer 121 between the first segment boundary 112 and the first barrier wall 201 forms a first slope 6, and an angle of a slope angle a1 of the first slope 6 is between 1 degree and 35 degrees.

[0120] In this implementation, after the organic layer 121 is made, the first slope 6 formed by the organic layer 121 between the first segment boundary 112 and the first barrier wall 201 has a relatively gentle slope angle a1, which reduces the height difference between the first groove 3 and the encapsulation layer, facilitates the passing of the touch layer wire, and at the same time reduces the depth of the first groove 3, facilitates the subsequent etching of the touch layer, and avoids the residual touch material, which causes touch failure.

[0121] Optionally, in the embodiment of the present disclosure, the angle of the slope angle a1 of the first slope 6 is between 10 degrees and 15 degrees.

[0122] As shown in Figure 6 , the first groove 3 has an organic layer, and the organic layer reduces the depth of the first groove 3, facilitating the subsequent etching of the touch layer.

[0123] Exemplarily, Figure 6 The slice schematic diagram can be a focused ion beam (English: focused ion beam, for short: FIB) slice diagram.

[0124] Referring again to Figure 3 , the display panel in the display area 1 further includes a first pixel definition layer (English: Pixel Definition Layer, for short: PDL) 105 located on the second planarization layer 115, and a portion of the first planarization layer 114, the second planarization layer 115 and the first pixel definition layer 105 close to the first barrier wall 201 form a second slope 7, and an edge of the first planarization layer 114, the second planarization layer 115 and the first pixel definition layer 105 corresponding to the first segment boundary 112 coincides with the first barrier wall 201.

[0125] The portion of the second planarization layer 115 and the first pixel definition layer 105 close to the first barrier wall 201 forms the second slope 7, so that the transition between the first pixel definition layer 105 and the bottom edge of the first groove 3 is gentle, facilitating the subsequent etching of the touch layer.

[0126] In one implementation of the embodiment of the present disclosure, an angle of a slope angle a2 of the second slope 7 is between 35 degrees and 55 degrees.

[0127] In this implementation, by limiting the angle range of the slope angle a2 of the second slope 7, on the one hand, the transition between the first pixel definition layer 105 and the bottom edge of the first groove 3 is gentle. On the other hand, it avoids that the second slope 7 is too gentle, causing the peripheral area to be too large, which is not conducive to the narrow frame design of the display panel.

[0128] As shown in Figure 2 , the height of the planarization layer 101 near the second segment boundary 113 is lower than the height of the planarization layer 101 near the first segment boundary 112, that is, the planarization layer 101 near the second segment boundary 113 is formed with a groove. Correspondingly, the height of the first pixel defining layer 105 corresponding to the first segment boundary 112 is greater than the height of the first pixel defining layer 105 corresponding to the second segment boundary 113, that is, the first pixel defining layer 105 is also formed with a groove. Since the ink in the organic layer 121 has fluidity, more ink will be deposited in the groove, so that the surface of the organic layer is flat, thereby making the surface of the encapsulation layer 102 located in the display area 1 flat.

[0129] Figure 7 is Figure 1 a schematic view of the cross section of the D-D plane. Referring to Figure 7 , the distance between the edge of the first barrier wall 201 opposite to the second segment boundary 113 and the first pixel defining layer 105 corresponding to the second segment boundary 113 is less than the distance between the edge of the first barrier wall 201 opposite to the second segment boundary 113 and the edge of the first pixel defining layer 105 opposite to the second segment boundary 113. Wherein, the edge of the first pixel defining layer 105 opposite to the first side 111 refers to the edge of the first pixel defining layer 105 and the first side 111 located on the same side of the display area and facing the display area.

[0130] In this implementation, since the second segment boundary 113 protrudes towards the first barrier wall 201 relative to the first segment boundary 112, the edge of the first pixel defining layer 105 can be inwardly retracted into the display area 1, so that the slope formed by the planarization layer 101 and the first pixel defining layer 105 of the second segment boundary 113 is relatively gentle. During printing, the ink is more likely to flow from the second segment boundary 113 to the first groove 3, so that the first groove 3 corresponding to the second segment boundary 113 also has printed ink, and the depth of the first groove 3 corresponding to the second segment boundary 113 is shallower, which is convenient for subsequent film layer manufacturing.

[0131] In the embodiment of the present disclosure, since the thickness of the ink in the first groove 3 corresponding to the second segment boundary 113 is higher, when the organic layer 121 is manufactured, the slope angle of the first slope 6 is less than the slope angle of the slope formed by the organic layer 121 between the second segment boundary 113 and the first barrier wall 201, wherein the slope angle of the first slope 6 is the slope angle of the first slope 6 formed by the organic layer 121 between the first segment boundary 112 and the first barrier wall 201.

[0132] Again referring to Figure 1 , Figure 3 and Figure 7The display panel further comprises a second barrier wall 202, the second barrier wall 202 is located in the peripheral area 2 and surrounds the periphery of the first barrier wall 201, the first barrier wall 201 and the second barrier wall 202 have a second groove 4 therebetween, the height of the second barrier wall 202 is greater than the height of the first barrier wall 201, the distance between the first surface of the planarization layer 101 and the second surface of the first pixel definition layer 105 is greater than the height of the second barrier wall 202, the height of the first barrier wall 201 is the distance from the top surface of the substrate 100 to the first surface of the planarization layer 101 in the direction b perpendicular to the bearing surface of the substrate 100, and the height of the second barrier wall 202 is the distance from the top surface of the substrate 100 to the first surface of the planarization layer 101 in the direction b perpendicular to the bearing surface of the substrate 100. The first surface of the planarization layer 101 is the surface of the planarization layer 101 close to the substrate 100, and the second surface of the first pixel definition layer 105 is the surface of the first pixel definition layer 105 away from the substrate 100.

[0133] In this implementation, the display panel is provided with the second barrier wall 202, which can also block the external water vapor or oxygen from entering the display area 1, and the first barrier wall and the second barrier wall are provided, which can enhance the water-oxygen blocking effect and avoid water-oxygen erosion to affect the devices in the display area 1 and thus affect the display effect.

[0134] In the related art, the depth of the second groove 4 (i.e., the distance from the bottom of the second groove 4 to the top of the first barrier wall 201) is generally used to define the exposure depth, and because the height of the first pixel definition layer 105 is greater than the height of the second barrier wall 202, the depth of the first groove 3 is greater than the depth of the second groove 4, which causes the touch control material to be left over when the touch control material layer is exposed and etched. However, the organic layer is arranged in the first groove 3 in the present disclosure, which reduces the depth of the first groove 3, so that the depth of the first groove 3 is less than the exposure depth, and thus the touch control material is not left over when the touch control material layer is exposed and etched, which avoids short circuit between the touch control signal lines and causes the touch control to fail.

[0135] In the embodiment of the present disclosure, when the display panel is provided with the second barrier wall 202, the first inorganic encapsulation layer 122 and the second inorganic encapsulation layer 123 cover the display area, the first barrier wall 201 and the second barrier wall 202.

[0136] Again referring to Figure 3 and Figure 7The first barrier wall 201 comprises a third planarization layer 211, a second pixel defining layer 212 and a photo spacer (PS) layer 110 which are sequentially stacked, and the second barrier wall 202 comprises a third planarization layer 211, a fourth planarization layer 213, a second pixel defining layer 212 and a photo spacer layer 110 which are sequentially stacked; the third planarization layer 211 is in the same layer as the first planarization layer 114, the fourth planarization layer 213 is in the same layer as the second planarization layer 115, and the second pixel defining layer 212 is in the same layer as the first pixel defining layer 105. The same layer means that the film layers for forming specific patterns are formed by the same film forming process, and then the layer structure is formed by one patterning process using the same mask plate. According to different specific patterns, the same patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses.

[0137] In this implementation, the third planarization layer 211 is in the same layer as the first planarization layer 114, and the fourth planarization layer 213 is in the same layer as the second planarization layer 115. In production, two layers of planarization films can be first produced, and then the first planarization layer 114 and the second planarization layer 115 are respectively formed in the display area by a patterning process, and the third planarization layer 211 and the fourth planarization layer 213 are formed in the peripheral area. Then a layer of pixel defining film is produced, and then the first pixel defining layer 105 is formed in the display area by a patterning process, the second pixel defining layer 212 is formed on the third planarization layer 211 in the peripheral area and constitutes the first barrier wall 201, and the second pixel defining layer 212 is formed on the third planarization layer 211 and the fourth planarization layer 213 in the peripheral area and constitutes the second barrier wall 202. In this way, the third planarization layer 211 can be formed when the first planarization layer 114 is produced, the fourth planarization layer 213 can be formed when the second planarization layer 115 is produced, and the second pixel defining layer 212 can be formed when the first pixel defining layer 105 is produced, so that the first barrier wall 201 and the second barrier wall 202 are finally formed, and the production is convenient.

[0138] In the embodiments of the present disclosure, the material of the third planarization layer 211 is the same as that of the first planarization layer 114. The material of the fourth planarization layer 213 is the same as that of the second planarization layer 115. The material of the second pixel defining layer 212 is the same as that of the first pixel defining layer 105.

[0139] In the embodiments of the present disclosure, the photo spacer layer 110 is located on the second pixel defining layer 212, so as to ensure the height of the second barrier wall 202 and the first barrier wall 201.

[0140] In the embodiments of the present disclosure, the pixel area of the display area 1 of the display panel can also be arranged with the spacer layer 110, which is used to support the mask plate when the organic light-emitting layer is evaporated.

[0141] In an implementation of the embodiments of the present disclosure, the height difference between the second barrier wall 202 and the first barrier wall 201 is between 0.4 microns and 1.0 microns.

[0142] In this implementation, the height of the first barrier wall 201 is defined to be slightly lower than that of the second barrier wall 202, so as to avoid that the height difference between the first barrier wall 201 and the second barrier wall 202 is too large to affect the blocking effect of the first barrier wall 201.

[0143] For example, the height of the first barrier wall 201 can be between 3.0 microns and 4.0 microns, for example, the height of the first barrier wall 201 can be 3.47 microns.

[0144] For example, the height of the second barrier wall 202 can be between 3.5 microns and 4.5 microns, for example, the height of the second barrier wall 202 can be 4.0 microns.

[0145] Again referring to Figure 2 and Figure 3 , the first barrier wall 201 and the second barrier wall 202 both have slopes. The slope angle (i.e., the taper angle of the first barrier wall) α3 of the slope of the side of the first barrier wall 201 can be between 15 degrees and 50 degrees, and the slope angle (i.e., the taper angle of the second barrier wall) α4 of the slope of the side of the second barrier wall 202 can be between 15 degrees and 50 degrees.

[0146] For example, the taper angle α3 of the slope of the first barrier wall 201 can be 46.37 degrees, and the taper angle α4 of the slope of the second barrier wall 202 can be 45 degrees. Through the above angle setting, the touch signal line can pass through the first barrier wall and the second barrier wall.

[0147] In the embodiments of the present disclosure, in the display area, the substrate 100 is stacked with the thin film transistor array layer 104, the planarization layer 101, the first pixel defining layer 105, the spacer layer 110 (not shown in Figure 3 ), the light-emitting layer (not shown in Figure 3 ), the encapsulation layer 102, and the touch layer 103. The light-emitting layer is located in the groove of the first pixel defining layer 105, and the light-emitting layer is used for light-emitting display of the display panel.

[0148] In the embodiments of the present disclosure, in the peripheral region, the substrate 100 is stacked with the thin film transistor array layer 104, the third planarization layer 211, the fourth planarization layer 213, the second pixel defining layer 212, the spacer layer 110, the encapsulation layer 102 and the touch layer 103.

[0149] In the implementation, the substrate 100 provides support for the internal structure of the display panel. The thin film transistor array layer 104 forms a TFT structure to control the display panel to display a picture.

[0150] In the embodiments of the present disclosure, the light-emitting layer includes an anode layer, an electron transport layer, an organic light-emitting layer, a hole transport layer and a cathode layer stacked together, the anode layer, the electron transport layer, the organic light-emitting layer and the hole transport layer are arranged in the groove formed by the pixel defining layer, and the cathode layer can be arranged above the pixel defining layer.

[0151] In the embodiments of the present disclosure, the display panel further includes a polarizer 120 and a cover plate 200 stacked on the touch layer 103.

[0152] In the implementation, the cover plate 200 protects the internal structure of the display panel. The polarizer 120 can change the polarization direction of light, control the polarization direction of light through the polarizer 120, filter out the interference light in the display panel, and ensure the display effect.

[0153] Exemplarily, a filling layer 130 can be arranged on the touch layer 103, which makes the surface of the touch layer 103 flat and easy to arrange the polarizer 120.

[0154] Exemplarily, the cover plate 200 can be a glass cover plate or a transparent plastic cover plate, which ensures the light transmittance of the cover plate 200.

[0155] Referring again to Figure 2 , Figure 3 , Figure 5 and Figure 7 , the substrate 100 includes a first substrate 1001 and a second substrate 1002, the first substrate 1001 is provided with a first barrier layer (English: Barrier) 161, and the second substrate 1002 is provided with a second barrier layer 162.

[0156] In the embodiments of the present disclosure, the barrier layer is formed on the substrate, and the insulating layer is formed through the barrier layer, which avoids the influence of external static electricity on the internal circuit of the display panel, and the barrier layer can also block the heat from spreading to the internal structure of the display panel, thereby avoiding damage to the display panel caused by high temperature.

[0157] The two layers of barrier layers are arranged to ensure the insulation effect of the barrier layers. Meanwhile, the first barrier layer 161 and the second barrier layer 162 are respectively arranged on the two substrates. When the surface of the substrate is uneven, the first barrier layer 161 can improve the surface flatness of the first substrate 1001, and the second barrier layer 162 can improve the surface flatness of the second substrate 1002. The first barrier layer 161 has good adhesion, which facilitates the adhesion of the first substrate 1001 and the second substrate 1002.

[0158] In the embodiments of the present disclosure, the substrate can be a flexible substrate, which can be made of a flexible organic material, such as a resin material such as polyimide (English: Polyimide, abbreviated as: PI), polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0159] In the embodiments of the present disclosure, the first barrier layer 161 and the second barrier layer 162 can include inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, and can be formed in multiple layers or a single layer.

[0160] Optionally, the display panel further includes a buffer layer 107 arranged on the second barrier layer 162. The thin film transistor array layer 104 is arranged on the buffer layer 107.

[0161] The buffer layer 107 separates the barrier layer and the thin film transistor array layer 104, avoids the influence of the barrier layer on the work of the thin film transistor array layer 104, and facilitates the manufacture of the thin film transistor array layer 104.

[0162] For example, the buffer layer 107 can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or a stack formed by any two or three of the silicon oxide layer, the silicon nitride layer, and the silicon oxynitride layer, to ensure the insulation effect of the buffer layer 107.

[0163] Optionally, the thin film transistor array layer 104 includes an active layer 141, a gate insulator (English: Gate Insulator, abbreviated as: GI) layer 142, a gate (English: Gate) layer 143, an inter-layer dielectric layer (English: Inter-Layer Dielectric) 144, and a source-drain electrode layer 145, which are sequentially stacked on the buffer layer 107. Figure 3 and Figure 5 The thin film transistor shown is only an example, and the display panel can also include a thin film transistor of other structures.

[0164] In the embodiments of the present disclosure, the gate insulating layer 142 is located between the active layer 141 and the gate layer 143, and the active layer 141 and the gate layer 143 are separated by the gate insulating layer 142, so that the active layer 141 and the gate layer 143 can transmit signals independently.

[0165] Exemplarily, the active layer 141 can be a low temperature poly-silicon (LTPS) layer. The LTPS has high mobility and good stability, and can meet the requirements of high-resolution displays.

[0166] Exemplarily, the gate insulating layer 142 and the interlayer dielectric layer 144 can be inorganic insulating layers, such as silicon nitride layers or silicon oxynitride layers, or can be organic insulating layers, such as annular resin insulating layers. The silicon nitride, silicon oxynitride and annular resin have good insulation, so as to ensure the insulation of the gate insulating layer 142 and the interlayer dielectric layer 144. The materials of the gate insulating layer 142 and the interlayer dielectric layer 144 can be the same or different.

[0167] In the embodiments of the present disclosure, the gate layer 143 and the source-drain layer 145 can be metal layers or indium tin oxide layers, so as to ensure the stability of the electrical signal transmission of the gate layer 143 and the source-drain layer 145.

[0168] Optionally, the display panel further comprises an insulating layer (PVX) 108 located on the source-drain layer 145, and the insulating layer 108 separates the source-drain layer 145 and the anode layer located in the first pixel defining layer 105, so that the source-drain layer 145 and the anode layer can transmit signals independently.

[0169] Optionally, the display panel further comprises a third barrier layer 109 located on the encapsulation layer 102. The barrier layers are arranged on the opposite sides of the display panel, so as to increase the effect of preventing water oxygen.

[0170] In the embodiments of the present disclosure, the third barrier layer 109 can comprise inorganic materials such as silicon oxide, silicon nitride or silicon oxynitride, and can be formed as multiple layers or a single layer.

[0171] Figure 8 is a printed effect diagram of a first side of a display panel provided by the embodiments of the present disclosure. Figure 9 is a printed effect diagram of a first side of a display panel provided by the embodiments of the present disclosure. Referring to Figure 8 and Figure 9 The boundary of the organic layer 121 is in the first groove, but does not exceed the boundary of the first barrier wall 201, so as to reduce the depth of the first groove and avoid encapsulation failure.

[0172] Figure 10 is a flowchart of manufacturing a display panel provided by an embodiment of the present disclosure. Referring to Figure 10 , the method comprises:

[0173] Step S101: forming a first barrier wall, a planarization layer and an encapsulation layer on a substrate.

[0174] The substrate has a display area, a peripheral area surrounding the periphery of the display area, and a pad area located on the side of the peripheral area away from the display area, the first barrier wall is located in the peripheral area and surrounds the periphery of the display area, the planarization layer is located in the display area, the first barrier wall and the planarization layer have a first groove therebetween, the extension direction of the edge of the first side of the planarization layer includes a first segment boundary and a second segment boundary connected in sequence, and the first side and the pad area are located on the same side of the display area; wherein the encapsulation layer comprises an organic layer, and the distance between the edge of the organic layer and the first segment boundary of the planarization layer is greater than the distance between the edge of the organic layer and the second segment boundary.

[0175] Figures 11 to 15 is a manufacturing process diagram of a display panel provided by the present disclosure. In the following Figures 11 to 15 The display panel manufacturing method of the present disclosure is introduced.

[0176] Exemplarily, the step S101 can comprise:

[0177] First step: providing a substrate.

[0178] Referring to Figure 11 , a substrate 100 is provided. The substrate 100 can be a transparent substrate, such as a glass substrate, a plastic substrate, etc.

[0179] Second step: sequentially manufacturing a barrier layer and a buffer layer on the substrate.

[0180] Referring to Figure 12 , a barrier layer 106 and a buffer layer 107 are sequentially manufactured on the substrate 100.

[0181] Exemplarily, the first barrier layer 161 can be manufactured on the first substrate 1001 by evaporation, and after the first barrier layer 161 is manufactured, the second substrate 1002 can be covered on the first barrier layer 161, then the second barrier layer 162 is formed on the second substrate 1002, and then the buffer layer 107 is manufactured on the second barrier layer 162 by evaporation.

[0182] Exemplarily, the first barrier layer 161 and the second barrier layer 162 can comprise inorganic materials such as silicon oxide, silicon nitride or silicon oxynitride, and can be formed as multiple layers or a single layer.

[0183] Exemplarily, the buffer layer 107 can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or a stack of any two or three of the silicon oxide layer, the silicon nitride layer, and the silicon oxynitride layer, to ensure the insulation effect of the buffer layer 107.

[0184] Step 3: Forming a thin film transistor array layer on the buffer layer.

[0185] Referring to Figure 13 The thin film transistor array layer 104 is formed on the buffer layer 107.

[0186] This step can include sequentially forming an active layer 141, a gate insulating layer 142, a gate layer 143, an interlayer dielectric layer 144, and a source-drain layer 145 on the buffer layer 107.

[0187] Exemplarily, the active layer 141 can be a polycrystalline silicon layer or a monocrystalline silicon layer.

[0188] Exemplarily, the gate insulating layer 142 and the interlayer dielectric layer 144 can be inorganic insulating layers, such as a silicon nitride layer or a silicon oxynitride layer, or can be organic insulating layers, such as a ring resin insulating layer. The silicon nitride, the silicon oxynitride, and the ring resin have good insulation, to ensure the insulation of the gate insulating layer 142 and the interlayer dielectric layer 144. The materials of the gate insulating layer 142 and the interlayer dielectric layer 144 can be the same or different.

[0189] Exemplarily, the gate layer 143 and the source-drain layer 145 can be metal layers or indium tin oxide layers, to ensure the stability of the electrical signal transmission of the gate layer 143 and the source-drain layer 145.

[0190] Exemplarily, the active layer 141 can be formed on the buffer layer 107 by evaporation, the gate insulating layer 142 can be formed on the active layer 141 by evaporation, the gate layer 143 can be formed on the gate insulating layer 142 by sputtering, the interlayer dielectric layer 144 can be formed on the gate layer 143 by evaporation, and the source-drain layer 145 can be formed on the interlayer dielectric layer 144 by sputtering.

[0191] Step 4: Forming a planarization layer and an encapsulation layer on the thin film transistor array layer in sequence.

[0192] Referring to Figure 14 The insulating layer 108 can be formed on the thin film transistor array layer 104, and then the planarization layer 101, the first pixel defining layer 105, and the encapsulation layer 102 can be formed on the insulating layer 108.

[0193] Exemplarily, the planarization layer 101 can be an insulating layer, and the material of the insulating layer can be one or more of polyimide, epoxy resin, acrylic, polyester, and the like.

[0194] Exemplarily, the planarization layer 101 can include a first planarization layer 114 and a second planarization layer 115, the first planarization layer 114 is located on the substrate 100, and the second planarization layer 115 is located on the first planarization layer 114. Arranging two layers of planarization layers increases the planarization effect.

[0195] In the embodiment of the present disclosure, two layers of planarization films can be first made, and then the first planarization layer 114 and the second planarization layer 115 are respectively formed in the display area by a patterning process, and the third planarization layer 211 and the fourth planarization layer 213 are respectively formed in the peripheral area by the patterning process. Then, one layer of pixel definition film is made, and then the first pixel definition layer 105 is formed in the display area by the patterning process, the second pixel definition layer 212 is formed on the third planarization layer 211 in the peripheral area and constitutes the first barrier wall 201, and the second pixel definition layer 212 is formed on the third planarization layer 211 and the fourth planarization layer 213 in the peripheral area and constitutes the second barrier wall 202.

[0196] Then, the first inorganic encapsulation layer 122, the organic layer 121 and the second inorganic encapsulation layer 123 are formed on the pixel definition layer.

[0197] In the embodiment of the present disclosure, after the first pixel definition layer 105 is made, the light-emitting layer is formed in the groove of the first pixel definition layer 105.

[0198] Exemplarily, the first inorganic encapsulation layer 122 can be made on the pixel definition layer by a chemical vapor deposition method, the organic layer 121 can be made on the first inorganic encapsulation layer 122 by an inkjet printing method, and then the second inorganic encapsulation layer 123 can be made on the organic layer 121 by a chemical vapor deposition method.

[0199] Exemplarily, when the organic layer is made, the printing area can be first defined according to the size of the back plate by a CAD drawing, and then printing is performed.

[0200] Step S102: forming a touch layer on the encapsulation layer, the touch layer including a touch signal line and a touch electrode pattern, one end of the touch signal line being electrically connected with the touch electrode pattern, the other end of the touch signal line extending from the display area to the pad area and being electrically connected with the pad of the pad area, and the touch signal line passing through the first boundary.

[0201] Referring to Figure 15 , the third barrier layer 109 is first formed on the encapsulation layer 102, and then the touch layer 103 is formed on the third barrier layer 109. The touch layer 103 includes a touch signal line and a touch electrode pattern.

[0202] Exemplarily, the third barrier layer 109 can be formed on the encapsulation layer 102 by a chemical vapor deposition method, then the first touch signal line thin film layer is formed on the encapsulation layer 102, then the first touch signal line thin film layer is subjected to a patterning process to form a first touch sub-layer. The first touch sub-layer includes a touch bridge. Then the touch insulating sub-layer is formed on the first touch sub-layer, and the second touch signal line thin film layer is formed on the touch insulating sub-layer, then the second touch signal line thin film layer is subjected to a patterning process to form a second touch sub-layer. The second touch sub-layer includes a plurality of touch drive electrodes and a plurality of touch sensing electrodes, the touch drive electrodes and the touch sensing electrodes are arranged in a cross manner, and the touch drive electrodes and the touch sensing electrodes are insulated and spaced apart by the touch insulating layer at the intersection. Finally, the touch layer 103 is formed. Then subsequent module assembly is performed, the polarizing plate 120 is attached on the touch layer 103, and then the cover plate 200 is covered on the polarizing plate 120, thereby forming the display panel.

[0203] The display device provided by the embodiments of the present disclosure can be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any product or component having a display function.

[0204] In a specific implementation, the display device provided by the embodiments of the present disclosure can be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any product or component having a display function.

[0205] The above description is only optional embodiments of the present disclosure, and is not used to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate having: a display area; a peripheral area surrounding a periphery of the display area; a pad area located on a side of the peripheral area away from the display area; a first barrier wall located in the peripheral area and surrounding a periphery of the display area; a planarization layer located in the first barrier wall, the first barrier wall and the planarization layer having a first groove therebetween, an edge of a first side of the planarization layer extending in a direction of the edge of the first side comprising a first segment boundary and a second segment boundary connected in sequence, the first side being on a same side of the display area as the pad area; an encapsulation layer covering the planarization layer; a touch layer on the encapsulation layer, the touch layer comprising a touch signal line and a touch electrode pattern, one end of the touch signal line being electrically connected to the touch electrode pattern, the other end of the touch signal line extending from the display area to the pad area and being electrically connected to a pad of the pad area, and the touch signal line passing through the first segment boundary; wherein the encapsulation layer comprises an organic layer, an edge of the organic layer on the same side of the display area as the first side of the planarization layer being located in the first groove, a distance between the edge of the organic layer and the first segment boundary being greater than a distance between the edge of the organic layer and the second segment boundary; the first side of the planarization layer comprising a first segment slope and a second segment slope connected in sequence, a bottom edge of the first segment slope being the first segment boundary, and a bottom edge of the second segment slope being the second segment boundary; in a direction perpendicular to a bearing surface of the substrate, a height of the first segment slope is greater than a height of the second segment slope, the height of the first segment slope being a distance from a top surface of the first segment slope to a bottom surface of the substrate in a direction perpendicular to the bearing surface of the substrate, and the height of the second segment slope being a distance from a top surface of the second segment slope to the bottom surface of the substrate in the direction perpendicular to the bearing surface of the substrate.

2. The display panel of claim 1, wherein, a distance between an edge of the first barrier wall opposite to the second segment boundary and the second segment boundary is less than a distance between an edge of the first barrier wall opposite to the first segment boundary and the first segment boundary.

3. The display panel of any of claims 1-2, wherein, The display panel further comprises a thin film transistor array layer, the planarization layer being located on the thin film transistor array layer; the thin film transistor array layer comprising gate lines and data lines, the gate lines and the data lines extending from the display area to the pad area and passing through the second segment boundary.

4. The display panel of any of claims 1-2, wherein, In the direction of the extension of the edge of the first side, a length of the organic layer between the first segment boundary and the first barrier wall is between 1 millimeter and 3 millimeters.

5. The display panel of any of claims 1-2, wherein, The distance between the edge of the organic layer and the first segment boundary is between 50 micrometers and 150 micrometers. 6.The display panel of any one of claims 1-2, wherein, The first side of the planarization layer comprises two first segment boundaries, in the direction of the extension of the edge of the first side, the two first segment boundaries are respectively located on two sides of the second segment boundary.

7. The display panel of any of claims 1-2, wherein, The organic layer between the first segment boundary and the first barrier wall forms a first slope, an angle of a slope angle of the first slope is between 1 degree and 35 degrees. 8.The display panel of any one of claims 1-2, wherein, The planarization layer comprises a first planarization layer and a second planarization layer. The display area further comprises a first pixel defining layer on the second planarization layer. The first planarization layer, the second planarization layer and the first pixel defining layer corresponding to the first segment boundary form a second slope near the pad area, and edges of the first planarization layer, the second planarization layer and the first pixel defining layer corresponding to the first segment boundary coincide.

9. The display panel of claim 8, wherein, The angle of the slope angle of the second slope is between 35 degrees and 55 degrees.

10. The display panel of claim 8, wherein, The distance between the edge of the first barrier wall opposite to the second segment boundary and the second segment boundary is smaller than the distance between the edge of the first barrier wall opposite to the second segment boundary and the edge of the first pixel defining layer opposite to the second segment boundary.

11. The display panel of claim 8, wherein, The display panel further comprises a second barrier wall in the peripheral area and surrounding the first barrier wall. The first barrier wall and the second barrier wall have a second groove therebetween, the height of the second barrier wall is greater than the height of the first barrier wall, the distance between the first surface of the planarization layer and the second surface of the first pixel defining layer is greater than the height of the second barrier wall, the height of the first barrier wall is the distance from the top surface of the substrate to the first surface of the planarization layer in the direction perpendicular to the bearing surface of the substrate, the height of the second barrier wall is the distance from the top surface of the substrate to the first surface of the planarization layer in the direction perpendicular to the bearing surface of the substrate, the first surface of the planarization layer is the surface of the planarization layer close to the substrate, and the second surface of the first pixel defining layer is the surface of the first pixel defining layer away from the substrate.

12. The display panel of claim 11, wherein, The first barrier wall comprises a third planarization layer, a second pixel defining layer and a spacer layer arranged in sequence. The second barrier wall comprises the third planarization layer, a fourth planarization layer, the second pixel defining layer and the spacer layer arranged in sequence. The third planarization layer is in the same layer as the first planarization layer, the fourth planarization layer is in the same layer as the second planarization layer, and the second pixel defining layer is in the same layer as the first pixel defining layer.

13. The display panel of claim 12, wherein, The difference between the height of the second barrier wall and the height of the first barrier wall is between 0.4 microns and 1.0 microns. 14.The display panel of any one of claims 1-2, wherein, The touch electrode pattern comprises a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged in a cross manner, the touch driving electrodes and the touch sensing electrodes are insulated and spaced apart by a touch insulating layer at the intersection, each touch driving electrode and each touch sensing electrode correspond to a touch signal line.

15. The display panel of any one of claims 1-2, wherein, The encapsulation layer further comprises a first inorganic encapsulation layer and a second inorganic encapsulation layer, and the organic layer is between the first inorganic encapsulation layer and the second inorganic encapsulation layer. 16.The display panel of any one of claims 1-2, wherein, In the display area, the substrate has a thin film transistor array layer, the planarization layer, the first pixel defining layer, the spacer layer, the light emitting layer, the encapsulation layer and the touch layer stacked thereon.

17. The display panel of claim 16, wherein, In the peripheral region, the substrate is stacked with the thin film transistor array layer, a third planarization layer, a fourth planarization layer, a second pixel definition layer, the spacer layer, the encapsulation layer and the touch layer.

18. The display panel of claim 17, wherein, The display panel further comprises a polarizer and a cover plate stacked on the touch layer.

19. A manufacturing method of a display panel, comprising: The method comprises: forming a first barrier, a planarization layer and an encapsulation layer on a substrate, the substrate having a display region, a peripheral region surrounding a periphery of the display region, and a pad region located on a side of the peripheral region away from the display region, the first barrier being located in the peripheral region and surrounding the periphery of the display region, the planarization layer being located in the display region, the first barrier and the planarization layer having a first groove therebetween, along an extension direction of a first side edge of the planarization layer, the first side edge comprising a first segment boundary and a second segment boundary connected in sequence, the first side being on the same side of the display region as the pad region; wherein the encapsulation layer comprises an organic layer, a distance between an edge of the organic layer and the first segment boundary of the planarization layer is greater than a distance between the edge of the organic layer and the second segment boundary; the first side of the planarization layer comprises a first segment slope and a second segment slope connected in sequence, a bottom edge of the first segment slope being the first segment boundary, and a bottom edge of the second segment slope being the second segment boundary; in a direction perpendicular to a bearing surface of the substrate, a height of the first segment slope is greater than a height of the second segment slope, the height of the first segment slope being a distance from a top surface of the first segment slope to a bottom surface of the substrate in a direction perpendicular to the bearing surface of the substrate, and the height of the second segment slope being a distance from a top surface of the second segment slope to the bottom surface of the substrate in the direction perpendicular to the bearing surface of the substrate; forming a touch layer on the encapsulation layer, the touch layer comprising a touch signal line and a touch electrode pattern, one end of the touch signal line being electrically connected to the touch electrode pattern, the other end of the touch signal line extending from the display region to the pad region and being electrically connected to a pad of the pad region, and the touch signal line passing through the first segment boundary.

20. A display device comprising: The display device comprises the display panel according to any one of claims 1 to 18. The display device comprises the display panel according to any one of claims 1 to 18.

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