Processing unit, synchronization method for processing unit and corresponding product

Abstract

The present disclosure discloses a processing unit, a multi-core processor, a synchronization method for a processing unit / multi-core processor, and related products. The processing unit can be implemented as a computing device included in a combined processing device, and the combined processing device can also include an interface device and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operations specified by the user. The combined processing device can also include a storage device, which is respectively connected to the computing device and other processing devices, and is used to store data of the computing device and other processing devices. The processing unit provided by the solution of the present disclosure can effectively realize data synchronization between multiple cores through various synchronization instructions.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and in particular to a processing unit, a multi-core processor, a synchronization method for a processing unit / multi-core processor, a chip, and a board. Background Art

[0002] With the development of computer technology, various applications (such as video structure, advertising recommendation, intelligent translation, etc.) have higher and higher requirements on the storage capacity and computing power of machines. Since single-core processors can no longer meet the needs of applications, various multi-core processor systems have emerged. A key issue of multi-core processor systems is the collaborative work between multiple cores. Therefore, how to achieve inter-core collaboration based on multi-core structures is an urgent problem to be solved. Summary of the invention

[0003] In order to solve one or more technical problems mentioned above, the present disclosure provides a processing unit, a multi-core processor and a synchronization method for a processing unit / multi-core processor in multiple aspects, wherein the provided synchronization method can achieve data synchronization between multiple cores in a multi-core processor architecture.

[0004] In a first aspect, the present disclosure provides a processing unit comprising at least one first core, wherein: the first core is configured to: send an access permission signal to a second core in response to a first synchronization instruction associated with the second core, the access permission signal comprising information about data allowed to be accessed; receive an access operation signal to the data from the second core; and perform the access operation.

[0005] In a second aspect, the present disclosure provides a processing unit comprising at least one second core, wherein: the second core is configured to: in response to receiving an access permission signal from a first core, send an access operation signal to the first core based on information about the data allowed to be accessed included in the access permission signal; and in response to a second synchronization instruction, send a release signal to the first core to release access to the data.

[0006] In a third aspect, the present disclosure provides a multi-core processor, comprising a processing unit according to any embodiment of the first aspect and a processing unit according to any embodiment of the second aspect.

[0007] In a fourth aspect, the present disclosure provides a chip, in which is encapsulated a processing unit as in any embodiment of the first aspect, or a processing unit as in any embodiment of the second aspect, or a multi-core processor as in any embodiment of the third aspect.

[0008] In a fifth aspect, the present disclosure provides a board comprising a chip according to any one of the embodiments of the fourth aspect.

[0009] In a sixth aspect, the present disclosure provides a synchronization method for a processing unit, the processing unit comprising at least one first core, the method comprising: the first core sending an access permission signal to the second core in response to a first synchronization instruction associated with the second core, the access permission signal comprising information about data allowed to be accessed; the first core receiving an access operation signal to the data from the second core; and the first core performing the access operation.

[0010] In the seventh aspect, the present disclosure provides a synchronization method for a processing unit, wherein the processing unit includes at least one second core, the method comprising: the second core, in response to receiving an access permission signal from the first core, sends an access operation signal to the first core based on information about the data allowed to be accessed included in the access permission signal; and the second core, in response to a second synchronization instruction, sends a release signal to the first core to release access to the data.

[0011] In the eighth aspect, the present disclosure provides a synchronization method for a multi-core processor, wherein the multi-core processor includes a first processing unit and a second processing unit, and the method includes: the first processing unit executes the synchronization method according to any embodiment of the aforementioned sixth aspect; and the second processing unit executes the synchronization method according to any embodiment of the aforementioned seventh aspect.

[0012] Through the processing unit, multi-core processor, synchronization method for processing unit / multi-core processor, chip and board provided above, the disclosed embodiment provides a solution for data synchronization between two cores in a multi-core processor architecture, thereby ensuring the collaborative work between the cores in the multi-core processor architecture, which is conducive to the flexible scheduling of multi-core processor tasks and the improvement of processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0014] Figure 1 An exemplary structural diagram showing a multi-core processor architecture to which the disclosed embodiments may be applied;

[0015] Figure 2 An exemplary internal architectural diagram of a processor core is shown;

[0016] Figure 3A-3C A schematic flow chart showing a synchronization method according to an embodiment of the present disclosure;

[0017] Figure 4A-4B A schematic diagram showing a data storage space according to an embodiment of the present disclosure;

[0018] Figure 5 A structural diagram showing a combined processing device according to an embodiment of the present disclosure; and

[0019] Figure 6 A schematic diagram of the structure of a board according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0021] It should be understood that the terms "first", "second", "third", and "fourth" and the like that may be used in the claims, specifications, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their collections.

[0022] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0023] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0024] The specific implementation of the present disclosure is described in detail below with reference to the accompanying drawings.

[0025] Figure 1 An exemplary structural diagram of a multi-core processor architecture to which the disclosed embodiments can be applied is shown. The multi-core processor 100 can be used to process input data such as computer vision, speech, natural language, data mining, etc. Figure 1 The multi-core processor 100 in the embodiment adopts a multi-core hierarchical structure design. The multi-core processor 100 can be used as a system on chip, which can include multiple clusters (Clusters), and each cluster includes multiple cores (Cores). In other words, the multi-core processor 100 is composed of a hierarchy of system on chip-cluster-core.

[0026] At the system-on-chip level, Figure 1 As shown, the multi-core processor 100 includes an external memory controller 111 , a peripheral communication module 112 , an on-chip interconnect module 113 , and a plurality of clusters 115 .

[0027] There may be multiple external storage controllers 111, and two are shown in the figure as an example, which are used to respond to access requests issued by the processor core, access external storage devices (such as DRAM), and read or write data from outside the chip. The peripheral communication module 112 is used to receive a control signal from a processing device (not shown) through an interface device (not shown) to start the multi-core processor 100 to perform tasks. The on-chip interconnect module 113 connects the external storage controller 111, the peripheral communication module 112 and multiple clusters 115 to transmit data and control signals between each module. Multiple clusters 115 are the computing cores of the multi-core processor 100. Four are shown in the figure as an example. With the development of hardware, the multi-core processor 100 disclosed in the present disclosure may also include 8, 16, 64, or even more clusters 115. Clusters 115 are used to efficiently execute deep learning algorithms.

[0028] At the cluster level, Figure 1 As shown, each cluster 115 includes a plurality of processor cores (IPU cores) 121 and a memory core (MEM core) 122 .

[0029] Four processor cores 121 are shown in the figure as an example, but the present disclosure does not limit the number of processor cores 121 .

[0030] The storage core 122 is mainly used for storage and communication, that is, to store shared data or intermediate results between the processor cores 121, and to perform communication between the cluster 115 and the DRAM 127, communication between the clusters 115, and communication between the processor cores 121. In other embodiments, the storage core 122 has the capability of scalar operations and is used to perform scalar operations.

[0031] The storage core 122 includes a shared memory unit (SMEM) 124, a broadcast bus 123, a cluster direct memory access module (CDMA) 126, and a global direct memory access module (GDMA) 125. SMEM 124 plays the role of a high-performance data transfer station. The data reused between different processor cores 121 in the same cluster 115 does not need to be obtained from DRAM 127 by each processor core 121, but is transferred between the processor cores 121 through SMEM 124. The storage core 122 only needs to quickly distribute the reused data from SMEM 124 to multiple processor cores 121 to improve the efficiency of inter-core communication and greatly reduce on-chip and off-chip input / output access. The broadcast bus 123, CDMA 126, and GDMA 125 are respectively used to perform communication between processor cores 121, communication between clusters 115, and data transmission between clusters 115 and DRAM 127. They will be explained below.

[0032] The broadcast bus 123 is used to complete high-speed communication between the processor cores 121 in the cluster 115. The broadcast bus 123 of this embodiment supports inter-core communication modes including unicast, multicast and broadcast. Unicast refers to point-to-point (i.e., single processor core to single processor core) data transmission, multicast is a communication mode of transmitting a copy of data from the SMEM 124 to several specific processor cores 121, and broadcast is a communication mode of transmitting a copy of data from the SMEM 124 to all processor cores 121, which is a special case of multicast.

[0033] The CDMA 126 is used to control memory access of the SMEM 124 between different clusters 115 in the same multi-core processor 100 .

[0034] The GDMA 125 cooperates with the external memory controller 111 to control memory access from the SMEM 124 of the cluster 115 to the DRAM 127 , or reads data from the DRAM 127 to the SMEM 124 .

[0035] Although Figure 1 The multi-core processor architecture is described by taking a multi-core processor 100 of a single system on chip as an example. Those skilled in the art will appreciate that a multi-core processor may also be constructed by using multiple single-core or multi-core processing units, and the present disclosure is not limited in this regard.

[0036] Figure 2 FIG. 1 shows an exemplary internal architecture diagram of the processor core 121. Figure 2 As shown, the processor core 121 may include three modules: a control module 21 , a computing module 22 and a storage module 23 .

[0037] The control module 21 is used to coordinate and control the operation of the operation module 22 and the storage module 23 to complete the deep learning task, and includes an instruction fetch unit (IFU) 211 and an instruction decode unit (IDU) 212. The instruction fetch unit 211 is used to obtain instructions from a processing device (not shown), and the instruction decode unit 212 decodes the obtained instructions and sends the decoding results to the operation module 22 and the storage module 23 as control information.

[0038] The operation module 22 includes a vector operation unit 221 and a matrix operation unit 222. The vector operation unit 221 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformation; the matrix operation unit 222 is responsible for the core calculation of the deep learning algorithm, such as matrix multiplication and convolution.

[0039] The storage module 23 is used to store or move related data, including a neuron RAM (NRAM) 231, a weight RAM (WRAM) 232, an input / output direct memory access module (IODMA) 233, and a move direct memory access module (MVDMA) 234. NRAM 231 is used to store input and output data and intermediate results for calculation by the processor core 121; WRAM 232 is used to store the weights of the deep learning network; IODMA 233 is used to store the weights of the deep learning network through the broadcast bus 123 (see Figure 1 ) controls the memory access of NRAM 231 / WRAM 232 and DRAM 127; MVDMA 234 is used to control the memory access of NRAM 231 / WRAM 232 and SMEM 124.

[0040] In some embodiments, GDMA 125 (see Figure 1 ) functions and IODMA 233 (see Figure 2) can be integrated into the same component. For the convenience of description, the present disclosure regards GDMA 125 and IODMA 233 as different components. For those skilled in the art, as long as the functions they implement and the technical effects they achieve are similar to those of the present disclosure, they belong to the protection scope of the present disclosure. Furthermore, the functions of GDMA 125, IODMA 233, CDMA 126, and MVDMA 234 can also be implemented by the same component. Similarly, as long as the functions they implement and the technical effects they achieve are similar to those of the present disclosure, they belong to the protection scope of the present disclosure.

[0041] In a multi-core processor architecture, multiple processes can run simultaneously on multiple cores, and some processes may be associated with each other. Multiple processes may need to synchronize data in order to complete the same task. In multi-core processing mode, each core maintains the data under its own resources, which is not seen by other cores, nor can it see the data of other cores. Therefore, before the data to be synchronized is transmitted, synchronization is required to ensure that both ends of the synchronization are ready before data transmission can be performed. Based on the aforementioned multi-core processor architecture, data synchronization can include synchronization between storage cores between different clusters, and synchronization between storage cores and processor cores within the same cluster. The disclosed embodiment provides a synchronization mechanism for a multi-core processor architecture, which can be applied to any of the above-mentioned synchronization scenarios.

[0042] In an embodiment of the present disclosure, a synchronization mechanism of a lend / return mode is provided for a multi-core processor architecture, in which one core (lender) lends the data in its own core to another core, so that the other core (borrower or user) can directly access the data in the core.

[0043] To facilitate understanding of the exemplary embodiments of the present disclosure, Figure 3A An exemplary flow chart of an interactive synchronization method between two cores in a multi-core processor architecture according to an embodiment of the present disclosure is shown. The multi-core processor architecture may be, for example, the one described above with reference to Figure 1-Figure 2 An exemplary multi-core processor architecture is described. Figure 3A As shown, the synchronization method involves at least two cores: a first core 310 and a second core 320, and data synchronization is performed between the first core 310 and the second core 320. The first core and the second core can be provided by different processing units or by the same processing unit, and the present disclosure is not limited here. For the convenience of description, it is assumed that the first core 310 is a lending end, which lends the data in its own core to another core, that is, it provides data access information in its own core; the second core 320 is a user end or a borrower end, which can directly access the data of the lending end according to the data access information provided by the lending end.

[0044] Those skilled in the art will appreciate that for different synchronization scenarios, the first core and the second core may represent different cores. For example, for inter-cluster synchronization of a multi-core processor, the first core and the second core may be storage cores of different clusters in the multi-core processor (see Figure 1 For another example, for intra-cluster synchronization of a multi-core processor, the first core and the second core may be processor cores or storage cores in the same cluster of the multi-core processor. Specifically, the first core may be a processor core and the second core may be a storage core; or vice versa, the first core may be a storage core and the second core may be a processor core.

[0045] In an embodiment of the present disclosure, two synchronization instructions are provided: a first synchronization instruction and a second synchronization instruction.

[0046] The first synchronization instruction is used for a core that is a data lender in a multi-core processor architecture, such as the first core 310 in this embodiment. The first synchronization instruction may be a lend instruction, which is used to instruct that the designated data of the lender is lent to another core for use in a synchronization event.

[0047] The first synchronization instruction may include information related to the data to be synchronized involved in the synchronization event, information related to the synchronization object, and so on. The synchronization object may be, for example, a core in a multi-core processor that serves as a data borrowing end, such as the second core 320 in this embodiment. In the embodiment of the present disclosure, due to the use of a synchronization mechanism in a lend (Lend) / return (Return) mode, the lending end needs to lend the data in its own core to another core, that is, it is necessary to provide the other core with a way to access the data in its own core. In this regard, when the data to be synchronized is tensor data, a descriptor of the tensor data may be included in the first synchronization instruction, so that another core (borrowing end or using end) can directly access the data of the lending end based on the descriptor. The specific content of the descriptor of tensor data will be described later. In addition, the information related to the synchronization object may include, for example, the identification of the core.

[0048] The second synchronization instruction is used for a core in a multi-core processor architecture that is a data borrower or user, such as the second core 320 in this embodiment. The second synchronization instruction may be a return instruction, which is used to indicate that the borrowed data has been used up by the relevant second core.

[0049] The second synchronization instruction may include various information as needed, such as identification information of the relevant synchronization event. Thus, the data borrowing end may determine the synchronization object (e.g., the data lending end) corresponding to the synchronization event and / or the borrowed synchronization data based on the identification information of the synchronization event. Then, the data borrowing end may return the borrowed data to the data lending end.

[0050] See also Figure 3A, which shows the interaction process for data synchronization between the first core 310 and the second core 320. The first core 310 and the second core 320 can each execute corresponding instructions, which may include synchronization instructions, such as the first synchronization instruction or the second synchronization instruction, for indicating data synchronization events between the cores.

[0051] In step S311, the first core may encounter a first synchronization instruction during the execution of the instruction. As described above, the first synchronization instruction means that there is a data synchronization event, in which the first core, as a data lending end, needs to lend the data in its core to another core for use. The first synchronization instruction may include information related to the data to be synchronized involved in the synchronization event, information related to the synchronization object, and so on. In this example, the synchronization object is the second core 320, that is, the data borrowing end or the using end. In some embodiments, when the data to be synchronized is tensor data, the information related to the data to be synchronized is a descriptor of the tensor data, at least used to describe the shape information of the tensor data.

[0052] Next, in step S313, the first core sends an access permission signal to the synchronization object indicated in the first synchronization instruction (the second core 320 in this example) in response to the first synchronization instruction, and the access permission signal includes information about the data that is allowed to be accessed. As described above, when the data to be synchronized is tensor data, the information about the data that is allowed to be accessed can be a descriptor of the tensor data.

[0053] At this time, the first core is ready to lend the data in its own core to the second core, so the first core can wait for the access operation from the second core.

[0054] At the second core 320 , when the second core receives the access permission signal from the first core, it may send an access operation signal to the first core for the data based on the information on the data allowed to be accessed included in the access permission signal (step S323 ).

[0055] In some embodiments, before sending the access operation signal, the second core may first perform fusion processing and decoding on the local instruction to generate an access operation (step S322).

[0056] Specifically, the second core generates a fused instruction based on information about the data allowed to be accessed and instructions related to the data to be executed in the second core in response to receiving an access permission signal from the first core. In other words, when the second core wishes to directly use the data on the first core, it can extract instructions related to the data on the first core from the local instruction stream, and modify these instructions according to the data information provided in the received access permission signal, so that the modified instructions are operation instructions directly for the data on the first core. In some implementations, when the data is tensor data, the descriptor information of the tensor data contained in the access permission signal can be extracted and fused into the relevant instructions of the local instruction stream.

[0057] Next, the fused instruction may be decoded or decoded into an access operation to the data; and an access operation signal including the access operation may be sent to the first core.

[0058] In the synchronization mechanism provided by the disclosed embodiment, the core as the data lending end only needs to provide access information of the lent data and passively accept access, and the decoding of instructions and the processing of data are completely undertaken by the data borrowing end or the data using end.

[0059] In some embodiments, the access operation may include one or more access operations to the data. These access operations may be sent to the first core in a combined access operation signal, or may be sent to the first core one by one through multiple access operation signals. The present disclosure is not limited in this regard.

[0060] The access operation to the data may include any of the following types: a read operation and a write operation. The access operation includes relevant physical address information. For example, when the access operation is a read operation, it may include the physical address information of the data to be read. For another example, when the access operation is a write operation, it may include the physical address information to which the data is to be written. For tensor data, the relevant physical address information may be a descriptor of the tensor data. The first core may determine the corresponding physical address according to the descriptor of the tensor data when instructing these access operations.

[0061] Next, the method may flow to the first core 310. When the first core receives the access operation signal to the data from the second core, it may perform the access operation.

[0062] Specifically, in step S314, the first core may insert the received access operation into a local instruction stream of the first core and execute the instruction stream accordingly.

[0063] During the execution of the local instruction stream, the first core still maintains the dependency of the instruction stream. That is, the first core treats the access operations generated by the inserted second core as its own local instructions for execution, and also applies the instruction order preservation method adopted by the first core locally to these access operations. In other words, the borrowed data still maintains the dependency in the local core. The first core can adopt various instruction order preservation methods known to those skilled in the art, and this disclosure is not limited to this, so its description is omitted.

[0064] Figure 3A Two access operations are exemplarily shown, for example, step S315, performing a read operation to transmit the read data to the second core; and step S316, performing a write operation to write the data specified in the operation to the accessible data address in the first core. Those skilled in the art can understand that the above two access operations are only exemplary, there may be more or less operations, and the order of operations may also be different, and the present disclosure is not limited in this respect.

[0065] When the second check related data is used up, it may execute the second synchronization instruction (step S324). As mentioned above, the second synchronization instruction may be a return instruction, which is used to indicate that the data borrowed by the second check has been used up. The second synchronization instruction may include identification information of the related synchronization event.

[0066] Thus, in response to the second synchronization instruction, the second core may send a release signal to the first core in step S326 to release access to the loaned data. The data borrowing end may determine the synchronization object (e.g., the data lending end) and / or the borrowed synchronization data corresponding to the synchronization event based on the identification information of the synchronization event. Then, the data borrowing end may return the borrowed data to the data lending end. Accordingly, the first core may release the lending status of the relevant data according to the received release signal (not shown in the figure).

[0067] Alternatively or additionally, in some embodiments, when the second core receives the access permission signal from the first core, it can record the relevant synchronization event (step S321). The record indicates that there is a data synchronization event associated with the first core, and in this event, the second core needs to borrow data from the first core. In these embodiments, when the second core executes the second synchronization instruction, it can query whether there is an associated unprocessed synchronization event (step S325); and when there is an associated unprocessed synchronization event ("yes" branch), send a release signal (step S326) and cancel the synchronization event. Otherwise ("no" branch), continue to wait until a synchronization event is received.

[0068] Optionally or additionally, in some embodiments, before the first core sends an access permission signal to the second core, the method further includes step S312, checking whether the instructions that have a dependency relationship with the data to be lent have been completed. The access permission signal is sent to the second core only after the instructions that have a dependency relationship are completed ("yes" branch). Otherwise ("no" branch), it is necessary to wait for the completion of these instructions. In this way, it can be ensured that the dependency relationship between the lent data and other instructions has been processed before the lent data is lent, thereby avoiding errors when it is accessed by the second core later.

[0069] Those skilled in the art will appreciate that, since the first core and the second core can execute their respective instruction streams in parallel, the instruction execution progresses may be different from each other. Figure 3A 3 shows the case where the first core 310 executes the synchronization instruction before the second core 320. Those skilled in the art can understand that when the second core 320 executes the synchronization instruction before the first core 310, the synchronization process can be implemented similarly, which will not be described in detail here.

[0070] During the period when the second core performs operations on the data lent by the first core, since the first core only provides the lent data and does not perform other operations, all exceptions that occur during the execution process are gathered to the borrowing end, that is, the second core reports the instruction. Therefore, in some embodiments, when an exception occurs on the borrowing end side and enters the dynamic reset equipment state, the borrowed data is returned to the lending end (the first core) to avoid the data lent at the lending end from being unable to be released, resulting in a deadlock in subsequent instructions.

[0071] The various signal transmissions between the first core and the second core described above may be implemented in various ways. These signal transmissions include, for example, access permission signals, release signals, etc. In some embodiments, the transmission of these signals may be implemented in the form of semaphores.

[0072] For ease of understanding, Figure 3A The synchronization mechanism provided by the embodiment of the present disclosure is illustrated in an interactive manner. However, those skilled in the art can understand that the embodiment of the present disclosure also provides a synchronization method for each core in the synchronization process.

[0073] Figure 3B An exemplary flow chart of a synchronization method for a processing unit according to an embodiment of the present disclosure is shown, wherein the processing unit includes at least one first core.

[0074] like Figure 3BAs shown, method 300B includes step S331, in which the first core sends an access permission signal to the second core in response to a first synchronization instruction associated with the second core, wherein the access permission signal includes information about data that is allowed to be accessed. The first synchronization instruction is, for example, a lend instruction, which indicates that the data in the first core is lent to the second core for use. Then, in step S332, the first core receives an access operation signal for the data from the second core. Finally, in step S333, the received access operation is executed.

[0075] In some embodiments, step S333 may include: step S3331, inserting the access operation into the local instruction stream of the first core; and step S3332, executing the local instruction stream and maintaining the dependency between the instruction streams during the execution of the local instruction stream.

[0076] An access operation may include one or more access operations to data, and an access operation may include any of the following types of operations: a read operation and a write operation.

[0077] Optionally or additionally, before sending the access permission signal to the second core, the method 300B may further include: checking whether instructions having a dependency relationship with the data to be borrowed have been completed; and sending the access permission signal to the second core only after the instructions having a dependency relationship have been completed.

[0078] In some embodiments, the data to be lent is tensor data, and the information about the data to be accessed includes a descriptor of the tensor data. The descriptor may include at least shape information of the tensor data.

[0079] In some embodiments, the access grant signal is sent in the form of a semaphore.

[0080] Figure 3C An exemplary flow chart of a synchronization method for a processing unit according to an embodiment of the present disclosure is shown, wherein the processing unit includes at least one second core.

[0081] like Figure 3C As shown, the method 300C includes step S341, in response to receiving an access permission signal from the first core, sending an access operation signal to the first core based on information about the data allowed to be accessed included in the access permission signal.

[0082] Specifically, in some embodiments, before sending the access operation signal, step S3411 may be included, where the second core may generate a fusion instruction based on information about the data allowed to be accessed and instructions related to the data to be executed in the second core. In some implementations, when the data is tensor data, the descriptor information of the tensor data contained in the access permission signal may be extracted and fused into the related instructions of the local instruction stream.

[0083] Next, in step S3412, the second core may decode or decode the fused instruction into an access operation to the data. Finally, in step S3413, an access operation signal including the access operation is sent to the first core.

[0084] In the synchronization mechanism provided by the disclosed embodiment, the core as the data lending end only needs to provide access information of the lent data and passively accept access, and the decoding of instructions and the processing of data are completely undertaken by the data borrowing end or the data using end.

[0085] In some embodiments, the access operation may include one or more access operations to the data. These access operations may be sent to the first core in a combined access operation signal, or may be sent to the first core one by one through multiple access operation signals. The present disclosure is not limited in this regard.

[0086] The access operation to the data may include any of the following types: a read operation and a write operation. The access operation includes relevant physical address information. For example, when the access operation is a read operation, it may include the physical address information of the data to be read. For another example, when the access operation is a write operation, it may include the physical address information to which the data is to be written. For tensor data, the relevant physical address information may be a descriptor of the tensor data. The first core may determine the corresponding physical address according to the descriptor of the tensor data when instructing these access operations.

[0087] When the second check related data is used up, it may execute the second synchronization instruction. As mentioned above, the second synchronization instruction may be a return instruction, which is used to indicate that the data borrowed by the second check has been used up. The second synchronization instruction may include identification information of the related synchronization event.

[0088] Therefore, at step S342, in response to the second synchronization instruction, the second core may send a release signal to the first core to release access to the loaned data. The data borrowing end may determine the synchronization object (e.g., the data lending end) corresponding to the synchronization event and / or the borrowed synchronization data based on the identification information of the synchronization event. Then, the data borrowing end may return the borrowed data to the data lending end. Accordingly, the first core may release the lending status of the relevant data according to the received release signal.

[0089] Alternatively or additionally, in some embodiments, when the second core receives the access permission signal from the first core, it may record the relevant synchronization event ( Figure 3C(not shown). The record indicates that there is a data synchronization event associated with the first core, and in the event, the second core wants to borrow data from the first core. In these embodiments, when the second core executes the second synchronization instruction, it can query whether there is an associated unprocessed synchronization event; and when there is an associated unprocessed synchronization event, send a release signal and cancel the synchronization event. Otherwise, continue to wait until a synchronization event is received.

[0090] Figure 3B and Figure 3C The specific implementation of each step can refer to the previous combination Figure 3A The description is not repeated here.

[0091] from FIG. 3A to FIG. 3C As can be seen from the method flow chart, the disclosed embodiment provides a synchronization mechanism of a lend / return mode, in which one core (lender end) lends the data in its own core to another core, so that the other core (borrower end or user end) can directly access the data in the core. In the case where the lent data is tensor data, the lender end needs to provide the descriptor of the tensor data to the borrower end. The borrower end accesses the tensor data according to the descriptor.

[0092] Although during the data synchronization process, instructions exist in both the first core (lending end) and the second core (borrowing end), and each maintains sequential consistency within the core, the second core (borrowing end) takes the initiative and is also the actual executor. For example, the lending end only provides access information to the data to be lent and passively receives access, while the borrowing end is responsible for instruction decoding and data processing. In some implementations, exception handling is also implemented on the borrowing end. When an exception occurs during the execution of the lent data, the second core enters the dynamic reset equipment state and returns the borrowed data to the lending end (first core) to avoid the data lent at the lending end from being unable to be released, resulting in a deadlock in subsequent instructions.

[0093] The synchronization mechanism applied to a multi-core processor of the embodiment of the present disclosure has been described above with reference to the flowchart. It should be noted that for the aforementioned method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited to the described order of actions, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0094] It should be further explained that although Figure 3A-3CThe steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3A-3C At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0095] With the development of artificial intelligence technology, in tasks such as image processing and pattern recognition, the operands are often multi-dimensional vectors (i.e., tensor data), which are usually processed on the multi-core processor of the disclosed embodiment. Therefore, how to synchronize tensor data between multiple cores of a multi-core processor is also a problem that needs to be solved in the current computing field.

[0096] In the embodiments of the present disclosure, when the data to be synchronized is tensor data, a descriptor may be included in the operand in the synchronization instruction, and information related to the tensor data may be quickly obtained through the descriptor. For example, the first synchronization instruction may include a descriptor of the tensor data to be borrowed, and send it to the second core (borrowing end) through an access permission signal, and then the second core (borrowing end) may access the tensor data based on the descriptor.

[0097] Specifically, the descriptor may indicate at least the following information: shape information of the tensor data. The shape information of the tensor data may be used to determine a data address of the tensor data corresponding to the operand in the data storage space.

[0098] Various possible implementations of the shape information of tensor data will be described in detail below with reference to the accompanying drawings.

[0099] Tensors can contain data in many different forms. Tensors can be of different dimensions, for example, scalars can be considered as 0-dimensional tensors, vectors can be considered as 1-dimensional tensors, and matrices can be 2-dimensional or higher tensors. The shape of a tensor includes information such as the dimensions of the tensor and the size of each dimension of the tensor. For example, for a 3D tensor:

[0100] x 3 =[[[1, 2, 3], [4, 5, 6]]; [[7, 8, 9], [10, 11, 12]]]

[0101] The shape or dimensions of this tensor can be represented as X 3=(2, 2, 3), that is, the three parameters indicate that the tensor is a three-dimensional tensor, and the size of the first dimension of the tensor is 2, the size of the second dimension is 2, and the size of the third dimension is 3. When storing tensor data in a memory, the shape of the tensor data cannot be determined according to its data address (or storage area), and further, related information such as the relationship between multiple tensor data cannot be determined, resulting in low access efficiency of the processor to the tensor data.

[0102] In one possible implementation, a descriptor may be used to indicate the shape of N-dimensional tensor data, where N is a positive integer, such as N=1, 2, or 3, or zero. The three-dimensional tensor in the above example may be represented by a descriptor as (2, 2, 3). It should be noted that the present disclosure has no limitation on the manner in which a descriptor indicates the shape of a tensor.

[0103] In one possible implementation, the value of N can be determined according to the dimension (also called order) of the tensor data, or it can be set according to the usage requirements of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor can be used to indicate the shape (e.g., offset, size, etc.) of the three-dimensional tensor data. It should be understood that those skilled in the art can set the value of N according to actual needs, and this disclosure does not limit this.

[0104] Although tensor data can be multi-dimensional, because the layout of the memory is always one-dimensional, there is a corresponding relationship between the tensor and the storage on the memory. Tensor data is usually allocated in a continuous storage space, that is, the tensor data can be expanded one-dimensionally (for example, row-first) and stored in the memory.

[0105] This relationship between the tensor and the underlying storage can be expressed by the offset of the dimension, the size of the dimension, the stride of the dimension, etc. The offset of the dimension refers to the offset relative to the reference position in that dimension. The size of the dimension refers to the size of the dimension, that is, the number of elements in that dimension. The stride of the dimension refers to the interval between adjacent elements in that dimension. For example, the stride of the three-dimensional tensor above is (6,3,1), that is, the stride of the first dimension is 6, the stride of the second dimension is 3, and the stride of the third dimension is 1.

[0106] Figure 4A FIG. 2 is a schematic diagram showing a data storage space according to an embodiment of the present disclosure. Figure 4AAs shown, the data storage space 41 stores two-dimensional data in a row-first manner, which can be represented by (x, y) (where the X axis is horizontal to the right and the Y axis is vertical to the bottom). The size in the X-axis direction (the size of each row, or the total number of columns) is ori_x (not shown in the figure), the size in the Y-axis direction (the total number of rows) is ori_y (not shown in the figure), and the starting address PA_start (reference address) of the data storage space 41 is the physical address of the first data block 42. The data block 43 is part of the data in the data storage space 41, and its offset 45 in the X-axis direction is represented by offset_x, its offset 44 in the Y-axis direction is represented by offset_y, its size in the X-axis direction is represented by size_x, and its size in the Y-axis direction is represented by size_y.

[0107] In a possible implementation, when a descriptor is used to define the data block 43, the data reference point of the descriptor can use the first data block of the data storage space 41, and the reference address of the descriptor can be agreed to be the starting address PA_start of the data storage space 41. Then, the content of the descriptor of the data block 43 can be determined by combining the size ori_x of the data storage space 41 on the X axis, the size ori_y of the data storage space 41 on the Y axis, the offset offset_y of the data block 43 in the Y axis direction, the offset offset_x in the X axis direction, the size size_x in the X axis direction, and the size size_y in the Y axis direction.

[0108] In a possible implementation, the following formula (1) may be used to represent the content of the descriptor:

[0109]

[0110] It should be understood that although in the above examples, the content of the descriptor represents a two-dimensional space, those skilled in the art may set the specific dimension represented by the content of the descriptor according to actual conditions, and the present disclosure does not limit this.

[0111] In one possible implementation, a reference address of a data reference point of the descriptor in the data storage space may be agreed upon, and based on the reference address, the content of the descriptor of the tensor data may be determined according to the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point.

[0112] For example, the reference address PA_base of the data reference point of the descriptor in the data storage space can be agreed upon. For example, a data (e.g., data at position (2, 2)) can be selected in the data storage space 41 as the data reference point, and the physical address of the data in the data storage space is used as the reference address PA_base. The position of the two vertices at the diagonal position relative to the data reference point can be used to determine the reference address PA_base. Figure 4A The content of the descriptor of the data block 43 in the data block 43. First, the positions of at least two vertices at the diagonal positions of the data block 43 relative to the data reference point are determined, for example, the positions of the diagonal vertices from the upper left to the lower right direction relative to the data reference point are used, wherein the relative position of the upper left vertex is (x_min, y_min), and the relative position of the lower right vertex is (x_max, y_max), and then the content of the descriptor of the data block 43 can be determined according to the reference address PA_base, the relative position of the upper left vertex (x_min, y_min), and the relative position of the lower right vertex (x_max, y_max).

[0113] In a possible implementation, the following formula (2) may be used to represent the content of the descriptor (the base address is PA_base):

[0114]

[0115] It should be understood that although the above example uses the vertices at the upper left corner and the lower right corner to determine the content of the descriptor, those skilled in the art can set the specific vertices of at least two vertices at the diagonal positions according to actual needs, and the present disclosure does not limit this.

[0116] In a possible implementation, the content of the descriptor of the tensor data can be determined based on the reference address of the data reference point of the descriptor in the data storage space and the mapping relationship between the data description position and the data address of the tensor data indicated by the descriptor. The mapping relationship between the data description position and the data address can be set according to actual needs. For example, when the tensor data indicated by the descriptor is three-dimensional space data, the function f(x, y, z) can be used to define the mapping relationship between the data description position and the data address.

[0117] In a possible implementation, the following formula (3) may be used to represent the content of the descriptor:

[0118]

[0119] In a possible implementation, the descriptor is also used to indicate the address of the N-dimensional tensor data, wherein the content of the descriptor also includes at least one address parameter representing the address of the tensor data. For example, the content of the descriptor may be the following formula (4):

[0120]

[0121] Where PA is an address parameter. The address parameter can be a logical address or a physical address. When parsing the descriptor, PA can be used as any vertex, middle point or preset point of the vector shape, and the corresponding data address can be obtained by combining the shape parameters in the X direction and the Y direction.

[0122] In a possible implementation, the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address includes a starting address of the data storage space.

[0123] In a possible implementation, the descriptor may further include at least one address parameter representing the address of the tensor data. For example, the content of the descriptor may be the following formula (5):

[0124]

[0125] Among them, PA_start is the reference address parameter and will not be repeated here.

[0126] It should be understood that those skilled in the art can set the mapping relationship between the data description location and the data address according to actual conditions, and this disclosure does not limit this.

[0127] In a possible implementation, an agreed reference address can be set in a task, and the descriptors in the instructions under this task all use this reference address, and the descriptor content may include shape parameters based on this reference address. This reference address can be determined by setting the environmental parameters of this task. The relevant description and use of the reference address can be found in the above embodiment. In this implementation, the content of the descriptor can be mapped to a data address more quickly.

[0128] In a possible implementation, the reference address may be included in the content of each descriptor, and the reference address of each descriptor may be different. Compared with the method of setting a common reference address using environmental parameters, each descriptor in this method can describe data more flexibly and use a larger data address space.

[0129] In a possible implementation, the data address of the data corresponding to the operand of the processing instruction in the data storage space can be determined according to the content of the descriptor. The calculation of the data address is automatically completed by hardware, and the calculation method of the data address will be different when the content of the descriptor is expressed in different ways. The present disclosure does not limit the specific calculation method of the data address.

[0130] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y, respectively, and the size is size_x*size_y. Then, the starting data address PA1 of the tensor data indicated by the descriptor in the data storage space is (x，y) It can be determined using the following formula (6):

[0131] PA1 (x，y )=PA_start+(offset_y-1)*ori_x+offset_x (6)

[0132] The data starting address PA1 is determined according to the above formula (6): (x，y) , combined with the offsets offset_x and offset_y, and the sizes size_x and size_y of the storage area, the storage area of ​​the tensor data indicated by the descriptor in the data storage space can be determined.

[0133] In one possible implementation, when the operand also includes a data description position for the descriptor, the data address of the data corresponding to the operand in the data storage space can be determined according to the content of the descriptor and the data description position. In this way, part of the data (e.g., one or more data) in the tensor data indicated by the descriptor can be processed.

[0134] For example, the content of the descriptor in the operand is expressed using formula (2). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y, respectively, and the size is size_x*size_y. The data description position for the descriptor included in the operand is (x q ,y q ), then the data address PA2 of the tensor data indicated by the descriptor in the data storage space (x，y) It can be determined using the following formula (7):

[0135] PA2 (x，y) =PA_start+(offset_y+y q -1)*ori_x+(offset_x+x q ) (7)

[0136] In a possible implementation, the descriptor may indicate the data in blocks. Data blocks can effectively speed up the operation and improve the processing efficiency in many applications. For example, in graphics processing, convolution operations often use data blocks for fast operation processing.

[0137] Figure 4B FIG. 2 is a schematic diagram showing data blocks in a data storage space according to an embodiment of the present disclosure. Figure 4B As shown, the data storage space 46 also uses a row-first approach to store two-dimensional data, which can be represented by (x, y) (where the X axis is horizontal to the right and the Y axis is vertical to the bottom). The size in the X-axis direction (the size of each row, or the total number of columns) is ori_x (not shown in the figure), and the size in the Y-axis direction (the total number of rows) is ori_y (not shown in the figure). Figure 4A Tensor data of Figure 4B The tensor data stored in includes multiple data blocks.

[0138] In this case, the descriptor needs more parameters to represent these data blocks. Taking the X axis (X dimension) as an example, the following parameters may be involved: ori_x, x.tile.size (size in the block 47), x.tile.stride (the step length in the block 48, that is, the distance between the first point of the first small block and the first point of the second small block), x.tile.num (number of blocks, Figure 4B ), x.stride (the overall step size, i.e., the distance from the first point in the first row to the first point in the second row), etc. Other dimensions can similarly include corresponding parameters.

[0139] In a possible implementation, the descriptor may include an identifier of the descriptor and / or content of the descriptor. The identifier of the descriptor is used to distinguish the descriptor, for example, the identifier of the descriptor may be a number for it; the content of the descriptor may include at least one shape parameter representing the shape of the tensor data. For example, the tensor data is 3D data, and among the three dimensions of the tensor data, the shape parameters of two dimensions are fixed, and the content of its descriptor may include the shape parameter representing another dimension of the tensor data.

[0140] In one possible implementation, the data address of the data storage space corresponding to each descriptor may be a fixed address. For example, a separate data storage space may be divided for tensor data, and the starting address of each tensor data in the data storage space corresponds to the descriptor one by one. In this case, the circuit or module responsible for parsing the computing instruction (e.g., an entity outside the computing device of the present disclosure) can determine the data address of the data corresponding to the operand in the data storage space according to the descriptor.

[0141] In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor can also be used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor may also include at least one address parameter representing the address of the tensor data. For example, the tensor data is 3D data, and when the descriptor points to the address of the tensor data, the content of the descriptor may include an address parameter representing the address of the tensor data, such as the starting physical address of the tensor data, or may include multiple address parameters of the address of the tensor data, such as the starting address + address offset of the tensor data, or address parameters of the tensor data based on each dimension. Those skilled in the art may set the address parameters according to actual needs, and this disclosure is not limited thereto.

[0142] In one possible implementation, the address parameter of the tensor data may include a reference address of a data reference point of the descriptor in the data storage space of the tensor data. The reference address may be different according to the change of the data reference point. The present disclosure does not limit the selection of the data reference point.

[0143] In a possible implementation, the reference address may include the starting address of the data storage space. When the data reference point of the descriptor is the first data block of the data storage space, the reference address of the descriptor is the starting address of the data storage space. When the data reference point of the descriptor is other data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

[0144] In a possible implementation, the shape parameters of the tensor data include at least one of the following: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address. Among them, the data description position is the mapping position of the point or area in the tensor data indicated by the descriptor. For example, when the tensor data is 3D data, the descriptor can use a three-dimensional coordinate space (x, y, z) to represent the shape of the tensor data, and the data description position of the tensor data can be the position of the point or area mapped in the three-dimensional space represented by the three-dimensional space coordinates (x, y, z).

[0145] It should be understood that those skilled in the art can select shape parameters representing tensor data according to actual conditions, and this disclosure does not limit this. By using descriptors in the data access process, associations between data can be established, thereby reducing the complexity of data access and improving instruction processing efficiency.

[0146] Figure 5 is a structural diagram showing a combined processing device 500 according to an embodiment of the present disclosure. Figure 5 As shown in FIG. 5 , the combined processing device 500 includes a computing device 502, an interface device 504, other processing devices 506, and a storage device 508. According to different application scenarios, the computing device may include one or more computing devices 510, which may be configured as Figure 1 The multi-core processor shown is used to implement the present invention in combination with Figure 3A-3B The operation described.

[0147] In different embodiments, the computing processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, the computing processing device of the present disclosure may be considered to have a homogeneous multi-core structure.

[0148] In exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0149] In one or more embodiments, the other processing device can serve as an interface between the computing device disclosed herein (which can be embodied as an artificial intelligence such as a computing device related to neural network computing) and external data and control, and perform basic controls including but not limited to data handling, starting and / or stopping the computing device, etc. In other embodiments, the other processing device can also cooperate with the computing device to jointly complete computing tasks.

[0150] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it into a storage device (or memory) on the computing and processing device chip. Further, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them into a control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0151] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0152] In some embodiments, the present disclosure also discloses a chip (e.g. Figure 6 In one implementation, the chip is a system on chip (SoC) and integrates one or more Figure 5 The chip can be connected to an external interface device (such as Figure 6 The external interface device 606 shown in the figure is connected to other related components. The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as a video codec) and / or interface modules (such as a DRAM interface) may be integrated on the chip. In some embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure further discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 6 The board is described in detail.

[0153] Figure 6 FIG. 6 is a schematic diagram showing the structure of a board 600 according to an embodiment of the present disclosure. Figure 6 As shown in , the board includes a storage device 604 for storing data, which includes one or more storage units 610. The storage device can be connected and data can be transmitted with the control device 608 and the chip 602 described above by means of, for example, a bus. Further, the board also includes an external interface device 606, which is configured for data relay or switching between the chip (or the chip in the chip packaging structure) and an external device 612 (such as a server or computer, etc.). For example, the data to be processed can be transmitted to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0154] In one or more embodiments, the control device in the disclosed board may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a microcontroller unit (MCU) to regulate the working state of the chip.

[0155] According to the above combination Figure 5 and Figure 6 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0156] According to different application scenarios, the electronic equipment or device disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, transportation, household appliances, and / or medical equipment. The transportation includes airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs. The electronic equipment or device disclosed herein may also be applied to the Internet, IoT, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and medical fields. Further, the electronic equipment or device disclosed herein may also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, electronic devices or devices with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or devices with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0157] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein may not necessarily be necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art may appreciate the parts that are not described in detail in a certain embodiment of the present disclosure, and may also refer to the relevant descriptions of other embodiments.

[0158] In terms of specific implementation, based on the disclosure and teaching of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented by other methods not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article divides them on the basis of considering logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0159] In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

[0160] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0161] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP and ASIC, etc. Further, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

[0162] The foregoing content can be better understood in accordance with the following terms:

[0163] Clause 1. A processing unit comprising at least one first core, wherein:

[0164] The first core is configured to:

[0165] In response to a first synchronization instruction associated with a second core, sending an access permission signal to the second core, the access permission signal including information about data that is allowed to be accessed;

[0166] receiving an access operation signal to the data from the second core; and

[0167] The access operation is performed.

[0168] Clause 2. The processing unit of clause 1, wherein the first core is further configured to:

[0169] inserting the access operation into a native instruction stream of the first core; and

[0170] During execution of the native instruction stream, dependencies of the instruction stream are maintained.

[0171] Clause 3. A processing unit according to any one of clauses 1-2, wherein the access operation includes one or more access operations to the data, and the access operation includes any of the following: a read operation and a write operation.

[0172] Clause 4. The processing unit of any one of clauses 1-3, wherein the first core is further configured to:

[0173] Before sending the access permission signal to the second core, checking whether the instruction having a dependency relationship with the data has been completed; and

[0174] An access permission signal is sent to the second core only after the instruction with the dependency relationship is completed.

[0175] Clause 5. A processing unit according to any one of Clauses 1-4, wherein the data is tensor data, and the information about the data allowed to be accessed includes a descriptor of the tensor data, and the descriptor includes at least shape information of the tensor data.

[0176] Clause 6. A processing unit according to any one of clauses 1 to 5, wherein:

[0177] The first core is configured to send the access permission signal in a semaphore manner.

[0178] Clause 7. A processing unit according to any one of clauses 1 to 6, wherein:

[0179] The first core and the second core are storage cores of different clusters in a multi-core processor architecture; or

[0180] The first core and the second core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

[0181] Clause 8. A processing unit according to any one of clauses 1 to 7, wherein:

[0182] The first synchronization instruction is a lend instruction, which indicates that the data in the first core is lent to the second core for use.

[0183] Clause 9. A processing unit comprising at least one second core, wherein:

[0184] The second core is configured to:

[0185] In response to receiving an access permission signal from the first core, based on information on the data to which access is permitted included in the access permission signal, sending an access operation signal to the first core for the data; and

[0186] In response to the second synchronization instruction, a release signal is sent to the first core to release access to the data.

[0187] Clause 10. The processing unit of clause 9, wherein the second core is further configured to:

[0188] In response to receiving the access permission signal from the first core, generating a fusion instruction based on the information about the data to be accessed and an instruction related to the data to be executed in the second core;

[0189] Decoding the fused instruction into an access operation to the data; and

[0190] An access operation signal including the access operation is sent to the first core.

[0191] Clause 11. The processing unit of clause 10, wherein the access operation comprises one or more access operations to the data, and the access operation comprises any of: a read operation and a write operation.

[0192] Clause 12. A processing unit according to any of clauses 10-11, wherein the access operation includes associated physical address information.

[0193] Clause 13. A processing unit according to any one of clauses 9-12, wherein the second core is further configured to:

[0194] In response to receiving the access enable signal from the first core, recording a synchronization event;

[0195] In response to the second synchronization instruction, query whether there is an associated unprocessed synchronization event; and

[0196] When there is an associated unprocessed synchronization event, the release signal is sent and the synchronization event is cancelled.

[0197] Clause 14. A processing unit according to any one of Clauses 9-13, wherein the data is tensor data, and the information about the data allowed to be accessed includes a descriptor of the tensor data, and the descriptor includes at least shape information of the tensor data.

[0198] Clause 15. A processing unit according to any one of clauses 9 to 14, wherein:

[0199] The second core is configured to send the release signal in a semaphore manner.

[0200] Clause 16. A processing unit according to any one of clauses 9 to 15, wherein:

[0201] The second core and the first core are storage cores of different clusters in a multi-core processor architecture; or

[0202] The second core and the first core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

[0203] Clause 17. A processing unit according to any one of clauses 9 to 16, wherein:

[0204] The second synchronization instruction is a return instruction, which indicates that the second check has finished using the data.

[0205] Clause 18. A multi-core processor, characterized by comprising a processing unit as described in any one of Clauses 1-8 and a processing unit as described in any one of Clauses 9-17.

[0206] Clause 19. A chip, characterized in that the chip is encapsulated with a processing unit as described in any one of Clauses 1-8, or a processing unit as described in any one of Clauses 9-17, or a multi-core processor as described in Clause 18.

[0207] Clause 20. A board, characterized in that the board comprises the chip described in Clause 19.

[0208] Clause 21. A synchronization method for a processing unit, the processing unit comprising at least one first core, the method comprising:

[0209] The first core sends an access permission signal to the second core in response to a first synchronization instruction associated with the second core, the access permission signal including information about data that is allowed to be accessed;

[0210] The first core receives an access operation signal to the data from the second core; and

[0211] The first core performs the access operation.

[0212] Clause 22. The synchronization method according to clause 21, wherein the method further comprises:

[0213] The first core inserts the access operation into a native instruction stream of the first core; and

[0214] During execution of the native instruction stream, dependencies of the instruction stream are maintained.

[0215] Clause 23. A synchronization method according to any one of Clauses 21-22, wherein the access operation comprises one or more access operations to the data, and the access operation comprises any one of the following: a read operation and a write operation.

[0216] Clause 24. A synchronization method according to any one of clauses 21 to 23, wherein the method further comprises:

[0217] Before sending the access permission signal to the second core, the first core checks whether the instruction having a dependency relationship with the data has been completed; and

[0218] An access permission signal is sent to the second core only after the instruction with the dependency relationship is completed.

[0219] Clause 25. A synchronization method according to any one of Clauses 21-24, wherein the data is tensor data, and the information about the data allowed to be accessed includes a descriptor of the tensor data, and the descriptor includes at least shape information of the tensor data.

[0220] Clause 26. A synchronization method according to any one of clauses 21 to 25, wherein:

[0221] The access permission signal is sent in the form of a semaphore.

[0222] Clause 27. A synchronization method according to any one of clauses 21 to 26, wherein:

[0223] The first core and the second core are storage cores of different clusters in a multi-core processor architecture; or

[0224] The first core and the second core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

[0225] Clause 28. A synchronization method according to any one of clauses 21 to 27, wherein:

[0226] The first synchronization instruction is a lend instruction, which indicates that the data in the first core is lent to the second core for use.

[0227] Clause 29. A synchronization method for a processing unit, the processing unit comprising at least one second core, the method comprising:

[0228] The second core, in response to receiving the access permission signal from the first core, sends an access operation signal to the first core based on information on the data allowed to be accessed included in the access permission signal; and

[0229] In response to the second synchronization instruction, the second core sends a release signal to the first core to release access to the data.

[0230] Clause 30. The synchronization method according to clause 29, wherein the method further comprises:

[0231] In response to receiving the access permission signal from the first core, the second core generates a fusion instruction based on the information about the data that is allowed to be accessed and an instruction related to the data to be executed in the second core;

[0232] Decoding the fused instruction into an access operation to the data; and

[0233] An access operation signal including the access operation is sent to the first core.

[0234] Clause 31. The synchronization method according to Clause 30, wherein the access operation comprises one or more access operations to the data, and the access operation comprises any of the following: a read operation and a write operation.

[0235] Clause 32. A synchronization method according to any one of clauses 30-31, wherein the access operation includes associated physical address information.

[0236] Clause 33. A synchronization method according to any one of clauses 29 to 32, wherein the method further comprises:

[0237] The second core records a synchronization event in response to receiving the access enable signal from the first core;

[0238] In response to the second synchronization instruction, the second core queries whether there is an associated unprocessed synchronization event; and

[0239] When there is an associated unprocessed synchronization event, the release signal is sent to the first core, and the synchronization event is cancelled.

[0240] Clause 34. A synchronization method according to any one of Clauses 29-33, wherein the data is tensor data, and the information about the data allowed to be accessed includes a descriptor of the tensor data, and the descriptor includes at least shape information of the tensor data.

[0241] Clause 35. A synchronization method according to any one of clauses 29 to 34, wherein:

[0242] The release signal is sent in the form of a semaphore.

[0243] Clause 36. Synchronization according to any of clauses 29-35, wherein:

[0244] The second core and the first core are storage cores of different clusters in a multi-core processor architecture; or

[0245] The second core and the first core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

[0246] Clause 37. A synchronization method according to any one of clauses 29 to 36, wherein:

[0247] The second synchronization instruction is a return instruction, which indicates that the second check has finished using the data.

[0248] Clause 38. A synchronization method for a multi-core processor, wherein the multi-core processor includes a first processing unit and a second processing unit, the method comprising:

[0249] The first processing unit performs a synchronization method according to any one of clauses 21-28; and

[0250] The second processing unit executes the synchronization method according to any one of clauses 29-37.

Claims

1. A processing unit, comprising at least one first core, wherein: The first core is configured to: In response to a first synchronization instruction associated with a second core, sending an access permission signal to the second core, the access permission signal including information about data that is allowed to be accessed; receiving an access operation signal to the data from the second core; as well as Execute the access operation; The first core inserts the access operation signal into a local instruction stream of the first core and executes the instruction stream.

2. The processing unit of claim 1 , wherein the first core is further configured to: During execution of the native instruction stream, dependencies of the instruction stream are maintained.

3. The processing unit according to any one of claims 1 to 2, wherein: The access operation includes one or more access operations to the data, and the access operation includes any of the following: a read operation and a write operation.

4. The processing unit according to any one of claims 1-2, wherein the first core is further configured to: Before sending the access permission signal to the second core, checking whether the instruction having a dependency relationship with the data has been completed; and An access permission signal is sent to the second core only after the instruction with the dependency relationship is completed.

5. The processing unit according to any one of claims 1 to 2, wherein: The data is tensor data, and the information about the access-permitted data includes a descriptor of the tensor data, the descriptor including at least shape information of the tensor data.

6. The processing unit according to any one of claims 1-2, wherein: The first core is configured to send the access permission signal in a semaphore manner.

7. The processing unit according to any one of claims 1 to 2, wherein: The first core and the second core are storage cores of different clusters in a multi-core processor architecture; or The first core and the second core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

8. The processing unit according to any one of claims 1-2, wherein: The first synchronization instruction is a lend instruction, which indicates that the data in the first core is lent to the second core for use.

9. A processing unit, comprising at least one second core, wherein: The second core is configured to: In response to receiving an access permission signal from the first core, based on information about the data allowed to be accessed included in the access permission signal, sending an access operation signal to the first core for the data; as well as In response to a second synchronization instruction, sending a release signal to the first core to release access to the data; The first core inserts the access operation signal into a local instruction stream of the first core and executes the instruction stream.

10. The processing unit of claim 9, wherein the second core is further configured to: In response to receiving the access permission signal from the first core, generating a fusion instruction based on the information about the data to be accessed and an instruction related to the data to be executed in the second core; Decoding the fused instruction into an access operation to the data; as well as An access operation signal including the access operation is sent to the first core.

11. The processing unit according to claim 10, wherein: The access operation includes one or more access operations to the data, and the access operation includes any of the following: a read operation and a write operation.

12. The processing unit according to any one of claims 10-11, wherein the access operation includes related physical address information.

13. The processing unit according to any one of claims 9 to 11, wherein the second core is further configured to: In response to receiving the access enable signal from the first core, recording a synchronization event; In response to the second synchronization instruction, query whether there is an associated unprocessed synchronization event; and When there is an associated unprocessed synchronization event, the release signal is sent and the synchronization event is cancelled.

14. The processing unit according to any one of claims 9 to 11, wherein: The data is tensor data, and the information about the access-permitted data includes a descriptor of the tensor data, the descriptor including at least shape information of the tensor data.

15. The processing unit according to any one of claims 9 to 11, wherein: The second core is configured to send the release signal in a semaphore manner.

16. The processing unit according to any one of claims 9 to 11, wherein: The second core and the first core are storage cores of different clusters in a multi-core processor architecture; or The second core and the first core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

17. The processing unit according to any one of claims 9 to 11, wherein: The second synchronization instruction is a return instruction, which indicates that the second check has finished using the data.

18. A multi-core processor, characterized in that: It comprises a processing unit as described in any one of claims 1-8 and a processing unit as described in any one of claims 9-17.

19. A chip, characterized in that: The chip encapsulates a processing unit as described in any one of claims 1-8, or a processing unit as described in any one of claims 9-17, or a multi-core processor as described in claim 18.

20. A board, characterized in that: The board includes the chip according to claim 19.

21. A synchronization method for a processing unit, the processing unit comprising at least one first core, the method comprising: The first core sends an access permission signal to the second core in response to a first synchronization instruction associated with the second core, the access permission signal including information about data that is allowed to be accessed; The first core receives an access operation signal to the data from the second core; as well as The first core performs the access operation; The first core inserts the access operation signal into a local instruction stream of the first core and executes the instruction stream.

22. The synchronization method according to claim 21, wherein the method further comprises: The first core maintains the dependency relationship of the instruction stream during execution of the local instruction stream.

23. The synchronization method according to any one of claims 21-22, wherein: The access operation includes one or more access operations to the data, and the access operation includes any of the following: a read operation and a write operation.

24. The synchronization method according to any one of claims 21-22, wherein the method further comprises: Before sending the access permission signal to the second core, the first core checks whether the instruction having a dependency relationship with the data has been completed; as well as An access permission signal is sent to the second core only after the instruction with the dependency relationship is completed.

25. The synchronization method according to any one of claims 21-22, wherein: The data is tensor data, and the information about the access-permitted data includes a descriptor of the tensor data, the descriptor including at least shape information of the tensor data.

26. The synchronization method according to any one of claims 21-22, wherein: The access permission signal is sent in the form of a semaphore.

27. The synchronization method according to any one of claims 21-22, wherein: The first core and the second core are storage cores of different clusters in a multi-core processor architecture; or The first core and the second core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

28. The synchronization method according to any one of claims 21-22, wherein: The first synchronization instruction is a lend instruction, which indicates that the data in the first core is lent to the second core for use.

29. A synchronization method for a processing unit, the processing unit comprising at least one second core, the method comprising: In response to receiving the access permission signal from the first core, the second core sends an access operation signal to the first core based on information about the data allowed to be accessed included in the access permission signal; as well as The second core sends a release signal to the first core in response to the second synchronization instruction to release access to the data; The first core inserts the access operation signal into a local instruction stream of the first core and executes the instruction stream.

30. The synchronization method according to claim 29, wherein the method further comprises: In response to receiving the access permission signal from the first core, the second core generates a fusion instruction based on the information about the data that is allowed to be accessed and an instruction related to the data to be executed in the second core; Decoding the fused instruction into an access operation to the data; as well as An access operation signal including the access operation is sent to the first core.

31. The synchronization method according to claim 30, wherein: The access operation includes one or more access operations to the data, and the access operation includes any of the following: a read operation and a write operation.

32. A synchronization method according to any one of claims 30-31, wherein the access operation includes relevant physical address information.

33. The synchronization method according to any one of claims 29 to 31, wherein the method further comprises: The second core records a synchronization event in response to receiving the access enable signal from the first core; The second core queries, in response to the second synchronization instruction, whether there is an associated unprocessed synchronization event; as well as When there is an associated unprocessed synchronization event, the release signal is sent to the first core, and the synchronization event is cancelled.

34. The synchronization method according to any one of claims 29 to 31, wherein: The data is tensor data, and the information about the access-permitted data includes a descriptor of the tensor data, the descriptor including at least shape information of the tensor data.

35. The synchronization method according to any one of claims 29 to 31, wherein: The release signal is sent in the form of a semaphore.

36. The synchronization method according to any one of claims 29 to 31, wherein: The second core and the first core are storage cores of different clusters in a multi-core processor architecture; or The second core and the first core are respectively processor cores or storage cores in the same cluster in a multi-core processor architecture.

37. The synchronization method according to any one of claims 29 to 31, wherein: The second synchronization instruction is a return instruction, which indicates that the second check has finished using the data.

38. A synchronization method for a multi-core processor, wherein the multi-core processor comprises a first processing unit and a second processing unit, the method comprising: The first processing unit executes the synchronization method according to any one of claims 21-28; as well as The second processing unit executes the synchronization method according to any one of claims 29-37.

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