DDR signal quality test method, test device and test equipment

Abstract

The present application provides a DDR signal quality testing method, testing device, and testing equipment. The method includes: obtaining a de-skew value of a DDR signal to be tested when the chip is in a light-load operating mode, using the de-skew value as the initial center value of a window scan of the DDR signal to be tested; controlling the de-skew value to change around the initial center value until the chip fails to operate normally, thereby obtaining a window boundary value; and determining the window size of the DDR signal to be tested based on the window boundary value. The method adjusts the de-skew value of the DDR signal to determine the maximum and minimum values ​​of the de-skew value, thereby obtaining the window size of the DDR signal. The larger the DDR signal window, the better the signal quality of the DDR signal. There is no need to scrape or solder the signal line, simplifying the test operation and solving the problem of overly complex DDR signal quality testing methods in the prior art.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a DDR signal quality testing method, a testing device, a computer-readable storage medium, and a testing equipment. Background Art

[0002] As SoCs become increasingly complex, high-speed DDR caches are increasingly used. DDR signal quality is crucial for SoC system stability, and the eye diagram is a key indicator of DDR high-speed signal quality. However, the DDR training eye results integrated into the chip's DDR PHY often only partially reflect the DDR signal eye diagram quality under light system load, resulting in significant deviations from the actual system's operating conditions. Furthermore, even when measuring eye diagrams under heavy system load, eye diagram measurement itself presents various challenges. For example, eye diagram quality varies across different chips, PCBs (printed circuit boards), DDR components, and application scenarios. The measurement point significantly impacts the results, making eye diagram measurement and analysis time-consuming and labor-intensive. Measurements require individual alignment of the numerous DDR signal lines, requiring PCB scraping and soldering, all of which can adversely affect the PCB. Summary of the Invention

[0003] The main purpose of this application is to provide a DDR signal quality testing method, testing device, computer-readable storage medium and testing equipment to solve the problem that the DDR signal quality testing method in the prior art is too complicated.

[0004] According to one aspect of an embodiment of the present invention, a method for testing DDR signal quality is provided, comprising: obtaining a de-skew value of a DDR signal to be tested when a chip is in a light-load operating mode, and using the de-skew value as an initial center value for a window scan of the DDR signal to be tested; controlling the de-skew value to vary around the initial center value until the chip fails to operate normally, thereby obtaining a window boundary value; and determining a window size of the DDR signal to be tested based on the window boundary value.

[0005] Optionally, controlling the change of the initial center value until the chip fails to work properly to obtain a window boundary value includes: controlling the de-skew value of the DDR test signal to increase from the initial center value until the chip fails to work properly to obtain a window maximum value; controlling the de-skew value of the DDR test signal to decrease from the initial center value until the chip fails to work properly to obtain a window minimum value.

[0006] Optionally, controlling the de-skew value of the DDR signal to be tested to increase from the initial center value until the chip fails to work properly and obtaining a window maximum value includes: controlling the de-skew value of the DDR signal to be tested to increase from the initial center value to obtain a test intermediate value; determining whether the chip works normally within a first predetermined time when the de-skew value is the test intermediate value; when the chip works normally, controlling the de-skew value of the DDR signal to be tested to continue increasing from the test intermediate value until the chip fails to work properly and determining that the current test intermediate value is the window maximum value.

[0007] Optionally, when the chip fails to work normally, the method further includes: controlling the chip to restart.

[0008] Optionally, before obtaining the de-skew value of the DDR test signal of the chip in the light load working mode and using the de-skew value as the initial center value of the DDR test signal window scan, the method also includes: controlling the chip to enter the light load working mode, and the light load working mode is an working mode in which the load rate of the chip is less than a first predetermined value.

[0009] Optionally, after obtaining the de-skew value of the DDR test signal of the chip in the light-load working mode and using the de-skew value as the initial center value of the window scan of the DDR test signal, the de-skew value is controlled to change around the initial center value until the chip fails to work normally and before the window boundary value is obtained, the method also includes: controlling the chip to enter the heavy-load working mode, the heavy-load working mode is an working mode in which the load rate of the chip is greater than a second predetermined value, and the second predetermined value is greater than or equal to the first predetermined value.

[0010] Optionally, the chip cannot work normally because a target serial port has no response within a second predetermined time and / or a system error occurs in the chip, and the target serial port is a serial port of the chip that receives the de-skew value.

[0011] According to another aspect of an embodiment of the present invention, a DDR signal quality testing device is provided, comprising: an acquisition unit, configured to acquire a de-skew value of a DDR signal to be tested when the chip is in a light-load operating mode, and use the de-skew value as an initial center value for a window scan of the DDR signal to be tested; a control unit, configured to control the de-skew value to vary around the initial center value until the chip fails to operate normally, thereby obtaining a window boundary value; and a determination unit, configured to determine a window size of the DDR signal to be tested based on the window boundary value.

[0012] According to yet another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein the program executes any one of the methods described above.

[0013] According to another aspect of an embodiment of the present invention, a testing device is provided. The testing device includes a memory and a processor. The memory stores a program. The processor is configured to run the program. When the program is run, any one of the methods is executed.

[0014] In an embodiment of the present invention, in the above-mentioned DDR signal quality testing method, first, the de-skew value of the DDR test signal of the chip in the light-load operating mode is obtained, and the de-skew value is used as the initial center value of the window scan of the DDR test signal; then, the de-skew value is controlled to change around the initial center value until the chip fails to work normally, and the window boundary value is obtained; finally, the window size of the DDR test signal is determined based on the window boundary value. The larger the window of the DDR test signal, the better the signal quality of the DDR signal. Compared with the prior art of measuring eye diagrams by connecting an oscilloscope to the signal line, the testing method of the present application does not require signal line scraping, welding, etc. on the PCB board, thereby avoiding damage to the chip PCB board from scraping and welding operations during testing, and avoiding the influence of different welding points on the test results, simplifying the testing process, and improving test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0016] Figure 1 A schematic diagram showing a method for testing DDR signal quality according to an embodiment of the present application is shown;

[0017] Figure 2 A schematic diagram of a DDR signal quality testing device according to an embodiment of the present application is shown;

[0018] Figure 3 A flowchart of automatically scanning a DDR window according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0020] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] As mentioned in the background technology, the DDR signal quality testing method in the prior art is too complicated. In order to solve the above problem, the present application provides a DDR signal quality testing method, testing device, computer-readable storage medium and testing equipment.

[0023] According to an embodiment of the present application, a method for testing DDR signal quality is provided.

[0024] Figure 1 FIG. 1 is a flow chart of a method for testing DDR signal quality according to an embodiment of the present application. Figure 1 As shown, the method includes the following steps:

[0025] Step S101, obtaining a de-skew value of a DDR signal to be tested when the chip is in a light-load working mode, and using the de-skew value as an initial center value of a window scan of the DDR signal to be tested;

[0026] Specifically, each DDR signal has a delay chain inside, and the de-skew value is the value of the delay chain. The purpose of configuration is to perform timing matching. In actual applications, the de-skew value is stored in the internal register of the chip. The de-skew value stored in the internal register of the chip can be read through the serial port. The de-skew value of the DDR test signal under the light-load working mode of the chip is obtained as the initial center value of the window scan of the DDR test signal.

[0027] Step S102, controlling the de-skew value to change around the initial center value until the chip fails to work properly, thereby obtaining a window boundary value;

[0028] Specifically, the de-skew value inside the chip can be changed by changing the value of the chip register, that is, the de-skew value is controlled to change around the initial center value until the de-skew value changes to a certain value, at which point the chip cannot work properly. This value can be used as the window boundary value.

[0029] Step S103: determining the window size of the DDR signal to be tested according to the window boundary value.

[0030] Specifically, the window size of the DDR signal to be tested can be determined according to the window boundary value, and the window size can represent the signal quality of the DDR signal.

[0031] In the above-mentioned DDR signal quality testing method, first, the de-skew value of the DDR test signal of the chip in light-load operating mode is obtained, and the de-skew value is used as the initial center value of the DDR test signal window scan; then, the de-skew value is controlled, changing around the initial center value until the chip fails to operate normally, and the window boundary value is obtained; finally, the window size of the DDR test signal is determined based on the window boundary value. The larger the window of the DDR test signal, the better the signal quality of the DDR signal. Compared with the existing technology of measuring eye diagrams by connecting an oscilloscope to the signal line, the testing method of the present application does not require signal line scraping or welding on the PCB board, thus preventing the chip PCB board from being damaged by scraping and welding during testing, and avoiding the influence of different welding points on the test results, simplifying the testing process and improving test accuracy.

[0032] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] In a specific embodiment of the present application, the chip may be a SOC (System on Chip, SOC for short) chip.

[0034] In one embodiment of the present application, controlling the change of the initial center value until the chip fails to operate normally to obtain a window boundary value includes: controlling the de-skew value of the DDR test signal to increase from the initial center value until the chip fails to operate normally to obtain a window maximum value; and controlling the de-skew value of the DDR test signal to decrease from the initial center value until the chip fails to operate normally to obtain a window minimum value. Specifically, the window boundary value includes a window maximum value and a window minimum value, and the difference between the window maximum value and the window minimum value is calculated to obtain the window size of the DDR signal.

[0035] In one embodiment of the present application, the de-skew value of the DDR signal to be tested is controlled to increase from the initial center value until the chip fails to work properly and a window maximum value is obtained, including: controlling the de-skew value of the DDR signal to be tested to increase from the initial center value to obtain a test intermediate value; determining whether the chip works normally when the de-skew value is the test intermediate value within a first predetermined time; when the chip works normally, controlling the de-skew value of the DDR signal to be tested to continue to increase from the above-mentioned test intermediate value until the chip fails to work properly, and determining that the current test intermediate value is the window maximum value.

[0036] In this embodiment, of course, the above can also control the de-skew value of the DDR test signal to decrease from the initial center value to obtain a test intermediate value; determine whether the chip works normally within a first predetermined time when the de-skew value is the test intermediate value; when the chip works normally, control the de-skew value of the DDR test signal to continue to decrease from the test intermediate value until the chip fails to work normally, and determine the current test intermediate value to be the minimum value of the window. For example, after increasing or decreasing the de-skew value by a change value, determine whether the chip works normally within the first predetermined time. When it is determined that the chip can work normally, continue to increase or decrease the change value until the chip fails to work normally within the first predetermined time after the increase or decrease of the change value. This not only ensures that the test intermediate value will be fully configured and effective in the chip, but also ensures that the SOC works for a period of time under this configuration without causing abnormal output or hanging of the chip. The change value increased or decreased each time can be the same or different.

[0037] In actual application, the above-mentioned change value may be 1, but is not limited to 1, and may also be other feasible values, which may be specifically adjusted according to actual application conditions.

[0038] In another embodiment of the present application, when the chip fails to operate normally, the method further includes: controlling the chip to restart. For example, after controlling the de-skew value of the DDR test signal to increase from the initial center value until the chip fails to operate normally and a window maximum value is obtained, controlling the chip to restart; after controlling the de-skew value of the DDR test signal to decrease from the initial center value until the chip fails to operate normally and a window minimum value is obtained, controlling the chip to restart.

[0039] Specifically, in actual application, the power switch of the SOC can be controlled by a programmable microcontroller. Since DDR is a key unit of the system, when scanning the DDR signal, the system will hang when the signal boundary is scanned. At this time, the SOC cannot resume work independently. The microcontroller needs to control the power switch to power off the SOC and power on the SOC to resume startup.

[0040] In one embodiment of the present application, the above-mentioned chip cannot work normally because the target serial port has no response within the second predetermined time and / or a system error occurs in the above-mentioned chip. The above-mentioned target serial port is the serial port of the above-mentioned chip that receives the above-mentioned de-skew value. Subsequently, when it is determined that the above-mentioned chip has no response within the second predetermined time, or a system error occurs in the chip, or the above-mentioned chip has no response within the second predetermined time and a system error occurs in the chip, the above-mentioned chip is controlled to restart, further ensuring that the above-mentioned chip can resume normal operation as soon as possible.

[0041] In another embodiment of the present application, before obtaining a de-skew value of a DDR test signal when the chip is in a light-load operating mode and using the de-skew value as an initial center value for a window scan of the DDR test signal, the method further includes: controlling the chip to enter a light-load operating mode, wherein the light-load operating mode is an operating mode in which the chip's load rate is less than a first predetermined value. In this embodiment, when determining the initial center value for the window scan of the DDR test signal, the chip is controlled to operate in the light-load mode. This ensures that the initial center value of the DDR signal read does not exceed a boundary value, and that the chip does not malfunction when entering a heavy-load operating mode with this initial center value.

[0042] In order to ensure that the test can be carried out quickly and the test results are reliable, in another embodiment of the present application, after obtaining the de-skew value of the DDR test signal of the chip in the light-load working mode, and using the de-skew value as the initial center value of the window scan of the DDR test signal, the de-skew value is controlled to change around the initial center value until the chip fails to work normally and before the window boundary value is obtained, the method also includes: controlling the chip to enter the heavy-load working mode, and the heavy-load working mode is a working mode in which the load rate of the chip is greater than a second predetermined value, and the second predetermined value is greater than or equal to the first predetermined value.

[0043] In actual application, after the microcontroller starts or restarts the SOC, you can use the serial port and other interfaces to automatically perform video playback, games or browser operations, control the above-mentioned chips to work in overload mode, and test the DDR signal quality in the SOC overload working mode. This can not only quickly test and quickly locate the problem signal without damaging the PCB board, but also ensure the reliability of the test results when testing in the SOC overload working mode.

[0044] It should be noted that in actual application, the above-mentioned DDR test signals include multiple signals, such as AC (Address & Command) signals and DQ (DQ / DQS / DQSB) signals. Each DDR test signal is tested in turn using the above-mentioned method to obtain the window size of all DDR test signals to characterize the signal quality of each DDR test signal.

[0045] In a specific embodiment of the present application, all DDR signals to be tested can be configured according to a preset order first, and then all DDR signals to be tested can be tested according to the pre-configured preset order. Specifically, after completing the test of the first DDR signal to be tested according to the above-mentioned test method, it is determined whether there are any untested DDR signals to be tested. If so, the de-skew value of the untested DDR signal to be tested under the light-load working mode of the chip is obtained as the initial center value of the window scan of the untested DDR signal to be tested, and the next round of testing is started until all DDR signals to be tested are tested, the confirmation process is completed, and the test report is output.

[0046] The present application also provides a DDR signal quality test device. It should be noted that the DDR signal quality test device of the present application can be used to perform the DDR signal quality test method provided in the present application. The following describes the DDR signal quality test device provided in the present application.

[0047] Figure 2FIG. 1 is a schematic diagram of a DDR signal quality test device according to an embodiment of the present application. Figure 2 As shown, the device includes:

[0048] An acquiring unit 10 is configured to acquire a de-skew value of a DDR signal to be tested when the chip is in a light-load working mode, and use the de-skew value as an initial center value of a window scan of the DDR signal to be tested;

[0049] A first control unit 20 is configured to control the de-skew value to change around an initial center value until the chip fails to work properly, thereby obtaining a window boundary value;

[0050] The determining unit 30 is configured to determine the window size of the DDR signal to be tested according to the window boundary value.

[0051] In the above-mentioned DDR signal quality testing device, an acquisition unit acquires the de-skew value of the DDR test signal when the chip is in a light-load operating mode, and uses the de-skew value as the initial center value for scanning the window of the DDR test signal; a control unit controls the de-skew value, changing it around the initial center value until the chip fails to operate normally, thereby obtaining a window boundary value; and a determination unit determines the window size of the DDR test signal based on the window boundary value. The larger the window size of the DDR test signal, the better the signal quality of the DDR signal. Compared to the prior art method of measuring eye diagrams by connecting an oscilloscope to a signal line, the testing method of the present application does not require signal line scraping or welding on the PCB board, thereby preventing damage to the chip's PCB board from scraping or welding during testing, and preventing the influence of different welding points on the test results. This simplifies the testing process and improves test accuracy.

[0052] In a specific embodiment of the present application, the chip may be a SOC (System on Chip, SOC for short) chip.

[0053] In one embodiment of the present application, the control unit includes a first control module and a second control module, wherein the first control module is used to control the de-skew value of the DDR signal to be tested to increase from the initial center value until the chip fails to operate normally, thereby obtaining a window maximum value; and the second control module is used to control the de-skew value of the DDR signal to be tested to decrease from the initial center value until the chip fails to operate normally, thereby obtaining a window minimum value. Specifically, the window boundary value includes a window maximum value and a window minimum value, and the difference between the window maximum value and the window minimum value is calculated to obtain the window size of the DDR signal.

[0054] In one embodiment of the present application, the above-mentioned first control module includes a first control sub-module, a determination sub-module and a second control sub-module, wherein the above-mentioned first control sub-module is used to control the de-skew value of the DDR signal to be tested to increase from an initial center value to obtain a test intermediate value; determine whether the chip works normally within a first predetermined time when the de-skew value is the test intermediate value; the above-mentioned second control sub-module is used to control the de-skew value of the DDR signal to be tested to continue to increase from the test intermediate value when the chip works normally, until the chip fails to work normally, and determine that the current test intermediate value is the window maximum value.

[0055] In this embodiment, of course, the above can also control the de-skew value of the DDR signal to be tested to decrease from the initial center value to obtain a test intermediate value; determine whether the chip works normally when the de-skew value is the test intermediate value within a first predetermined time; when the chip works normally, control the de-skew value of the DDR signal to be tested to continue to decrease from the above test intermediate value until the chip fails to work normally, and determine that the current test intermediate value is the window minimum value.

[0056] To ensure that the chip can resume normal operation, in another embodiment of the present application, when the chip fails to operate normally, the device further includes a second control unit, configured to control the chip to restart. For example, the de-skew value of the DDR test signal is controlled to increase from the initial center value until the chip fails to operate normally and a window maximum value is obtained, and then the chip is controlled to restart. The de-skew value of the DDR test signal is controlled to decrease from the initial center value until the chip fails to operate normally and a window minimum value is obtained, and then the chip is controlled to restart.

[0057] Specifically, in actual application, the power switch of the SOC can be controlled by a programmable microcontroller. Since DDR is a key unit of the system, when scanning the DDR signal, the system will hang when the signal boundary is scanned. At this time, the SOC cannot resume work independently. The microcontroller needs to control the power switch to power off the SOC and power on the SOC to resume startup.

[0058] In another embodiment of the present application, the device also includes a third control unit, which is used to control the chip to enter the light load working mode before obtaining the de-skew value of the DDR test signal of the chip in the light load working mode and using the de-skew value as the initial center value of the DDR test signal window scan. The light load working mode is a working mode in which the load rate of the chip is less than a first predetermined value.

[0059] In order to ensure that the test can be carried out quickly and the test results are reliable, in another embodiment of the present application, the device also includes a fourth control unit, which is used to obtain the de-skew value of the DDR test signal of the chip in the light-load working mode, and use the de-skew value as the initial center value of the window scan of the DDR test signal. Then, the de-skew value is controlled to change around the initial center value until the chip cannot work normally. Before the window boundary value is obtained, the chip is controlled to enter the heavy-load working mode. The heavy-load working mode is a working mode in which the load rate of the chip is greater than a second predetermined value, and the second predetermined value is greater than or equal to the first predetermined value.

[0060] In actual application, after the microcontroller starts or restarts the SOC, you can use the serial port and other interfaces to automatically perform video playback, games or browser operations, control the above-mentioned chips to work in overload mode, and test the DDR signal quality in the SOC overload working mode. This can not only quickly test and quickly locate the problem signal without damaging the PCB board, but also ensure the reliability of the test results when testing in the SOC overload working mode.

[0061] In one embodiment of the present application, the above-mentioned chip cannot work normally because the target serial port has no response within the second predetermined time and / or a system error occurs in the above-mentioned chip. The above-mentioned target serial port is the serial port of the above-mentioned chip that receives the above-mentioned de-skew value. Subsequently, when it is determined that the above-mentioned chip has no response within the second predetermined time, or a system error occurs in the chip, or the above-mentioned chip has no response within the second predetermined time and a system error occurs in the chip, the above-mentioned chip is controlled to restart, further ensuring that the above-mentioned chip can resume normal operation as soon as possible.

[0062] In order to make those skilled in the art more clearly understand the technical solution of this application, the following will be described with reference to specific embodiments:

[0063] Example 1

[0064] like Figure 3 The following are the specific steps for testing DDR signal quality:

[0065] Step 1: Use a programmable microcontroller to control the power switch of the SOC (i.e., chip). Since DDR is a key unit of the system, when scanning the DDR signal, the system may hang when the signal boundary is scanned. At this time, the SOC cannot recover on its own. The microcontroller needs to control the power switch to power off and on the SOC to resume startup.

[0066] Step 2: Use the serial port of the SOC to read the DDR signal and the de-skew value of the DDR signal, and automatically update these values ​​to the script. These values ​​will serve as the initial center value of the DDR window scan;

[0067] Step 3: The MCU controls the SOC power switch. The MCU periodically monitors the results printed by the SOC serial port. For example, if the serial port has no response for a long time or a system error keyword appears, the MCU restarts the SOC.

[0068] Step 4: After the microcontroller starts or restarts the SOC, use the serial port and other interfaces to automatically perform video playback, games, or browser operations to put the SOC into heavy-load working mode;

[0069] Step 5: Perform addition and subtraction operations on the DDR signal from the center value in the order preset by the script. According to the script execution result, the signal for the next operation is determined. For example, assuming that the first test signal is DQ0 in the write direction, first subtract 1 from the left (i.e., the change value) and then encounter a system hang. The left boundary of DQ0 in the write direction is obtained. After the SOC restarts, the script will determine the right boundary of DQ0 in the write direction for the next test based on the test results. That is, add 1 to the right until the system hangs and the right boundary of DQ0 in the write direction is obtained. After the SOC restarts again, the script will determine the left boundary of DQ1 in the write direction for the next test based on the test results. The script is executed in the order preset by the script until all DDR signals are tested. After all tests are completed, jump to step 7;

[0070] Step 6: Update the value of the signal to be tested through the SOC's serial port or other interfaces. Update the DDR signal configuration to the SOC by subtracting 1 from the center value to the left or adding 1 to the right at a fixed time interval. A certain time interval (i.e., the first predetermined time) is required. On the one hand, it can ensure that the configuration is fully effective in the SOC. On the other hand, the configuration needs to run for at least a period of time to prove that it is indeed a valid DDR configuration and will not cause abnormal output or hang of the SOC system, thus ensuring the reliability of the test results. If the serial port is unresponsive for a long time or a system error keyword appears or the de-skew value has been increased to the maximum or decreased to the minimum, return to step 3 and restart the SOC;

[0071] Step 7: SOC completes scanning of all windows and collects and prints the results;

[0072] Step 8: Use the script to automatically process and print the results, and output the boundary values ​​of all DDR signals to be tested to an Excel spreadsheet.

[0073] Example 2

[0074] Eye diagram measurements are often not possible at extreme temperatures due to limitations in instrument testing conditions. When an abnormality occurs in the system at these extreme temperatures and DDR issues need to be located, eye diagram measurements cannot be performed. Dynamic window scanning via scripts eliminates temperature limitations and allows DDR window scanning at any temperature. For example, if a PCB high / low temperature copy machine experiences a low-temperature hang-up, preliminary investigation reveals a DDR stability issue. Further investigation is required to determine which type or signal in the DDR is causing the problem. This can be achieved through stable and precise location using the following methods:

[0075] For example, in a low-temperature copy machine with 10 PCB boards, one board, board 6, often freezes due to low temperature, while the other 9 boards all perform normally at low temperatures;

[0076] The above-mentioned automated script is used to dynamically scan the window to obtain the DDR window information of 10 PCBs at low temperature in turn. The obtained window information is shown in Table 1. Table 1 only extracts a small part of the scanning results as an example. The register represents the DDR signal. Each signal corresponds to a unique register. The read value is the test value of the DDR signal in the light-load working mode, which is pre-configured in the register as the initial center value of the test window. The maximum value is the maximum value of the window obtained by scanning in the heavy-load working mode, and the minimum value is the minimum value of the window obtained by scanning in the heavy-load working mode. The window size value is obtained by subtracting the window minimum value from the window maximum value, and the window center value is the center value of the window scanned in the heavy-load working mode.

[0077] Table 1

[0078] register Reading Maximum Minimum Window size Window center value 0x1e6c2fdc 0x9 0xe 0x2 12 8 0x1e6c2ccc 0x11 0x17 0xb 12 17 0x1e6c2d20 0x13 0x18 0xd 11 18.5 0x1e6c2e4c 0x15 0x1a 0xf 11 20.5 0x1e6c2ea0 0x17 0x1b 0x13 8 23 0x1e6c2cc8 0x1a 0x1e 0x15 9 25.5 0x1e6c2d1c 0x1a 0x1e 0x15 9 25.5 0x1e6c2e48 0x1a 0x1e 0x18 6 27 0x1e6c2e9c 0x1a 0x1d 0x16 7 25.5

[0079] First, a comparative analysis is performed based on the window information results of the 10 PCBs shown in Table 1. This comparative analysis reveals that the window in the DDR signal of board 6 is significantly smaller than that of the DDR signals of other PCBs, thus confirming that there is a problem with board 6. Then, all DDR signals of board 6 are compared one by one with the DDR signals of other boards. If the window value of a certain DDR signal is significantly smaller than that of other PCBs, then a problem with that DDR signal can be confirmed. Finally, at room temperature, the DDR signals of test board 6 and other PCBs are compared, and the window sizes of the DDR signal of test board 6 and other DDR signals of board 6 are compared. Finally, the specific problem causing the small window size of the DDR signal is located, and the specific cause of the system abnormality can be determined. Therefore, according to the above test method, the final test results can be quickly obtained, and based on the test results, the problem of which DDR signal is causing the system abnormality can be quickly located, thereby improving the test efficiency of the chip system.

[0080] The above-mentioned DDR signal quality testing device includes a processor and a memory. The above-mentioned acquisition unit, first control unit, determination unit, etc. are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0081] The processor includes a core, which retrieves the corresponding program unit from the memory. One or more cores can be set, and the problem of overly complex DDR signal quality testing methods in the prior art can be solved by adjusting the core parameters.

[0082] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0083] An embodiment of the present invention provides a computer-readable storage medium having a program stored thereon. When the program is executed by a processor, the above-mentioned DDR signal quality testing method is implemented.

[0084] An embodiment of the present invention provides a testing device, comprising a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, at least the following steps are performed:

[0085] Step S101, obtaining a de-skew value of a DDR signal to be tested when the chip is in a light-load working mode, and using the de-skew value as an initial center value of a window scan of the DDR signal to be tested;

[0086] Step S102, controlling the de-skew value to change around the initial center value until the chip fails to work properly, thereby obtaining a window boundary value;

[0087] Step S103: determining the window size of the DDR signal to be tested according to the window boundary value.

[0088] The electronic devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0089] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the above-mentioned units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0091] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0092] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0093] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a computer-readable storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present invention. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0094] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0095] In the above-mentioned DDR signal quality testing method, testing device, and testing equipment of the present application, first, the de-skew value of the DDR test signal of the chip in the light-load working mode is obtained, and the de-skew value is used as the initial center value of the window scan of the DDR test signal; then, the de-skew value is controlled to change around the initial center value until the chip fails to work normally, and the window boundary value is obtained; finally, the window size of the DDR test signal is determined according to the window boundary value. The larger the window size of the DDR test signal, the better the signal quality of the DDR signal. Compared with the existing technology of measuring the eye diagram by connecting an oscilloscope to the signal line, the testing method of the present application does not require the PCB board to perform signal line scraping, welding, and other operations, thereby avoiding damage to the chip PCB board by scraping and welding operations during the testing process, and avoiding the influence of different welding points on the test results, simplifying the testing process, and improving the test accuracy.

[0096] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for testing DDR signal quality, characterized in that: include: Obtaining a de-skew value of a DDR test signal of the chip in a light-load operating mode, and using the de-skew value as an initial center value of a window scan of the DDR test signal, wherein the light-load operating mode is an operating mode in which a load rate of the chip is less than a first predetermined value; Controlling the de-skew value to change around the initial center value until the chip fails to work properly, thereby obtaining a window boundary value; Determine the window size of the DDR signal to be tested according to the window boundary value; The controlling the change of the initial center value until the chip fails to work properly, thereby obtaining a window boundary value, includes: Controlling the de-skew value of the DDR signal to be tested to increase from the initial center value until the chip fails to work normally, thereby obtaining a window maximum value; Controlling the de-skew value of the DDR signal to be tested to decrease from the initial center value until the chip fails to work normally, thereby obtaining a window minimum value; After obtaining a de-skew value of a DDR test signal when the chip is in a light-load operating mode and using the de-skew value as an initial center value for a window scan of the DDR test signal, the method further includes: controlling the de-skew value to vary around the initial center value until the chip fails to operate normally and a window boundary value is obtained. The chip is controlled to enter a heavy-load operating mode, where the heavy-load operating mode is an operating mode in which a load rate of the chip is greater than a second predetermined value, and the second predetermined value is greater than or equal to the first predetermined value.

2. The method according to claim 1, characterized in that Controlling the de-skew value of the DDR signal to be tested to increase from the initial center value until the chip fails to work properly, thereby obtaining a window maximum value, comprising: Controlling the de-skew value of the DDR signal to be tested to increase from an initial center value to obtain a test intermediate value; determining whether the chip operates normally when the de-skew value is the test intermediate value within a first predetermined time; When the chip operates normally, the de-skew value of the DDR signal to be tested is controlled to continue to increase from the test intermediate value until the chip fails to operate normally, and the current test intermediate value is determined to be the window maximum value.

3. The method according to claim 1, characterized in that When the chip fails to work properly, the method further includes: Control the chip to restart.

4. The method according to claim 1, wherein Before obtaining a de-skew value of a DDR signal to be tested when the chip is in a light-load working mode and using the de-skew value as an initial center value of a window scan of the DDR signal to be tested, the method further includes: Control the chip to enter a light-load operating mode.

5. The method according to any one of claims 1 to 4, characterized in that The chip cannot work properly because the target serial port has no response within a second predetermined time and / or a system error occurs in the chip, and the target serial port is the serial port of the chip that receives the de-skew value.

6. A DDR signal quality testing device, characterized in that: include: an acquiring unit, configured to acquire a de-skew value of a DDR test signal of the chip in a light-load operating mode, and use the de-skew value as an initial center value of a window scan of the DDR test signal, wherein the light-load operating mode is an operating mode in which a load rate of the chip is less than a first predetermined value; a first control unit, configured to control the de-skew value to change around the initial center value until the chip fails to work properly, thereby obtaining a window boundary value; a determining unit, configured to determine a window size of the DDR signal to be tested according to the window boundary value; The first control unit includes a first control module and a second control module, wherein the first control module is used to control the de-skew value of the DDR test signal to increase from the initial center value until the chip fails to work properly, thereby obtaining a window maximum value; and the second control module is used to control the de-skew value of the DDR test signal to decrease from the initial center value until the chip fails to work properly, thereby obtaining a window minimum value. The device also includes a fourth control unit, which is used to obtain a de-skew value of a DDR test signal of the chip in a light-load working mode, and use the de-skew value as the initial center value of a window scan of the DDR test signal. The fourth control unit is used to control the de-skew value to change around the initial center value until the chip fails to work normally. Before obtaining the window boundary value, the fourth control unit is used to control the chip to enter a heavy-load working mode. The heavy-load working mode is a working mode in which the load rate of the chip is greater than a second predetermined value, and the second predetermined value is greater than or equal to the first predetermined value.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 5.

8. A testing device, characterized in that: The testing device includes a memory and a processor, wherein the memory stores a program, and the processor is configured to run the program, wherein the method according to any one of claims 1 to 5 is executed when the program is run.

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