Memory subsystem management based on dynamic control of word line activation voltage

Abstract

A request to perform a write operation at a memory device is received. Current word line start voltage (WLSV) information associated with a particular memory section of a plurality of memory sections is retrieved. The write operation is performed on the particular memory section. In a firmware log in a memory sub-system controller, information indicating a last written memory page associated with the particular memory section on which the write operation was performed is stored. The firmware log is managed in view of the information indicating the last written memory page associated with the performed write operation. Each entry of the firmware log includes one or more identifying indicia associated with a respective memory section, at least one of the identifying indicia being a word line start voltage (WLSV) associated with the respective memory section.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory subsystem management based on word line start voltage (WSLV) dynamically controlled by firmware. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This section describes an example data structure of a firmware record containing markers for identifying multiple memory segments of a memory device, according to some embodiments of the present disclosure.

[0006] Figure 3 This is a flowchart of an example method for managing firmware records in view of the written operation performed, according to embodiments of the present disclosure.

[0007] Figure 4 This is a flowchart of an example method for modifying firmware records before performing a write operation, according to an embodiment of the present disclosure.

[0008] Figure 5 This is a flowchart illustrating example methods for optimizing the management of firmware records according to embodiments of the present disclosure.

[0009] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0010] This disclosure pertains to memory subsystem management based on dynamic control of word line start-up voltage (WLSV). The memory subsystem can be a memory device, a memory module, or a combination of both. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that contains one or more components (such as memory devices) for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0011] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package having one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0012] A memory device may consist of bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line (WL) may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and may comprise a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of the memory device to allow concurrent operation on each plane. The memory device may include circuitry for performing concurrent memory page accesses on two or more memory planes. For example, the memory device may include corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types.

[0013] One existing technique for memory management is Dynamic Word Line Start-up Voltage (DWLSV) operation. In automated Dynamic Word Line Start-up Voltage (ADWLSV) operation with memory device-level control, page mapping is associated with a specific block of memory cells in the memory device. The memory device can apply one or more of an automated sequence of incrementing voltages to determine a minimum voltage (e.g., word line start-up voltage), at which the first page of the word line can be programmed with valid data. Other pages of the same word line can be programmed using the word line start-up voltage determined for the first page of the word line.

[0014] In some embodiments, programming operations do not write all word lines in a particular block, making the block an open block. An "open" block can refer to a physical block of memory cells where the pages have not yet been fully written. In some embodiments, the block may remain open until the last page of the block is programmed. After the last page of the block is programmed, the block is closed. When the block is closed, the WLSV entries (i.e., the values ​​of the WLSV) of the particular block are released and made available to another block. Therefore, it is important to keep track of open and closed blocks in the memory subsystem to increase overall programming efficiency, such as the reduction in programming time (t). prog As indicated.

[0015] Typically, only one DWLSV memory element (a user-accessible register) is allocated per die to store WLSV information. This imposes a significant limitation on the maximum number of open blocks in the tracked die that the memory device can maintain, as the available space for WLSV information can be quickly exhausted as the number of open blocks increases. Additional logic circuitry and memory elements will need to be incorporated into the memory device to perform ADWLSV on a larger scale, where a large number of open blocks can be tracked.

[0016] This disclosure addresses the above and other deficiencies by shifting the Dynamic Word Line Start-up Voltage (DWLSV) operation from the memory device level to the memory subsystem controller level through manual or semi-automatic configuration of the memory subsystem controller's firmware to determine the appropriate word line start-up voltage for the first page of a particular word line. Firmware-controlled DWLSV operation is simply referred to as "manual" DWLSV or MDWLSV, but the term "manual" encompasses a degree of automation combined with manual configuration of the firmware by the user. Therefore, the phrases "manual" or "semi-automatic" are often used in the specification. Since MDWLSV is not limited to storing WLSV records in only one memory element per die, large-scale DWLSV operations involving tracking a large number (e.g., hundreds) of open blocks are feasible. By shifting DWLSV operations to the firmware, the memory device design can remain unchanged while the number of open blocks being tracked can increase from single digits to hundreds or even thousands.

[0017] The advantages of controlling DWLSV operations at the memory subsystem controller level rather than the memory device level include, but are not limited to, shorter overall programming time (t). prog This means less programming time loss without having to change the storage capacity at the memory device level. Furthermore, MDWLSV can be performed for multi-plane programming operations, where multiple planes of the die can be written in parallel (e.g., simultaneously), further increasing programming efficiency.

[0018] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device containing memory and processing power.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0023] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may include processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into instructions for accessing the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0033] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 includes a DWLSV manager 113, which can manually or semi-automatically control WLSVs to program open blocks in the memory device. The memory subsystem controller 115 may contain a firmware (f / w) record 114 accessed by the DWLSV manager 113. Figure 2 As shown, firmware record 114 may have identification markers (e.g., block index, page index, plane index, plane mask information, etc.) stored therein. In some embodiments, firmware record 114 may be part of DWLSV manager 113. In some embodiments, firmware record 114 may be part of local memory 119. In some embodiments, at least a portion of DWLSV manager 113 is part of host system 120, an application, or an operating system. It is possible that in some embodiments, local media controller 135 includes at least a portion of DWLSV manager 113 and is configured to perform the functionality described herein, but one of the objectives of this disclosure is to control DWLSV operation at the firmware level rather than the memory device level, and therefore local media controller 135 may not have any portion of DWLSV manager 113.

[0035] Figure 2Example data structure 200 of a firmware record (e.g., firmware record 114) containing identifiers of multiple memory segments of a memory device, according to some embodiments of the present disclosure. The term "memory segment" encompasses a memory block or a sub-block within a memory block. A memory segment may contain multiple memory pages. The physical units of a memory block may be distributed across one or more planes. Firmware record 114 may also store plane mask information. The plane mask of firmware record 114 identifies the planes and the state (e.g., good or bad) of the memory blocks of those planes. As an example, if the plane mask is 4b'0000, then "4b'" identifies four bits used to describe the four planes of the block. "0000" indicates the plane and the state of the block of said plane. The least significant bit (LSB) (rightmost position) represents plane 0, the second LSB (second rightmost position) represents plane 1, the second most significant bit (MSB) (second leftmost position) represents plane 2, and the MSB (leftmost position) represents plane 3. In some embodiments, more than one of the planes may be planes of the same die. "0" represents a good block. "1" represents a bad block. A bad block is a block that is no longer used to store information. "0000" indicates that all blocks in planes 0 to 3 are good blocks. "0001" indicates that blocks in planes 1 to 3 are good blocks, and blocks in plane 0 are bad blocks.

[0036] exist Figure 2 In the data structure 200 shown, instances of firmware record 114 are labeled as a firmware DWLSV list based on logical unit number (LUN). Each entry in the list has multiple identification markers, such as block index, plane index, page index, WLSV value, and plane mask information. Each entry in the firmware DWLSV list is called a "slot". Slots are numbered 0, 1, ..., 7. Although eight slots are shown in the figure, the number of slots can be any number supported by the system design. Figure 2 In the example shown, the block index, plane index, and page index are specified for the current programming request of a particular LUN. The firmware-based DWLSV manager 113 determines which time slot has an open block (e.g., time slot 2 in the example shown) and retrieves the WLSV information for that time slot stored in the memory device. After managing the firmware DWLSV list (i.e., clearing or updating it, as discussed below with respect to the flowchart), the WLSV value can be updated at the memory device to match the WLSV value stored at the firmware.

[0037] Figure 3This is a flowchart of an example method for managing firmware records in view of the performed write operation, according to embodiments of the present disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The DWLSV manager 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0038] At operation 305, the processing logic receives a request to perform a write operation on the memory device. It should be noted that a "write" operation is sometimes also referred to as a "programming" operation. As mentioned above, the memory device has multiple segments (e.g., blocks), each segment containing multiple pages. It should be noted that a block may have multiple sub-blocks, where a sub-block may refer to a set of pages programmed using some common parameters. For example, the set of pages may be associated with the same word line having a predetermined (or retrieved) WLSV.

[0039] At operation 310, the processing logic retrieves the current WLSV information for a specific segment of the memory device. The segment can be selected based on whether it has additional capacity (“open block”) to write more data.

[0040] At operation 315, the processing logic performs a programming operation, i.e., writes data to the memory device. At operation 320, the processing logic stores information indicating the last written memory page (e.g., at local memory 119) in the specific memory segment where the write operation was performed. The last written memory page may indicate whether additional data can be written to the memory segment. The stored information may include one or more identification flags, such as the block index, plane index, and plane mask of the last written page. In some embodiments, the processing logic may additionally save the WLSV of the last written page. To determine whether the WLSV of the last written location is also saved, additional logical operations may be performed, as described in example flowcharts 400 and 500.

[0041] At operation 325, the processing logic, based on the write operation performed, manages the firmware record (such as...). Figure 1 and 2(As described in [the document]). Managing firmware records may involve determining whether the last written page is the last memory page among multiple pages associated with a common word line. In response to determining that the last written memory page is indeed the last memory page associated with a common word line, the WLSV in the firmware entry for a particular memory segment is cleared. This operation saves programming time because clearing the firmware entry indicates that the block is not an "open" block, but rather a closed block. Therefore, it is not necessary to track the WLSV value, and the WLSV value can be reused for subsequent programming operations. On the other hand, if it is determined that the last written memory page is not the last memory page associated with a common word line, the processing logic updates the WLSV in the firmware entry for the particular memory segment. In this way, open blocks and their WLSVs are tracked. It should be noted that the processing logic may check whether the plane mask of the memory page for a particular memory segment is compatible with the plane mask of another memory page for the same memory segment. If the plane masks are compatible, then multiple memory pages can be programmed together.

[0042] Figure 4 This is a flowchart of an example method for modifying firmware records before performing a write operation according to embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The DWLSV manager 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0043] At operation 405, the processing unit in controller 115 maintains records corresponding to multiple memory segments in the memory device (e.g., Figure 1 Firmware record 114 in the file is also displayed as Figure 2 The firmware DWLSV list 200 is included. Each entry in the firmware record contains one or more identification flags associated with a corresponding memory segment among multiple memory segments. At least one of the identification flags is a WLSV associated with the corresponding memory segment.

[0044] At operation 410, the processing device receives a request to perform a write operation on the memory device. This operation is similar to operation 305 in method 300.

[0045] At operation 415, the processing logic retrieves the current WLSV information associated with a specific memory segment. It should be noted that the processing logic may retrieve the current WLSV information from a memory device (as in operation 310 of method 300). In some embodiments, the processing logic may retrieve WLSV information currently stored in a firmware record, for example... Figure 2 The firmware DWLSV list shown in the document is 200.

[0046] At operation 420, the processing logic determines whether to modify the corresponding entry for the specific memory segment in the firmware record before performing the requested write operation, based on at least one of one or more identification flags associated with a specific memory segment and current WLSV information retrieved from the memory device. The decision on whether to modify the firmware record involves determining whether the last written memory page is the last memory page among a plurality of pages associated with a common word line. In response to determining that the last written memory page is indeed the last memory page associated with the common word line, the WLSV in the firmware entry for the specific memory segment is cleared (operation 430). On the other hand, in response to determining that the last written memory page is not the last memory page associated with the common word line, the WLSV in the firmware entry for the specific memory segment is updated (operation 425). In any case, this modification of the firmware record is performed before the write operation (operation 435). Normally, MDWLSV management is not performed before an erase operation, but it is performed before a write operation.

[0047] Subsequent write operations after MDWLSV can use the Least Recently Used (LRU) algorithm to make space available for newer entries associated with newer memory segments. The LRU algorithm checks if the number of entries in the firmware record meets a threshold number of entries. If the number of entries meets the threshold number of entries, a command is issued to remove the corresponding entry associated with the earlier memory segment from the firmware record.

[0048] Figure 5 This is a flowchart illustrating example methods for optimizing the management of firmware records according to embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing means, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1The DWLSV manager 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0049] At operation 505, the processing logic receives a request to perform a write operation.

[0050] At operation 510, the processing logic checks whether the block record of the memory device is valid. If the block record is valid, then subsequent optimization operations are performed. Otherwise, regular programming operations continue at operation 555 without any further optimization.

[0051] At operation 515, the processing logic checks whether the current block matches a block record entry retrieved from the memory device. If no match is found, the normal programming operation continues at operation 555 without optimization. If a match is found, the operation proceeds to 520.

[0052] At operation 520, the processing logic checks whether the plane masks of multiple pages, which can be programmed using a common WL but distributed across multiple planes, match. If the plane masks match, the method continues at operation 555. On the other hand, if the plane masks are compatible with each other, then the plane masks do not need to match exactly. Plane mask compatibility means that the blocks of information for each plane are the same (if not completely identical) between the two masks. Plane mask compatibility is used to force the memory device to resample. Programming operations can be modified (e.g., if a plane is identified as having “bad” blocks, then a 4-plane operation can be changed to a 3-plane operation) to ensure plane mask compatibility. As mentioned above, the plane masks of firmware record 114 identify the planes and the state (e.g., good or bad) of the memory blocks of those planes. As an illustrative example, 4b'1110, 4b'1101, 4b'1011 and 4b'0111 are compatible. However, 4b'1001, 4b'1100 and 4b'0011 are not compatible.

[0053] At operation 540, the processing logic checks whether the last page written to the firmware entry is the last page of the word line. If it is indeed the last page, then the WLSV value for the firmware entry is cleared (operation 545), thereby indicating that the block is closed. If the last page written is not the last page of the word line, then the block remains open, and the method proceeds to retrieving the WLSV entry from the memory device (operation 550).

[0054] Figure 6This describes an instance machine of computer system 600, within which an instruction set executable for causing the machine to perform any or more of the methods discussed herein is provided. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the DWLSV manager 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0055] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0056] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0057] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a Network Processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0058] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more sets of instructions 626 or software embodying any or more of the methods or functions described herein are stored. The instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to… Figure 1 The memory subsystem 110.

[0059] In one embodiment, instruction 626 includes implementing a component corresponding to the DWLSV manager (e.g., Figure 1 The DWLSV manager 113) provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0060] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0061] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0062] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0064] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0065] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method of operating a memory device, comprising: A request to perform a write operation is received at the memory device, wherein the memory device includes a plurality of memory segments, each of the plurality of memory segments including a plurality of memory pages; Retrieve current word line start voltage (WLSV) information associated with a specific memory segment among the plurality of memory segments from the memory device; The write operation is performed on the specific memory segment; Information indicating the last written memory page associated with the specific memory segment to which the write operation was performed is stored in a firmware record in the memory subsystem controller; as well as The firmware record, comprising multiple entries, is managed in light of the information indicating the last written memory page associated with the performed write operation, wherein each of the multiple entries in the firmware record includes one or more identification flags associated with a corresponding memory segment, at least one of which is a word line start voltage (WLSV) associated with the corresponding memory segment.

2. The method of claim 1, wherein managing the firmware record further comprises: Determine whether the last written memory page is the last memory page among a plurality of pages associated with a common word line.

3. The method according to claim 2, further comprising: In response to determining that the last written memory page is the last memory page among a plurality of pages associated with the common word line, the WLSV in the corresponding entry for the specific memory segment in the firmware record is cleared.

4. The method of claim 2, further comprising: In response to determining that the last written memory page is not the last memory page among a plurality of pages associated with the common word line, the WLSV in the corresponding entry for the specific memory segment in the firmware record is updated.

5. The method of claim 1, wherein the identification mark associated with a memory segment among the plurality of memory segments includes at least one of a memory segment index, a memory plane index, a memory page index, a WLSV value, or plane mask information.

6. The method of claim 1, wherein performing the write operation further comprises: Identify the planes on which the multiple memory pages of the specific memory segment are distributed.

7. The method of claim 1, further comprising: Check whether the first plane mask for the first memory page of the specific memory segment is compatible with the second plane mask for the second memory page of the specific memory segment.

8. A memory system comprising: A memory device, wherein the memory device includes a plurality of memory segments, each of the plurality of memory segments including a plurality of memory pages; as well as A processing device, operatively coupled to the memory device, performs operations including: Maintain firmware records corresponding to the plurality of memory segments in the memory device, each entry of the firmware record including one or more identification flags associated with a corresponding memory segment among the plurality of memory segments, at least one of the identification flags being a word line start voltage (WLSV) associated with the corresponding memory segment; Receive a request to perform a write operation on the memory device; Retrieve current WLSV information associated with a specific memory segment among the plurality of memory segments from the memory device; as well as Whether to modify the corresponding entry of the specific memory segment in the firmware record before performing the write operation is determined based on at least one of the one or more identification flags associated with the specific memory segment among the plurality of memory segments and the current WLSV information retrieved from the memory device.

9. The memory system of claim 8, wherein, in order to determine whether to modify the corresponding entry of the particular memory segment, the processing means further performs operations including: Determine whether the last page written to memory is the last memory page among multiple pages associated with a common word line.

10. The memory system of claim 9, wherein the processing means further performs the following operations: Determine the corresponding entry in the firmware record that modifies the specific memory segment; and In response to determining that the last written memory page is the last memory page among a plurality of pages associated with the common word line, the WLSV in the corresponding entry for the specific memory segment in the firmware record is cleared.

11. The memory system of claim 9, wherein the processing means further performs the following operations: Determine the corresponding entry in the firmware record that modifies the specific memory segment; and In response to determining that the last written memory page is not the last memory page among a plurality of pages associated with the common word line, the WLSV in the corresponding entry for the specific memory segment in the firmware record is updated.

12. The memory system of claim 8, wherein the identification mark associated with a memory segment among the plurality of memory segments includes at least one of a memory segment index, a memory plane index, a memory page index, a WLSV value, or plane mask information.

13. The memory system of claim 8, wherein the processing means further performs operations including: The write operation is performed after the firmware record is updated.

14. The memory system of claim 13, wherein the processing means further performs the following operations: A command is submitted to the memory device to remove the corresponding entry associated with the earlier memory segment from the firmware record and to make space available for a new entry associated with the newer memory segment to be written, in light of the write operation.

15. The memory system of claim 14, wherein submitting the command to remove the corresponding entry associated with the earlier memory segment further comprises: Determine whether the number of entries recorded in the firmware meets the threshold number of entries; In response to determining that the number of entries recorded in the firmware meets the threshold number of entries, the least recently used memory segment is removed.

16. A non-transitory computer-readable medium including instructions that, when executed by a processing means, cause the processing means to perform operations including: Receive a request to perform a write operation at a memory device, wherein the memory device includes a plurality of memory segments, each of the plurality of memory segments including a plurality of memory pages; Retrieve current word line start voltage (WLSV) information associated with a specific memory segment among the plurality of memory segments from the memory device; The write operation is performed on the specific memory segment; Information indicating the last written memory page associated with the specific memory segment to which the write operation was performed is stored in a firmware record in the memory subsystem controller; as well as The firmware record, comprising multiple entries, is managed in light of the information indicating the last written memory page associated with the performed write operation, wherein each of the multiple entries in the firmware record includes one or more identification flags associated with a corresponding memory segment, at least one of which is a word line start voltage (WLSV) associated with the corresponding memory segment.

17. The non-transitory computer-readable medium of claim 16, wherein managing the firmware record further comprises: Determine whether the last written memory page is the last memory page among a plurality of pages associated with a common word line.

18. The non-transitory computer-readable medium of claim 17, wherein the operation further comprises: In response to determining that the last written memory page is the last memory page among a plurality of pages associated with the common word line, the WLSV in the corresponding entry for the specific memory segment in the firmware record is cleared.

19. The non-transitory computer-readable medium of claim 17, wherein the operation further comprises: In response to determining that the last written memory page is not the last memory page among a plurality of pages associated with the common word line, the WLSV in the corresponding entry for the specific memory segment in the firmware record is updated.

20. The non-transitory computer-readable medium of claim 16, wherein the identification mark associated with a memory segment among the plurality of memory segments includes at least one of a memory segment index, a memory plane index, a memory page index, a WLSV value, or plane mask information.

Images