Code generation method, method for accessing a memory chip, bus interface, and storage medium

Abstract

An embodiment of the present invention provides a code generation method, a method for accessing a memory chip, a bus interface, and a storage medium. The program code generation method for accessing a memory chip includes: obtaining operation timing information corresponding to a predetermined access operation on the memory chip, where the operation timing information includes an information sequence containing multiple signal jump state information, and each signal jump state information characterizes the duration for which a signal line maintains a signal state and includes information on the signal line identifier, signal holding state, and duration; setting an operation instruction for executing the predetermined access operation according to the operation timing information; and generating program code corresponding to the predetermined access operation according to the operation instruction. By setting multiple nested counters for superimposed counting, data transmission of the memory peripheral interface bus protocol is realized, thereby greatly simplifying the complex state machine jump design of the memory chip and reducing the area of the bus interface circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory chips, and in particular, to a method for generating program code for accessing a memory chip, a method for accessing a memory chip through a bus interface, a bus interface, and a storage medium. Background Art

[0002] Flash Memory buses, I2C (Inter-Integrated Circuit) communication protocol buses, I2S (Inter-IC Sound) audio communication protocol buses, Universal Asynchronous Receiver / Transmitter (UART) interface buses, Serial Peripheral Interface (SPI) buses, etc. are commonly used peripheral buses in various memory chips. Many important functions in memory chips, such as power-on startup, storage, reading and writing internal registers of the chip, printing internal information of the chip, etc., are inseparable from these peripheral buses. Since the interface speed of the controller circuit of the peripheral bus will not be higher than the system clock speed, various signals of the bus interface are usually implemented by dividing the system clock frequency.

[0003] The designs of existing peripheral bus controllers are usually implemented according to the following two methods: ① implemented by the cooperation of a state machine and a counter divider; ② implemented by combinational logic for functions and a counter divider for frequency division.

[0004] For the implementation method ①, if the functions of the bus controller are very complex, the states and jumps of the state machine will be particularly numerous, making the design code of the bus controller overly lengthy and the readability of the design code poor. In addition, due to too many state machine jumps and strong pertinence, it is difficult to adapt to various memory chips, resulting in the design code being not easy to reuse.

[0005] For the implementation method ②, implementing the functions of the controller through combinational logic makes it difficult to consider all variables, prone to errors, and once the circuit is complex, the timing will become difficult to control and difficult to read. In addition, the circuit design is not intuitive, and multiple signals may be designed in one timing or combinational logic block, affecting the verification efficiency. Summary of the Invention

[0006] The purpose of the embodiments of the present invention is to provide a technical solution for accessing a memory chip through a bus interface to simplify the design of signal jump states for accessing the memory chip.

[0007] According to one aspect of an embodiment of the present invention, there is provided a method for generating program code for accessing a memory chip, including: obtaining operation timing information corresponding to a predetermined access operation on the memory chip, where the operation timing information includes an information sequence containing multiple signal jump state information, and each of the signal jump state information characterizes the duration for which a signal line maintains a signal state and includes information on the signal line identifier, signal holding state, and duration; setting an operation instruction for performing the predetermined access operation according to the operation timing information, where the operation instruction includes operation instructions for performing the following operations: sequentially generating an instruction sequence of signal jump instructions including the signal line identifier and signal holding state of each of the signal jump state information in the operation timing information, setting a first register and assigning the first register the value of the number of the signal jump state information, setting a first counter, where the first counter is used to count the currently executing signal jump instruction according to the value of the first register when executing the instruction sequence of the predetermined access operation, setting multiple second registers and sequentially assigning the multiple second registers the information on the durations of the multiple signal jump state information, setting a second counter, where the second counter is used to count the duration of the signal jump state information corresponding to the currently executing signal jump instruction according to the duration information of the second register corresponding to the value of the first counter when executing the instruction sequence of the predetermined access operation, setting a third register, where the third register is used to record the number of bytes corresponding to the predetermined access operation when executing the instruction sequence of the predetermined access operation, setting a third counter, where the third counter is used to count the cumulative number of bytes of the predetermined access operation according to the value of the third register when executing the instruction sequence of the predetermined access operation; generating program code corresponding to the predetermined access operation according to the operation instruction.

[0008] Optionally, the program code is a function corresponding to the predetermined access operation in a bus interface driver program.

[0009] Optionally, the predetermined access operation is a write operation, the operation timing information includes 6 signal jump state information, and the 6 signal jump state information are, in sequence, the time TEADC for continuously pulling up the device address enable ALE signal, the time TEAHC for pulling down the ALE signal and maintaining a low level, the time TACSE for enabling the address to chip select signal, the time TCS from enabling the chip select signal to pulling down the write enable signal, the time TWP for continuously pulling down the write enable signal, and the time TCH for maintaining the high level after pulling up the write enable signal.

[0010] Optionally, the predetermined access operation is a read operation, and the operation timing information includes five signal jump state information, which are, in sequence, the effective time TEADC of the external latch latch signal being high, the time TEAHC for the external latch latch signal to maintain a low level, the time TACSE for the address to chip select signal to be enabled, the time TACO from the chip select signal being enabled to the read enable signal being pulled low, and the time TRAD for the read enable signal to be continuously pulled low.

[0011] According to another aspect of an embodiment of the present invention, there is provided a method for accessing a memory chip through a bus interface, including: receiving a request for accessing a memory chip, where the request at least includes an access operation and an access address; and performing the access operation on the access address of the memory chip through program code generated by any of the foregoing program code generation methods for accessing a memory chip.

[0012] Optionally, the access operation is a write operation, and the request further includes data to be written and length information of the data to be written.

[0013] Optionally, the access operation is a read operation, and the request further includes length information of the data to be read.

[0014] Optionally, the method is executed through a driver program of the bus interface.

[0015] According to another aspect of an embodiment of the present invention, there is further provided a bus interface of a memory chip, characterized by including: a driver program for executing any of the foregoing methods for accessing a memory chip through a bus interface.

[0016] According to yet another aspect of an embodiment of the present invention, there is further provided a computer-readable storage medium, characterized in that the computer-readable storage medium stores executable instructions, and the executable instructions cause a processor to execute the steps of any of the foregoing methods for accessing a memory chip through a bus interface.

[0017] Through the program code generation method for accessing a memory chip and the method for accessing a memory chip through a bus interface according to the embodiments of the present invention, the state jump of the predetermined access operation to the memory chip is simplified in the form of hardware settings and software logic. Among them, nested multiple counters are set for superimposed counting to achieve data transmission of the memory peripheral interface bus protocol, thereby greatly simplifying the complex state machine jump design of the memory chip and reducing the area of the bus interface circuit. Description of the Drawings

[0018] Figure 1 is a schematic diagram showing the write operation timing of a flash memory;

[0019] Figure 2 is a schematic diagram showing the read operation timing of a flash memory;

[0020] Figure 3 is showing Figure 1 a schematic diagram of the state machine jumps of the write operation timing shown in;

[0021] Figure 4 is a flowchart showing a method for generating program code for accessing a memory chip according to an embodiment of the present invention;

[0022] Figure 5 is showing Figure 4 a flowchart of an exemplary process of step S520 in;

[0023] Figure 6 is a flowchart of a method for accessing a memory chip through a bus interface according to an embodiment of the present invention. Detailed implementation manners

[0024] The following combines the accompanying drawings (the same reference numerals in several accompanying drawings represent the same elements) and embodiments to further elaborate in detail on the specific implementation manners of the embodiments of the present invention. The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0025] Figure 1 is a schematic diagram showing the write operation timing of a flash memory (Flash Memory), Figure 2 is a schematic diagram showing the read operation timing of a Flash.

[0026] As Figure 1 shown, the write operation timing of a Flash consists of multiple signals, and completing a write command requires a combination of signal controls for multiple signal lines. The conventional way to implement such a Flash controller is to use a state machine to divide the timing of these buses into many signal states, and then drive the buses according to the states to complete the storage function of the Flash. However, in a more complex Flash, there is not only this one kind of state and command. The more complex the Flash, the more states and more complex state jumps there are, and simply distinguishing these states will take a lot of time.

[0027] In order to implement the functions supported by this Flash, the existing implementation method designs a detailed and complex state machine for it.

[0028] In view of the above problems, the inventor, through analyzing the timings shown in Figure 1 and Figure 2 , found that there are many repetitive and similar actions in these timings, such as Figure 3As shown. For example, TEADC represents the time when the device address enable ALE signal is continuously pulled high for 6 clocks, and TEAHC represents the time when the ALE signal is pulled low and maintained at a low level (pulled low until the address signal driving ends) for 3 clocks. The signals of such peripherals are pulled high or low in a certain order, and they occur sequentially and have certain relationships. However, these relationships do not necessarily need to be implemented by a state machine because as the functions become more complex, the state machine will also become more complex.

[0029] Therefore, according to the inventive concept of the present invention, for example, the aforementioned Figure 1 and Figure 2 the TEADC, TEAHC, TACSE, etc. in the operation timing information shown are defined as signal jump state information. Therefore, the operation timing information includes an information sequence containing multiple signal jump state information, and each signal jump state information characterizes the duration for which a signal line maintains a signal state, and includes information on the signal line identifier, the signal holding state, and the duration. Here, the signal holding state can be understood as the target signal state achieved by controlling a specified signal line or a certain signal state or signal jump state maintained by controlling a specified signal line. For example, as Figure 3 shown, the operation timing information of the write operation includes 6 signal jump state information, and the 6 signal jump state information are, in sequence, the time TEADC when the device address enable ALE signal is continuously pulled high for 6 clocks, the time TEAHC when the ALE signal is pulled low and maintained at a low level for 3 clocks, the time TACSE when the address to chip select signal is enabled for 5 clock cycles, the time TCS from the chip select signal being enabled to the write enable signal being pulled low for 5 clock cycles, the time TWP when the write enable signal is continuously pulled low for 5 clock cycles, and the holding time TCH for 3 clocks after the write enable signal is pulled high.

[0030] First, there is a necessary sequential relationship between these signal jump state information. When designing the operation instructions of the bus interface of the memory chip, a jump timing counter (referred to as the first counter here) can be set to represent their sequential relationship, and a register (referred to as the first register here) can be used to record the number of signal jump state information counted by the first counter. It can be seen that the first register and the first counter used in combination are used to perform jumps on the signal states of the state machine for a predetermined access operation.

[0031] Secondly, multiple registers (hereinafter referred to as the second registers) are further set to record the time information of each signal jump state information. For example, 6 in TEADC is recorded in the first second register, 3 in TEAHC is recorded in the second second register, and so on. Since these 6 signal jump states do not occur simultaneously, when performing a predetermined access operation (write operation), the same timing number counter (hereinafter referred to as the second counter) can be time-division multiplexed to count the time of the signal jump state that is occurring, which can reduce the area of the bus interface circuit and save system resources. Here, the second register and the second counter used in cooperation are used to control the signal duration of the state machine of the predetermined access operation in a specified signal jump state.

[0032] Thirdly, a byte transfer counter (the third counter) for counting the number of bytes of the access operation can also be set to record the cumulative number of bytes of the access operation, thereby completing the transfer of multi-byte data.

[0033] In addition, other access operations for the memory chip can also be implemented through a design similar to the foregoing.

[0034] The foregoing describes an exemplary design for the access operation of the Micron MT29F2G08ABAEAH4 model flash memory. It should be noted that for different models and different types of peripherals, the signal jump state information in the operation timing information, including the signal lines, signal holding states, and duration information in each signal jump state information, may be different, but a similar design concept can be adopted to implement the state machine jump of its access operation.

[0035] Through the foregoing design, it is possible to perform superimposed counting by setting multiple nested counters, realize the data transfer of the memory peripheral interface bus protocol, thereby greatly simplifying the complex state machine jump design of the memory chip and reducing the area of the bus interface circuit. In addition, for memory bus interfaces where the peripheral bus speed is slower than the system bus speed, such as interfaces of protocols such as SPI, i2c, and UART, the design of the present application is applicable.

[0036] Figure 4 It is a flowchart showing a program code generation method for accessing a memory chip according to an embodiment of the present invention. The program code generated by this method is used for the bus interface driver program of the memory chip.

[0037] Refer to Figure 4 , in step S510, obtain the operation timing information corresponding to the predetermined access operation for the memory chip.

[0038] The operation timing information includes an information sequence containing multiple signal transition state information, and each of the signal transition state information characterizes the duration for which a signal line maintains a signal state and includes information on the signal line identifier, signal holding state, and duration. For example, Figure 1 and Figure 2 respectively show the operation timing information for performing a write operation and a read operation on a memory chip.

[0039] Among them, the operation timing information for the write operation includes 6 signal transition state information, and the 6 signal transition state information are, in sequence, the time (i.e., the time of 6 clock cycles) TEADC for continuously pulling high the device address enable ALE signal, the time (i.e., the time of 3 clock cycles) TEAHC for pulling low the ALE signal and maintaining it at a low level, the time (i.e., the time of 5 clock cycles) TACSE for enabling the address to chip select signal, the time (i.e., the time of 5 clock cycles) TCS from enabling the chip select signal to pulling low the write enable signal, the time TWP for continuously pulling low the write enable signal, and the holding time (i.e., the time of 3 clock cycles) TCH after pulling high the write enable signal.

[0040] Among them, the operation timing information for the read operation includes 5 signal transition state information, and the 5 signal transition state information are, in sequence, the valid time TEADC for the external latch to latch a high signal, the time TEAHC for the external latch to maintain a low level of the latch signal, the time TACSE for enabling the address to chip select signal, the time TACO from enabling the chip select signal to pulling low the read enable signal, and the time TRAD for continuously pulling low the read enable signal.

[0041] In step S520, according to the operation timing information, an operation instruction for performing the predetermined access operation is set.

[0042] Here, the set operation instruction can be a pseudocode, text, or program code segment reflecting the corresponding processing logic, or a combination of two or three of the foregoing pseudocode, text, and program code segments, and is used to generate program code according to these operation instructions in step S530 later.

[0043] Figure 5 is a flowchart showing an exemplary process of step S520.

[0044] Specifically, in step S521, an instruction sequence of signal transition instructions including the signal line identifier and signal holding state of each of the signal transition state information in the operation timing information is sequentially generated.

[0045] Specifically, signal line identifiers of each signal jump state information and signal jump instructions of corresponding signal hold states are generated from multiple signal jump state information in the operation timing information to form the instruction sequence. For example, the signal line identifier involved in the signal jump instruction generated for the signal jump state information TEADC is ALE, and the corresponding signal hold state is high; the signal line identifier involved in the signal jump instruction generated for the signal jump state information TEAHC is ALE, and the corresponding signal hold state is low, and so on.

[0046] For example, the signal line identifiers and signal hold states involved in each signal jump state information of the instruction sequence can be recorded through multiple registers, or pseudo-codes reflecting these signal jump instructions can be generated.

[0047] In step S522, a first register is set, and the first register is assigned the number of the signal jump state information.

[0048] As described above, the set first register is used to record the number of the signal jump state information, so it is assigned the number of the signal jump state information.

[0049] In step S523, a first counter is set. The first counter is used to count the currently executing signal jump instruction according to the value of the first register when executing the instruction sequence of the predetermined access operation.

[0050] The set first counter is used in cooperation with the first register. The first counter is initially assigned 0, and the value in the first register is 6.

[0051] For example, for a write operation, when starting to execute the instruction sequence of the predetermined access operation, according to the value of the first counter (which is 0), the signal jump instruction corresponding to TEADC is executed at this time; when the signal jump state of TEADC is completed, the first counter is incremented by 1, and according to the value of the first counter (which is 1), the signal jump instruction corresponding to TEAHC is executed at this time; and so on, until the value of the first counter reaches 5 (that is, the first counter has counted 6 times from 0 to 5), the data transfer corresponding to the predetermined access operation is executed. Thus, it can be seen that the value of the first counter can realize the signal state jump of the state machine of the predetermined access operation.

[0052] In step S524, a plurality of second registers are set, and the plurality of second registers are sequentially assigned the information of the duration of the plurality of signal jump state information.

[0053] For example, for a write operation, 6 second registers are set, and the 6 second registers are respectively assigned [6, 3, 5, 5, 5, 3].

[0054] In step S525, a second counter is set. The second counter is used to count the duration of the signal jump status information corresponding to the currently executing signal jump instruction according to the duration information of the second register corresponding to the value of the first counter when executing the instruction sequence of the predetermined access operation.

[0055] The set second counter is initially assigned a value of 0, is used in cooperation with multiple second registers, and when executing the instruction sequence of the predetermined access operation, the second register for which the second counter counts is corresponding to the value of the first counter.

[0056] For example, for a write operation, when executing the instruction sequence of the predetermined access operation, the value of the first counter is the initial value 0. At this time, the signal jump instruction corresponding to TEADC is executed, and the second counter counts according to the value (i.e., 6) in the second register [0] corresponding to the value of the first counter. At this time, the signal jump instruction with the ALE signal continuously pulled high is executed, and the second counter counts the duration of the ALE signal continuously pulled high until the counted time reaches 6, and then the transmission and writing of the data to be written start. After that, the first counter is incremented by 1 and becomes 1. At this time, the signal jump instruction corresponding to TEAHC is executed. Among them, the second counter is initialized to 0 and counts the duration of the ALE signal pulled low and held low according to the value (i.e., 3) in the second register [1] corresponding to the current value of the first counter until the counted time of the second counter reaches 3. Then, the first counter is incremented by 1 and becomes 2. At this time, the signal jump instruction corresponding to TACSE is executed. Among them, the second counter is initialized to 0 and counts the duration of the address to chip select signal enabled according to the value (i.e., 5) in the second register [2] corresponding to the current value of the first counter until the counted time of the second counter reaches 5. And so on, until the first counter is incremented to 5 and the second counter counts the holding time after the write enable signal is pulled high to reach the value in the second register [5], the data to be written is written and transmitted to the memory chip. At this point, the first counter has counted 6 times, and the processing of the write operation is completed.

[0057] According to an exemplary embodiment of the present invention, the first counter and the second counter perform the corresponding number of counting times according to the values in the first register and the second register.

[0058] In step S526, a third register is set. The third register is used to record the number of bytes corresponding to the predetermined access operation when executing the instruction sequence of the predetermined access operation.

[0059] That is to say, when a request to perform a predetermined access operation is actually received from the bus interface of the memory chip, the set third register is assigned a value, and the third register is assigned the number of bytes of the predetermined access operation, such as the number of bytes of data to be written.

[0060] In step S527, a third counter is set, and the third counter is used to count the cumulative number of bytes of the predetermined access operation according to the value of the third register when executing the instruction sequence of the predetermined access operation.

[0061] The set third counter is used in conjunction with the third register. The third counter is initially assigned a value of 0, and the value in the first register is 6.

[0062] In the example of the foregoing write operation, when the first counter accumulates from 0 to 5 and the second counter counts the holding time after the write enable signal is pulled high to reach the value in the second register [5], a write transfer of the data to be written is performed on the memory chip. At this time, the third counter counts the cumulative number of bytes transferred by the write operation until the cumulative number of bytes transferred reaches the value of the third register. It should be noted here that the processing order of the foregoing steps S521 to S527 does not have to be the order described above, but can be adjusted under the condition of conforming to the processing logic. For example, steps S526 to S527 can be executed Figure 5 at any flow position shown, such as before executing S521 to S523; for another example, steps S524 to S525 can be executed after steps S526 to S527.

[0063] Since then, through the processing of steps S521 to S527, the state jump reflecting the predetermined access operation on the memory chip has been simplified in the form of hardware settings and software logic. Among them, nested multiple counters are set for superimposed counting to achieve data transmission of the memory peripheral interface bus protocol, thereby greatly simplifying the complex state machine jump design of the memory chip and reducing the area of the bus interface circuit.

[0064] In step S530, according to the operation instruction set in step S520, program code corresponding to the predetermined access operation is generated.

[0065] In this step, program code reflecting the operation instruction set in step S520 is generated. The program code can be source code that meets the programming requirements of the memory peripheral interface, such as C language source code, Python source code, assembly language code, etc., but is not limited thereto.

[0066] As described above, the program code generated by this method is used for the bus interface driver of the memory chip. Optionally, the program code is encoded as a function corresponding to the predetermined access operation in the bus interface driver and can be repeatedly called.

[0067] An embodiment of the present invention further provides a method for accessing a memory chip through a bus interface. In the process of executing this method, the access operation on the memory chip is performed by using the program code generated by any of the aforementioned program code generation methods for accessing the memory chip.

[0068] Figure 6 is a flowchart of the method for accessing a memory chip through a bus interface according to an embodiment of the present invention.

[0069] Referring to Figure 6 , in step S710, a request for accessing the memory chip is received, and the request includes at least an access operation and an access address. The access address is the starting access address of the access operation.

[0070] For example, the access operation may be a write operation. Correspondingly, the request for accessing the memory chip further includes the data to be written and the length information of the data to be written, which is used to indicate the data to be written and the length information of the data to be written when performing the write operation.

[0071] For another example, the access operation may be a read operation. The request for accessing the memory chip further includes the length information of the data to be read, which is used to indicate the length information of the data to be read when performing the read operation. The bus interface that calls this method can determine to read a specified number of bytes (such as 256 bytes, 512 bytes, etc.) or a specified number of bits (such as 256 bits, 512 bits, etc.) of data at a time, so that each time the method for accessing the memory chip through the bus interface is called, the specified number of bytes or the specified number of bits of data is read, and this method is iteratively called until all the data of a certain file, for example, is read.

[0072] In addition, for both the write operation and the read operation, the received request may further include the number of bytes per access transfer (write transfer and read transfer), which is used to indicate the data length of each access transfer.

[0073] In step S720, the access operation is performed on the access address of the memory chip by using the program code generated by any of the aforementioned program code generation methods for accessing the memory chip.

[0074] The following takes the schematic diagram of the state machine jump of the write operation timing shown in Figure 3 as an example to describe the state jump process of performing the write operation in step S720.

[0075] When starting to execute the program code corresponding to the write operation timing, the first counter timing_num_cnt = 0. At this time, the ALE signal is pulled high, that is, ALE = 1, and the address value is sampled. At the same time, the second counter timing_cnt counts to 5 according to the value (6) of the second register [timing_num_cnt], so that the state of the ALE signal being pulled high is maintained for 6 clock cycles, and then enters the state where the first counter timing_num_cnt = 1. At this time, it enters the signal jump state of TEAHC, pulls the ALE signal low and keeps it low level, that is, ALE = 0. At the same time, the second counter timing_cnt counts to 2 according to the value (3) of the second register [timing_num_cnt], so that the state of the ALE signal being pulled low and kept low level is maintained for 3 clock cycles, and then enters the state where the first counter timing_num_cnt = 2. And so on, until the first counter timing_num_cnt = 5 and the second counter timing_cnt counts to 2 according to the value (3) of the second register [timing_num_cnt]. At this time, the transmission of the data to be written starts. Among them, in step S710, the number of unit bytes of each write transmission can also be received in the received request. The number of unit bytes can be, for example, 1 byte or 2 bytes, etc. In the write transmission of the data to be written, each time the write transmission of the data to be written with the number of unit bytes is performed, and the third counter byte_cnt is used for counting until the third counter byte_cnt reaches the value of the third register, and the transmission of all the data to be written is completed. It can be seen that the state jump of the state machine is controlled by the value of the first counter timing_num_cnt, and in any specified signal jump state, the duration of each jump state is controlled by the counting of the corresponding second counter timing_cnt.

[0076] Optionally, the foregoing method of accessing the memory chip through the bus interface is executed by a driver of the bus interface of the memory chip.

[0077] The following describes the process of performing a write operation on a memory chip through a bus interface according to an embodiment of the present invention. The processes of read operations and other access operations are similar to the process of write operations in the processing manner.

[0078] When the client sends a command to write data to a memory (such as Flash) through the bus interface of the memory chip, at step S710, the bus interface (driver) of the memory chip receives a request to perform a write operation on the memory chip, and the request includes information indicating the write operation, the write address, the data to be written, and the length information of the data to be written (such as the number of bytes). At step S720, the bus interface (driver) of the memory chip calls the program code generated for the write operation, and passes the information of the write operation, the write address, the data to be written, and the length information of the data to be written (such as the number of bytes) to the program code in the form of parameters. Through the program code generated for the write operation, signal jumps such as device address enabling, addressing, and data signal locking are performed on the memory chip, and then the data to be written is written and transmitted to the write address of the memory chip.

[0079] An embodiment of the present invention further provides a bus interface of a memory chip, and the bus interface includes: a driver for executing any of the foregoing methods for accessing a memory chip through a bus interface.

[0080] An embodiment of the present invention further provides a computer-readable storage medium, and the computer-readable storage medium stores executable instructions, and the executable instructions cause a processor to execute the steps of any of the foregoing methods for accessing a memory chip through a bus interface.

[0081] The above embodiments are only used to illustrate the embodiments of the present invention, rather than to limit the embodiments of the present invention. Those of ordinary skill in the relevant art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A method for generating program code for accessing a memory chip, comprising: Obtaining operation timing information corresponding to a predetermined access operation on the memory chip, where the operation timing information includes an information sequence containing a plurality of signal jump state information, and each of the signal jump state information characterizes the duration for which a signal line maintains a signal state and includes information on the signal line identifier, signal holding state, and duration; Setting an operation instruction for performing the predetermined access operation according to the operation timing information, where the operation instruction includes operation instructions for performing the following operations: Sequentially generating an instruction sequence of signal jump instructions including the signal line identifier and signal holding state of each of the signal jump state information in the operation timing information, Setting a first register and assigning the first register with the number of the signal jump state information, Setting a first counter, which is used for counting the currently executing signal jump instruction according to the value of the first register when executing the instruction sequence of the predetermined access operation, Setting a plurality of second registers and sequentially assigning the plurality of second registers with the information on the durations of the plurality of signal jump state information, Setting a second counter, which is used for counting the duration of the signal jump state information corresponding to the currently executing signal jump instruction according to the duration information of the second register corresponding to the value of the first counter when executing the instruction sequence of the predetermined access operation, Setting a third register, which is used for recording the number of bytes corresponding to the predetermined access operation when executing the instruction sequence of the predetermined access operation, Setting a third counter, which is used for counting the cumulative number of bytes of the predetermined access operation according to the value of the third register when executing the instruction sequence of the predetermined access operation, Generating program code corresponding to the predetermined access operation according to the operation instruction, where the program code is a function corresponding to the predetermined access operation in the bus interface driver program.

2. The method according to claim 1, wherein The predetermined access operation is a write operation, and the operation timing information includes 6 signal jump state information, and the 6 signal jump state information are, in sequence, the time TEADC for continuously pulling high the device address enable ALE signal, the time TEAHC for pulling down the ALE signal and maintaining it at a low level, the time TACSE for enabling the address to chip select signal, the time TCS from enabling the chip select signal to pulling down the write enable signal, the time TWP for continuously pulling down the write enable signal, and the time TCH for maintaining the high level after pulling up the write enable signal.

3. The method according to claim 1, characterized in that The predetermined access operation is a read operation, and the operation timing information includes 5 signal jump state information, and the 5 signal jump state information are, in sequence, the effective time TEADC for the external latch latch signal to be high, the time TEAHC for the external latch latch signal to maintain a low level, the time TACSE for enabling the address to chip select signal, the time TACO from enabling the chip select signal to pulling down the read enable signal, and the time TRAD for continuously pulling down the read enable signal.

4. A method for accessing a memory chip through a bus interface, comprising: Receiving a request for accessing a memory chip, the request at least including an access operation and an access address; Performing the access operation on the access address of the memory chip through program code generated by the method for generating program code for accessing a memory chip according to any one of claims 1 to 3.

5. The method according to claim 4, wherein The access operation is a write operation, and the request further includes data to be written and length information of the data to be written.

6. The method according to claim 4, characterized in that, The access operation is a read operation, and the request further includes length information of data to be read.

7. The method according to any one of claims 4 to 6, characterized in that Executing the method through a driver of the bus interface.

8. A bus interface of a memory chip, characterized in that, Comprising: A driver for executing the method for accessing a memory chip through a bus interface according to any one of claims 4 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores executable instructions, and the executable instructions cause a processor to execute the steps of the method for accessing a memory chip through a bus interface according to any one of claims 4 to 7.

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