Cyclic Redundancy Check (CRC) decoded using the inverse CRC generator polynomial

Abstract

A cyclic redundancy check (CRC) decoder circuit (300) includes: an input terminal for receiving an input stream (303) having an input bit sequence from a predefined CRC generator polynomial that encodes the input bit sequence, the input bit sequence including information bits and CRC bits; and at least one processor (301) configured to perform a CRC decoding calculation of the input bit sequence. The at least one processor (301) is configured to: apply an inverse processing operation of the predefined CRC generator polynomial that encodes the input bit sequence to generate a data set; calculate a CRC syndrome from the data set; and determine whether the CRC syndrome contains any 1-valued bits indicating a CRC error.

Description

Technical Field

[0001] The field of the invention relates to a cyclic redundancy check (CRC) circuit, a communication unit and a method for calculating a CRC. The field of the invention is applicable to, but not limited to, channel coding for current and future generations of communication standards. Background Art

[0002] It is known that a cyclic redundancy check (CRC) can be used to detect whether any errors have been introduced into a sequence of information bits as it passes from a source to a sink.

[0003] Source-side CRC calculation

[0004] At the source end, for the sequence of A information bits a=[a0,a l ,a2,...,a A-1 ] performs a CRC calculation to generate a sequence of L parity bits p = [p0, p1, p2, ..., p L-1 ].

[0005] A sequence of parity bits, p, is generated as a function of the A information bits of a according to a CRC generator polynomial. The CRC generator polynomial is typically specified in the communication standard being implemented, such as the L=6-bit CRC generator polynomial of 3GPP New Radio [1]: g CRC6 (D)=[D 6 +D 5 +1]. It is worth noting that communication standards usually specify constraints that govern the generation of a CRC, but do not specify how it can be implemented. More specifically, communication standards usually only specify that the calculation be performed in a systematic form such that the polynomial a0D A+L-1 +a1D A+L-2 +…+a A-1 D L +p0D L-1 +p1D L-2 +…+p L-2 D 1 +p L-1 When divided by the CRC generator polynomial, a remainder equal to "0" is produced in GF(2).

[0006] A sequence of L parity bits, p, is usually appended to the end of a sequence of A information bits, a, to produce a CRC code sequence of B = A + L bits.

[0007] b=[b0,b l ,b2,...,b B-1 ],in

[0008] b k =a k , for k = 0, 1, 2, ... A-1 and

[0009] b k =p k-A , for k=A,A+1,A+2,…,A+L-1.

[0010] Some communication standards specify that, before CRC calculation, a sequence a of A information bits may be appended to the end of a sequence of L 1-valued bits to generate an extended information bit sequence comprising L+A bits:

[0011] a′=[a′0,a′1,a′2,...,a′ L+A-1 ],in

[0012] a′ k =1, for k=0,1,2,…L-1 and

[0013] a′ k =a k-L , for k = L, L+1, L+2,…, L+A-1.

[0014] In these cases, the sequence of L parity bits, p, can be computed as a function of all L+A bits of the extended information bit sequence a′, rather than as a function of the A bits of the information bit sequence a. The sequence of L parity bits can be appended to the end of the sequence of A information bits a to produce the CRC coded sequence:

[0015] B=A+L digit b=[b0,b l ,b2,...,b B-1 ], as above.

[0016] In some cases, the bits of the CRC code sequence b may be scrambled, interleaved, and / or channel coded at the source.

[0017] Sink CRC calculation

[0018] At the sink, a CRC calculation can be performed to detect a sequence of B=A+L recovered CRC coded bits. If there is an error, it will be different from the CRC encoded bit sequence b obtained in the source. Here, the recovered CRC encoded bit sequence A sequence of L recovered parity bits can be represented as The sequence appended to the A recovered information bits At the end of , if there is an error, it will be different from the parity bit sequence p and information bit sequence a obtained in the source.

[0019] Errors can be detected by performing a CRC calculation as The function of A recovered information bits obtains L calculated parity bit sequences If the calculated parity bit sequence and the recovered parity bit sequence Alternatively, a CRC calculation can be performed as A function of all B = A + L recovered CRC coded bits of obtains a sequence of L calculated parity bits To detect errors. In this case, the parity bit sequence calculated Become the syndrome of CRC (as understood). If the syndrome If the CRC is not equal to a sequence of L zero-valued bits, an error has been detected. Note that standards generally do not specify how CRCs are used to detect errors, allowing implementers to choose the method described here or another method.

[0020] In the case where the source obtains the extended information bit sequence a′ by appending a sequence a of A information bits to the end of a sequence of L 1-valued bits, the same extension operation is performed in the sink. More specifically, the sequence of A recovered information bits is appended to the end of a sequence of L 1-valued bits. Appended to the end of the sequence of L 1-valued bits to generate an extended recovered information bit sequence consisting of L+A bits:

[0021] in

[0022] For k = 0, 1, 2, ... L-1 and

[0023] For k=L, L+1, L+2,…, L+A-1.

[0024] In these cases, the sequence of L calculated parity bits The recovered information bit sequence can be used as an extension It is calculated as a function of all L+A bits, rather than as a sequence of recovered information bits Alternatively, the sequence of B recovered CRC coded bits is can be appended to the end of the sequence of L 1-valued bits to generate an extended recovered CRC encoded bit sequence consisting of L+B bits:

[0025] in

[0026] For k = 0, 1, 2, ... L-1 and

[0027] For k=L, L+1, L+2,…, L+B-1.

[0028] In these cases, the sequence of L calculated syndrome bits The CRC encoded bit sequence that can be recovered as an extension is calculated as a function of all L+B bits, rather than as a recovered CRC coded bit sequence The function calculation of B bits.

[0029] In the case where the source performs scrambling, interleaving and / or channel coding on the bits of the CRC coded sequence b, inverse descrambling, deinterleaving and / or channel decoding operations may be performed in the sink to obtain the recovered CRC coded bit sequence In the case that the scrambling of the CRC code sequence b in the source affects only the bits provided by the parity bit sequence p, the sink can perform the scrambling of the calculated parity bit sequence p after the CRC calculation. Apply an inverse scrambling operation instead to the recovered CRC encoded bit sequence before CRC calculation Apply the inverse scrambling operation.

[0030] CRC calculation using shift register

[0031] Now refer to Figure 1 , shows the L=6-bit CRC generator polynomial g of the source circuit CRC6 (D)=[D 6 +D 5 +1] is a known shift register implementation 100. The CRC generator polynomial can be interpreted as a linear feedback shift register 101, such as Figure 1 L = 6-bit CRC generator polynomial g for [1] CRC6 (D)=[D 6 +D 5 +1] as illustrated by the example.

[0032] The shift register can be used to calculate the sequence s = [s0, s1, s2, ..., s K-1 ]103The corresponding sequence of L parity bits p=[p0,p1,p2,...,p L-1 ]102, the sequence of K input bits can be composed of the information bit sequence a, the extended information bit sequence a′, the restored information bit sequence Recovered CRC encoded bit sequence Recovered extended information bit sequence or the recovered extended CRC coded bit sequence supply. Figure 1 At 104 it is shown how the sequence of A=12 information bits looks like:

[0033] a = [0 1 1 0 0 1 1 1 0 1 1 0] can be converted into a sequence of L = 6 parity bits:

[0034] p = [1 0 0 1 0 1], where K = A and s = a. These parity bits can be appended to the end of the sequence a of information bits to obtain a sequence of B = 18 CRC coded bits:

[0035] b=[0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1].

[0036] Note that some applications may use the inverse of the CRC generator polynomial, which can be obtained by subtracting each of its exponents from L. For example, L = 6-bit CRC generator polynomial g CRC6 (D)=[D 6 +D 5 +1]=[D 6 +D 5 +D 0 The inverse of ] is given by: g invCRC6 (D)=[D L-6 +D L-5 +D L-0 ]=[D 6 +D+1].

[0037] The inverse generator polynomial can be represented by the inverse linear feedback shift register 201, as Figure 2 For L=6 bits, the inverse CRC generator polynomial g invCRC6 (D)=[D 6 +D+1] as illustrated.

[0038] Now see Figure 2 , shows the L=6-bit inverse CRC generator polynomial g of the source circuit invCRC6 (D)=[D 6 +D+1] is a known shift register implementation 200.

[0039] Figure 2 At 204 it is shown how the same sequence of A=12 information bits looks like:

[0040] From Figure 1 a=[0 1 1 0 0 1 1 1 0 1 1 0] can be converted into a sequence of L=6 parity bits:

[0041] p = [1 0 0 1 1 1], where K = A and s = a.

[0042] Note that these parity bits are Figure 1 Because the inverse generator polynomial ginvCRC6 (D)=[D 6 +D+1] is different from the generator polynomial g CRC6 (D)=[D 6 +D 5 +1].

[0043] CRC calculation using generator matrix

[0044] The generator matrix can be used to generate a sequence of K input bits s = [s0,s1,s2,…,s K-1 ] performs CRC calculation, the sequence of K input bits can be composed of information bit sequence a, extended information bit sequence a′, restored information bit sequence Recovered CRC encoded bit sequence Recovered extended information bit sequence or the recovered extended CRC coded bit sequence More specifically, the sequence of L parity bits p = [p0, p1, p2, ..., p L-1 ] can be generated as a function of the input bit sequence s according to p = sG, where G is the K × L generator matrix of the CRC, and the matrix multiplication is performed in GF(2). The K-th row of the generator matrix G is obtained as the sequence of parity bits produced when computing the CRC of a sequence of K input bits, where the K-th bit is set to 1 and all other bits are set to 0. For example, in the case of an L = 6-bit CRC generator polynomial, g CRC6 (D)=[D 6 +D 5 +1] is used to calculate the CRC of a sequence of K = 12 input bits, and the generator matrix is ​​given by:

[0045]

[0046] Note that in the example sequence a = [0 1 1 0 0 1 1 1 0 1 1 0] of A = 12 information bits from above, bits 2, 3, 6, 7, 8, 10, and 11 are set to 1. In this case, the sequence p = [1 0 0 1 01] of L = 6 parity bits can be obtained as the exclusive-OR of rows 2, 3, 6, 7, 8, 10, and 11 of the generator matrix.

[0047] Note that when the generator matrix is ​​applied to the recovered CRC coded bit sequence To obtain the syndrome , the generator matrix behaves as a parity check matrix. In the example sequence b = [0 1 1 0 0 1 1 10 1 1 0 1 0 0 1 0 1] of B = 18 CRC coded bits from above, bits 2, 3, 6, 7, 8, 10, 11, 13, 16, 18 are set to 1. As might be expected, the syndrome can be obtained as the exclusive-OR of rows 2, 3, 6, 7, 8, 10, 11, 13, 16, and 18 of the generator matrix for K = 18 input bits, which is given by:

[0048]

[0049] It can be observed that in the generator matrix G corresponding to a particular number K′ of input bits, the last K rows are equal to the generator matrix G corresponding to K input bits, where K ≤ K′. For example, the last 12 rows of the generator matrix G with K=18 above are equal to the generator matrix G with K=12 above.

[0050] In the case where the bits of the CRC coded sequence b are interleaved in the source, the sink may apply the corresponding deinterleaving operation to obtain the recovered CRC coded bit sequence The CRC calculation is then performed using the generator matrix G. Alternatively, the rows of the generator matrix G may be interleaved accordingly and used to encode the bit sequence based on the recovered CRC This enables, for example, early termination of polarity decoding during blind decoding in the Physical Downlink Control Channel (PDCCH) of 3GPP New Radio [1] [2].

[0051] In summary, it is known that the CRC calculation can be equivalently described in a number of ways, including generator polynomials such as: g CRC6 (D)=[D 6 +D 5 +1]; a linear feedback shift register, such as 101; or a generator matrix G, such as the example above.

[0052] Parallel processing can be used to implement CRC calculations with low latency. Here, a set of two or more parallel processors can operate under the direction of a controller to process two or more bits at a time and calculate the corresponding CRC bits within a set of registers. In some known embodiments, the processors can perform multiplication of the bits with a binary representation of a generator polynomial [3]. However, multiplication is a relatively complex operation compared to, for example, an XOR operation, and there is a need for improved CRC methods, such as when using parallel processing. Summary of the Invention

[0053] The present invention provides a method for performing low-latency CRC calculations using a process. In particular, the present invention details memory mapping and introduces a lookup table (LUT) that eliminates the need for a permutation network between the memory and the processor. Specific embodiments of the present invention are set forth in the dependent claims. These and other aspects of the present invention will become apparent and will be elucidated with reference to the embodiments described below.

[0054] In a first aspect of the present invention, a cyclic redundancy check (CRC) decoder circuit includes: an input terminal for receiving an input stream having an input bit sequence from a predefined CRC generator polynomial that encodes the input bit sequence, the input bit sequence including information bits and CRC bits; and at least one processor configured to perform a CRC decoding calculation on the input bit sequence. The at least one processor is configured to: apply an inverse processing operation of the predefined CRC generator polynomial that encodes the input bit sequence to generate a data set; calculate a CRC syndrome from the data set; and determine whether the CRC syndrome contains any 1-valued bits indicating a CRC error.

[0055] In an alternative example, the CRC decoder circuit may include a lookup table (LUT) operatively coupled to the at least one processor and including a plurality of addresses, wherein at least one of the plurality of addresses is configured to store one or more rows of a CRC generator matrix aligned with input bits of the input stream. In this manner, and because the input stream is aligned with the rows of the CRC generator matrix, a single parity bit sequence may be obtained without complex routing that would be required to enable any input bit to be combined with any row of the CRC generator matrix.

[0056] In an optional example, at least one processor can be configured to first combine the LUT data with the input stream by masking one or more rows of a CRC generator matrix stored in the LUT using one or more bits of the aligned input stream. In this way, rows of the generator matrix that do not contribute to the calculated parity bits can be eliminated.

[0057] In an optional example, the CRC decoder circuit may further include: a lookup table (LUT) operatively coupled to the at least two processors and including a plurality of addresses, wherein at least one of the plurality of addresses is configured to store two or more rows of a CRC generator matrix aligned with input bits of the input stream; wherein the at least two processors may be configured to: first combine the LUT data with the input stream to generate two or more intermediate parity bit sequences; and second combine the two or more intermediate parity bit sequences into a single parity bit sequence. In this manner, the number of steps required to complete a CRC calculation may be reduced by using parallel processing.

[0058] In an optional example, two or more rows of the CRC generator matrix stored in the LUT can be aligned with the input bit sequence by zero padding. In this way, the zero padding repositions the bits within the input bit sequence so that they align with corresponding rows of the CRC generator matrix.

[0059] In an alternative example, aligning two or more rows of a CRC generator matrix stored in the LUT may include one of: at least two processors receiving an input stream with zero padding providing a length of the input bit sequence; or wherein the input bit sequence has a first length and at least one of the two or more processors zero pads the input bit sequence. In this manner, bits of the input bit sequence may be evenly distributed among the P parallel processors, thereby allowing all of the parallel processors to operate in the same manner without requiring special independent control of any of the processors.

[0060] In an alternative example, the number of rows in the CRC generator matrix stored in the LUT is equal to or exceeds the maximum supported input bit sequence length (K max ) divided by the number of processors P. In this way, a single LUT can be used to enable CRC processing for any supported input bit sequence length, avoiding the need to use different CRC processing mechanisms for different input bit sequence lengths.

[0061] In an optional example, the CRC decoder circuit may further include a controller operatively coupled to and configured to control the at least one processor and the LUT. In this manner, the controller may coordinate the operation of the parallel processors and read rows of the CRC generator matrix from the LUT.

[0062] In an optional example, generating the two or more intermediate parity bit sequences includes performing the first combination of data a multiple of [K / P] times, where K is the length of the input bit sequence. In this manner, the number of steps required to process K bits of the input sequence is divided by the number of parallel processors, thereby minimizing the number of processing steps and maximizing processing efficiency.

[0063] In an alternative example, the second combination of the two or more intermediate parity bit sequences is performed a multiple of [log2(P)] times to generate a single parity bit sequence, where P is the number of the two or more parallel processors. In this manner, the number of steps required to process the K bits of the input sequence is reduced to the logarithm of the number of parallel processors, thereby minimizing the number of processing steps and maximizing processing efficiency.

[0064] In an alternative example, L bits in at least one of the rows of the generator matrix (G) may be padded with zero-valued bits to increase the bit sequence to a second length (L′). In this manner, the length may be adjusted to a length that is more convenient for storage in a conventional memory architecture (such as a 32-bit RAM).

[0065] In a second aspect of the invention, a communication unit is described comprising a CRC calculation circuit according to the first aspect.

[0066] In a third aspect of the present invention, a method for a cyclic redundancy check (CRC) is described. The method includes receiving an input stream having an input bit sequence from a predefined CRC generator polynomial that encodes the input bit sequence, the input bit sequence including information bits and CRC bits; and performing a CRC decoding calculation on the input bit sequence. The method also includes applying an inverse processing operation of the predefined CRC generator polynomial that encodes the input bit sequence to generate a data set; calculating a CRC syndrome from the data set; and determining whether the CRC syndrome contains any 1-valued bits that indicate a CRC error. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Further details, aspects, and embodiments of the present invention will be described by way of example only with reference to the accompanying drawings. In the accompanying drawings, like reference numerals are used to identify similar or functionally similar elements. The elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale.

[0068] Figure 1 The L=6-bit CRC generator polynomial g of the source circuit is shown CRC6 (D)=[D 6 +D 5 +1] and provides an example of how a sequence a = [0 1 1 0 0 1 1 1 0 1 1 0] of A = 12 information bits can be converted into a sequence p = [1 0 0 1 0 1] of L = 6 parity bits, where K = A and s = a.

[0069] Figure 2 The L=6-bit inverse CRC generator polynomial g of the source circuit is shown invCRC6 (D)=[D 6 +D+1] and provides an example of how a sequence a=[0 1 1 0 0 1 1 1 0 1 1 0] of A=12 information bits can be converted into a sequence p=[1 0 0 1 1 1] of L=6 parity bits, where K=A and s=a.

[0070] Figure 3 An example embodiment of the present invention is shown for the case where P=4.

[0071] Figure 4 The CRC generator polynomial g corresponding to L=6 bits in an exemplary embodiment of the present invention is shown. CRC6 (D)=[D 6 +D 5 +1] in the LUT, where: L′=8, K max =18 and P=4. Figure 4 An example is also provided of how a sequence of A=9 information bits a=[1 1 0 1 1 0 0 1 1] can be converted to a sequence of L=6 parity bits p=[0 00 1 0 1], where: K=A and s=a.

[0072] Figure 5 A flow chart illustrating the operation of a controller in an example embodiment of the present invention.

[0073] Figure 6 The L=6-bit inverse CRC generator polynomial g for the sink circuit is shown. invCRC6 (D)=[D 6 +D+1] shift register implementation for calculating the L=6-bit CRC generator polynomial g using the source circuit CRC6 (D)=[D 6 +D 5 +1] generated by the CRC encoding bit sequence. Figure 6 It also provides how a sequence of B = 18 CRC coded bits b = [0 1 1 0 0 1 1 1 01 1 0 1 0 0 1 1 1] can be converted into a sequence of L = 6 syndrome bits Example where K = B, s = b and

[0074] Figure 7 The inverse CRC generator polynomial g corresponding to L=6 bits in an exemplary embodiment of the present invention is shown. invCRC6 (D)=[D 6 +D+1] inverse generator matrix G′ in LUT, where L′=8, K max =18 and P=4. Figure 7 It also provides how a sequence of B = 15 CRC coded bits b = [1 1 0 1 1 0 0 1 1 00 0 1 0 1] can be converted into a sequence of L = 6 syndrome bits Example where K = B, s = b and

[0075] Figure 8A typical computing system that may be employed in an electronic device or wireless communication unit to perform CRC calculations according to some example embodiments of the present invention is shown.

[0076] Figure 9 A flow chart illustrating the operation of a controller in an example embodiment of the present invention, the controller operating based on the inverse generator matrix G'. DETAILED DESCRIPTION

[0077] Parallel processing of CRC calculations using the generator matrix according to the first aspect

[0078] Now refer to Figure 3 , shows an example cyclic redundancy check CRC calculation circuit 300 of the present invention for the case of P=4. The first aspect of the present invention is to solve the challenge of efficiently performing L-bit CRC calculation on a continuous sequence of input bits using a set of P parallel processors 301. Here, the number of parallel processors adopts a fixed value P, which can be selected to be any value greater than or equal to "2" during design. In contrast, the number of bits K∈[1,K max ] may vary at runtime, where the maximum input bit sequence length K max MAY BE SPECIFICATIONS IN THE APPLICABLE STANDARD. Figure 3 For the example shown where P=4, parallel processor 301 is assisted by lookup table (LUT) 302, input stream 303, register bank 304, and controller 305. In other examples, the number of parallel processors 301 may vary.

[0079] In the steps of the CRC calculation process, multiple (and in some examples, each) of the P processors 301 can calculate an AND 307 of a set of L′ bits with a mask bit, and then calculate an XOR 308 of the resulting set of L′ bits with another set of L′ bits, where L′≥L can be selected to be a value convenient for implementation, such as, for example, 8, 16, or 32 bits. Multiple of the processors can also optionally perform only one or neither of these AND 307 and XOR 308 operations during some steps. In some examples, each step can correspond to at least one clock cycle in a hardware implementation. In some examples, each processor can be a processing unit in a single instruction, multiple data (SIMD) processor. Note that instead of using an AND 307 operation, the masking operation can be implemented in an alternative arrangement by using clock or power gating to disable the transfer of a set of L′ bits when the mask bit is set to zero. Thereafter, using two or more bits of input stream 303 to mask aligned two or more rows of the CRC generator matrix stored in LUT 302 and thereby generating two or more intermediate parity bit sequences includes such clock or power gating techniques as disabling the transfer of groups of bits.

[0080] Some examples of the present invention exploit the following observation: max In the generator matrix G for K input bits, the last K rows are equal to the generator matrix G corresponding to K input bits, where K ≤ K max Therefore, it is possible to Figure 3 The continuous CRC calculation process is completed with the help of the same LUT 302, for example, the LUT 302 can be implemented in a read-only memory (ROM) or a random access memory (RAM). Here, in a dedicated hardware embodiment of the present invention, a specially configured ROM can be used to store the LUT, while in an embodiment using a general-purpose processor, a RAM can be used to store the LUT 302. More specifically, the LUT 302 can store the input bits K corresponding to the maximum supported number. max The generator matrix G of K max A line.

[0081] Now refer to Figure 4 In the exemplary embodiment of the present invention, the CRC generator polynomial g corresponding to L=6 bits is shown. CRC6 (D)=[D 6 +D 5 +1] in the LUT, where L′=8, K max =18 and P=4. Figure 4 An example is also provided of how a sequence of A=9 information bits a=[1 1 0 1 1 0 0 1 1] can be converted to a sequence of L=6 parity bits p=[0 0 0 1 0 1], where K=A and s=a.

[0082] As shown, in some examples, the L bits in each row of the generator matrix G stored in the LUT can be optionally padded with zero-valued bits 401 to increase its length to L′ bits. For example, where the rows of the generator matrix G include L=24 bits, they can be padded with 8 zero-valued bits to increase their length to L′=32 bits and allow them to be stored in a 32-bit RAM. In some examples, the padding bits can be added to the beginning of each row of the generator matrix G, while in other examples they can be added to the end of each row. Rather than applying padding to each row of the generator matrix G stored in the LUT, it is envisaged that in an alternative arrangement, padding can be added to the rows at some point during their subsequent processing after the rows have been read from the LUT.

[0083] K of the generator matrix G max The rows are stored in groups of P rows 402 in the LUT 302. max If it is not divisible by P, a group of additional mod(-Kmax , P) rows 403 in order to expand the number of its rows to a multiple of P. These additional rows can contain any arbitrary bit values. [K max Each of the [P] consecutive groups of P rows (and their padding bits) 402 may be concatenated and stored in consecutive addresses of the LUT 302, where the first group of P rows may be indexed by address 0. Here, [x] is the smallest integer greater than or equal to x.

[0084] In an alternative arrangement, the bits of each (filled) row of the generator matrix G may be reversed before they are concatenated. In an alternative arrangement, the number [K max / P] consecutive groups of P rows 402 may be stored at other addresses within the LUT 302. Figure 4 It is shown that for L′=8, K max =18 and P=4, corresponding to L=6-bit CRC generator polynomial g CRC6 (D)=[D 6 +D 5 +1] in the LUT 302.

[0085] Also refer to Figure 3 , Figure 3 The input stream 303 of LUT 302 is used to provide continuous input bit sequence s. The position of input sequence s is provided by input stream 303 in a manner aligned with the arrangement of the row of the generator matrix G in LUT 302. As will be described in detail below, this alignment avoids the need for complex routing between input stream 303, LUT 302 and processor 301. More specifically, when input stream 303 provides them, alignment is achieved by arranging the K positions in the input bit sequence s into several groups of P positions 404. In the case where K cannot be divided evenly by P, alignment can be achieved by prepending one group of mod (-K, P) zero-filling positions 405 to the input bit sequence s so that its length is extended to a multiple of P. Quantity [K / P] continuous groups of P positions 404 from (extended) input bit sequence can be provided by input stream 303 in the continuous steps of the CRC calculation process. Note that in some arrangements, [K / P] consecutive groups of P bits (404) from the (extended) input bit sequence provided by the input stream may be read from consecutive addresses of a RAM having at least [K max / P] address capacity.

[0086] The CRC calculation process of the K-bit sequence of input bit s is Figure 3 The controller 305 is used under the guidance of Figure 5The two sets of steps shown in the flowchart of are completed. A set of P intermediate sequences 406 of L parity bits can be calculated during the first set of [K / P] steps. Then during the second set of [log2(P)] steps, the P intermediate parity bit sequences 406 can be combined into a single sequence of the desired L parity bits p = [p0, p1, p2, ..., p L-1 ]102.

[0087] Now refer to Figure 5 ,refer to Figure 3 and Figure 4 In accordance with the previous discussion, flowchart 500 illustrates the operation of the controller according to an exemplary embodiment of the present invention. During the first set of [K / P] steps, the P intermediate parity bit sequences 406 are Figure 3 The register set 304 is accumulated. The register set 304 includes P registers, each of which can store L′ bits. The counter c 306 in the controller 305 is initialized 501 to a value of 0 at the beginning of the first step in a group of [K / P] steps 511, and the counter c 306 is incremented 502 at the beginning of multiple consecutive steps thereafter. In multiple (e.g., each) steps, the address ([K max / P]-[K / P]+c) reads 503 a set of P rows 402 of the generator matrix G. At the same time, a set of P bits 404 with index c from the (extended) input bit sequence is provided 504 by the input stream 303.

[0088] In each of the first set of [K / P] steps, each of the P rows of the generator matrix G provided by the LUT 302 is masked 505 by a corresponding one of the P input bits provided by the input stream 303. More specifically, each of the P processors 301 performs a corresponding one of these P masking operations by ANDing 307 each of the L′ bits in the corresponding row of the generator matrix G with the corresponding input bit. Due to the alignment between the arrangement of the P input bits in the input stream 303 and the P rows of the generator matrix G in the LUT 302, this masking can be advantageously performed without requiring complex routing between the input stream 303, the LUT 302, and the processors 301.

[0089] Note that in the first step of [K / P] steps, in this example and when c = 0, a set of P input bits 404 provided by the input stream 303 will include mod(-K,P) leading zero-padding bits 405 in the case where K is not a multiple of P. As described above, these zero-padding bits are used to achieve alignment and to mask the corresponding mod(-K,P) rows of a set of P rows 402 of the generator matrix G read from the LUT 302. In this case, these mod(-K,P) masked rows will be before the last K rows of the generator matrix G, thus advantageously ensuring that only the last K rows of the generator matrix G will have the opportunity to affect the sequence of P intermediate parity bits 406. As described above, the last K rows of the K max rows of the generator matrix G stored in the LUT 302 are equal to the generator matrix G corresponding to K input bits. In this way, even if K is not a multiple of P, the same LUT 302 storing the generator matrix G corresponding to K max input bits can be advantageously reused for all values of K.

[0090] During the first step 506 of the first set of [K / P] steps, when c = 0, the P masked rows of the generator matrix G obtained during this step are written 507 to the register bank 304 to initialize the sequence of P intermediate parity bits 406. In multiple subsequent steps, when 0 < c < [K / P], the sequence of P intermediate parity bits 406 is read 508 from the register bank 304 and provided to the P processors 301, where they are "exclusive OR"ed 308 509 with the P masked rows of the generator matrix G obtained in this step. The result is then written back 510 to the register bank 304 to accumulate the sequence of P intermediate parity bits 406. Note that the action of the counter c 306 is to read the [K / P] addresses in the LUT 302 in ascending order, consistent with the input stream 303 providing several sets of P input bits 404 in its natural order. However, in other arrangements, the input stream 303 can provide several sets of P input bits 404 in any order and can read the addresses of the LUT in the corresponding order. Figure 4 An example is provided of how a sequence a = [1 1 0 1 1 0 0 1 1] 303 of A = 9 information bits can be converted into a set of P = 4 intermediate parity bit sequences 4​​During the second set of [log2(P)] steps 514, the register bank 304 is used to combine the P intermediate parity bit sequences 406 into a single desired parity bit sequence 102. The counter c 306 is initialized 512 to a value of 0 at the beginning of the first step in the set of [log2(P)] steps, and the counter c 306 is incremented 513 at the beginning of successive steps thereafter. In the plurality of steps where 0 ≤ c < [log2(P)], the first P / 2 counters in the bank 304 of P registers are initialized 512 to a value of 0. c Register read 515 a group of P / 2 c A set of P / 2 c The intermediate parity bit sequence is then decomposed into two subsets, each consisting of P / 2 c+1 Then P / 2 c+1 Each intermediate parity bit sequence in the first subset of intermediate parity bit sequences is associated with a sequence from P / 2 c+1 The corresponding intermediate parity check bit sequences of the second subset of the intermediate parity check bit sequences are "exclusively ORed" 308 516. The resulting set of P / 2 c+1 The XORed 308 intermediate parity bit sequence is then written 517 to the first P / 2 of the P register groups 304. c+1 registers.

[0092] After the last step in the second set of [log2(P)] steps is completed, the P intermediate parity bit sequences will be combined into a single desired parity bit sequence, which is stored in the first register in the set of P registers 304. The parity bit sequence p = [p0, p1, p2, ..., p] can then be extracted 518 from the L' bits of the register by removing the zero-valued padding bits. L-1 Note that in the method described herein, P intermediate parity bit sequences are successively grouped into the first register of the P registers in the register bank 304.

[0093] In an alternative arrangement, the P intermediate parity bit sequences may be sequentially combined into any of the P registers in register bank 304. For example and referring back to Figure 4 , provides an example of how a set of P=4 intermediate parity bit sequences 406 can be combined into a sequence of L=6 parity bits p=[0 0 0 1 0 1] 102, where K=A and s=a.

[0094] Syndrome calculation using inverse generator matrix and associated parallel processing in the first aspect of the present invention

[0095] Now refer to Figure 6, showing the L=6-bit inverse CRC generator polynomial g for the sink circuit invCRC6 (D)=[D 6 +D+1] shift register implementation 600 for calculating an L=6-bit CRC generator polynomial g using a source circuit CRC6 (D)=[D 6 +D 5 +1] generated by the CRC encoding bit sequence. Figure 6 It also provides how a sequence of B = 18 CRC coded bits b = [0 1 1 00 1 1 1 0 1 1 0 1 0 0 1 1 1] can be converted into a sequence of L = 6 syndrome bits Example where K = B, s = b and

[0096] In the sink, the inverse of the CRC generator polynomial can be used to perform the recovery of the CRC encoded bit sequence. The syndrome CRC calculation, even if the CRC calculation is performed using the regular CRC generator polynomial in the source. More specifically, the shift register representation of the inverse CRC generator polynomial can be used as the sequence The sequence of L syndrome bits is calculated as a function of all B=A+L recovered CRC coded bits in However, when using the shift register representation of the inverse CRC generator polynomial to compute the syndrome The sequence must be processed in reverse order when If the syndrome is not equal to a sequence of L zero-valued bits, an error has been detected. Figure 6 is shown as a sequence of L parity bits 102, where the inverse CRC generator polynomial g invCRC6 (D)=[D 6 +D+1] is used to calculate Figure 1 The error-free B = 18-bit CRC code sequence b and the L = 6-bit syndrome Where: K=B, 102 and s=reverse(b) is obtained by reversing the order of the bits in b 103. Note that the syndrome Including L=6 zero-valued bits confirms that b is error-free.

[0097] Alternatively, a K×L generator matrix G of the inverse CRC generator polynomial may be used to perform the sequence of B recovered CRC coded bits The L-bit syndrome CRC calculation, where: K = B. Here, the order of the rows in the generator matrix G can be reversed to obtain the inverse generator matrix G'. This advantageously allows the sequence to be processed in forward order rather than in reverse order. More specifically, the syndrome can be calculated as: In the example sequence b = [0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1] of B = 18 CRC coded bits from above, bits 2, 3, 6, 7, 8, 10, 11, 13, 16, and 18 are set to 1. As might be expected, the L = 6-bit syndrome Can be used as the inverse CRC generator polynomial g with K=18 invCRC6 (D)=[D 6 +D+1] is obtained by the exclusive OR of the 2nd, 3rd, 6th, 7th, 8th, 10th, 11th, 13th, 16th and 18th rows of the K×L inverse generator matrix of [D+D+1], which is given by the following formula:

[0098]

[0099] It can be observed that in the inverse generator matrix G′ corresponding to a specific number K′ of input bits, the first K rows are equal to the inverse generator matrix G′ corresponding to K input bits, where K ≤ K′. For example, the first 12 rows of the generator matrix G′ for K=18 above are equal to the inverse generator matrix G′ for K=12. This is in contrast to the conventional generator matrix G corresponding to a specific number K′ of input bits, in which the last K rows are equal to the generator matrix G corresponding to K input bits, where K ≤ K′.

[0100] In some examples of the present invention, this property of the inverse generator matrix G′ can be used to adapt Figure 3 The scheme makes it possible to recover the CRC coded bit sequence No leading zero-valued padding bits 405 are required when used as input bit sequence s. This advantageously allows the CRC encoded bit sequence to be stored in a more convenient format. If the CRC check succeeds, the CRC code bit sequence can be directly output As mentioned above, Figure 3 The LUT 302 stores the input bits corresponding to the maximum supported number K max The inverse generator matrix G′ of K max A row, and Figure 3 The input stream 303 provides K bits of the input bit sequence s. However, when K max When it is not divisible by the number of parallel processors P, a set of mod(-K max,P) arbitrary rows 403, but append these additional rows 703 to the bottom of the inverse generator matrix G′, as Figure 7 shown.

[0101] Now refer to Figure 7 , according to an exemplary embodiment of the present invention, an L=6-bit inverse CRC generator polynomial g is shown. invCRC6 (D)=[D 6 +D+1] inverse generator matrix G′700 is stored in the LUT, where L′=8, K max =18 and P=4. Figure 7 It also provides how a sequence of B = 15 CRC coded bits b = [1 1 0 1 1 0 0 1 1 0 0 0 1 0 1] can be converted into a sequence of L = 6 syndrome bits Example where K = B, s = b and

[0102] like Figure 7 As shown, when K is not divisible by the number of parallel processors P, instead of prepending a group of zero-valued padding bits 405 modulo (-K, P) to the beginning of the input bit sequence s, these additional padding bits 705 are appended to the end of the input bit sequence s. As described above, multiple consecutive groups of P rows 702 of the (extended) inverse generator matrix are stored at consecutive addresses in the LUT 302, where the first group of P rows can be indexed by address 0. Similarly, in consecutive steps of the CRC calculation, the input stream 303 provides multiple consecutive groups of P bits 704 of the (extended) input bit sequence.

[0103] Figure 7 It is shown that for L′=8, K max =18 and P=4 corresponds to L=6 bits inverse CRC generator polynomial g invCRC6 (D)=[D 6 +D+1] inverse generator matrix G′ in LUT 302. As described above, counter c 306 is initialized to a value of 0 at the beginning of the first step in a set of [K / P] steps, and the counter c 306 is incremented at the beginning of multiple (e.g., each) consecutive steps thereafter. However, instead of starting from the address ([K max / P]-[K / P]+c) reads a set of P rows 402 of the generator matrix, but reads a set of P rows 702 of the inverse generator matrix G′ from address c. At the same time, a set of P bits 704 with index c from the (extended) input bit sequence is provided by the input stream 303, as described above. Apart from these differences, Figure 7 The operation of the scheme can also be carried out as described above.

[0104] More specifically, operations such as Figure 9 As shown in the flowchart, Figure 5 The only difference is the calculation 903 of the addresses for reading a set of P rows 402 of the generator matrix from the LUT.

[0105] therefore, Figure 7 This provides an example of how a sequence of B=15 CRC coded bits a=[1 1 0 1 1 0 0 1 1 0 0 0 1 01] 303 can be converted into a set of P=4 intermediate parity check bit sequences 706 (which are then combined into a sequence of L=6 syndrome bits). ), where K = B, s = b and

[0106] Figure 9 A flow chart illustrating the operation of a controller in an example embodiment of the present invention, the controller operating based on the inverse generator matrix G'.

[0107] application

[0108] Now refer to Figure 8 , shows a typical computing system 800 that can be used to implement CRC calculations according to some example embodiments of the present invention. This type of computing system can be used in a wireless communication unit. Those skilled in the relevant art will also recognize how to use other computer systems or architectures to implement the present invention. Computing system 800 can represent, for example, a desktop, laptop or notebook computer, a handheld computing device (PDA, mobile phone, palmtop, etc.), a mainframe, a server, a client, or any other type of dedicated or general-purpose computing device that may be desired or applicable for a given application or environment. Computing system 800 may include at least one processor, such as processor 804. Processor 804 can be implemented using a general-purpose or dedicated processing engine (such as, for example, a microprocessor, microcontroller or other control logic). In this example, processor 804 is connected to bus 802 or other communication medium. In some examples, computing system 800 can be a non-transitory tangible computer program product including executable code stored therein for implementing CRC calculations.

[0109] The computing system 800 may also include a main memory 808, such as a random access memory (RAM) or other dynamic storage, for storing information and instructions to be executed by the processor 804. The main memory 808 may also be used to store temporary variables or other intermediate information during execution of instructions to be executed by the processor 804. The computing system 800 may also include a read-only memory (ROM) or other static storage device coupled to the bus 802 for storing static information and instructions for the processor 804.

[0110] The computing system 800 may also include an information storage system 810, which may include, for example, a media drive 812 and a removable storage interface 820. The media drive 812 may include a drive or other mechanism that supports fixed or removable storage media, such as a hard drive, a floppy disk drive, a tape drive, an optical drive, a compact disk (CD) or digital video drive (DVD) read or write drive (R or RW), or other removable or fixed media drive. The storage medium 818 may include, for example, a hard drive, a floppy disk, a tape, an optical disk, a CD or DVD, or other fixed or removable media that is read and written by the media drive 812. As shown in these examples, the storage medium 818 may include a computer-readable storage medium having specific computer software or data stored therein.

[0111] In alternative embodiments, the information storage system 810 may include other similar components for allowing computer programs or other instructions or data to be loaded into the computing system 800. Such components may include, for example, removable storage units 822 and interfaces 820, such as a program cartridge and cartridge interface, removable memory (e.g., a flash memory or other removable memory module) and memory slots, and other removable storage units 822 and interfaces 820 that allow software and data to be transferred from the removable storage unit 818 to the computing system 800.

[0112] The computing system 800 may also include a communication interface 824. The communication interface 824 can be used to allow software and data to be transferred between the computing system 800 and external devices. Examples of the communication interface 824 may include a modem, a network interface (such as an Ethernet or other NIC card), a communication port (such as a Universal Serial Bus (USB) port), a PCMCIA slot and card, and the like. The software and data transferred via the communication interface 824 are in the form of signals, which may be electronic, electromagnetic, optical, or other signals that can be received by the communication interface 824. These signals are provided to the communication interface 824 via a channel 828. The channel 828 may carry signals and may be implemented using a wireless medium, a wire or cable, an optical fiber, or other communication medium. Some examples of a channel include a telephone line, a cellular phone link, an RF link, a network interface, a local or wide area network, and other communication channels.

[0113] In this document, the terms "computer program product," "computer-readable medium," and the like may be generally used to refer to media, such as, for example, memory 808, storage device 818, or storage unit 822. These and other forms of computer-readable media may store at least one instruction for use by processor 804 to cause the processor to perform a specified operation. Such instructions, often referred to as "computer program code" (which may be grouped in the form of a computer program or other grouping), when executed, enable computing system 800 to perform the functions of embodiments of the present invention. Note that the code may directly cause the processor to perform the specified operation, be compiled to perform the specified operation, and / or be combined with other software, hardware, and / or firmware elements (e.g., libraries for performing standard functions) to perform the specified operation.

[0114] In embodiments using software-implemented elements, the software may be stored on a computer-readable medium and loaded into computing system 800 using, for example, removable storage drive 822, drive 812, or communications interface 824. The control logic (in this example, software instructions or computer program code), when executed by processor 804, causes processor 804 to perform the functions of the present invention as described herein.

[0115] Now refer to Figure 9 , in the second aspect of the invention and with reference to Figure 3 and Figure 4 The previous discussion does not necessarily use parallel processing, but the flowchart 900 shows Figure 7 During the first set of [K / P] steps, the P intermediate parity bit sequences 706 are Figure 3 304. The register set 304 includes P registers, each of which can store L′ bits. A counter c 306 within the controller 305 is initialized 901 to a value of “0” at the start of the first step in a set of [K / P] steps 911, and the counter c 306 is incremented 902 at the start of a plurality of subsequent steps. In a plurality of (e.g., each) step, a set of P rows 702 of the generator matrix G is read 903 from the address (c) of the LUT 302. Simultaneously, a set of P bits 704 with index c from the (extended) input bit sequence is provided 904 by the input stream 303.

[0116] In each of the first set of [K / P] steps, each of the P rows of the generator matrix G provided by the LUT 302 is masked 905 by a corresponding one of the P input bits provided by the input stream 303. More specifically, each of the P processors 301 performs a corresponding one of these P masking operations by ANDing 307 each of the L′ bits in the corresponding row of the generator matrix G with the corresponding input bit. Due to the alignment between the arrangement of the P input bits in the input stream 303 and the P rows of the generator matrix G in the LUT 302, this masking can be advantageously performed without requiring complex routing between the input stream 303, the LUT 302, and the processors 301.

[0117] Note that in the first of the [K / P] steps, in this example and when c=0, the set of P input bits 704 provided by the input stream 303 will include mod(-K,P) leading zero-valued padding bits 705 if K is not a multiple of P. As described above, these zero-valued padding bits are used to achieve alignment and to mask the corresponding mod(-K,P) rows of the set of P rows 702 from the generator matrix G read from the LUT 302. In this case, these mod(-K,P) masked rows will precede the last K rows of the generator matrix G, thereby advantageously ensuring that only the last K rows of the generator matrix G will have the opportunity to affect the P intermediate parity bit sequences 706. As described above, the K rows of the generator matrix G stored in the LUT 302 max The last K rows of P are equal to the generator matrix G corresponding to K input bits. In this way, even if K is not a multiple of P, the storage corresponding to K max The same LUT 302 of the generator matrix G for 100 input bits can also advantageously be reused for all values ​​of K.

[0118] During the first step 906 of the first set of [K / P] steps, when c = 0, the P masked rows of the generator matrix G obtained during this step are written 907 to the register bank 304 to initialize the P intermediate parity bit sequences 706. In a plurality of subsequent steps, when 0 < c < [K / P], the P intermediate parity bit sequences 706 are read 908 from the register bank 304 and provided to the P processors 301, where they are "exclusive-ored" 308 909 with the P masked rows of the generator matrix G obtained in this step. The result is then written back 910 to the register bank 304 to accumulate the P intermediate parity bit sequences 706. Note that the action of the counter c 306 is to read the [K / P] addresses in the LUT 302 in ascending order, consistent with the input stream 303 providing several groups of P input bits 704 in their natural order. However, in other arrangements, the input stream 303 can provide several groups of P input bits 704 in any order and the addresses of the LUT can be read in the corresponding order. Figure 7 An example of how a sequence a = [1 1 0 1 1 0 0 1 1 0 0 0 1 0 1] 303 of B = 15 CRC encoded bits can be converted into a set of P = 4 intermediate parity bit sequences 706 is provided.

[0119] During the second set of [log2(P)] steps 914, the register bank 304 is used to combine the P intermediate parity bit sequences 706 into a single desired parity bit sequence 102. The counter c 306 is initialized 912 to a value of 0 at the start of the first step of a set of [log2(P)] steps, and the counter c 306 is incremented 913 at the start of each subsequent consecutive step. In a plurality of steps when 0 ≤ c < [log2(P)], a set of P / 2 c intermediate parity bit sequences are read 915 from the first P / 2 c registers of the P registers of the register bank 304. A set of P / 2 c intermediate parity bit sequences are then split into two subsets, each subset including P / 2 c+1 intermediate parity bit sequences. Then each intermediate parity bit sequence in the first subset of the P / 2 c+1 intermediate parity bit sequences is "exclusive-ored" �08 916 with the corresponding intermediate parity bit sequence from the second subset of the P / 2 c+1 [[ID=1⑦]]intermediate parity bit sequences. The resulting set of P / 2 c+1 "exclusive-ored" 308 intermediate parity bit sequences is then written 917 to the first set of P / 2 c+1 registers of the P registers of the register bank 304.

[0120] After the last step in the second set of [log2(P)] steps is completed, the P intermediate parity bit sequences will be combined into a single desired parity bit sequence, which is stored in the first register in the set of P registers 304. The parity bit sequence p = [p0, p1, p2, ..., p] can then be extracted 918 from the L' bits of the register by removing the zero-valued padding bits. L-1 Note that in the method described herein, P intermediate parity bit sequences are successively grouped into the first register of the P registers in the register bank 304.

[0121] In an alternative arrangement, the P intermediate parity bit sequences may be sequentially combined into any of the P registers in register bank 304. For example and referring back to Figure 7 , provides a set of P = 4 intermediate parity check bit sequences 706 can be combined into a sequence of L = 6 syndrome bits Example where K = B, s = b and

[0122] In the foregoing specification, the invention has been described with reference to specific examples of its embodiments. However, it will be apparent that various modifications and changes may be made therein without departing from the scope of the invention as set forth in the appended claims, and the claims are not limited to the specific examples described above.

[0123] As discussed herein, the connection can be any type of connection suitable for transmitting signals from or to a corresponding node, unit, or device, for example, via an intermediate device. Therefore, unless otherwise implied or indicated, the connection can be, for example, a direct connection or an indirect connection. Connections can be shown or described with reference to a single connection, multiple connections, unidirectional connections, or bidirectional connections. However, different embodiments can change the implementation of the connection. For example, a separate unidirectional connection can be used instead of a bidirectional connection, or vice versa. In addition, multiple connections can be replaced by a single connection that transmits multiple signals in serial or time-multiplexed fashion. Similarly, a single connection carrying multiple signals can be separated into various different connections that carry subsets of these signals. Therefore, there are multiple options for transmitting signals.

[0124] Those skilled in the art will recognize that the architectures described herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality.

[0125] Any arrangement of components that achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Thus, any two components herein combined to achieve a particular functionality may be considered to be "associated" with each other such that the desired functionality is achieved, regardless of architecture or intermediary components. Likewise, any two components so associated may also be considered to be "operably connected" or "operably coupled" to each other such that the desired functionality is achieved.

[0126] Furthermore, those skilled in the art will recognize that the boundaries between the above-described operations are illustrative only. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may be changed in various other embodiments.

[0127] The present invention is described herein with reference to an integrated circuit device comprising, for example, a microprocessor configured to perform a function of CRC calculation. However, it should be understood that the present invention is not limited to such integrated circuit devices and can be equally applied to integrated circuit devices comprising the operating functions of any alternative type. Examples of such integrated circuit devices comprising the operating functions of alternative types may include, as examples only, application specific integrated circuit (ASIC) devices, field programmable gate array (FPGA) devices, or integration with other components, etc. In addition, because the illustrated embodiments of the present invention can be implemented using electronic components and circuits known to those skilled in the art for the most part, for the understanding and appreciation of the basic concepts of the present invention, and in order not to confuse or disperse the teachings of the present invention, details are not explained to any greater extent than is considered necessary. Alternatively, circuit and / or component examples may be implemented as any number of separate integrated circuits or separate devices interconnected to each other in a suitable manner.

[0128] Furthermore, for example, the examples or portions thereof may be implemented as physical circuitry or as soft or code representations of logical representations convertible into physical circuitry, such as in any appropriate type of hardware description language.

[0129] Furthermore, the present invention is not limited to physical devices or units implemented in non-programmable hardware, but may be applied to programmable devices or units capable of performing the desired CRC calculation by operating according to suitable program code, such as minicomputers, personal computers, notepads, personal digital assistants, electronic games, automobiles and other embedded systems, cell phones and various other wireless devices, which are generally referred to in this application as "computer systems."

[0130] However, other modifications, changes, and substitutions are possible. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0131] In the claims, any reference numerals placed between brackets should not be interpreted as limiting the claims. The word "comprising" does not exclude the presence of other elements or steps other than those listed in the claim. In addition, as used herein, the term "one" or "an" is defined as at least one rather than one. In addition, the use of introductory phrases such as "at least one" and "at least one" in the claims should not be interpreted as implying that the introduction of another claim element by the indefinite article "one" or "an" will limit any particular claim containing such introduced claim elements to an invention containing only one such element, even if the same claim includes the introductory phrase "at least one" or "at least one" and an indefinite article (such as, "one" or "an"). The same applies to the use of definite articles. Unless otherwise stated, terms such as "first" and "second" are used to make arbitrary distinctions between the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements. The simple fact of listing certain measures in mutually different claims does not indicate that the combination of these measures cannot be used to exert an advantage.

[0132] References

[0133] [1] “3rd Generation Partnership Project; Technical Specification Group Radio Access Network; NR; Multiplexing and channel coding (Release 15)”, 3GPP TS 38.212 V15.2.0, June 2018.

[0134] [2] Nokia, Alcatel-Lucent Shanghai Bell, “Rl-1703497 Details of CRC distribution of polar design”, 3GPP TSG-RAN WG1 Meeting #88, Athens, Greece, February 2017.

[0135] [3] Intel, “Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction”, December 2009.

Claims

1. A cyclic redundancy check (CRC) decoder circuit, comprising: an input terminal for receiving an input stream having a K-bit input bit sequence s from a predefined CRC generator polynomial encoding the K-bit input bit sequence, the input bit sequence s comprising information bits and CRC bits; and P processors of the at least one processor are configured to perform a CRC decoding calculation of the K-bit input bit sequence s; a lookup table LUT operatively coupled to the at least one processor and comprising a plurality of addresses, The at least one processor is configured to: generating a data set using the inverse of the predefined CRC generator polynomial that encodes the K-bit input bit sequence s; Calculating a CRC syndrome from the data set; and determining whether the CRC syndrome contains any 1-valued bits indicating a CRC error, wherein at least one of the plurality of addresses is configured as one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial, wherein a set of mod (-K, P) zero-valued padding bits is appended to the end of the K-bit input bit sequence s, and wherein the order of the rows of the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

2. The CRC decoder circuit of claim 1 , wherein: At least one processor is configured to combine the LUT data with the input stream by first masking the one or more rows of the CRC generator matrix stored in the LUT using one or more bits of the aligned input stream.

3. The CRC decoder circuit of claim 1 , wherein: The number of rows in the CRC generator matrix stored in the LUT is equal to or exceeds the maximum supported input bit sequence length (K max ) divided by the number P of the one or more processors.

4. The CRC decoder circuit of claim 1 , further comprising: A controller is operably coupled and configured to control the at least one processor and the LUT.

5. The CRC decoder circuit of claim 1 , wherein: The number of bits in at least one of the rows of the generator matrix (G) is a first length (L) and is padded with zero-valued bits to increase the number of bits in the at least one row to a second length (L').

6. The CRC decoder circuit of claim 2, wherein: The lookup table LUT is operatively coupled to at least two processors and includes a plurality of addresses, wherein the number of processors is two or more, and wherein the number p of rows stored in each address of the LUT is two or more; and Wherein, the at least two processors are configured to: first combining the LUT data with the input stream to generate two or more intermediate parity bit sequences; and The two or more intermediate parity bit sequences are then combined into a single parity bit sequence.

7. The CRC decoder circuit of claim 3, wherein: The two or more rows of the CRC generator matrix stored in each address of the LUT are aligned by the set of mod (-K, P) zero-valued padding bits appended to the K-bit input bit sequence s.

8. The CRC decoder circuit of claim 7, wherein: Aligning with the two or more rows of the CRC generator matrix stored in the LUT includes one of: The at least two processors receive the input stream providing a K-bit input bit sequence of length K+mod(-K,P) with zero padding; The K-bit input bit sequence has a first length K, and at least one of the two or more processors appends the mod (-K, P) zero-valued padding bits to the end of the K-bit input bit sequence.

9. The CRC decoder circuit of claim 6, wherein: Generating two or more intermediate parity bit sequences includes performing a first combination of data a multiple of [K / P] times, where K is the length of the K-bit input bit sequence.

10. The CRC decoder circuit of claim 6, wherein: The second combination of the two or more intermediate parity bit sequences is performed a multiple of [log2(P)] times to generate a single parity bit sequence, where P is the number of the two or more parallel processors.

11. A communication unit comprising a cyclic redundancy check (CRC) decoder circuit, the CRC decoder circuit comprising: an input terminal for receiving an input stream having a K-bit input bit sequence s from a predefined CRC generator polynomial encoding the K-bit input bit sequence, the input bit sequence s comprising information bits and CRC bits; and P processors of the at least one processor are configured to perform a CRC decoding calculation of the K-bit input bit sequence s; a lookup table LUT operatively coupled to the at least one processor and comprising a plurality of addresses, The at least one processor is configured to: generating a data set using the inverse of the predefined CRC generator polynomial that encodes the K-bit input bit sequence s; Calculating a CRC syndrome from the data set; and determining whether the CRC syndrome contains any 1-valued bits indicating a CRC error, wherein at least one of the plurality of addresses is configured as one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial, wherein a set of mod (-K, P) zero-valued padding bits is appended to the end of the K-bit input bit sequence s, and wherein the order of the rows of the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

12. The communication unit according to claim 11, wherein At least one processor is configured to combine the LUT data with the input stream by first masking the one or more rows of the CRC generator matrix stored in the LUT using one or more bits of the aligned input stream.

13. The communication unit according to claim 11, wherein The number of rows in the CRC generator matrix stored in the LUT is equal to or exceeds the maximum supported input bit sequence length (K max ) divided by the number P of the one or more processors.

14. The communication unit according to claim 11, further comprising: A controller is operably coupled and configured to control the at least one processor and the LUT.

15. The communication unit according to claim 11, wherein The number of bits in at least one of the rows of the generator matrix (G) is a first length (L) and is padded with zero-valued bits to increase the number of bits in the at least one row to a second length (L'). The communication unit according to claim 12 , wherein: The lookup table LUT is operatively coupled to at least two processors and includes a plurality of addresses, wherein the number of processors is two or more, and wherein the number p of rows stored in each address of the LUT is two or more; and Wherein, the at least two processors are configured to: first combining the LUT data with the input stream to generate two or more intermediate parity bit sequences; and The two or more intermediate parity bit sequences are then combined into a single parity bit sequence.

17. A method for a cyclic redundancy check (CRC), comprising: receiving an input stream having a K-bit input bit sequence from a predefined CRC generator polynomial that encodes the K-bit input bit sequence s, the K-bit input bit sequence s comprising information bits and CRC bits; and Performing a CRC decoding calculation of the K-bit input bit sequence s by P processors of at least one processor; generating a data set using the inverse of the predefined CRC generator polynomial that encodes the K-bit input bit sequence s; Calculating a CRC syndrome from the data set; as well as determining whether the CRC syndrome contains any 1-valued bits indicating a CRC error, wherein a lookup table LUT operatively coupled to the at least one processor comprises a plurality of addresses, wherein at least one of the plurality of addresses is configured as one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial, wherein a set of mod (-K, P) zero-valued padding bits is appended to the end of the K-bit input bit sequence s, and wherein the order of the rows of the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

18. The method for cyclic redundancy check (CRC) according to claim 17, further comprising: The LUT data is first combined with the input stream by masking the one or more rows of the CRC generator matrix stored in the LUT using one or more bits of the aligned input stream.

19. The method for cyclic redundancy check (CRC) according to claim 17, wherein: The number of rows in the CRC generator matrix stored in the LUT is equal to or exceeds the maximum supported input bit sequence length (K max ) divided by the number P of the one or more processors.

20. The method for cyclic redundancy check (CRC) according to claim 17, wherein: The number of bits in at least one of the rows of the generator matrix (G) is a first length (L), and the method further includes: filling the number of bits in at least one of the rows of the generator matrix (G) of the first length (L) with zero-value bits to increase the number of bits in the at least one row to a second length (L').

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