Display device

Abstract

The object of the present invention is to provide a display device that can reduce parasitic capacitance between wirings, a display device with high display quality, and a display device that can reduce power consumption. The display device of the present invention includes: a signal line; a scan line; a first electrode; a second electrode; a third electrode; a first pixel electrode; a second pixel electrode; and a semiconductor film, wherein the signal line intersects the scan line, the first electrode is electrically connected to the signal line, the first electrode includes an area overlapping the scan line, the second electrode is opposite to the first electrode, the third electrode is opposite to the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is arranged between the scan line and the first electrode to the third electrode.

Description

[0001] This application is a divisional application of the invention patent application with application number 201680009371.3, application date February 3, 2016, and name “Display Device”. Technical Field

[0002] One embodiment of the present invention relates to a display device. Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, more specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, there can be cited semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, camera devices, driving methods of these devices or manufacturing methods of these devices. Background Art

[0003] In recent years, as a liquid crystal display device with improved viewing angle characteristics and display quality, a vertically aligned (VA) type liquid crystal display device has been proposed. In addition, as a VA type liquid crystal display device, a multi-domain structure liquid crystal display device has been proposed, in which a plurality of pixel electrodes and a transistor connected to each pixel electrode and controlling the potential of the pixel electrode are included in one pixel. By providing a plurality of pixel electrodes in one pixel, the orientation of the liquid crystal can be made different for each pixel electrode, and therefore, the viewing angle of the multi-domain structure liquid crystal display device can be larger than that of the existing VA type liquid crystal display device (see patent document 1).

[0004] In addition, the screen size of liquid crystal display devices tends to be larger, such as 60 inches or more on the diagonal, and further, development is being carried out with the goal of screen sizes of 120 inches or more on the diagonal. In addition, the screen also tends to be high-definition, such as full high-definition quality (FHD, 1920×1080) or 4K quality (3840×2160), and the development of so-called 8K high-resolution liquid crystal display devices with a pixel count of 7680×4320 is currently being accelerated.

[0005] In addition, in order to reduce afterimages and improve display quality, high-speed driving that doubles the driving speed (also called double-speed driving) is being developed, and further, research on high-speed driving that triples the driving speed is also being conducted. In addition, in order to realize a liquid crystal display device for three-dimensional (3D) display, it is necessary to alternately display images for the right eye and images for the left eye, so that the liquid crystal display device needs to be operated at a speed of more than double the speed.

[0006] [References]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2006-317867 Summary of the invention

[0009] However, as liquid crystal display devices become larger and higher definition, the number of pixels required increases significantly, and the writing time per pixel becomes shorter. As a result, transistors that control the potential of pixel electrodes are required to operate at high speed and have high on-state current.

[0010] In addition, the increase in parasitic capacitance generated between wirings causes a delay in signal transmission to the end of the signal line, which may result in a decrease in display quality such as display unevenness or poor grayscale, and an increase in power consumption.

[0011] Therefore, one of the purposes of one embodiment of the present invention is to provide a display device capable of reducing parasitic capacitance between wirings. In addition, one of the purposes of one embodiment of the present invention is to provide a display device with high display quality. In addition, one of the purposes of one embodiment of the present invention is to provide a display device capable of reducing power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device or a novel display device, etc.

[0012] Note that the recording of these purposes does not prevent the existence of other purposes. One mode of the present invention does not necessarily have to achieve all of the above purposes. In addition, the description of the specification, drawings, claims, etc. clearly contains purposes other than the above purposes, and the purposes other than the above purposes can be obtained from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a display device, which includes a signal line, a scanning line intersecting the signal line, a first electrode electrically connected to the signal line, a second electrode opposite to the first electrode, a third electrode opposite to the first electrode, a first pixel electrode electrically connected to the second electrode, a second pixel electrode electrically connected to the third electrode, and a semiconductor film in contact with the first electrode to the third electrode and arranged between the scanning line and the first electrode to the third electrode, wherein the first electrode includes an area overlapping with the scanning line.

[0014] In addition, one embodiment of the present invention is the above-mentioned display device, which includes a gate insulating film between a scanning line and a semiconductor film, wherein a first transistor is constituted by the scanning line, the gate insulating film, the semiconductor film, the first electrode and the second electrode, and a second transistor is constituted by the scanning line, the gate insulating film, the semiconductor film, the first electrode and the third electrode.

[0015] In addition, one embodiment of the present invention is the above-mentioned display device, which includes a first capacitor wiring electrically connected to a first pixel electrode and a second capacitor wiring electrically connected to a second pixel electrode, wherein the signal line includes an overlapping area between the first pixel electrode and the second pixel electrode, and the signal line does not include an overlapping area with the first capacitor wiring and the second capacitor wiring.

[0016] In addition, one embodiment of the present invention is the above-mentioned display device, wherein the first electrode is provided between the second electrode and the third electrode in the top surface shape.

[0017] In addition, one embodiment of the present invention is the above-mentioned display device, wherein the semiconductor film includes an oxide containing In, M (M is aluminum, gallium, yttrium, or tin), and Zn.

[0018] In addition, one embodiment of the present invention is the above-mentioned display device, wherein the semiconductor film includes a first semiconductor film and a second semiconductor film including a region overlapping with the first semiconductor film, and the first semiconductor film contains an oxide having a larger atomic number ratio of In relative to the atomic number ratio of M than the second semiconductor film.

[0019] Thus, by adopting one mode of the present invention, the parasitic capacitance between the wirings of the display device can be reduced. In addition, by adopting one mode of the present invention, the display quality of the display device can be improved. In addition, by adopting one mode of the present invention, the power consumption of the display device can be reduced. In addition, by adopting one mode of the present invention, a novel semiconductor device or a novel display device can be provided. Note that the description of these effects does not prevent the existence of other effects.

[0020] In addition, one embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects are obvious from the description of the specification, drawings, claims, etc., and effects other than the above effects can be extracted from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1C It is a top view and circuit diagram of a pixel;

[0022] Figure 2A and Figure 2B is a top view and a circuit diagram of a pixel illustrating one embodiment of the present invention;

[0023] Figure 3A and Figure 3B It is a top view and circuit diagram of a pixel;

[0024] Figure 4 is a cross-sectional view of a pixel in one manner;

[0025] Figure 5 It is a top view of one way of looking at pixels;

[0026] Figure 6 It is a top view of one way of looking at pixels;

[0027] 7A to 7D It is a top view and circuit diagram of a pixel;

[0028] Fig. 8A and Figure 8B It is a top view and circuit diagram of a pixel;

[0029] Fig. 9 is a cross-sectional view of one way of looking at a pixel;

[0030] FIG. 10A to FIG. 10C is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0031] FIG. 11A to FIG. 11C is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0032] FIG. 12A to FIG. 12C is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0033] Fig.13A and Fig. 13B is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0034] FIG. 14A to FIG. 14C A cross-sectional view showing an example of a manufacturing process of a semiconductor device, and a plan view and a cross-sectional view showing one embodiment of a semiconductor device;

[0035] FIG. 15A to FIG. 15C is a cross-sectional view showing one aspect of a semiconductor device;

[0036] Fig.16A and Fig. 16B A top view and a cross-sectional view showing one embodiment of a semiconductor device;

[0037] 17A to 17C is a cross-sectional view showing one aspect of a semiconductor device;

[0038] Fig.18 is a diagram illustrating the band structure;

[0039] 19A to 19D is a Cs-corrected high-resolution TEM image of a cross section of CAAC-OS and a schematic cross-sectional view of CAAC-OS;

[0040] FIG. 20A to FIG. 20D is a Cs-corrected high-resolution TEM image in the plane of CAAC-OS;

[0041] FIG. 21A to FIG. 21C is a diagram illustrating structural analysis of CAAC-OS and a single crystal oxide semiconductor obtained by XRD;

[0042] Fig. 22 A and Fig. 22 B is a diagram showing an electron diffraction pattern of CAAC-OS;

[0043] Fig.23 is a diagram showing changes in the crystal part of In-Ga-Zn oxide caused by electron irradiation;

[0044] Fig.24 is a top view showing one aspect of a display device;

[0045] Fig.25 is a cross-sectional view showing one embodiment of a display device;

[0046] Fig.26 is a cross-sectional view showing one embodiment of a display device;

[0047] Fig. 27 is a diagram illustrating a display module;

[0048] FIG. 28A to FIG. 28G It is a diagram for explaining an electronic device. DETAILED DESCRIPTION

[0049] Below, the embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the following description. A person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that when describing the structure of the present invention with reference to the accompanying drawings, the same reference numerals are used in common in different drawings to represent the same constituent elements.

[0050] In addition, the terms such as first, second, third to nth (n is a natural number) used in the present specification are used to avoid confusion among constituent elements and are not used to limit the number.

[0051] In addition, depending on the situation or condition, the words "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced by "conductive film". Also, "insulating film" can sometimes be replaced by "insulating layer".

[0052] Implementation Method 1

[0053] In this embodiment, referring to FIGS. 1 to Fig. 9 The structure of one pixel of a liquid crystal display device will be described.

[0054] Figure 1A 1 is a top view of a pixel 100 of a liquid crystal display device having a multi-domain structure shown in this embodiment mode. Figure 1B Show Figure 1A A circuit diagram of a pixel 100 is shown. Figure 2A is a top view of a pixel 200 of a conventional multi-domain liquid crystal display device. Figure 2B Show Figure 2A Circuit diagram of the pixel shown.

[0055] like Figure 1A and Figure 1B As shown, the pixel 100 includes a scanning line 103 and a signal line 121 intersecting the scanning line 103. The pixel 100 also includes a capacitor wiring 105a and a capacitor wiring 105b extending in the same direction as the scanning line 103. The scanning line 103 is provided between the capacitor wiring 105a and the capacitor wiring 105b.

[0056] A transistor 136 and a transistor 137 are provided near the intersection of the scan line 103 and the signal line 121. The transistor 136 includes a semiconductor film 135 overlapping the scan line 103, and a first electrode 123 and a second electrode 125a overlapping the semiconductor film 135. The first electrode 123 is electrically connected to the signal line 121. The first electrode 123 is used as one of a source electrode and a drain electrode in the transistor 136. The second electrode 125a is used as the other of a source electrode and a drain electrode in the transistor 136.

[0057] The transistor 137 includes a semiconductor film 135 overlapping the scan line 103, and a first electrode 123 and a third electrode 125b overlapping the semiconductor film 135. The first electrode 123 is used as one of a source electrode and a drain electrode in the transistor 137. The third electrode 125b is used as the other of the source electrode and the drain electrode in the transistor 137.

[0058] exist Figure 1A In the top surface shape, a portion of the end portion of the semiconductor film 135 of the transistor 136 and the transistor 137 is located outside the scanning line 103 used as a gate electrode, but the present invention is not limited to this. Figure 1C As shown, in the transistor 136 and the transistor 137 included in the pixel 100 , the end portion of the semiconductor film 135 may be located inside the end portion of the scanning line 103 .

[0059] The second electrode 125a included in the transistor 136 is electrically connected to the pixel electrode 139a through the opening 144a. In other words, the transistor 136 is connected to the liquid crystal element 142 including the pixel electrode 139a through the second electrode 125a. In addition, one electrode of the capacitor 140 is electrically connected to the pixel electrode 139a and the second electrode 125a of the transistor 136, and the other electrode is electrically connected to the capacitor wiring 105a (see Figure 1B ).

[0060] The third electrode 125b included in the transistor 137 is electrically connected to the pixel electrode 139b through the opening 144b. In other words, the transistor 137 is connected to the liquid crystal element 143 including the pixel electrode 139b through the third electrode 125b. In addition, one electrode of the capacitor 141 is electrically connected to the pixel electrode 139b and the third electrode 125b of the transistor 137, and the other electrode is electrically connected to the capacitor wiring 105b (refer to Figure 1B ).

[0061] The opening 144a and the opening 144b are provided in the insulating film 116 described later. Figure 1A and Figure 2A In the figure, no hatching is added to the pixel electrode 139a and the pixel electrode 139b, and only the outline of the top surface shape is shown by the dotted line.

[0062] The transistor 136 and the transistor 137 are located substantially in the center of the pixel 100 in terms of the top surface shape, and are formed between the pixel electrode 139 a and the pixel electrode 139 b of each sub-pixel in the pixel 100 .

[0063] One embodiment of the present invention is a display device, which includes a signal line 121, a scan line 103, a first electrode 123, a second electrode 125a, a third electrode 125b, a first pixel electrode 139a, a second pixel electrode 139b and a semiconductor film 135, wherein the signal line 121 intersects the scan line 103, the first electrode 123 is electrically connected to the signal line 121, the first electrode 125a includes an area overlapping with the scan line 103, the second electrode 125a is opposite to the first electrode 123, the third electrode 125b is opposite to the first electrode 123, the first pixel electrode 139a is electrically connected to the second electrode 125a, the second pixel electrode 139b is electrically connected to the third electrode 125b, the semiconductor film 135 is in contact with the first electrode 123, the second electrode 125a and the third electrode 125b, and the semiconductor film 135 is arranged between the scan line 103 and the first electrode 123 to the third electrode 125b.

[0064] In addition, the following display device is also a method of the present invention: the display device includes a gate insulating film 107, a transistor 136 and a transistor 137, the gate insulating film 107 is arranged between the scanning line 103 and the semiconductor film 135, the transistor 136 includes the scanning line 103, the gate insulating film 107, the semiconductor film 135, the first electrode 123 and the second electrode 125a, and the transistor 137 includes the scanning line 103, the gate insulating film 107, the semiconductor film 135, the first electrode 123 and the third electrode 125b.

[0065] The transistor 136 and the transistor 137 share the first electrode 123 as one of the source electrode and the drain electrode, and the first electrode 123 overlaps the scanning line 103. With this structure, in one pixel 100 constituting the display device, parasitic capacitance generated between one electrode of the transistor 136 and the transistor 137 and the scanning line 103 can be reduced.

[0066] In addition, if Figure 1B As shown, in the transistor 136, a parasitic capacitance C1 is generated at the overlapping portion of the scanning line 103 and the second electrode 125a. In addition, in the transistor 137, a parasitic capacitance C2 is generated at the overlapping portion of the scanning line 103 and the third electrode 125b. In addition, parasitic capacitances C5, C6, and C7 are generated at the overlapping portion of the signal line 121 and the scanning line 103, the overlapping portion of the signal line 121 and the capacitor wiring 105a, and the overlapping portion of the signal line 121 and the capacitor wiring 105b, respectively.

[0067] Here, as a comparative example, Figure 2A A top view of a pixel 200 is shown, in which electrodes different from each other in two transistors included in one pixel are electrically connected to a signal line and the electrodes do not overlap with a scan line. Figure 2B 2 shows a circuit diagram of the pixel 200. In the description of the pixel 200, the same components as those of the pixel 100 are denoted by the same reference numerals, and the description of the components is omitted.

[0068] like Figure 2B As shown, the pixel 200 includes a scanning line 203 and a signal line 212 intersecting the scanning line 203. The pixel 200 also includes a capacitor wiring 105a and a capacitor wiring 105b extending in the same direction as the scanning line 203. The scanning line 203 is provided between the capacitor wiring 105a and the capacitor wiring 105b.

[0069] In addition, transistors 236 and 237 are provided near the intersection of the scanning line 203 and the signal line 221. The transistor 236 includes a gate electrode protruding from the scanning line 203, a fourth electrode 223a protruding from the signal line 221, and a second electrode 125a connected to the liquid crystal element 142. One electrode of the capacitor 140 is electrically connected to the pixel electrode 139a included in the liquid crystal element 142 and the second electrode 125a of the transistor 236, and the other electrode of the capacitor 140 is electrically connected to the capacitor wiring 105a (see Figure 2B ).

[0070] The transistor 237 includes a gate electrode protruding from the scanning line 203, a fifth electrode 223b protruding from the signal line 121, and a third electrode 125b connected to the liquid crystal element 143. One electrode of the capacitor 141 is electrically connected to the pixel electrode 139b included in the liquid crystal element 143 and the third electrode 125b of the transistor 237, and the other electrode of the capacitor 141 is electrically connected to the capacitor wiring 105b (see Figure 2B ).

[0071] The transistors 236 and 237 differ from the transistors 136 and 137 in the pixel 100 in that they include a fourth electrode 223a and a fifth electrode 223b as one of a source electrode and a drain electrode, respectively. In addition, the fourth electrode 223a and the fifth electrode 223b protruding from the signal line 221 do not overlap the scan line 203.

[0072] In addition, in the transistor 236, a parasitic capacitor C11 is generated at the overlapping portion of the scanning line 203 and the second electrode 125a. In addition, a parasitic capacitor C13 is generated at the overlapping portion of the scanning line 203 and the fourth electrode 223a. In the transistor 237, a parasitic capacitor C12 is generated at the overlapping portion of the scanning line 203 and the third electrode 125b. In addition, a parasitic capacitor C14 is generated at the overlapping portion of the scanning line 203 and the fifth electrode 223b. In addition, parasitic capacitors C15, C16, and C17 are generated at the overlapping portion of the signal line 221 and the scanning line 203, the overlapping portion of the signal line 221 and the capacitor wiring 105a, and the overlapping portion of the signal line 221 and the capacitor wiring 105b, respectively.

[0073] In transistor 136 and transistor 236, if the area of ​​the overlapping portion of scan line 103 and second electrode 125a and the area of ​​the overlapping portion of scan line 203 and second electrode 125a are substantially the same, parasitic capacitance C1 and parasitic capacitance C11 are substantially the same. In addition, in transistor 137 and transistor 237, if the area of ​​the overlapping portion of scan line 103 and third electrode 125b and the area of ​​the overlapping portion of scan line 203 and third electrode 125b are substantially the same, parasitic capacitance C2 and parasitic capacitance C12 are substantially the same. In addition, if the area of ​​the overlapping portion of signal line 121 and scan line 103 and the area of ​​the overlapping portion of signal line 221 and scan line 203 are substantially the same, parasitic capacitance C5 and parasitic capacitance C15 are substantially the same. In addition, if the area of ​​the overlapping portion of signal line 121 and capacitor wiring 105a and the area of ​​the overlapping portion of signal line 221 and capacitor wiring 105a are substantially the same, parasitic capacitance C6 and parasitic capacitance C16 are substantially the same. In addition, the area of ​​the overlapping portion between the signal line 121 and the capacitor wiring 105b and the area of ​​the overlapping portion between the signal line 221 and the capacitor wiring 105b are substantially the same, and the parasitic capacitance C7 and the parasitic capacitance C17 are substantially the same.

[0074] In pixel 200 as a comparative example, the electrodes used as the source electrode and the drain electrode in transistor 236 and transistor 237 are different electrodes from each other (in transistor 236, it is the fourth electrode 223a, and in transistor 237, it is the fifth electrode 223b), and therefore, a parasitic capacitance C13 is generated between the scanning line 203 and the fourth electrode 223a, and a parasitic capacitance C14 is generated between the scanning line 203 and the fifth electrode 223b.

[0075] However, in the pixel 100 shown in this embodiment, the electrode (first electrode 123) used as one of the source electrode and the drain electrode in the transistor 136 and the transistor 137 is common, and the electrode overlaps the scanning line 103 at the overlapping portion of the signal line 121 and the scanning line 103. Therefore, in the transistor 136 and the transistor 137, the parasitic capacitance generated at the overlapping portion of the electrode and the scanning line 103 is included in the above-mentioned parasitic capacitance C5. The parasitic capacitance C5 is substantially the same as the parasitic capacitance C15, and therefore, the parasitic capacitance in the pixel 100 is less than that in the pixel 200, and the difference is equal to the parasitic capacitance C13 and the parasitic capacitance C14. As described above, the display device of one embodiment of the present invention can reduce the parasitic capacitance generated between the wirings of one pixel 100.

[0076] In the pixel 100 described in this embodiment, the transistor 136 and the transistor 137 include a common semiconductor film. Therefore, the transistor 136 and the transistor 137 can share a region where the first electrode 123 is in contact with the semiconductor film 135. As a result, the area occupied by the transistor 136 and the transistor 137 in the pixel 100 can be reduced.

[0077] In addition, if Figure 3A and Figure 3B As shown in FIG. 1 , in the pixel 100, a structure in which adjacent pixels share the capacitor wiring 105a and the capacitor wiring 105b can also be adopted. By adopting this structure, the number of capacitor wirings included in the display device can be reduced. Figure 3A As shown, by increasing the overlapping area of ​​the pixel electrode 139a and the capacitor wiring 105a, the capacitance of the capacitor element 140 can be increased. Similarly, by increasing the overlapping area of ​​the pixel electrode 139b and the capacitor wiring 105b, the capacitance of the capacitor element 141 can be increased.

[0078] Next, refer to Figure 4 The structures of transistors and capacitors included in the pixel 100 are described.

[0079] Figure 4 Show Figure 1A The cross-sectional structure of the transistor 136 and the capacitor 140 is shown between the dot-dash line AB.

[0080] The transistor 136 includes, on the substrate 101 , a scan line 103 , a semiconductor film 135 , a gate insulating film 107 provided between the scan line 103 and the semiconductor film 135 , a first electrode 123 in contact with the semiconductor film 135 , and a second electrode 125 a in contact with the semiconductor film 135 .

[0081] The capacitor 140 includes a capacitor wiring 105 a , a second electrode 125 a , and a gate insulating film 107 provided between the capacitor wiring 105 a and the second electrode 125 a on the substrate 101 .

[0082] An insulating film 116 is provided over the gate insulating film 107, the semiconductor film 135, the first electrode 123, and the second electrode 125a. In addition, a pixel electrode 139a electrically connected to the second electrode 125a through an opening 144a provided in the insulating film 116 is provided over the insulating film 116.

[0083] Although not shown in the figure, the transistor 137 has the same structure as the transistor 136. Note that the capacitor 141 and the capacitor 140 are formed of the same components.

[0084] As the substrate 101, in addition to a glass substrate or a ceramic substrate, a plastic substrate or the like having heat resistance that can withstand the processing temperature of this manufacturing process can also be used. In addition, when the substrate does not need to be light-transmitting, a substrate in which an insulating film is provided on the surface of a metal substrate such as stainless steel can also be used. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass can be used. Note that there is no limitation on the size of the substrate 101. For example, third to tenth generation glass substrates commonly used in liquid crystal display devices can be used. In addition, as a material for the substrate 101, reference can be made to the material for the substrate 502 described in Embodiment 2.

[0085] A portion of the scanning line 103 is used as a gate electrode of the transistor 136. The scanning line 103 can be formed in a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or nickel, or an alloy material having these materials as main components. In addition, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, an Ag-Pd-Cu alloy, an Al-Nd alloy, an Al-Ni alloy, or the like can also be used.

[0086] For example, as a two-layer structure of the scanning line 103, the following structures are preferably adopted: a two-layer structure of a molybdenum film stacked on an aluminum film; a two-layer structure of a molybdenum film stacked on a copper film; a two-layer structure of a titanium nitride film or a tantalum nitride film stacked on a copper film; a two-layer structure of a titanium nitride film and a molybdenum film stacked; a two-layer structure of a copper-magnesium alloy film containing oxygen and a copper film stacked; a two-layer structure of a copper-manganese alloy film containing oxygen and a copper film stacked; a two-layer structure of a copper-manganese alloy film and a copper film stacked, etc. As a three-layer structure, a three-layer structure of a tungsten film or a tungsten nitride film, an alloy film of aluminum and silicon or an alloy film of aluminum and titanium, and a titanium nitride film or a titanium film stacked is preferably adopted. By stacking a metal film used as a barrier film on a low-resistance film, resistance can be reduced, and diffusion of metal elements from the metal film into the semiconductor film can be prevented. In addition, as a material for the scanning line 103, the material for the conductive film 504 described in Embodiment 2 can be referred to.

[0087] In addition, the capacitor wiring 105 a and the capacitor wiring 105 b have the same material and stacked structure as those of the scanning line 103 .

[0088] The gate insulating film 107 can be formed in a single layer or in a stacked layer using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film. In this embodiment, the gate insulating film 107 has a stacked layer structure of a gate insulating film 107a and a gate insulating film 107b. As materials for the gate insulating film 107a and the gate insulating film 107b, the materials for the insulating film 506 and the insulating film 507 described in Embodiment 2 can be referred to.

[0089] A silicon film or an oxide semiconductor film can be used as the semiconductor film 135. The semiconductor film 135 can have an amorphous structure, a polycrystalline structure, a single crystal structure, or another crystalline structure as appropriate.

[0090] In particular, an oxide semiconductor film is preferably used as the semiconductor film 135. Specifically, In-M (M is aluminum, gallium, yttrium, or tin) oxide or In-M-Zn oxide can be used. It is particularly preferable that an oxide semiconductor film 135a and an oxide semiconductor film 135b having different compositions are used as the semiconductor film 135. As materials for the oxide semiconductor film 135a and the oxide semiconductor film 135b, the materials for the oxide semiconductor film 508a and the oxide semiconductor film 508b described in Embodiment 2 can be referred to.

[0091] The first electrode 123 and the second electrode 125a can be formed in a single layer or a stacked layer using aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum or tungsten. Alternatively, the first electrode 123 and the second electrode 125a can be formed using an aluminum alloy to which an element for preventing hillocks is added (such as an Al-Nd alloy that can be used for the scanning line 103). In addition, crystalline silicon to which an impurity element that serves as a donor is added can also be used. In addition, a stacked structure can also be used, in which a film that contacts the crystalline silicon to which an impurity element that serves as a donor is added is formed using titanium, tantalum, molybdenum, tungsten or nitrides of these elements, and aluminum or an aluminum alloy is formed thereon. Moreover, a stacked structure can also be used in which the top and bottom surfaces of aluminum or an aluminum alloy are sandwiched by titanium, tantalum, molybdenum, tungsten or nitrides of these elements. In addition, as materials for the first electrode 123 and the second electrode 125a, reference can be made to the materials for the conductive film 512a and the conductive film 512b described in Embodiment 2.

[0092] The signal line 121 and the third electrode 125 b have the same material and stacked structure as the first electrode 123 .

[0093] In this embodiment, the insulating film 116 has a stacked-layer structure of an insulating film 116a, an insulating film 116b, and an insulating film 116c. As materials and formation methods for the insulating films 116a, 116b, and 116c, the description for the insulating film 514, the insulating film 516, and the insulating film 518 described in Embodiment 2 can be referred to. The insulating film 116 can be formed in a single layer or in a stacked layer using the same material as the gate insulating film 107.

[0094] The pixel electrode 139a can be formed in a single layer or a laminated layer using a metal film such as molybdenum, titanium, tantalum, tungsten, aluminum, silver, copper, chromium, neodymium, scandium, or an alloy film containing these metals. As alloys containing aluminum, aluminum-nickel-lanthanum alloys, aluminum-titanium alloys, aluminum-neodymium alloys, etc. can be cited. As alloys containing silver, silver-neodymium alloys, magnesium-silver alloys, etc. can be cited. In addition, alloys containing gold and copper can be used. In addition, metal nitride films containing titanium nitride, molybdenum nitride, tungsten nitride, etc. can also be used. In addition, as a material for the pixel electrode 139a, the material for the conductive film 520 described in Embodiment 2 can be referred to. The pixel electrode 139b has the same material and laminated structure as the pixel electrode 139a.

[0095] Alternatively, an oxide semiconductor film may be used as the pixel electrode. Figure 5 A top view of a pixel 100 including a pixel electrode 148 and a pixel electrode 149 formed of an oxide semiconductor film is shown. Figure 6 for Figure 5 The cross-sectional structure of the transistor 136 and the capacitor 145 is shown between the dot-dash line CD.

[0096] In this specification and the like, the oxide conductor film may be referred to alternatively as an oxide semiconductor film having high carrier density and low resistance, an oxide semiconductor film having conductivity, or an oxide semiconductor film having high conductivity.

[0097] If an oxide semiconductor film is used as the pixel electrode 148, when an oxide semiconductor film is used as the semiconductor film 135, the semiconductor film 135 and the pixel electrode 148 can be formed in the same process, so it is preferred. In the oxide semiconductor film, the resistivity can be controlled according to the concentration of oxygen defects in the film and / or impurities such as hydrogen and water in the film. Therefore, by selecting the oxide semiconductor film processed into an island shape to increase the oxygen defect and / or impurity concentration or to reduce the oxygen defect and / or impurity concentration, the resistivity of the semiconductor film 135 and the pixel electrode 148 formed in the same process can be controlled.

[0098] Specifically, by performing plasma treatment on the island-shaped oxide semiconductor film that will become the oxide conductor film 148a and the oxide conductor film 148b used as the pixel electrode 148, oxygen defects in the oxide semiconductor film and / or impurities such as hydrogen and water in the oxide semiconductor film are increased, thereby realizing an oxide semiconductor film with high carrier density and low resistance. On the other hand, insulating films 116a and 116b are provided on the transistor 136 so that the oxide semiconductor films 135a and 135b are not exposed to the above-mentioned plasma treatment. Figure 6 In the embodiment, the insulating films 116a and 116b are provided in such a manner as to selectively remove regions overlapping with the oxide conductor films 148a and 148b.

[0099] The plasma treatment performed on the oxide conductor films 148a and 148b may typically be a plasma treatment using a gas containing one or more selected from a rare gas (He, Ne, Ar, Kr, Xe), phosphorus, boron, hydrogen, and nitrogen. More specifically, the plasma treatment may be a plasma treatment in an Ar atmosphere, a plasma treatment in a mixed atmosphere of Ar and hydrogen, a plasma treatment in an ammonia atmosphere, a plasma treatment in a mixed atmosphere of Ar and ammonia, or a plasma treatment in a nitrogen atmosphere.

[0100] In addition, the pixel electrode 149 and the pixel electrode 148 have the same material and stacked structure. Figure 5 and Figure 6 In the pixel 100 shown, the capacitor 145 includes a capacitor wiring 105a, a pixel electrode 148, and a gate insulating film 107 provided between the capacitor wiring 105a and the pixel electrode 148. In addition, the capacitor 146 includes a capacitor wiring 105b, a pixel electrode 149, and a gate insulating film 107 provided between the capacitor wiring 105b and the pixel electrode 149.

[0101] A more detailed structure and a manufacturing method of the transistor 136 will be described in Embodiment 2. By using the transistor described in Embodiment 2 for the pixel 100 described in this embodiment, power consumption of the display device of one embodiment of the present invention can be reduced.

[0102] [Deformation Examples of Pixel Structure]

[0103] 7 to 7 Fig. 9 The structure of a pixel in a liquid crystal display device having a structure different from that of the above-described pixel 100 will be described.

[0104] Fig. 7A 1 is a top view of a pixel 300 of a liquid crystal display device having a multi-domain structure shown in this embodiment mode. Figure 7B Show Fig. 7A A circuit diagram of a pixel 300 is shown.

[0105] like Fig. 7A and Figure 7BAs shown, pixel 300 includes scan line 303 and signal line 321 intersecting with scan line 303. Signal line 321 includes the area overlapping with pixel electrode 339a and pixel electrode 339b. Pixel 300 also includes capacitor wiring 305a and capacitor wiring 305b extending in the same direction as signal line 321. In other words, signal line 321 does not include the area overlapping with capacitor wiring 305a and capacitor wiring 305b. In addition, capacitor wiring 305a and capacitor wiring 305b are electrically connected with pixel electrode 339a and pixel electrode 339b respectively. Signal line 321 is arranged between capacitor wiring 305a and capacitor wiring 305b.

[0106] A transistor 336 and a transistor 337 are provided near the intersection of the scan line 303 and the signal line 321. The transistor 336 includes a semiconductor film 335 overlapping the scan line 303 and a sixth electrode 323a and a seventh electrode 325a overlapping the semiconductor film 335. The sixth electrode 323a is electrically connected to the signal line 321. The sixth electrode 323a is used as one of a source electrode and a drain electrode in the transistor 336. The seventh electrode 325a is used as the other of a source electrode and a drain electrode in the transistor 336.

[0107] The transistor 337 includes a semiconductor film 335 overlapping the scan line 303, and an eighth electrode 323b and a ninth electrode 325b overlapping the semiconductor film 335. The eighth electrode 323b is electrically connected to the signal line 321. The eighth electrode 323b is used as one of a source electrode and a drain electrode in the transistor 337. The ninth electrode 325b is used as the other of a source electrode and a drain electrode in the transistor 337.

[0108] The seventh electrode 325a included in the transistor 336 is electrically connected to the pixel electrode 339a through the opening 344a. In other words, the transistor 336 is connected to the liquid crystal element 342 including the pixel electrode 339a through the seventh electrode 325a. In addition, one electrode of the capacitor 340 is electrically connected to the pixel electrode 339a and the seventh electrode 325a of the transistor 336, and the other electrode 345a is electrically connected to the capacitor wiring 305a through the opening 346a.

[0109] The ninth electrode 325b included in the transistor 337 is electrically connected to the pixel electrode 339b through the opening 344b. In other words, the transistor 337 is connected to the liquid crystal element 343 including the pixel electrode 339b through the ninth electrode 325b. In addition, one electrode of the capacitor 341 is electrically connected to the pixel electrode 339b and the ninth electrode 325b of the transistor 337, and the other electrode 345b is electrically connected to the capacitor wiring 305b through the opening 346b.

[0110] The openings 344a and 344b are provided in the insulating film 316 described later. The openings 346a and 346b are provided in the gate insulating film 307 described later. Fig. 7A In the figure, no hatching is added to the pixel electrode 339a and the pixel electrode 339b, and only the outline of the top surface shape is shown by the dotted line.

[0111] The transistor 336 and the transistor 337 are located substantially in the center of the pixel 300 in terms of the top surface shape, and are formed between the pixel electrode 339 a and the pixel electrode 339 b of each sub-pixel in the pixel 300 .

[0112] The sixth electrode 323a and the eighth electrode 323b, which are one of the source electrode and the drain electrode of the transistor 336 and the transistor 337, overlap the scanning line 303 at the overlapping portion of the signal line 321 and the scanning line 303. By adopting this structure, in one pixel 300 constituting the display element, it is possible to reduce the parasitic capacitance generated between one electrode of the transistor 336 and the transistor 337 and the scanning line 303. In addition, in the transistor 336 and the transistor 337, the seventh electrode 325a and the ninth electrode 325b, which are respectively used as the other of the source electrode and the drain electrode, overlap the scanning line 303.

[0113] In addition, if Figure 7B As shown, in the transistor 336, a parasitic capacitor C21 is generated at the overlapping portion of the scan line 303 and the seventh electrode 325a. In addition, in the transistor 337, a parasitic capacitor C22 is generated at the overlapping portion of the scan line 303 and the ninth electrode 325b. In addition, a parasitic capacitor C25 is generated at the overlapping portion of the signal line 321 and the scan line 303. The sixth electrode 323a and the eighth electrode 323b overlap with the scan line 303 at the overlapping portion of the signal line 321 and the scan line 303, so the parasitic capacitors generated at the overlapping portion of the sixth electrode 323a and the scan line 303 and the overlapping portion of the eighth electrode 323b and the scan line 303 are included in the above-mentioned parasitic capacitor C25.

[0114] Here, the pixel 300 including the transistor 336 and the transistor 337 is compared with the pixel 100 including the transistor 136 and the transistor 137. Since the area of ​​the overlapping portion of the seventh electrode 325a and the scanning line 303 is larger than the area of ​​the overlapping portion of the second electrode 125a and the scanning line 103, the parasitic capacitance C21 is larger than the parasitic capacitance C1. In addition, since the area of ​​the overlapping portion of the ninth electrode 325b and the scanning line 303 is larger than the area of ​​the overlapping portion of the third electrode 125b and the scanning line 103, the parasitic capacitance C22 is larger than the parasitic capacitance C2. In addition, if the area of ​​the overlapping portion of the scanning line 303 and the signal line 321 and the area of ​​the overlapping portion of the scanning line 103 and the signal line 121 are substantially the same, the parasitic capacitance C25 and the parasitic capacitance C5 are substantially the same.

[0115] In addition, in the pixel 100, parasitic capacitance C6 and parasitic capacitance C7 are generated at the overlapping portion of the signal line 121 and the capacitor wiring 105a and the overlapping portion of the signal line 121 and the capacitor wiring 105b, respectively. On the other hand, in the pixel 300, the signal line 321 does not include an area overlapping with the capacitor wiring 305a and the capacitor wiring 305b, so no parasitic capacitance is generated between the signal line 321 and the capacitor wiring 305a and between the signal line 321 and the capacitor wiring 305b.

[0116] In a liquid crystal display device including a plurality of pixels, the parasitic capacitance that causes the signal transmission delay of the signal line has a smaller influence on the signal transmission delay when it is generated in a portion of the signal transmission path that passes through a transistor closer to the end. For example, in the pixel 100, the parasitic capacitance C1 generated in the overlapping portion of the scanning line 103 and the second electrode 125a has a smaller influence on the signal transmission delay of the signal line 121 than the parasitic capacitance C6 generated in the overlapping portion of the signal line 121 and the capacitor wiring 105a. This is because: in the liquid crystal display device, if it is a parasitic capacitance C6, the same number of parasitic capacitances C6 as the capacitor wiring overlapping one signal line 121 affect the signal transmission, however, if it is a parasitic capacitance C1, it affects the signal transmission when one transistor 136 connected to one signal line 121 becomes conductive. Therefore, although the parasitic capacitance of pixel 300 is larger than that of pixel 100, the difference is equal to the difference between parasitic capacitance C21 and parasitic capacitance C1 and the difference between parasitic capacitance C22 and parasitic capacitance C2, but parasitic capacitance C6 and parasitic capacitance C7 generated in pixel 100 are not generated in pixel 300, so the parasitic capacitance that causes signal transmission delay of the signal line included in the liquid crystal display device can be reduced.

[0117] In addition, if Figure 7CAs shown in FIG. 1 , the end of the semiconductor film 335 may be extended in the extending direction of the signal line 321, and the seventh electrode 325a and the ninth electrode 325b may be arranged in such a manner that the overlapping area of ​​the seventh electrode 325a and the scanning line 303 and the overlapping area of ​​the ninth electrode 325b and the scanning line 303 are small. By adopting such a structure, the parasitic capacitance C21 and the parasitic capacitance C22 mentioned above can be reduced. In addition, as Fig.7D As shown in FIG. 1 , the semiconductor film 335 may be provided in such a manner that, in a plan view, the end of the semiconductor film 335 is located outside the overlapping portion of the signal line 321 and the scanning line 303. By forming the semiconductor film 335 between the signal line 321 and the scanning line 303 in addition to the gate insulating film 307, the parasitic capacitance generated in the overlapping portion of the signal line 321 and the scanning line 303 can sometimes be reduced.

[0118] In addition, if Fig. 8A and Figure 8B As shown in FIG. 1 , in pixel 300, a structure in which adjacent pixels share capacitor wiring 305a and capacitor wiring 305b can also be adopted. By adopting this structure, the number of capacitor wirings included in the display device can be reduced. Fig. 8A As shown, by increasing the area of ​​the overlap between the pixel electrode 339a and the capacitor wiring 305a, the capacitance of the capacitor element 340 can be increased. Similarly, by increasing the area of ​​the overlap between the pixel electrode 339b and the capacitor wiring 305b, the capacitance of the capacitor element 341 can be increased.

[0119] Next, refer to Fig. 9 The structures of transistors and capacitors included in the pixel 300 are described.

[0120] Fig. 9 Show Fig. 7A The cross-sectional structure of the transistor 336 and the capacitor 340 is shown between the dot-dash line CD.

[0121] The transistor 336 includes, on the substrate 301 , a scan line 303 , a semiconductor film 335 , a gate insulating film 307 provided between the scan line 303 and the semiconductor film 335 , a sixth electrode 323 a in contact with the semiconductor film 335 , and a seventh electrode 325 a in contact with the semiconductor film 335 .

[0122] The capacitor 340 includes an electrode 345 a , a seventh electrode 325 a , and a gate insulating film 307 provided between the electrode 345 a and the seventh electrode 325 a on the substrate 301 .

[0123] In addition, a capacitor wiring 305a electrically connected to the electrode 345a through an opening 346a provided in the gate insulating film 307 is provided on the gate insulating film 307. An insulating film 316 is provided on the gate insulating film 307, the semiconductor film 335, the sixth electrode 323a, the seventh electrode 325a, and the capacitor wiring 305a. A pixel electrode 339a electrically connected to the seventh electrode 325a through an opening 344a provided in the insulating film 316 is provided on the insulating film 316.

[0124] Although not shown, the transistor 337 has the same structure as the transistor 336. The capacitor 341 and the capacitor 340 are configured with the same components.

[0125] The layers constituting the transistor 336 and the capacitor 340 have the same material and stacked structure as the layers constituting the transistor 136 and the capacitor 140. In addition, as the insulating film 316 and the pixel electrode 339a, the same materials as the insulating film 116 and the pixel electrode 139a can be used. In addition, as the electrode 345a and the capacitor wiring 305a, the same materials as the scanning line 303 and the sixth electrode 323a are used.

[0126] A more detailed structure and a manufacturing method of the transistor 336 will be described in Embodiment 2. By using the transistor described in Embodiment 2 for the pixel 300 described in this embodiment, power consumption of the display device of one embodiment of the present invention can be reduced.

[0127] When the pixel 100 or pixel 300 described in this embodiment is included, the liquid crystal display device with a multi-domain structure can reduce the parasitic capacitance generated between the scan line and the signal line (in other words, between the scan line used as the gate electrode of the transistor and the signal line used as one of the source electrode and the drain electrode of the transistor). In addition, when the pixel 300 described in this embodiment is included, the liquid crystal display device with a multi-domain structure can reduce the parasitic capacitance generated between the signal line and the capacitor wiring. Therefore, the display quality of large liquid crystal display devices, liquid crystal display devices capable of high-speed driving, and liquid crystal display devices with high resolution can be improved in particular. In addition, the power consumption of the liquid crystal display device can be reduced.

[0128] In addition, although a structure in which two transistors are provided in one pixel is shown in this embodiment, the present invention is not limited thereto and one pixel may include a plurality of transistors of three or more and a plurality of pixel electrodes connected to the transistors.

[0129] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0130] Implementation Method 2

[0131] In this embodiment, referring to FIGS. 10 to 11 Fig.18 A semiconductor device and a method for manufacturing the semiconductor device according to one embodiment of the present invention will be described.

[0132] <Structural Example 1 of Semiconductor Device>

[0133] Fig. 14C is a top view of a transistor 500 as a semiconductor device according to one embodiment of the present invention. Fig. 14B Equivalent to following Fig. 14C The cross-sectional view of the cut surface along the dot-dash line X1-X2 and the cross-sectional view of the cut surface along the dot-dash line Y1-Y2 are shown. FIG. 10A to FIG. 14A Yes Description Fig. 14B A cross-sectional view showing a manufacturing process of transistor 500 is shown.

[0134] In addition, Fig. 14C For the sake of convenience, some components of transistor 500 (such as an insulating film used as a gate insulating film) are omitted. In addition, the dot-dash line X1-X2 direction is sometimes referred to as the channel length direction, and the dot-dash line Y1-Y2 direction is sometimes referred to as the channel width direction. Note that sometimes the top view of the transistor below is also different from the Fig. 14C Similarly, some of the components are omitted.

[0135] The transistor 500 includes: a conductive film 504 serving as a gate electrode on a substrate 502; an insulating film 506 on the substrate 502 and the conductive film 504; an insulating film 507 on the insulating film 506; an oxide semiconductor film 508 on the insulating film 507; a conductive film 512a serving as a source electrode electrically connected to the oxide semiconductor film 508; and a conductive film 512b serving as a drain electrode electrically connected to the oxide semiconductor film 508. In addition, on the transistor 500, in detail, insulating films 514, 516, and 518 are provided on the conductive films 512a, 512b, and the oxide semiconductor film 508. The insulating films 514, 516, and 518 function as protective insulating films of the transistor 500. Note that the insulating film 514 is sometimes referred to as a first protective insulating film, and the insulating film 516 is sometimes referred to as a second protective insulating film.

[0136] The oxide semiconductor film 508 includes a first oxide semiconductor film 508 a on the conductive film 504 side serving as a gate electrode and a second oxide semiconductor film 508 b over the first oxide semiconductor film 508 a. The insulating film 506 and the insulating film 507 function as a gate insulating film of the transistor 500 .

[0137] In—M (M is aluminum, gallium, yttrium, or tin) oxide or In—M—Zn oxide can be used as the oxide semiconductor film 508. In particular, In—M—Zn oxide is preferably used as the oxide semiconductor film 508.

[0138] Note that the first oxide semiconductor film 508 a preferably contains an oxide having a larger atomic ratio of In relative to the atomic ratio of M than the second oxide semiconductor film 508 b .

[0139] By making the first oxide semiconductor film 508a have a composition in which the atomic number ratio of In is greater than the atomic number ratio of M, the field effect mobility (sometimes simply referred to as mobility or μFE) of the transistor 500 can be improved. Specifically, the field effect mobility of the transistor 500 can exceed 10 cm 2 / Vs, preferably more than 30cm 2 / Vs.

[0140] For example, by using the above-mentioned transistor with high field effect mobility for a gate driver that generates a gate signal (in particular, a demultiplexer connected to the output terminal of a shift register included in the gate driver), a semiconductor device or display device with a narrow border width (also called a narrow border) can be provided.

[0141] On the other hand, by making the first oxide semiconductor film 508a have a composition in which the atomic number ratio of In is greater than the atomic number ratio of M, the electrical characteristics of the transistor 500 when irradiated with light are easily changed. However, in a semiconductor device of one embodiment of the present invention, a second oxide semiconductor film 508b is formed on the first oxide semiconductor film 508a. Since the second oxide semiconductor film 508b has a composition in which the atomic number ratio of In is smaller than that of the first oxide semiconductor film 508a, its band gap Eg is greater than that of the first oxide semiconductor film 508a. Therefore, the oxide semiconductor film 508 having a stacked structure of the first oxide semiconductor film 508a and the second oxide semiconductor film 508b has a higher resistance to a light negative bias stress test.

[0142] By using the oxide semiconductor film having the above structure, the amount of light absorbed by the oxide semiconductor film 508 when irradiated with light can be reduced. Therefore, changes in the electrical characteristics of the transistor 500 when irradiated with light can be suppressed.

[0143] In addition, when oxygen defects are formed in the oxide semiconductor film 508 of the transistor 500, electrons are generated as carriers, which makes it easy to become a normally-on characteristic. Note that the normally-on characteristic of the transistor refers to the characteristic that the current (for example, the current between the drain and the source (Ids)) flows when the gate voltage Vg=0V. Therefore, in order to obtain stable transistor characteristics, it is important to reduce the oxygen defects in the oxide semiconductor film 508, especially to reduce the oxygen defects in the first oxide semiconductor film 508a. Therefore, in the structure of a transistor of one embodiment of the present invention, excess oxygen is introduced into the insulating film on the oxide semiconductor film 508, and here, excess oxygen is introduced into the insulating film 514 and / or the insulating film 516 on the oxide semiconductor film 508, so that oxygen is moved from the insulating film 514 and / or the insulating film 516 to the oxide semiconductor film 508, thereby filling the oxygen defects in the oxide semiconductor film 508, especially filling the oxygen defects in the first oxide semiconductor film 508a. Alternatively, when the first barrier film 531 is formed on the insulating film 516, excess oxygen is introduced into the insulating film 516, so that oxygen moves from the insulating film 516 to the oxide semiconductor film 508, thereby filling oxygen defects in the oxide semiconductor film 508, especially filling oxygen defects in the first oxide semiconductor film 508a.

[0144] In addition, the insulating films 514 and 516 preferably have a region containing oxygen exceeding the stoichiometric composition (oxygen excess region). In other words, the insulating films 514 and 516 are insulating films that can release oxygen. In addition, in order to provide the oxygen excess region in the insulating films 514 and 516, for example, oxygen is introduced into the insulating films 514 and 516 after film formation to form the oxygen excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

[0145] In order to fill the oxygen vacancies in the first oxide semiconductor film 508a, the second oxide semiconductor film 508b is preferably formed thin near the channel region. For example, the thickness of the second oxide semiconductor film 508b near the channel region is preferably greater than 1 nm and less than 20 nm, and more preferably greater than 3 nm and less than 10 nm.

[0146] In order to fill the oxygen vacancies in the first oxide semiconductor film 508a, the second oxide semiconductor film 508b preferably has high oxygen permeability. By making the second oxide semiconductor film 508b have high oxygen permeability, excess oxygen in the insulating film 514 and the insulating film 516 can be effectively transmitted to the first oxide semiconductor film 508a.

[0147] Thus, in a semiconductor device of one embodiment of the present invention, by making the oxide semiconductor film a stacked structure and making the insulating film in contact with the oxide semiconductor film contain excess oxygen, a semiconductor device with high reliability can be provided. In addition, in one embodiment of the present invention, the temperature in the manufacturing process of the semiconductor device having the above structure can be reduced (typically below 400°C or below 375°C (preferably above 340°C and below 360°C)). In addition, the manufacturing process of the semiconductor device will be described later.

[0148] Next, other components included in the semiconductor device of this embodiment will be described in detail.

[0149] <Substrate>

[0150] Although there is no particular limitation on the material of the substrate 502, it is at least required to have heat resistance capable of withstanding subsequent heating treatment. For example, as the substrate 502, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, or the like, an SOI (Silicon On Insulator) substrate, or the like can also be used, and a substrate having a semiconductor element disposed thereon can also be used as the substrate 502. When a glass substrate is used as the substrate 502, a large display device can be manufactured by using a large-area substrate of the 6th, 7th, 8th, 9th, or 10th generation. The use of such a large-area substrate is preferred because the manufacturing cost can be reduced.

[0151] As the substrate 502, a flexible substrate may be used, and the transistor 500 may be directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 502 and the transistor 500. The peeling layer may be used in the case where a part or all of a semiconductor device is manufactured on the peeling layer, and then separated from the substrate 502 and transferred to another substrate. In this case, the transistor 500 may also be transferred to a substrate with low heat resistance or a flexible substrate.

[0152] <Conductive Film Used as Gate Electrode, Source Electrode, and Drain Electrode>

[0153] The conductive film 504 used as a gate electrode, the conductive film 512a used as a source electrode, and the conductive film 512b used as a drain electrode can be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), alloys containing the above metal elements, or alloys combining the above metal elements.

[0154] In addition, the conductive films 504, 512a, and 512b may also have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure of a titanium film stacked on an aluminum film, a two-layer structure of a titanium film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a tantalum nitride film or a tungsten nitride film, and a three-layer structure of a titanium film, an aluminum film, and a titanium film stacked in sequence may be cited. In addition, an alloy film or a nitride film formed by combining aluminum with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may also be used.

[0155] The conductive films 504, 512a, and 512b may be made of a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide.

[0156] In addition, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) may be applied as the conductive films 504, 512a, and 512b. By using the Cu-X alloy film, processing can be performed by a wet etching process, thereby reducing manufacturing costs.

[0157] <Insulating Film Serving as Gate Insulating Film>

[0158] As the insulating film 506 and the insulating film 507 used as the gate insulating film of the transistor 500, one or more insulating films including a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, etc. can be used. Note that a single layer or three or more insulating films selected from the above materials may be used instead of using a stacked structure of the insulating film 506 and the insulating film 507.

[0159] The insulating film 506 has a function as a barrier film that suppresses oxygen permeation. For example, when excessive oxygen is supplied to the insulating films 507, 114, and 516 and / or the oxide semiconductor film 508, the insulating film 506 can suppress oxygen permeation.

[0160] The insulating film 507 in contact with the oxide semiconductor film 508 used as the channel region of the transistor 500 is preferably an oxide insulating film, and more preferably includes a region containing oxygen exceeding the stoichiometric composition (oxygen excess region). In other words, the insulating film 507 is an insulating film capable of releasing oxygen. In order to provide an oxygen excess region in the insulating film 507, for example, the insulating film 507 can be formed in an oxygen atmosphere. Alternatively, oxygen can be introduced into the insulating film 507 after film formation to form an oxygen excess region. As a method for introducing oxygen, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, etc. can be used.

[0161] In addition, when hafnium oxide is used as the insulating film 507, the following effects are exerted. The relative dielectric constant of hafnium oxide is higher than that of silicon oxide or silicon oxynitride. Therefore, the thickness of the insulating film 507 can be made larger than that of using silicon oxide or silicon oxynitride, thereby reducing the leakage current caused by the tunnel current. In other words, a transistor with a small off-state current can be realized. Furthermore, compared with hafnium oxide having an amorphous structure, the relative dielectric constant of hafnium oxide having a crystalline structure is higher. Therefore, in order to form a transistor with a small off-state current, it is preferred to use hafnium oxide including a crystalline structure. As examples of crystalline structures, monoclinic system or cubic system can be cited. Note that one embodiment of the present invention is not limited to this.

[0162] Note that in this embodiment, a silicon nitride film is formed as the insulating film 506, and a silicon oxide film is formed as the insulating film 507. Compared with a silicon oxide film, a silicon nitride film has a higher relative dielectric constant and requires a greater thickness to obtain an electrostatic capacitance equivalent to that of a silicon oxide film. Therefore, by making the gate insulating film of the transistor 500 include a silicon nitride film, the physical thickness of the insulating film can be increased. Therefore, by suppressing a decrease in the dielectric withstand voltage of the transistor 500 and increasing the dielectric withstand voltage, electrostatic breakdown of the transistor 500 can be suppressed.

[0163] <Oxide Semiconductor Film>

[0164] As the oxide semiconductor film 508, the above materials can be used. When the oxide semiconductor film 508 is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1. In addition, when the oxide semiconductor film 508 is an In-M-Zn oxide, a target containing polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target containing polycrystalline In-M-Zn oxide, it is easy to form the oxide semiconductor film 508 having crystallinity. Note that the atomic ratio of the formed oxide semiconductor film 508 includes an error within the range of ±40% of the atomic ratio of the metal elements in the above sputtering target. For example, when using a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1, the atomic ratio of the formed oxide semiconductor film 508 may be around In:Ga:Zn = 4:2:3.

[0165] For example, the first oxide semiconductor film 508a can be formed using the above sputtering targets such as In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1. The atomic ratio of the first oxide semiconductor film 508a is preferably In:M:Zn = 4:α1(1.5≤α1≤2.5):α2(2.5≤α2≤3.5).

[0166] In addition, the second oxide semiconductor film 508b can be formed using the above sputtering targets such as In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2. The atomic ratio of the second oxide semiconductor film 508b is preferably In:M:Zn = 1:β1(0.8≤β1≤1.2):β2(0.8≤β2≤1.2). In addition, as the atomic ratio of the metal elements of the sputtering target for the second oxide semiconductor film 508b, it is not necessarily required to satisfy both In≥M and Zn≥M at the same time, and it may also satisfy In<M and / or Zn<M. Specifically, examples include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, etc.

[0167] The energy gap of the oxide semiconductor film 508 is greater than 2 eV, preferably greater than 2.5 eV, and more preferably greater than 3 eV. In this way, by using an oxide semiconductor with a wider energy gap, the off-state current of the transistor 500 can be reduced. In particular, an oxide semiconductor film with an energy gap of greater than 2.0 eV, preferably greater than 2.0 eV and less than 3.0 eV, is used as the first oxide semiconductor film 508a, and an oxide semiconductor film with an energy gap of greater than 2.5 eV and less than 3.5 eV is used as the second oxide semiconductor film 508b. In addition, it is preferred that the energy gap of the second oxide semiconductor film 508b is greater than the energy gap of the first oxide semiconductor film 508a.

[0168] The thickness of the first oxide semiconductor film 508 a and the second oxide semiconductor film 508 b are each greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, and more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0169] In addition, an oxide semiconductor film having a low carrier density is used as the first oxide semiconductor film 508 a. For example, the carrier density of the first oxide semiconductor film 508 a can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 In addition, an oxide semiconductor film having a low carrier density is used as the second oxide semiconductor film 508 b. For example, the carrier density of the second oxide semiconductor film 508 b may be 1×10 17 / cm 3 Below, preferably 1×10 15 / cm 3 Below, more preferably 1×10 13 / cm 3 Below, more preferably 1×10 11 / cm 3 the following.

[0170] The present invention is not limited to the above description, and a material having an appropriate composition can be used according to the desired semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. In addition, it is preferred to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the first oxide semiconductor film 508a and the second oxide semiconductor film 508b to obtain the desired semiconductor characteristics of the transistor.

[0171] By using an oxide semiconductor film with a low impurity concentration and a low defect state density as the first oxide semiconductor film 508a and the second oxide semiconductor film 508b, a transistor with better electrical characteristics can be manufactured, so it is preferred. Here, the state of low impurity concentration and low defect state density (few oxygen defects) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has fewer carrier generation sources, the carrier density can be reduced. Therefore, a transistor having a channel region formed in the oxide semiconductor film rarely has an electrical characteristic of a negative threshold voltage (also called a normally-on characteristic). Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density. The off-state current of the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is significantly low, even if the channel width is 1×10 6 For a device with a channel length of 10 μm and a source-drain voltage of 1 V to 10 V, the off-state current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 A or below.

[0172] Therefore, a transistor having a channel region formed in the above-mentioned high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film can be a transistor with small changes in electrical characteristics and high reliability. In addition, it takes a long time for the charge captured by the trap energy level of the oxide semiconductor film to disappear, and sometimes it acts like a fixed charge. Therefore, sometimes the electrical characteristics of a transistor having a channel region formed in an oxide semiconductor film with a high trap state density are unstable. Impurities include hydrogen, nitrogen, alkali metals or alkaline earth metals.

[0173] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atom to generate water, and at the same time, an oxygen defect is formed in the lattice where oxygen detachment occurs (or the portion where oxygen detachment occurs). When hydrogen enters the oxygen defect, electrons are sometimes generated as carriers. In addition, sometimes electrons are generated as carriers because a portion of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductor films containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the amount of hydrogen in the oxide semiconductor film 508 as much as possible. Specifically, in the oxide semiconductor film 508, the hydrogen concentration measured by SIMS (Secondary Ion Mass Spectrometry) is 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 Below, more preferably 1×10 16 atoms / cm 3 the following.

[0174] Note that the first oxide semiconductor film 508a preferably includes a portion having a lower hydrogen concentration than the second oxide semiconductor film 508b. When the first oxide semiconductor film 508a includes a portion having a lower hydrogen concentration than the second oxide semiconductor film 508b, a highly reliable semiconductor device can be provided.

[0175] In addition, when the first oxide semiconductor film 508a contains silicon or carbon, which is one of the elements of Group 14, oxygen vacancies increase in the first oxide semiconductor film 508a, causing the first oxide semiconductor film 508a to become n-type. Therefore, the concentration of silicon or carbon in the first oxide semiconductor film 508a and the concentration of silicon or carbon near the interface with the first oxide semiconductor film 508a (concentration measured by SIMS analysis) are 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0176] In addition, the concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 508a measured by SIMS analysis is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 When an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers are generated and the off-state current of the transistor is increased. Therefore, the concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 508a is preferably reduced.

[0177] When nitrogen is contained in the first oxide semiconductor film 508a, electrons are generated as carriers, and the carrier density increases, resulting in the n-type of the first oxide semiconductor film 508a. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have a normally-on characteristic. Therefore, it is preferable to reduce nitrogen in the oxide semiconductor film as much as possible. For example, the nitrogen concentration measured by SIMS analysis is preferably 5×10 18 atoms / cm 3 the following.

[0178] The first oxide semiconductor film 508a and the second oxide semiconductor film 508b may have a non-single-crystal structure, respectively. The non-single-crystal structure includes, for example, the following CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor: c-axis oriented crystalline oxide semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the defect state density of the amorphous structure is the highest, while the defect state density of the CAAC-OS is the lowest.

[0179] Here, refer to Fig.18 The energy band structures of the oxide semiconductor film 508 and the insulating film in contact with the oxide semiconductor film 508 are described.

[0180] Fig.18 1 is an example of an energy band structure in the film thickness direction of a stacked-layer structure including an insulating film 507, a first oxide semiconductor film 508a, a second oxide semiconductor film 508b, and an insulating film 514. In the energy band structure, for easy understanding, the conduction band bottom energy level (Ec) of the insulating film 507, the first oxide semiconductor film 508a, the second oxide semiconductor film 508b, and the insulating film 514 is shown.

[0181] exist Fig.18 In the energy band diagram shown, a silicon oxide film is used as the insulating film 507 and the insulating film 514, an oxide semiconductor film formed by using a metal oxide target material having an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 is used as the first oxide semiconductor film 508a, and a metal oxide film formed by using a metal oxide target material having an atomic ratio of metal elements of In:Ga:Zn=1:1:1.2 is used as the second oxide semiconductor film 508b.

[0182] like Fig.18 As shown, in the first oxide semiconductor film 508a and the second oxide semiconductor film 508b, the conduction band bottom energy level changes smoothly. In other words, the conduction band bottom energy level changes continuously or is continuously connected. In order to achieve such an energy band structure, impurities that form defect energy levels such as trap centers or recombination centers are not present at the interface between the first oxide semiconductor film 508a and the second oxide semiconductor film 508b.

[0183] In order to form a continuous junction between the first oxide semiconductor film 508a and the second oxide semiconductor film 508b, a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber may be used so that each film is not exposed to the atmosphere and is continuously stacked.

[0184] It can be seen that by adopting Fig.18In the structure shown in FIG. 1 , the first oxide semiconductor film 508 a functions as a well, and in a transistor using the stacked structure, a channel region is formed in the first oxide semiconductor film 508 a .

[0185] In addition, when the second oxide semiconductor film 508b is not formed, a trap level may be formed in the first oxide semiconductor film 508a. On the other hand, by adopting the above-mentioned stacked structure, the trap level may be formed in the second oxide semiconductor film 508b. Therefore, the trap level can be kept away from the first oxide semiconductor film 508a.

[0186] In addition, sometimes the trap energy level is farther from the vacuum energy level than the bottom energy level (Ec) of the conduction band of the first oxide semiconductor film 508a used as the channel region, and electrons are easily accumulated in the trap energy level. When electrons accumulate in the trap energy level, they become negative fixed charges, causing the threshold voltage of the transistor to drift in the positive direction. Therefore, it is preferred to adopt a structure in which the trap energy level is closer to the vacuum energy level than the bottom energy level (Ec) of the conduction band of the first oxide semiconductor film 508a. By adopting the above structure, electrons are not easily accumulated in the trap energy level, so the on-state current of the transistor can be increased, and the field effect mobility can also be improved.

[0187] exist Fig.18 In the embodiment of the present invention, the conduction band bottom energy level of the second oxide semiconductor film 508b is closer to the vacuum level than that of the first oxide semiconductor film 508a. Typically, the difference between the conduction band bottom energy level of the first oxide semiconductor film 508a and the conduction band bottom energy level of the second oxide semiconductor film 508b is 0.15 eV or 0.5 eV and 2 eV or 1 eV. In other words, the difference between the electron affinity of the second oxide semiconductor film 508b and the electron affinity of the first oxide semiconductor film 508a is 0.15 eV or 0.5 eV and 2 eV or 1 eV.

[0188] By adopting the above structure, the first oxide semiconductor film 508a becomes the main path of the current and is used as a channel region. Since the second oxide semiconductor film 508b includes one or more of the metal elements included in the first oxide semiconductor film 508a forming the channel region, interface scattering is not easily generated at the interface between the first oxide semiconductor film 508a and the second oxide semiconductor film 508b. As a result, since the movement of carriers in the interface is not hindered, the field effect mobility of the transistor is improved.

[0189] In order to prevent the second oxide semiconductor film 508b from being used as part of the channel region, the second oxide semiconductor film 508b uses a material with sufficiently low conductivity. Alternatively, the second oxide semiconductor film 508b uses a material whose electron affinity (difference between the vacuum energy level and the conduction band bottom energy level) is lower than that of the first oxide semiconductor film 508a and whose conduction band bottom energy level is different from that of the first oxide semiconductor film 508a (band offset). In addition, in order to suppress the difference between the threshold voltages caused by the drain voltage value, it is preferred to use a material whose conduction band bottom energy level of the second oxide semiconductor film 508b is closer to the vacuum energy level by more than 0.2 eV, preferably more than 0.5 eV, than that of the conduction band bottom energy level of the first oxide semiconductor film 508a.

[0190] The second oxide semiconductor film 508b preferably does not include a spinel-type crystal structure. When the second oxide semiconductor film 508b includes a spinel-type crystal structure, the constituent elements of the conductive films 512a and 512b may diffuse into the first oxide semiconductor film 508a at the interface between the spinel-type crystal structure and other regions. Note that in the case where the second oxide semiconductor film 508b is a CAAC-OS described later, the properties of the constituent elements of the blocking conductive films 512a and 512b, such as copper, are improved, so it is preferred.

[0191] The thickness of the second oxide semiconductor film 508b is greater than or equal to a thickness that can suppress the diffusion of constituent elements of the conductive films 512a and 512b into the oxide semiconductor film 508b and less than a thickness that suppresses the supply of oxygen from the insulating film 514 to the oxide semiconductor film 508b. For example, when the thickness of the second oxide semiconductor film 508b is greater than or equal to 10 nm, the diffusion of constituent elements of the conductive films 512a and 512b into the first oxide semiconductor film 508a can be suppressed. In addition, when the thickness of the second oxide semiconductor film 508b is less than or equal to 100 nm, oxygen can be effectively supplied from the insulating films 514 and 516 to the first oxide semiconductor film 508a.

[0192] <Insulating Film Serving as Protective Insulating Film of Transistor>

[0193] The insulating films 514 and 516 have a function of supplying oxygen to the oxide semiconductor film 508. The insulating film 518 has a function of a protective insulating film of the transistor 500. The insulating films 514 and 516 contain oxygen. The insulating film 514 is an insulating film that allows oxygen to pass through. Note that the insulating film 514 also serves as a film that mitigates damage to the oxide semiconductor film 508 when the insulating film 516 is formed later.

[0194] As the insulating film 514 , silicon oxide, silicon oxynitride, or the like can be used with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm.

[0195] Furthermore, the number of defects in the insulating film 514 is preferably small. Typically, the spin density of a signal at g=2.001 due to dangling bonds of silicon measured by ESR (Electron Spin Resonance) is preferably 3×10 17 spins / cm 3 This is because, if the defect density of the insulating film 514 is high, oxygen is bonded to the defects, and the amount of oxygen permeation in the insulating film 514 is reduced.

[0196] In the insulating film 514, sometimes all of the oxygen that enters the insulating film 514 from the outside does not move to the outside of the insulating film 514, but a part of it remains inside the insulating film 514. In addition, sometimes, when oxygen enters the insulating film 514, oxygen contained in the insulating film 514 moves to the outside of the insulating film 514, and oxygen movement occurs in the insulating film 514. When an oxide insulating film that allows oxygen to pass is formed as the insulating film 514, oxygen separated from the insulating film 516 provided on the insulating film 514 can be moved to the oxide semiconductor film 508 via the insulating film 514.

[0197] In addition, the insulating film 514 can be formed using an oxide insulating film having a low state density of nitride oxide. Note that the state density of the nitride oxide may be formed at an energy level (E ) at the top of the valence band of the oxide semiconductor film. V_OS ) and the energy of the conduction band bottom of the oxide semiconductor film (E C_OS ). As E v_os and E c_os As an oxide insulating film having a low state density of nitride oxides, a silicon oxynitride film having a small amount of nitride oxides released or an aluminum oxynitride film having a small amount of nitride oxides released can be used.

[0198] In addition, in thermal desorption spectrum analysis, the silicon oxynitride film with a small amount of nitrogen oxide release is a film that releases more ammonia than nitrogen oxide. Typically, the amount of ammonia molecules released is 1×10 18 Molecules / cm 3 Above and 5×10 19 Molecules / cm 3 Note that the amount of ammonia released is the amount released when the film surface temperature is heated to a temperature of 50° C. to 650° C., preferably 50° C. to 550° C.

[0199] Nitrogen oxides (NO x, x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2 or NO forms an energy level in the insulating film 514 or the like. This energy level is located in the energy gap of the oxide semiconductor film 508. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 514 and the oxide semiconductor film 508, sometimes this energy level captures electrons on one side of the insulating film 514. As a result, the captured electrons remain near the interface between the insulating film 514 and the oxide semiconductor film 508, thereby causing the threshold voltage of the transistor to drift in the positive direction.

[0200] In addition, when heat treatment is performed, nitrogen oxide reacts with ammonia and oxygen. When heat treatment is performed, nitrogen oxide contained in the insulating film 514 reacts with ammonia contained in the insulating film 516, thereby reducing nitrogen oxide contained in the insulating film 514. Therefore, electrons are not easily captured at the interface between the insulating film 514 and the oxide semiconductor film 508.

[0201] By using E as the insulating film 514 v_os and E c_os The oxide insulating film having a low state density of nitride oxides can reduce the drift of the threshold voltage of the transistor, thereby reducing the variation of the electrical characteristics of the transistor.

[0202] By performing a heat treatment in the manufacturing process of the transistor, typically a heat treatment at a temperature lower than 400°C or lower than 375°C (preferably at a temperature of 340°C or higher and 360°C or lower), in the spectrum of the insulating film 514 measured by ESR at 100K or lower, a first signal having a g value of 2.037 or higher and 2.039 or lower, a second signal having a g value of 2.001 or higher and 2.003 or lower, and a third signal having a g value of 1.964 or higher and 1.966 or lower are observed. In the ESR measurement of the X band, the split width between the first signal and the second signal and the split width between the second signal and the third signal are approximately 5 mT. In addition, the sum of the spin densities of the first signal having a g value of 2.037 or higher and 2.039 or lower, the second signal having a g value of 2.001 or higher and 2.003 or lower, and the third signal having a g value of 1.964 or higher and 1.966 or lower is less than 1×10 18 spins / cm 3 , typically 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 .

[0203] In the ESR spectrum below 100K, the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966 correspond to the emission of nitrogen oxides (NO x , x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2). Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, the smaller the total number of spin densities of the first signal having a g value of greater than or equal to 2.037 and less than or equal to 2.039, the second signal having a g value of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal having a g value of greater than or equal to 1.964 and less than or equal to 1.966, the less the content of nitrogen oxides in the oxide insulating film.

[0204] In addition, for E v_os and E c_os The nitrogen concentration of the low-density oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 the following.

[0205] The E is formed by a PECVD method using silane and nitrous oxide at a substrate temperature of 220° C. to 350° C. v_os and E c_os The oxide insulating film with low state density of nitrogen oxides can form a dense and high hardness film.

[0206] The insulating film 516 is formed using an oxide insulating film whose oxygen content exceeds the stoichiometric composition. The oxide insulating film whose oxygen content exceeds the stoichiometric composition is heated, and part of its oxygen is released. According to TDS analysis, the amount of oxygen released from the oxide insulating film whose oxygen content exceeds the stoichiometric composition is 1.0×10 19 atoms / cm 3 Above, preferably 3.0×10 20 atoms / cm 3 Note that the surface temperature of the film during the above TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0207] As the insulating film 516 , a silicon oxide film, a silicon oxynitride film, or the like can be used with a thickness of greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm.

[0208] Furthermore, it is preferable to reduce the number of defects in the insulating film 516. Typically, the spin density of the signal at g = 2.001 due to dangling bonds of silicon measured by ESR is less than 1.5×10 18spins / cm 3 , more preferably 1×10 18 spins / cm 3 Since the insulating film 516 is farther from the oxide semiconductor film 508 than the insulating film 514 , the defect density of the insulating film 516 can also be higher than that of the insulating film 514 .

[0209] In addition, since the insulating films 514 and 516 can be formed using the same type of material, the interface between the insulating film 514 and the insulating film 516 may not be clearly confirmed. Therefore, in this embodiment, the interface between the insulating film 514 and the insulating film 516 is shown by a dotted line. Note that in this embodiment, although a two-layer structure of the insulating film 514 and the insulating film 516 is described, the present invention is not limited to this, and for example, the insulating film 514 or the insulating film 516 may also have a single-layer structure.

[0210] The insulating film 518 has a function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. By providing the insulating film 518, oxygen can be prevented from diffusing from the oxide semiconductor film 508 to the outside, and oxygen contained in the insulating films 514 and 516 can be prevented from diffusing to the outside, and hydrogen, water, and the like can be prevented from invading the oxide semiconductor film 508 from the outside. As the insulating film 518, for example, a nitride insulating film can be used. As the nitride insulating film, there are silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, and the like. In particular, when silicon nitride oxide or a silicon nitride film is used as the insulating film 518, it is preferred because oxygen diffusion to the outside can be suppressed.

[0211] Alternatively, an oxide insulating film having a barrier effect on oxygen, hydrogen, water, etc. may be provided as the insulating film 518 instead of the nitride insulating film having a barrier effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Examples of the oxide insulating film having a barrier effect on oxygen, hydrogen, water, etc. include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film. As the oxide insulating film having a barrier effect on oxygen, hydrogen, water, etc., aluminum oxide, hafnium oxide, or yttrium oxide is particularly preferably used.

[0212] Although the various films such as the conductive film, insulating film, and oxide semiconductor film described above can be formed by sputtering or PECVD, they can also be formed by, for example, thermal CVD (Chemical Vapor Deposition: metal organic chemical vapor deposition) or ALD (Atomic Layer Deposition: atomic layer deposition). As an example of thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition: metal organic chemical vapor deposition) can be cited.

[0213] Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects due to plasma damage do not occur.

[0214] Film formation using thermal CVD can be performed by supplying a source gas and an oxidant simultaneously into a chamber, setting the pressure in the chamber to atmospheric pressure or reduced pressure, and causing them to react near or on a substrate to deposit on the substrate.

[0215] In addition, film formation using the ALD method can also be performed in the following method: the pressure in the chamber is set to atmospheric pressure or reduced pressure, the source gas used for the reaction is introduced into the chamber in sequence, and the gas is repeatedly introduced in this order. For example, by switching each switch valve (also called a high-speed valve) to supply two or more source gases into the chamber in sequence, in order to prevent the mixing of multiple source gases, an inert gas (argon or nitrogen, etc.) is introduced at the same time or after the first source gas is introduced, and then the second source gas is introduced. Note that when the first source gas and the inert gas are introduced at the same time, the inert gas is used as a carrier gas. In addition, the inert gas can be introduced at the same time as the second source gas. In addition, the first source gas can be discharged by vacuum pumping without introducing an inert gas, and then the second source gas is introduced. The first source gas adheres to the surface of the substrate to form a first layer, and the second source gas introduced thereafter reacts with the first layer, thereby stacking the second layer on the first layer to form a thin film. By repeatedly introducing gases in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas is introduced in sequence, the ALD method can accurately adjust the thickness and is suitable for manufacturing micro FETs.

[0216] Various films such as the conductive film, insulating film, oxide semiconductor film, and metal oxide film described in the above embodiments can be formed by a thermal CVD method such as an MOCVD method. For example, when an In-Ga-ZnO film is formed, trimethyl indium, trimethyl gallium, and dimethyl zinc are used. The chemical formula of trimethyl indium is In(CH3)3. The chemical formula of trimethyl gallium is Ga(CH3)3. In addition, the chemical formula of dimethyl zinc is Zn(CH3)2. In addition, without being limited to the above combination, triethyl gallium (chemical formula is Ga(C2H5)3) can be used instead of trimethyl gallium, and diethyl zinc (chemical formula is Zn(C2H5)2) can be used instead of dimethyl zinc.

[0217] For example, when forming a hafnium oxide film using a film forming apparatus utilizing the ALD method, the following two gases are used: a source gas obtained by gasifying a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium tetrakis dimethylamide (TDMAH) and other hafnium amides); and ozone (O3) used as an oxidant. The chemical formula of hafnium tetrakis dimethylamide is Hf[N(CH3)2]4. In addition, other material liquids include hafnium tetrakis (ethylmethylamide) and the like.

[0218] For example, when an aluminum oxide film is formed using a film forming apparatus using the ALD method, the following two gases are used: a source gas obtained by gasifying a liquid containing a solvent and an aluminum precursor compound (trimethylaluminum (TMA) or the like); and H2O used as an oxidant. In addition, the chemical formula of trimethylaluminum is Al(CH3)3. In addition, as other material liquids, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione), and the like.

[0219] For example, when a silicon oxide film is formed using a film forming apparatus utilizing the ALD method, hexachlorodisilane is attached to the film-forming surface to remove chlorine contained in the deposits, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the deposits.

[0220] For example, when forming a tungsten film using a film forming apparatus using the ALD method, WF6 gas and B2H6 gas are introduced repeatedly in sequence to form an initial tungsten film, and then WF6 gas and H2 gas are introduced repeatedly in sequence to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0221] For example, when an oxide semiconductor film such as an In-Ga-ZnO film is formed using a film forming device using the ALD method, In(CH3)3 gas and O3 gas are repeatedly introduced in sequence to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are repeatedly introduced in sequence to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced in sequence to form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases can also be mixed to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H2O gas obtained by bubbling with an inert gas such as Ar can also be used instead of O3 gas, it is preferred to use O3 gas that does not contain H. In addition, In(C2H5)3 gas can also be used instead of In(CH3)3 gas. Ga(C2H5)3 gas can also be used instead of Ga(CH3)3 gas. Zn(CH3)2 gas can also be used.

[0222] <Structural Example 2 of Semiconductor Device>

[0223] Next, refer to Fig.16A and Fig. 16B Description and Fig. 14B and Fig. 14C The transistor 500 shown in the figure is a different structural example. In addition, when a part having the same function as that described above is indicated, the same hatching is sometimes used without adding a special reference numeral.

[0224] Fig.16A is a top view of a transistor 570 which is a semiconductor device according to one embodiment of the present invention. Fig. 16B Equivalent to following Fig.16A The cross-section along the dotted line X3-X4 shown in FIG. Fig.16A The cross-sectional view is a cross-sectional view taken along the dashed line Y3 - Y4 shown.

[0225] The transistor 570 includes: a conductive film 504 serving as a first gate electrode on a substrate 502; an insulating film 506 on the substrate 502 and the conductive film 504; an insulating film 507 on the insulating film 506; an oxide semiconductor film 508 on the insulating film 507; an insulating film 514 on the oxide semiconductor film 508; an insulating film 516 on the insulating film 514; a conductive film 512a serving as a source electrode electrically connected to the oxide semiconductor film 508; a conductive film 512b serving as a drain electrode electrically connected to the oxide semiconductor film 508; an insulating film 514 on the oxide semiconductor film 508; an insulating film 516 on the insulating film 514; an insulating film 518 on the insulating film 516; a conductive film 520a on the insulating film 518; and a conductive film 520b on the insulating film 518. The insulating films 514, 516, and 518 function as a second gate insulating film of the transistor 570. In addition, the conductive film 520a is electrically connected to the conductive film 512b through the opening 542c provided in the insulating films 514, 516, and 518. In the transistor 570, the conductive film 520a has a function as, for example, a pixel electrode for a display device. In the transistor 570, the conductive film 520b serves as a second gate electrode (also referred to as a back gate electrode).

[0226] like Fig. 16B As shown, the conductive film 520b is connected to the conductive film 504 functioning as the first gate electrode in openings 542a and 542b provided in the insulating films 506, 507, 514, 516, and 518. Therefore, the same potential is applied to the conductive film 520b and the conductive film 504.

[0227] In addition, in this embodiment, the structure in which the openings 542a and 542b are provided to connect the conductive film 520b to the conductive film 504 is exemplified, but the present invention is not limited thereto. For example, a structure in which only one of the openings 542a and 542b is formed to connect the conductive film 520b to the conductive film 504, or a structure in which the openings 542a and 542b are not provided and the conductive film 520b is not connected to the conductive film 504 may be adopted. When the structure in which the conductive film 520b is not connected to the conductive film 504 is adopted, different potentials can be applied to the conductive film 520b and the conductive film 504, respectively.

[0228] like Fig. 16B As shown, the oxide semiconductor film 508 is located at a position opposite to the conductive film 504 used as a gate electrode and the conductive film 520b used as a second gate electrode, and is sandwiched between the two conductive films used as gate electrodes. The length of the conductive film 520b used as the second gate electrode in the channel length direction and the length of the channel width direction are both greater than the length of the oxide semiconductor film 508 in the channel length direction and the length of the channel width direction, and the conductive film 520b covers the entire oxide semiconductor film 508 via the insulating films 514, 516, and 518. In addition, since the conductive film 520b used as the second gate electrode is connected to the conductive film 504 used as a gate electrode in the openings 542a and 542b provided in the insulating films 506, 507, 514, 516, and 518, the side surface of the oxide semiconductor film 508 in the channel width direction is opposite to the conductive film 520b used as the second gate electrode via the insulating films 514, 516, and 518.

[0229] In other words, in the channel width direction of the transistor 570, the conductive film 504 used as a gate electrode and the conductive film 520b used as a second gate electrode are connected in an opening portion provided in the insulating films 506, 507 used as gate insulating films and the insulating films 514, 516, 518 used as second gate insulating films, and the conductive film 504 and the conductive film 520b surround the oxide semiconductor film 508 via the insulating films 506, 507 used as gate insulating films and the insulating films 514, 516, 518 used as second gate insulating films.

[0230] By adopting the above structure, the oxide semiconductor film 508 included in the transistor 570 is electrically surrounded by the electric field of the conductive film 504 used as the gate electrode and the conductive film 520b used as the second gate electrode. As shown in the transistor 570, the device structure of the transistor in which the oxide semiconductor film having the channel region is electrically surrounded by the electric field of the gate electrode and the second gate electrode can be called a surrounded channel (s-channel) structure.

[0231] Since the transistor 570 has an s-channel structure, an electric field for causing a channel can be effectively applied to the oxide semiconductor film 508 using the conductive film 504 used as a gate electrode. As a result, the current driving capability of the transistor 570 is improved, so that a high on-state current characteristic can be obtained. In addition, since the on-state current can be increased, the transistor 570 can be miniaturized. In addition, since the transistor 570 has a structure surrounded by the conductive film 504 used as a gate electrode and the conductive film 520b used as a second gate electrode, the mechanical strength of the transistor 570 can be improved.

[0232] Note that the other structures of the transistor 570 are the same as those of the above-described transistor 500 and exhibit the same effects.

[0233] In addition, the transistor of this embodiment mode can freely combine the above structures. Fig.14A and Fig. 14B The transistor 500 shown is used as a transistor of a pixel of a display device, and Fig.16A and Fig. 16B The transistor 570 shown is a transistor for a gate driver of a display device.

[0234] <Method 1 for manufacturing semiconductor device>

[0235] Next, refer to FIG. 10A to FIG. 14A A method for manufacturing the transistor 500 of the semiconductor device according to one embodiment of the present invention will be described in detail. FIG. 10A to FIG. 14A It is a cross-sectional view for explaining a method for manufacturing a semiconductor device.

[0236] First, a conductive film is formed on a substrate 502, and the conductive film is processed by a photolithography step and an etching step to form a conductive film 504 serving as a gate electrode. Next, insulating films 506 and 507 serving as gate insulating films are formed on the conductive film 504 (see FIG. 1 ). Fig. 10A ).

[0237] In this embodiment, a glass substrate is used as the substrate 502. A tungsten film with a thickness of 100 nm is formed by a sputtering method as the conductive film 504 used as the gate electrode. In addition, a silicon nitride film with a thickness of 400 nm is formed by a PECVD method as the insulating film 506, and a silicon oxynitride film with a thickness of 50 nm is formed by a PECVD method as the insulating film 507.

[0238] A stacked-layer structure of silicon nitride films can be used as the insulating film 506. Specifically, a three-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film can be used as the insulating film 506. An example of this three-layer structure can be formed by the following steps.

[0239] A first silicon nitride film with a thickness of 50 nm can be formed under the following conditions: for example, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm are used as source gases, the source gases are supplied into the reaction chamber of the PECVD device, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power.

[0240] A second silicon nitride film with a thickness of 300 nm can be formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 2000 sccm are used as source gases, the source gases are supplied into the reaction chamber of the PECVD device, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power.

[0241] A third silicon nitride film with a thickness of 50 nm can be formed under the following conditions: silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm are used as source gases, the source gas is supplied into the reaction chamber of the PECVD device, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power.

[0242] In addition, the substrate temperature during formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be set to 350° C. or less.

[0243] For example, when a conductive film including copper (Cu) is used as the conductive film 504 and a three-layer structure of a silicon nitride film is adopted as the insulating film 506 , the following effect is achieved.

[0244] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 504. The second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film used as a gate insulating film. The third silicon nitride film has a small amount of hydrogen released and can suppress the diffusion of hydrogen released from the second silicon nitride film.

[0245] The insulating film 507 is preferably formed using an insulating film containing oxygen in order to improve interface characteristics between the insulating film 507 and the oxide semiconductor film 508 (more specifically, the first oxide semiconductor film 508 a ) to be formed later.

[0246] Next, an oxide semiconductor film 509 is formed at a first temperature over the insulating film 507. In addition, as the oxide semiconductor film 509, a first oxide semiconductor film 509a is formed, and then a second oxide semiconductor film 509b is formed (see Fig. 10B ).

[0247] The first temperature for forming the oxide semiconductor film 509 is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and further preferably above 100°C and below 200°C. By heating to form the oxide semiconductor film 509, the crystallinity of the oxide semiconductor film 509 can be improved. On the other hand, when a large glass substrate (for example, the 6th to 10th generation) is used as the substrate 502, the substrate 502 sometimes deforms when the first temperature is above 150°C and below 340°C. Therefore, when using a large glass substrate, the deformation of the glass substrate can be suppressed by setting the first temperature to above 100°C and below 150°C.

[0248] The substrate temperatures during the formation of the first oxide semiconductor film 509a and the second oxide semiconductor film 509b may be the same or different, but preferably, the substrate temperatures of the first oxide semiconductor film 509a and the second oxide semiconductor film 509b are the same because manufacturing costs can be reduced.

[0249] In this embodiment, the first oxide semiconductor film 509a is formed by sputtering using an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn=4:2:4.1, and then the second oxide semiconductor film 509b is continuously formed by sputtering in a vacuum using an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1.2. In addition, the substrate temperature when forming the first oxide semiconductor film 509a and the second oxide semiconductor film 509b is set to 170°C.

[0250] In addition, in the case of forming the oxide semiconductor film 509 by sputtering, as the sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. In addition, when a mixed gas is used, it is preferred to increase the proportion of oxygen gas relative to the rare gas. In addition, the sputtering gas needs to be highly purified. For example, as a sputtering gas, oxygen gas or argon gas is used, and a high-purity gas with a dew point of less than -40°C, preferably less than -80°C, more preferably less than -100°C, and further preferably less than -120°C is used, thereby preventing moisture and the like from mixing into the oxide semiconductor film 509 as much as possible.

[0251] When the oxide semiconductor film 509 is formed by sputtering, it is preferable to perform high vacuum evacuation (evacuation to 5×10 -7 Pa or more and 1×10 -4Pa or less) to remove as much water and the like which are impurities to the oxide semiconductor film 509 as possible. Alternatively, it is preferable to combine a turbomolecular pump and a cold trap to prevent gas, especially gas containing carbon or hydrogen, from flowing back into the processing chamber from the exhaust system.

[0252] Next, the oxide semiconductor film 509 is processed to form an island-shaped oxide semiconductor film 508. Note that the first oxide semiconductor film 509a becomes the island-shaped first oxide semiconductor film 508a, and the second oxide semiconductor film 509b becomes the island-shaped second oxide semiconductor film 508b (see Fig. 10C ).

[0253] Next, a conductive film 512 to be a source electrode and a drain electrode is formed on the insulating film 507 and the oxide semiconductor film 508 by a sputtering method without performing a step at a temperature higher than the first temperature (see Fig.11A ).

[0254] In this embodiment, as the conductive film 512, a stacked film in which a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm are stacked in sequence is formed by sputtering. Although the conductive film 512 has a two-layer stacked structure in this embodiment, it is not limited to this. For example, the conductive film 512 may also have a three-layer structure in which a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm are stacked in sequence.

[0255] Next, masks 536a and 536b are formed in desired regions on the conductive film 512 (see Fig. 11B ).

[0256] In this embodiment, the masks 536 a and 536 b are formed by applying a photosensitive resin film on the conductive film 512 and patterning the photosensitive resin film by a photolithography process.

[0257] Next, the conductive film 512 is processed from above the conductive film 512 and the masks 536a and 536b using an etchant 538, thereby forming conductive films 512a and 512b separated from each other (see Fig. 11C ).

[0258] In this embodiment, the conductive film 512 is processed using a dry etching device. However, the processing method of the conductive film 512 is not limited to this. For example, a chemical solution may be used for the etchant 538 and a wet etching device may be used to process the conductive film 512 and the second oxide semiconductor film 508b. Note that, compared with the case where the conductive film 512 is processed using a wet etching device, a finer pattern can be formed by processing the conductive film 512 using a dry etching device. On the other hand, compared with the case where the conductive film 512 is processed using a dry etching device, processing the conductive film 512 using a wet etching device can reduce manufacturing costs.

[0259] Next, the surface of the second oxide semiconductor film 508b is cleaned from above the second oxide semiconductor film 508b, the conductive films 512a and 512b, and the masks 536a and 536b using an etchant 539 (see Fig. 12A ).

[0260] As the above-mentioned washing method, for example, washing using a chemical solution such as phosphoric acid can be cited. By washing using a chemical solution such as phosphoric acid, impurities attached to the surface of the second oxide semiconductor film 508b (for example, elements contained in the conductive films 512a and 512b) can be removed. Note that this washing does not necessarily have to be performed. Depending on the situation, this washing may not be performed.

[0261] In addition, when the conductive films 512a and 512b are formed and / or in the above-mentioned cleaning step, a region of the second oxide semiconductor film 508b exposed from the conductive films 512a and 512b may become thinner than the first oxide semiconductor film 508a.

[0262] Note that when the conductive films 512a and 512b are formed and / or in the above-mentioned cleaning step, the region of the second oxide semiconductor film 508b exposed from the conductive films 512a and 512b may not be thinned. Fig.15A and Fig. 15B An example of this is shown below. Fig.15A and Fig. 15B is a cross-sectional view showing an example of a semiconductor device. Fig.15A yes Fig. 14B The second oxide semiconductor film 508b of the transistor 500 shown in FIG. Fig. 15B As shown, the second oxide semiconductor film 508b may be formed thinner than the first oxide semiconductor film 508a in advance, and the thickness of the region exposed from the conductive films 512a and 512b may be set to be equal to Fig. 14B The transistor 500 shown is equal. Fig. 15CAs shown in FIG. 5 , the second oxide semiconductor film 508 b may be formed thinner than the first oxide semiconductor film 508 a in advance, and an insulating film 519 may be formed over the second oxide semiconductor film 508 b and the insulating film 507. At this time, an opening through which the second oxide semiconductor film 508 b is in contact with the conductive films 512 a and 512 b is formed in the insulating film 519. The insulating film 519 may be formed using the same material and the same formation method as the insulating film 514.

[0263] Next, by removing the masks 536a and 536b, a conductive film 512a serving as a source electrode on the second oxide semiconductor film 508b and a conductive film 512b serving as a drain electrode on the second oxide semiconductor film 508 are formed. The oxide semiconductor film 508 has a stacked structure of the first oxide semiconductor film 508a and the second oxide semiconductor film 508b (see Fig. 12B ).

[0264] Next, an insulating film 514 serving as a first protective insulating film and an insulating film 516 serving as a second protective insulating film are formed over the oxide semiconductor film 508 and the conductive films 512a and 512b, and then a first barrier film 531 is formed (see Fig. 12C ).

[0265] In addition, it is preferable that the insulating film 516 is continuously formed without being exposed to the atmosphere after the insulating film 514 is formed. After the insulating film 514 is formed, the insulating film 516 is continuously formed without being exposed to the atmosphere by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, thereby reducing the concentration of impurities derived from atmospheric components at the interface between the insulating film 514 and the insulating film 516, and oxygen contained in the insulating films 514 and 516 can be moved to the oxide semiconductor film 508, so that the amount of oxygen defects in the oxide semiconductor film 508 can be reduced.

[0266] For example, as the insulating film 514, a silicon oxynitride film can be formed by the PECVD method. At this time, as the source gas, it is preferred to use a deposition gas containing silicon and an oxidizing gas. Typical examples of deposition gases containing silicon are silane, disilane, trisilane, fluorinated silane, and the like. As oxidizing gases, there are nitrous oxide, nitrogen dioxide, and the like. In addition, the insulating film 514 containing nitrogen and having a small amount of defects can be formed by the PECVD method under the following conditions: the flow rate of the oxidizing gas is greater than 20 times and less than 100 times the flow rate of the above-mentioned deposition gas, preferably greater than 40 times and less than 80 times; and the pressure in the processing chamber is less than 100 Pa, preferably less than 50 Pa.

[0267] In this embodiment, as the insulating film 514, a silicon oxynitride film is formed by a PECVD method under the following conditions: the temperature of the substrate 502 is maintained at 220° C.; silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as source gases; the pressure in the processing chamber is 20 Pa; and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (power density is 1.6×10 -2 W / cm 2 ).

[0268] As the insulating film 516, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the temperature of the substrate in a vacuum-evacuated processing chamber installed in a PECVD device is maintained at 180° C. or higher and 350° C. or lower, a source gas is introduced into the processing chamber and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, preferably 100 Pa or higher and 200 Pa or lower, and 0.17 W / cm2 is supplied to an electrode provided in the processing chamber. 2 Above and 0.5W / cm 2 Below, more preferably 0.25W / cm 2 Above and 0.35W / cm 2 The following high frequency power.

[0269] In the film formation conditions of the insulating film 516, the high frequency power having the above power density is supplied in the reaction chamber having the above pressure, thereby improving the decomposition efficiency of the source gas in the plasma, increasing the oxygen radicals, and promoting the oxidation of the source gas, so that the oxygen content in the insulating film 516 exceeds the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, since the bonding force between silicon and oxygen is weak, part of the oxygen in the film is released by the heat treatment in the subsequent step. As a result, an oxide insulating film whose oxygen content exceeds the stoichiometric composition and part of the oxygen is released by heating can be formed.

[0270] In the step of forming the insulating film 516, the insulating film 514 is used as a protective film for the oxide semiconductor film 508. Therefore, the insulating film 516 can be formed using high-frequency power with high power density while reducing damage to the oxide semiconductor film 508.

[0271] In addition, in the film formation conditions of the insulating film 516, by increasing the flow rate of the deposition gas containing silicon relative to the oxidizing gas, the amount of defects in the insulating film 516 can be reduced. Typically, an oxide insulating film with a small amount of defects can be formed in which the spin density of the signal at g=2.001 due to the dangling bonds of silicon measured by ESR is less than 6×10 17 spins / cm 3 , preferably 3×10 17spins / cm 3 Below, more preferably 1.5×10 17 spins / cm 3 As follows. This can improve the reliability of the transistor.

[0272] Alternatively, heat treatment may be performed after the insulating films 514 and 516 are formed (in other words, after the insulating film 516 is formed and before the first barrier film 531 is formed). By this heat treatment, nitrogen oxides contained in the insulating films 514 and 516 can be reduced. Also, by this heat treatment, part of the oxygen contained in the insulating films 514 and 516 can be moved to the oxide semiconductor film 508 to reduce the amount of oxygen vacancies in the oxide semiconductor film 508.

[0273] The temperature of the heat treatment performed on the insulating films 514 and 516 is typically set to be lower than 400°C, preferably lower than 375°C, more preferably higher than 340°C and lower than 360°C, and further preferably higher than 150°C and lower than 350°C. The heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably lower than 1 ppm, and more preferably lower than 10 ppb) or a rare gas (argon, helium, etc.). The above-mentioned nitrogen, oxygen, ultra-dry air or rare gas preferably does not contain hydrogen, water, etc. The heat treatment can be performed using an electric furnace, an RTA device, etc.

[0274] The first barrier film 531 contains oxygen and a metal (at least one selected from indium, zinc, titanium, aluminum, tungsten, tantalum, molybdenum, hafnium, and yttrium). When indium tin oxide (also referred to as ITO (Indium Tin Oxide)), indium tin silicon oxide (hereinafter referred to as ITSO), or indium oxide is used as the first barrier film 531, since the coverage of the uneven surface is good, it is preferable.

[0275] In addition, the first barrier film 531 can be formed by a sputtering method. When the first barrier film 531 is very thin, it is sometimes difficult to suppress oxygen that may be released from the insulating film 516 to the outside. On the other hand, when the first barrier film 531 is very thick, oxygen may not be properly added to the insulating film 516. Therefore, the thickness of the first barrier film 531 is preferably not less than 1 nm and not more than 20 nm, and more preferably not less than 2 nm and not more than 10 nm. In this embodiment, ITSO with a thickness of 5 nm is formed as the first barrier film 531.

[0276] Next, oxygen 540 is added to the insulating film 516 serving as the second protective insulating film via the first barrier film 531. Note that in the drawings, oxygen added to the insulating film 516 is schematically indicated as oxygen 540a (see FIG. 5A ). Fig.13A ). In addition, oxygen 540 is sometimes added to the insulating film 514.

[0277] As a method of adding oxygen 540 to the insulating film 516 via the first barrier film 531, there are ion doping, ion implantation, plasma treatment, etc. In addition, as oxygen 540, excess oxygen or oxygen radicals can be cited. In addition, when adding oxygen 540, oxygen 540 can be effectively added to the insulating film 516 by applying a bias voltage to the substrate side. As the above-mentioned bias voltage, for example, the power density is set to 1 W / cm 2 Above and 5W / cm 2 By providing the first barrier film 531 over the insulating film 516 to add oxygen, the first barrier film 531 can be used as a protective film for suppressing the release of oxygen from the insulating film 516. Therefore, more oxygen can be added to the insulating film 516.

[0278] Next, the first barrier film 531 or a portion of the first barrier film 531 and a portion of the insulating film 516 serving as the second protective insulating film are removed using an etchant 542 (see Fig. 13B ).

[0279] As a method for removing the first barrier film 531 and a portion of the insulating film 516 serving as the second protective insulating film, dry etching, wet etching, or a method combining dry etching and wet etching can be cited. Note that when dry etching is used, the etchant 542 is an etching gas, and when wet etching is used, the etchant 542 is a chemical solution. In this embodiment, the first barrier film 531 is removed by wet etching. As a method for removing the first barrier film 531, wet etching is preferably used because it can reduce manufacturing costs.

[0280] Next, an insulating film 518 serving as a second barrier film is formed on the insulating film 516 (see Fig.14A ).

[0281] When the insulating film 518 is formed by the PECVD method, the substrate temperature is lower than 400° C., preferably lower than 375° C., and more preferably 340° C. to 360° C. When the substrate temperature is set to the above range when the insulating film 518 is formed, the excess oxygen or the oxygen radicals can be diffused into the oxide semiconductor film 508. When the substrate temperature is set to the above range when the insulating film 518 is formed, a dense film can be formed, which is preferred.

[0282] For example, when a silicon nitride film is formed as an insulating film 518 by a PECVD method, a deposition gas containing silicon, nitrogen, and ammonia are preferably used as source gases. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma to generate active species. The active species cuts the bond between silicon and hydrogen and the triple bond of nitrogen contained in the deposition gas containing silicon. As a result, the bonding between silicon and nitrogen can be promoted, and a silicon nitride film with fewer bonds between silicon and hydrogen, fewer defects, and a dense structure can be formed. On the other hand, when the amount of ammonia is large relative to nitrogen, the decomposition of the deposition gas containing silicon and nitrogen does not progress, and the bond between silicon and hydrogen remains, resulting in the formation of a silicon nitride film with more defects and less density. Therefore, in the source gas, the flow ratio of nitrogen to ammonia is set to be greater than 5 times and less than 50 times, preferably greater than 10 times and less than 50 times.

[0283] In this embodiment, as the insulating film 518, a silicon nitride film with a thickness of 50 nm is formed by using a PECVD device and using silane, nitrogen and ammonia as source gases. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure of the processing chamber is set to 100 Pa, the substrate temperature is set to 350°C, and a high-frequency power of 1000 W is supplied to the parallel plate electrode using a high-frequency power supply of 27.12 MHz. The PECVD device has an electrode area of ​​6000 cm 2 The parallel plate PECVD device, when the supplied electric power is converted into power per unit area (power density), is 1.7×10 -1 W / cm 2 .

[0284] Alternatively, heat treatment may be performed after forming the insulating film 518 serving as the second barrier film. In addition, by performing heat treatment after forming the insulating film 518, excess oxygen or oxygen radicals in the insulating film 516 can be diffused into the oxide semiconductor film 508, thereby filling oxygen defects in the oxide semiconductor film 508. Alternatively, by forming the insulating film 518 by heating, excess oxygen or oxygen radicals in the insulating film 516 can be diffused into the oxide semiconductor film 508, thereby filling oxygen defects in the oxide semiconductor film 508.

[0285] Through the above process, Fig. 14B Transistor 500 is shown.

[0286] <Method 2 for manufacturing semiconductor device>

[0287] Next, FIG. 10A to FIG. 14A Different manufacturing methods of the transistor 500 shown will be described below.

[0288] First, similarly to <Semiconductor device manufacturing method 1>, FIG. 10A to FIG. 12CThen, no Fig.13A , Fig. 13B , Fig.14A That is, Fig. 12C The structure shown has Fig. 14B and Fig. 14C The transistor 500 shown has the same function.

[0289] At this time, a metal oxide film is used as the first barrier film 531, and as the metal oxide film, aluminum oxide, hafnium oxide, or yttrium oxide is preferably formed.

[0290] When aluminum oxide, hafnium oxide, or yttrium oxide is formed by sputtering as the first barrier film 531, the sputtering gas preferably contains at least oxygen. When the first barrier film 531 is formed, oxygen is used as the sputtering gas, and the oxygen becomes oxygen radicals in the plasma, and either or both of the oxygen and the oxygen radicals may be added to the insulating film 516. Therefore, it is not necessary to perform sputtering. Fig.13A In other words, when forming the first barrier film 531, the oxygen addition process and the formation of the first barrier film 531 can be performed simultaneously. In addition, when forming the first barrier film 531 (especially in the initial stage of formation), the first barrier film 531 has the function of adding oxygen, and after the first barrier film 531 is formed, the first barrier film 531 has the function of blocking oxygen.

[0291] When aluminum oxide is formed as the first barrier film 531 by sputtering, for example, a mixed layer may be formed near the interface between the insulating film 516 and the first barrier film 531. When the insulating film 516 is a silicon oxynitride film, Al2O3 may be formed as the mixed layer. x Si y O z .

[0292] In addition, when aluminum oxide, hafnium oxide, or yttrium oxide is used as the first barrier film 531, aluminum oxide, hafnium oxide, and yttrium oxide have high insulation and high oxygen barrier properties. Fig. 13B The process of removing the first barrier film 531 is shown as well as Fig.14A Therefore, the first barrier film 531 has the same function as the insulating film 518.

[0293] In addition, by forming the first barrier film 531 by heating at a substrate temperature of less than 400° C., preferably less than 375° C., and more preferably 340° C. or more and 360° C. or less during film formation, excess oxygen or oxygen radicals added to the insulating film 516 can be diffused into the oxide semiconductor film 508. Alternatively, when heat treatment is performed at less than 400° C., preferably less than 375° C., and more preferably 340° C. or more and 360° C. or less after the first barrier film 531 is formed, excess oxygen or oxygen radicals added to the insulating film 516 can be diffused into the oxide semiconductor film 508.

[0294] In this way, by using aluminum oxide, hafnium oxide, or yttrium oxide as the first barrier film 531, the manufacturing process of the semiconductor device can be shortened, thereby reducing the manufacturing cost.

[0295] <Method 3 for manufacturing semiconductor device>

[0296] Next, refer to 17A to 17C A method for manufacturing the transistor 570 which is one embodiment of the present invention is described in detail. 17A to 17C It is a cross-sectional view for explaining a method for manufacturing a semiconductor device.

[0297] First, the same steps as those of the method for manufacturing the transistor 500 described above are performed (until FIG. 10A to FIG. 14A The process up to the process shown).

[0298] Next, a mask is formed on the insulating film 518 by a photolithography process, and an opening 542c is formed in a desired region of the insulating films 514, 516, and 518. In addition, a mask is formed on the insulating film 518 by a photolithography process, and openings 542a and 542b are formed in a desired region of the insulating films 506, 507, 514, 516, and 518. The opening 542c is formed so as to reach the conductive film 512b. In addition, the openings 542a and 542b are formed so as to both reach the conductive film 504 (see FIG. 1 ). Fig.17A ).

[0299] In addition, the openings 542a, 542b and the opening 542c may be formed in the same process or in different processes. When the openings 542a, 542b and the opening 542c are formed in the same process, for example, a gray tone mask or a half tone mask may be used. In addition, the openings 542a and 542b may be formed in multiple times. For example, the insulating films 506 and 507 may be processed, and then the insulating films 514, 516 and 518 may be processed.

[0300] Next, a conductive film 520 is formed on the insulating film 518 so as to cover the openings 542a, 542b, and 542c (see Fig. 17B ).

[0301] As the conductive film 520, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) can be used. In particular, the conductive film 520 can use a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, and indium tin silicon oxide (ITSO). In addition, for example, the conductive film 520 can be formed by sputtering. In this embodiment, ITSO with a thickness of 110 nm is formed by sputtering.

[0302] Next, a mask is formed on the conductive film 520 by a photolithography process, and the conductive film 520 is processed into a desired shape to form conductive films 520a and 520b (see FIG. Fig. 17C ).

[0303] Examples of a method for forming the conductive films 520a and 520b include dry etching, wet etching, or a method combining dry etching and wet etching. In this embodiment, the conductive film 520 is processed into the conductive films 520a and 520b using a wet etching method.

[0304] Through the above steps, we can produce Fig.16A and Fig. 16B Transistor 570 is shown.

[0305] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment as appropriate.

[0306] Implementation 3

[0307] In this embodiment, a structure of an oxide semiconductor included in a semiconductor device which is one embodiment of the present invention is described in detail.

[0308] <Structure of Oxide Semiconductor>

[0309] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semiconductor), a-like OS (amorphous like Oxide Semiconductor), and amorphous oxide semiconductors.

[0310] From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0311] As a definition of an amorphous structure, it is generally known that it is in a metastable state and is not fixed, has isotropy but does not have an inhomogeneous structure, etc. In other words, the bond angle of the amorphous structure is not fixed, has short-range order but does not have long-range order, etc.

[0312] From the opposite point of view, a substantially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. In addition, an oxide semiconductor that does not have isotropy (for example, having a periodic structure in a tiny region) cannot be called a completely amorphous oxide semiconductor. Note that a-like OS has a periodic structure in a tiny region, but also has voids (also called voids) and an unstable structure. Therefore, a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.

[0313] <caac-os>

[0314] First, CAAC-OS is described.

[0315] CAAC-OS is a type of oxide semiconductor including a plurality of c-axis-aligned crystal parts (also referred to as grains).

[0316] In the composite analysis image (also called high-resolution TEM image) of the bright field image and diffraction pattern of CAAC-OS obtained by observation using a transmission electron microscope (TEM), multiple particles are observed. However, in the high-resolution TEM image, no clear boundary between particles, i.e., grain boundary, is observed. Therefore, it can be said that in CAAC-OS, it is not easy to cause a decrease in electron mobility due to grain boundaries.

[0317] Next, CAAC-OS observed by TEM is described. Fig.19A A high-resolution TEM image of a cross section of the CAAC-OS obtained by observing from a direction roughly parallel to the sample surface is shown. The high-resolution TEM image is obtained using the spherical aberration corrector function. The high-resolution TEM image obtained using the spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be obtained using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0318] Fig.19B Show that Fig.19A A magnified Cs-corrected high-resolution TEM image of the region (1). Fig.19B It can be confirmed that metal atoms are arranged in layers in the particles. Each metal atom layer has a configuration reflecting the projections and depressions of the surface forming the CAAC-OS film (also referred to as the formed surface) or the top surface of the CAAC-OS and is arranged parallel to the formed surface or the top surface of the CAAC-OS.

[0319] like Fig.19B As shown, CAAC-OS has a unique atomic arrangement. Fig.19C A diagram showing a unique atomic arrangement with auxiliary lines. Fig.19B and Fig.19C It can be seen that the size of a particle is greater than 1 nm or greater than 3 nm, and the size of the gaps generated by the inclination between particles is about 0.8 nm. Therefore, the particles can also be called nanocrystals (nc). Note that CAAC-OS can also be called an oxide semiconductor with CANC (C-Axis Aligned nanocrystals: c-axis oriented nanocrystals).

[0320] Here, based on the Cs-corrected high-resolution TEM image, the configuration of the CAAC-OS particles 5100 on the substrate 5120 is schematically represented as a structure of accumulated bricks or blocks (see Fig.19D ).exist Fig.19C The tilt observed between particles is equivalent to Fig.19D Area 5161 shown.

[0321] also, Fig. 20A A Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface is shown. Fig. 20B , Fig. 20C and Fig.20D Show respectively Fig. 20A Cs-corrected high-resolution TEM images of areas (1), (2), and (3) in the image. Fig. 20B , Fig. 20C and Fig.20D It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape in the particles, but there is no regularity in the arrangement of the metal atoms between different particles.

[0322] Next, the CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of CAAC-OS including InGaZnO4 crystals is analyzed by the out-of-plane method, Fig.21A As shown, a peak often appears near the diffraction angle (2θ) of 31°. Since this peak originates from the (009) plane of InGaZnO4 crystal, it can be seen that the crystal in CAAC-OS has c-axis orientation, and the c-axis is roughly perpendicular to the direction of the formed surface or top surface.

[0323] Note that when the structure of CAAC-OS is analyzed using the out-of-plane method, in addition to the peak near 2θ of 31°, a peak sometimes appears near 2θ of 36°. The peak near 2θ of 36° indicates that a portion of CAAC-OS contains crystals that do not have c-axis orientation. Preferably, in the structure of CAAC-OS analyzed using the out-of-plane method, a peak appears near 2θ of 31° and no peak appears near 2θ of 36°.

[0324] On the other hand, when the structure of CAAC-OS is analyzed using the in-plane method in which X-rays are incident on the sample from a direction roughly perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. In CAAC-OS, even if 2θ is fixed to around 56° and the sample is rotated with the normal vector of the sample plane as the axis (φ axis), the analysis (φ scan) is still the same. Fig. 21B In contrast, in a single crystal oxide semiconductor of InGaZnO4, when φ scanning is performed with 2θ fixed at around 56°, as shown in FIG. Fig. 21C As shown, six peaks derived from a crystal plane equivalent to the (110) plane were observed. Therefore, it was confirmed from the structural analysis using XRD that there was no regularity in the orientation of the a-axis and the b-axis in CAAC-OS.

[0325] Next, the CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a beam diameter of 300 nm is incident on a CAAC-OS containing InGaZnO4 crystals in a direction parallel to the sample surface, the obtained Fig. 22 The diffraction pattern shown in A (also called selected area transmission electron diffraction pattern). The diffraction pattern contains spots caused by the (009) plane of InGaZnO4 crystal. Therefore, it can be seen from electron diffraction that the particles contained in CAAC-OS have c-axis orientation, and the c-axis is roughly perpendicular to the direction of the formed surface or top surface. On the other hand, Fig. 22 B shows the diffraction pattern of the same sample when an electron beam with a beam diameter of 300 nm is incident on the sample in a direction perpendicular to the sample surface. Fig. 22 B observed a ring-shaped diffraction pattern. Therefore, it can be seen from electron diffraction that the a-axis and b-axis of the particles contained in CAAC-OS are not oriented. Fig. 22 The first ring in B originates from the (010) and (100) planes of the InGaZnO4 crystal. Fig. 22 The second ring in B originates from the (110) plane, etc.

[0326] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be reduced due to the mixing of impurities or the generation of defects, from the opposite point of view, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (oxygen defects, etc.).

[0327] In addition, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, elements such as silicon that have a stronger bond with oxygen than the metal elements that constitute the oxide semiconductor will take away oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity. In addition, since heavy metals such as iron or nickel, argon, carbon dioxide, etc. have large atomic radii (or molecular radii), they will disrupt the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity.

[0328] When an oxide semiconductor contains impurities or defects, its properties may change due to light or heat. For example, impurities contained in an oxide semiconductor may sometimes become a carrier trap or a carrier generation source. In addition, oxygen defects in an oxide semiconductor may sometimes become a carrier trap or a carrier generation source by capturing hydrogen.

[0329] CAAC-OS with few impurities and oxygen defects is an oxide semiconductor with low carrier density. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and defect state density. In other words, it can be said that CAAC-OS is an oxide semiconductor with stable characteristics.

[0330] <nc-os>

[0331] Next, nc-OS will be described.

[0332] In the high-resolution TEM image of nc-OS, there are areas where the crystalline part can be observed and areas where no clear crystalline part is observed. The size of the crystalline part contained in nc-OS is mostly greater than 1nm and less than 10nm or greater than 1nm. Note that oxide semiconductors whose crystalline part size is greater than 10nm and less than 100nm are sometimes called microcrystalline oxide semiconductors. For example, in the high-resolution TEM image of nc-OS, the grain boundary is sometimes not clearly observed. Note that the source of the nanocrystals may be the same as the particles in CAAC-OS. Therefore, the crystalline part of nc-OS is sometimes referred to as a particle below.

[0333] In nc-OS, the atomic arrangement in a tiny region (for example, a region greater than 1 nm and less than 10 nm, especially a region greater than 1 nm and less than 3 nm) has periodicity. In addition, no regularity of crystal orientation is observed between different particles in nc-OS. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-likeOS or amorphous oxide semiconductors in certain analysis methods. For example, when the nc-OS is structurally analyzed using the out-of-plane method using X-rays whose beam diameter is larger than the particles, no peak representing the crystal plane is detected. When electron diffraction is performed on nc-OS using an electron beam whose beam diameter is larger than the particles (for example, greater than 50 nm), a diffraction pattern similar to a halo pattern is observed. On the other hand, when nanobeam electron diffraction is performed on nc-OS using an electron beam whose beam diameter is close to or smaller than the particles, spots are observed. In addition, in the nanobeam electron diffraction pattern of nc-OS, (ring-shaped) areas of high brightness such as circles are sometimes observed. Furthermore, in the nanobeam electron diffraction pattern of nc-OS, a plurality of spots are sometimes observed in a ring-shaped region.

[0334] Since there is no regularity in the crystal orientation among particles (nanocrystals), nc-OS can also be called an oxide semiconductor including RANC (Random Aligned nanocrystals) or an oxide semiconductor including NANC (Non-Aligned nanocrystals).

[0335] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, the defect state density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductors. However, the regularity of crystal orientation is not observed between different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

[0336] <a-like OS>

[0337] An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.

[0338] In the high-resolution TEM image of a-like OS, voids are sometimes observed. In addition, in the high-resolution TEM image, there are regions where the crystal part can be clearly observed and regions where the crystal part cannot be observed.

[0339] Since a-like OS contains voids, its structure is unstable. In order to prove that a-like OS has an unstable structure compared with CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0340] As samples to be irradiated with electrons, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) were prepared. Each sample was an In-Ga-Zn oxide.

[0341] First, a high-resolution cross-sectional TEM image of each sample was obtained. From the high-resolution cross-sectional TEM image, it was found that each sample had a crystal part.

[0342] Note that which part is to be regarded as a crystal part is determined as follows. For example, it is known that the unit lattice of InGaZnO4 crystal has a structure in which nine layers including three In-O layers and six Ga-Zn-O layers are stacked in layers in the c-axis direction. The spacing between these layers close to each other is almost equal to the lattice surface spacing of the (009) plane (also called d value), and its value is 0.29nm obtained by crystal structure analysis. Therefore, the part with a lattice fringe spacing of more than 0.28nm and less than 0.30nm can be regarded as an InGaZnO4 crystal part. Each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0343] Fig.23 The example of the average crystal size of the crystal parts (22 parts to 45 parts) of each sample is shown. Note that the crystal part size corresponds to the length of the lattice fringes mentioned above. Fig.23 It can be seen that in a-like OS, the crystal part gradually increases according to the cumulative electron dose. Fig.23 As shown in (1) of FIG. 1 , it can be seen that the initial crystal size of about 1.2 nm (also called the initial crystal nucleus) observed by TEM is 4.2×10 8 e - / nm 2 On the other hand, it can be seen that the cumulative irradiation dose of nc-OS and CAAC-OS from the start of electron irradiation to 4.2×10 8 e - / nm 2 In the range of , the size of the crystal part does not change. Fig.23 As shown in (2) and (3) in FIG. 1 , it can be seen that regardless of the cumulative irradiation dose of electrons, the average crystal size of nc-OS and CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively.

[0344] Thus, sometimes electron irradiation causes the growth of crystal parts in a-like OS. On the other hand, it can be seen that there is almost no growth of crystal parts caused by electron irradiation in nc-OS and CAAC-OS. In other words, a-like OS has an unstable structure compared with CAAC-OS and nc-OS.

[0345] In addition, since a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is greater than 78.6% and less than 92.3% of a single crystal oxide semiconductor having the same composition. The density of nc-OS and the density of CAAC-OS are greater than 92.3% and less than 100% of a single crystal oxide semiconductor having the same composition. Note that it is difficult to form an oxide semiconductor whose density is less than 78% of the density of a single crystal oxide semiconductor.

[0346] For example, in an oxide semiconductor where the atomic ratio satisfies In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4 with a rhombohedral structure is 6.357 g / cm 3 Therefore, for example, in an oxide semiconductor where the atomic ratio satisfies In:Ga:Zn=1:1:1, the density of a-like OS is 5.0 g / cm 3 Above and less than 5.9g / cm 3 In addition, for example, in an oxide semiconductor where the atomic ratio satisfies In:Ga:Zn=1:1:1, the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 Above and less than 6.3g / cm 3 .

[0347] Note that sometimes there are no single crystal oxide semiconductors with the same composition. In this case, by combining single crystal oxide semiconductors with different compositions in an arbitrary ratio, the density of the single crystal oxide semiconductor equivalent to the desired composition can be estimated. The density of the single crystal oxide semiconductor equivalent to the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferred to reduce the types of single crystal oxide semiconductors combined as much as possible to calculate the density.

[0348] As described above, oxide semiconductors have various structures and various characteristics. Note that the oxide semiconductor may be, for example, a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0349] Implementation 4

[0350] In this embodiment, using Figure 24 to Figure 26 An example of a display device including the transistor described in the above embodiment mode will be described.

[0351] Fig.24 is a plan view showing an example of a display device. Fig.24 The display device 700 shown includes: a pixel portion 702 arranged on a first substrate 701; a source driver circuit portion 704 and a gate driver circuit portion 706 arranged on the first substrate 701; a sealant 712 arranged in a manner surrounding the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706; and a second substrate 705 arranged in a manner opposite to the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. In other words, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Note that although in Fig.24 Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705.

[0352] In addition, in the display device 700, an FPC (Flexible printed circuit) terminal portion 708 electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in an area on the first substrate 701 that is not surrounded by the sealant 712. In addition, the FPC terminal portion 708 is connected to the FPC 716, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. In addition, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 are each connected to the wiring 710. Various signals supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the wiring 710.

[0353] In addition, a plurality of gate drive circuit units 706 may be provided in the display device 700. In addition, as the display device 700, although an example is shown in which the source drive circuit unit 704 and the gate drive circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, it is not limited to this structure. For example, only the gate drive circuit unit 706 may be formed on the first substrate 701, or only the source drive circuit unit 704 may be formed on the first substrate 701. In this case, a structure in which a substrate having a source drive circuit or a gate drive circuit formed thereon (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted on the first substrate 701 may also be adopted. In addition, there is no particular limitation on the connection method of the separately formed drive circuit substrate, and a COG (Chip On Glass) method, a wire bonding method, or the like may be adopted.

[0354] The pixel portion 702 , the source driver circuit portion 704 , and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors, and the transistors described in Embodiment 2 can be used as the transistors.

[0355] In addition, the display device 700 can be in various ways or have various display elements. As display elements, for example, liquid crystal elements, EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL elements or inorganic EL elements) including LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron emission elements, electrophoretic elements, display elements using micro-electromechanical systems (MEMS) such as grating light valves (GLV), digital micromirror devices (DMDs), digital micro shutters (DMS) elements, MIRASOL (registered trademark) displays, interferometric modulation (IMOD) elements, piezoelectric ceramic displays, etc., electrowetting (electrowetting) elements, etc. In addition, display media that change due to electrical or magnetic effects such as contrast, brightness, reflectivity, and transmittance can also be included. In addition, quantum dots can also be used as display elements. As examples of display devices using liquid crystal elements, there are liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays), etc. As an example of a display device using EL elements, there are EL displays, etc. As an example of a display device using electron emission elements, there are field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display: surface-conduction electron emission display), etc. As an example of a display device using quantum dots, there are quantum dot displays, etc. As an example of a display device using electronic ink or electrophoretic elements, there are electronic paper, etc. Note that when a semi-transmissive liquid crystal display or a reflective liquid crystal display is implemented, part or all of the pixel electrode can function as a reflective electrode. For example, part or all of the pixel electrode can contain aluminum, silver, etc. In addition, at this time, a storage circuit such as SRAM can also be set under the reflective electrode. Thereby, power consumption can be further reduced.

[0356] As a display mode of the display device 700, a progressive scanning mode or an interlaced scanning mode can be adopted. In addition, the color element controlled in the pixel when performing color display is not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it can be composed of four pixels of R pixel, G pixel, B pixel and W (white) pixel. Or, as in the PenTile arrangement, one color element can be composed of two colors in RGB, and two different colors can be selected according to the color element. Or one or more colors such as yellow, cyan, magenta, etc. can be added to RGB. In addition, the size of the display area of ​​each color element point can be different. However, the disclosed invention is not limited to a display device for color display, but can also be applied to a display device for black and white display.

[0357] In addition, in order to use white light (W) for backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) to enable the display device to display in full color, a coloring layer (also called a filter) can also be used. As a coloring layer, for example, red (R), green (G), blue (B), yellow (Y), etc. can be used in appropriate combinations. By using a coloring layer, the color reproducibility can be further improved compared to the case where a coloring layer is not used. At this time, it is also possible to directly use white light in the area that does not include the coloring layer for display by setting an area including the coloring layer and an area that does not include the coloring layer. By partially setting an area that does not include the coloring layer, when displaying a bright image, the brightness reduction caused by the coloring layer can sometimes be reduced and the power consumption can be reduced by about 20% to 30%. However, when using self-luminous elements such as organic EL elements or inorganic EL elements for full-color display, R, G, B, Y, and white (W) can also be emitted from elements with each luminous color. By using a self-luminous element, power consumption can sometimes be further reduced compared to the case where a coloring layer is used.

[0358] In this embodiment, using Fig.25 and Fig.26 The structure of a display device using a VA (vertical alignment) type liquid crystal element as a display element is described. VA type refers to a method of controlling the arrangement of liquid crystal molecules in a display device. A VA type liquid crystal display device is a normally black display device in which the liquid crystal molecules are oriented in a direction perpendicular to the panel surface when no voltage is applied. In the display device shown in this embodiment, one pixel is divided into several regions (sub-pixels) and the liquid crystal molecules are tilted in different directions. This is called multi-domain or multi-domain design.

[0359] Fig.25 yes Fig.24 A cross-sectional view between the dot-dash line QR is shown. Fig.25 The display device 700 shown includes: a routing wiring section 711; a pixel section 702; a source driver circuit section 704; and an FPC terminal section 708. In addition, the routing wiring section 711 includes a wiring 710. In addition, the pixel section 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit section 704 includes a transistor 752.

[0360] As the transistor 750 and the transistor 752 , the transistors described in Embodiment 2 can be used.

[0361] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which the formation of oxygen defects is suppressed. The transistor can reduce the current value in the off state (off-state current value). Therefore, the retention time of electrical signals such as image signals can be extended, and the write interval can also be extended in the state where the power is turned on. Therefore, the frequency of refresh work can be reduced, thereby achieving the effect of suppressing power consumption.

[0362] In addition, the transistor used in this embodiment can obtain a higher field effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driving transistor for a driving circuit portion can be formed on the same substrate. In other words, since a semiconductor device formed of a silicon wafer or the like does not need to be used separately as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, a high-quality image can also be provided in the pixel portion by using a transistor capable of high-speed driving.

[0363] The capacitor 790 has a structure having a dielectric between a pair of electrodes. More specifically, one electrode of the capacitor 790 uses a conductive film formed by the same process as the conductive film used as the gate electrode of the transistor 750, and the other electrode of the capacitor 790 uses a conductive film used as the source electrode and drain electrode of the transistor 750. In addition, the dielectric sandwiched between the pair of electrodes uses an insulating film used as the gate insulating film of the transistor 750.

[0364] In addition, Fig.25 In the embodiment of the present invention, insulating films 764 , 766 , and 768 and a planarizing insulating film 770 are provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0365] The insulating films 764, 766, and 768 can be formed using the same material and manufacturing method as the insulating films 514, 516, and 518 described in Embodiment 2. As the planarization insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, an epoxy resin, etc. can be used. The planarization insulating film 770 can also be formed by stacking a plurality of insulating films formed of these materials. In addition, a structure without the planarization insulating film 770 can also be used.

[0366] The wiring 710 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The wiring 710 may be formed using a conductive film formed in a different process from the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752, such as a conductive film used as a gate electrode. For example, when a material containing copper is used as the wiring 710, signal delay due to wiring resistance is reduced, and a large-screen display can be realized.

[0367] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The connection electrode 760 and the terminal included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0368] Note that a glass substrate, for example, can be used as the first substrate 701 and the second substrate 705. Note that the first substrate 701 and the second substrate 705 can be made of the same material as the substrate 502 described in Embodiment 2.

[0369] On the second substrate 705 side, a light-shielding film 738 serving as a black matrix, a coloring layer 736 serving as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the coloring layer 736 are provided.

[0370] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film and is used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may be used as the structure 778.

[0371] In addition, if Fig.26 As shown, a stack of multiple coloring layers 736 may be used as a spacer instead of the structure 778. For example, Fig.26 The display device 700 shown includes a red coloring layer 736R, a green coloring layer 736G, and a blue coloring layer 736B. The coloring layer 736G and the coloring layer 736B are provided on the coloring layer 736R at a position overlapping with the light shielding film 738. By adopting such a structure, the step of forming the structure 778 can be omitted. In addition, Fig.26 The display device 700 shown does not include the insulating film 734. Alternatively, as the spacer, a stack of any two of the coloring layer 736R, the coloring layer 736G, and the coloring layer 736B may be used.

[0372] In this embodiment, the structure 778 is provided on the first substrate 701 side, but the present invention is not limited to this. For example, the structure 778 may be provided on the second substrate 705 side or on both the first substrate 701 and the second substrate 705.

[0373] The display device 700 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and serves as a counter electrode. The display device 700 can display an image by changing the orientation state of the liquid crystal layer 776 by applying a voltage to the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light. A protrusion 744 is provided on the conductive film 774.

[0374] The conductive film 772 is connected to the conductive film used as the source electrode and the drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770 and used as a pixel electrode, that is, an electrode of the display element. In addition, the conductive film 772 has the function of a reflective electrode. The display device 700 is a so-called reflective color liquid crystal display device in which external light is reflected by the conductive film 772 and displayed through the coloring layer 736.

[0375] In addition, as the conductive film 772, a conductive film that is translucent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is translucent to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film that is reflective to visible light, for example, a material containing aluminum or silver is preferably used. In this embodiment, a conductive film that is reflective to visible light is used as the conductive film 772.

[0376] In addition, when a conductive film that is reflective to visible light is used, the conductive film 772 may also have a stacked structure. For example, an aluminum film having a thickness of 100 nm is formed as a lower layer, and a silver alloy film (e.g., an alloy film containing silver, palladium, and copper) having a thickness of 30 nm is formed as an upper layer. By adopting the above structure, the following excellent effects are exerted.

[0377] The above-mentioned excellent effects are as follows: (1) the adhesion between the base film and the conductive film 772 can be improved; (2) the aluminum film and the silver alloy film can be etched together using a chemical solution; (3) the cross-sectional shape of the conductive film 772 can be made into a good shape (for example, a tapered shape). The reason for (3) is considered to be as follows: when etching is performed using a chemical solution, the etching speed of the aluminum film is slower than that of the silver alloy film, or when the lower aluminum film is exposed after the upper silver alloy film is etched, electrons are extracted from the metal that is cheaper than the silver alloy film, in other words, aluminum with a high ionization tendency, thereby suppressing the etching of the silver alloy film and accelerating the etching of the lower aluminum film.

[0378] In addition, as Figure 25 to Figure 27 The display device 700 shown in the figure is a reflective color liquid crystal display device, but the display device 700 is not limited to this. For example, a transmissive color liquid crystal display device using a conductive film having light transmittance to visible light as the conductive film 772 may also be used. In the case where the display device 700 is a transmissive liquid crystal display device, a pair of electrodes included in the capacitor element 790 is set at a position that does not overlap with the conductive film 772. In addition, each layer provided in the path of light incident from the substrate 701 through the liquid crystal element 775 and the coloring layer 736 is preferably a layer having light transmittance to visible light.

[0379] The conductive film 772 includes a slit 725. The slit 725 is provided to control the orientation of liquid crystal molecules. An orientation film 746 is provided on the conductive film 772, the planarization insulating film 770, and the structure 778. Similarly, an orientation film 748 is provided on the conductive film 774.

[0380] When a voltage is applied to the conductive film 772 formed with the slit 725, an electric field strain (inclined electric field) is generated near the slit 725. By arranging the slit 725 and the protrusion 744 on the side of the substrate 705 in a manner that they are interlocked with each other, an inclined electric field is effectively generated and the orientation of the liquid crystal is controlled, and the orientation of the liquid crystal is made different according to each position. That is, by making the liquid crystal molecules invert in different directions in each sub-pixel included in one pixel, multi-domain formation is performed, thereby expanding the viewing angle of the liquid crystal display panel.

[0381] In addition, although Fig.25 Although not shown in the figure, optical components (optical substrates) such as polarization components, phase difference components, and anti-reflection components may be appropriately provided. For example, circular polarization using a polarization substrate and a phase difference substrate may also be used. In addition, backlight, side light, etc. may also be used as a light source.

[0382] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0383] Implementation method 5

[0384] In this embodiment, refer to Fig. 27 A display module and an electronic device including a semiconductor device according to one embodiment of the present invention are described through FIG. 28 .

[0385] Fig. 27 The display module 8000 shown includes a touch panel 8004 connected to an FPC 8003 , a display panel 8006 connected to an FPC 8005 , a backlight 8007 , a frame 8009 , a printed circuit board 8010 , and a battery 8011 between an upper cover 8001 and a lower cover 8002 .

[0386] The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0387] The shapes and sizes of the upper cover 8001 and the lower cover 8002 may be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

[0388] The touch panel 8004 may be a resistive film touch panel or an electrostatic capacitive touch panel, and may be formed in a manner overlapping with the display panel 8006. In addition, the opposing substrate (sealing substrate) of the display panel 8006 may also have a touch panel function. In addition, a light sensor may be provided in each pixel of the display panel 8006 to form an optical touch panel.

[0389] Backlight 8007 includes light source 8008. Note that although Fig. 27 2 shows a structure in which the light source 8008 is arranged on the backlight 8007, but the present invention is not limited thereto. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusion plate may be used. When a self-luminous light-emitting element such as an organic EL element is used, or when a reflective panel is used, a structure in which the backlight 8007 is not arranged may be adopted.

[0390] The frame 8009 has a function of protecting the display panel 8006 and also has an electromagnetic shielding function for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. In addition, the frame 8009 may also have a function of a heat sink.

[0391] The printed circuit board 8010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, either an external commercial power supply or a separately provided battery 8011 can be used. When a commercial power supply is used, the battery 8011 can be omitted.

[0392] In addition, components such as a polarizing plate, a phase difference plate, and a prism sheet may also be provided in the display module 8000 .

[0393] FIG. 28A to FIG. 28G 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, an operation key 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 (having a function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 5008, etc.

[0394] Fig.28A A mobile computer is shown, which may include a switch 5009, an infrared port 5010, etc. in addition to the above. Fig.28B A portable image reproduction device (for example, a DVD reproduction device) provided with a recording medium is shown, and the portable image reproduction device may include a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above. Fig.28C A goggle-type display is shown, which may include a second display portion 5002, a support portion 5012, headphones 5013, etc. in addition to the above. Fig.28D The portable game machine is shown, and the portable game machine may include a recording medium reading unit 5011 and the like in addition to the above. Fig.28E A digital camera having a television reception function is shown, and the digital camera may include an antenna 5014, a shutter button 5015, an image receiving unit 5016, and the like in addition to the above. Fig.28F 2004 , a portable game machine is shown, which may include a second display portion 5002 , a recording medium reading portion 5011 , and the like in addition to the above. Figure 28G A portable television receiver is shown, which may include a charger 5017 capable of transmitting and receiving signals, etc. in addition to the above.

[0395] FIG. 28A to FIG. 28G The electronic device shown may have various functions. For example, it may have the following functions: displaying various data (static images, dynamic images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date or time, etc.; controlling processing by utilizing various software (programs); performing wireless communications; connecting to various computer networks by utilizing a wireless communication function; sending or receiving various data by utilizing a wireless communication function; reading out programs or data stored in a recording medium to display them on a display unit, etc. Furthermore, in an electronic device having multiple display units, it may have the following functions: one display unit mainly displays image data, while another display unit mainly displays text data; or, images that take parallax into account are displayed on multiple display units to display stereoscopic images, etc. Furthermore, in an electronic device having an image receiving unit, it may have the following functions: capturing static images; capturing dynamic images; automatically or manually correcting captured images; storing captured images in a recording medium (external or built into a camera); displaying captured images on a display unit, etc. Note that, FIG. 28A to FIG. 28G The functions that the electronic device shown may have are not limited to the above functions, but may have various functions.

[0396] The electronic device described in this embodiment mode has a display portion for displaying certain information. The display device described in Embodiment Mode 4 can be appropriately applied to the display portion.

[0397] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0398] Explanation of symbols

[0399] 100 pixels

[0400] 101 Substrate

[0401] 103 scan lines

[0402] 105a Capacitor wiring

[0403] 105b Capacitor wiring

[0404] 107 Gate insulating film

[0405] 107a Gate insulating film

[0406] 107b Gate insulating film

[0407] 114 Insulation film

[0408] 116 Insulation film

[0409] 116a Insulation film

[0410] 116b Insulation film

[0411] 116c Insulation film

[0412] 121 signal line

[0413] 123 Electrode

[0414] 125a Electrode

[0415] 125b Electrode

[0416] 135 Semiconductor Film

[0417] 135a Oxide semiconductor film

[0418] 135b Oxide semiconductor film

[0419] 136 Transistors

[0420] 137 Transistor

[0421] 139a Pixel electrode

[0422] 139b Pixel electrode

[0423] 140 Capacitor Components

[0424] 141 Capacitor Components

[0425] 142 Liquid crystal element

[0426] 143 Liquid crystal element

[0427] 144a Opening

[0428] 144b Opening

[0429] 145 Capacitor Components

[0430] 146 Capacitor Components

[0431] 148 pixel electrodes

[0432] 148a Oxide conductor film

[0433] 148b Oxide conductor film

[0434] 149 pixel electrodes

[0435] 200 pixels

[0436] 203 scan lines

[0437] 221 signal line

[0438] 223a Electrode

[0439] 223b Electrode

[0440] 236 Transistors

[0441] 237 Transistor

[0442] 300 pixels

[0443] 301 substrate

[0444] 303 scan lines

[0445] 305a Capacitor wiring

[0446] 305b Capacitor wiring

[0447] 307 Gate insulation film

[0448] 316 Insulation film

[0449] 321 signal line

[0450] 323a Electrode

[0451] 323b Electrode

[0452] 325a Electrode

[0453] 325b Electrode

[0454] 335 Semiconductor Film

[0455] 336 Transistors

[0456] 337 Transistor

[0457] 339a Pixel electrode

[0458] 339b Pixel electrode

[0459] 340 Capacitor Components

[0460] 341 Capacitor Components

[0461] 342 Liquid crystal element

[0462] 343 Liquid crystal element

[0463] 344a Opening

[0464] 344b Opening

[0465] 345a Electrode

[0466] 345b Electrode

[0467] 346a Opening

[0468] 346b Opening

[0469] 500 transistors

[0470] 502 substrate

[0471] 504 Conductive film

[0472] 506 Insulation film

[0473] 507 Insulation Film

[0474] 508 Oxide semiconductor film

[0475] 508a Oxide semiconductor film

[0476] 508b Oxide semiconductor film

[0477] 509 Oxide semiconductor film

[0478] 509a Oxide semiconductor film

[0479] 509b Oxide semiconductor film

[0480] 512 Conductive film

[0481] 512a Conductive film

[0482] 512b Conductive film

[0483] 514 Insulation film

[0484] 516 Insulation film

[0485] 518 Insulation film

[0486] 519 Insulation Film

[0487] 520 Conductive film

[0488] 520a Conductive film

[0489] 520b Conductive film

[0490] 531 Barrier Film

[0491] 536a Mask

[0492] 536b Mask

[0493] 538 Etching Agent

[0494] 539 Etching Agent

[0495] 540 Oxygen

[0496] 540a Oxygen

[0497] 542 Etching Agent

[0498] 542a Opening

[0499] 542b Opening

[0500] 542c Opening

[0501] 570 transistors

[0502] 700 Display Device

[0503] 701 Substrate

[0504] 702 Pixel Department

[0505] 704 Source driver circuit

[0506] 705 substrate

[0507] 706 Gate drive circuit unit

[0508] 708 FPC terminal

[0509] 710 Wiring

[0510] 711 Wiring Department

[0511] 712 Sealant

[0512] 716 FPC

[0513] 725 Slit

[0514] 734 Insulation film

[0515] 736 Coloring Layer

[0516] 736B Coloring layer

[0517] 736G Coloring Layer

[0518] 736R Coloring Layer

[0519] 738 shading film

[0520] 744 Protrusion

[0521] 746 Oriented Film

[0522] 748 Oriented Film

[0523] 750 transistors

[0524] 752 transistors

[0525] 760 Connecting electrodes

[0526] 764 Insulation film

[0527] 766 Insulation film

[0528] 768 Insulation film

[0529] 770 Planarization insulation film

[0530] 772 Conductive film

[0531] 774 Conductive film

[0532] 775 Liquid crystal element

[0533] 776 Liquid crystal layer

[0534] 778 Structure

[0535] 780 Anisotropic Conductive Film

[0536] 790 Capacitor Components

[0537] 5000 Housing

[0538] 5001 Display

[0539] 5002 Display unit

[0540] 5003 Speaker

[0541] 5004 LED Light

[0542] 5005 Operation keys

[0543] 5006 Connection Terminal

[0544] 5007 Sensor

[0545] 5008 Microphone

[0546] 5009 Switch

[0547] 5010 Infrared port

[0548] 5011 Recording medium reading unit

[0549] 5012 support part

[0550] 5013 Headphones

[0551] 5014 Antenna

[0552] 5015 Shutter button

[0553] 5016 Image Receiving Unit

[0554] 5017 Charger

[0555] 5100 particles

[0556] 5120 Substrate

[0557] 5161 Area

[0558] 8000 Display Module

[0559] 8001 Cover

[0560] 8002 Lower cover

[0561] 8003 FPC

[0562] 8004 Touch Panel

[0563] 8005 FPC

[0564] 8006 Display Panel

[0565] 8007 Backlight

[0566] 8008 Light Source

[0567] 8009 Framework

[0568] 8010 Printed Circuit Board

[0569] 8011 Battery

Claims

1. A semiconductor device comprising: A pixel, the pixel comprising: a first transistor; a second transistor; a first pixel electrode electrically connected to the first transistor; and a second pixel electrode electrically connected to the second transistor, wherein the first conductive layer is in contact with the substrate and has a first region serving as a gate electrode of the first transistor and a second region serving as a gate electrode of the second transistor, The second conductive layer contacts the substrate and comprises the same material as the first conductive layer. Wherein, a gate insulating layer is disposed on the first conductive layer and the second conductive layer, wherein the semiconductor layer is disposed on the gate insulating layer and includes a channel formation region of the first transistor and a channel formation region of the second transistor, wherein the third conductive layer is disposed on the semiconductor layer and includes a first region serving as one of a source electrode and a drain electrode of the first transistor and a second region serving as one of a source electrode and a drain electrode of the second transistor, wherein the fourth conductive layer is provided on the semiconductor layer and includes a region serving as the other of the source electrode and the drain electrode of the first transistor, Wherein, the first insulating layer is arranged on the third conductive layer and the fourth conductive layer, The second conductive layer includes a first region, a second region, and a third region between the first region and the second region. Wherein, in the top-view direction of the pixel, the first region of the second conductive layer includes a region overlapping with a first contact hole provided in the first insulating layer, wherein the first region of the second conductive layer comprises a first width, Wherein, in the top-view direction of the pixel, the second region of the second conductive layer includes a region overlapping with a second contact hole provided in the gate insulating layer, wherein the second region of the second conductive layer comprises a second width, Wherein, in the top-view direction of the pixel, the third region of the second conductive layer includes a third width, wherein the first width is greater than the second width, wherein the second width is greater than the third width, The fourth conductive layer includes a region overlapping with the first contact hole and not overlapping with the second contact hole, and Wherein, the first pixel electrode includes a region overlapping with the second contact hole.

2. The semiconductor device according to claim 1, in, The second conductive layer serves as one electrode of the capacitive element.

3. The semiconductor device according to claim 1, in, The fourth conductive layer serves as one electrode of the capacitive element.

Images