Data processing calibration method, device, chip, equipment, medium, product

Abstract

The present application provides a calibration method, device, chip, equipment, medium, and product for data processing, and the relevant embodiments can be applied to various scenarios such as cloud technology, artificial intelligence, and smart transportation. The calibration method for data processing includes: performing measurement processing based on a clock measurement unit during data processing to obtain multiple measurement clock cycles; the measurement clock cycle is used to represent multiple clock measurement units; according to the number of clock measurement units represented by the multiple measurement clock cycles, determining whether there is clock drift between the multiple measurement clock cycles; when there is clock drift between the multiple measurement clock cycles, determining the delay parameter for the clock drift based on at least part of the measurement clock cycles with the latest measurement time in the multiple measurement clock cycles; and performing clock calibration processing during the data processing according to the delay parameter. The present application can improve the accuracy of data processing and effectively avoid the problem of data processing errors caused by clock drift.

Description

Technical Field

[0001] The present application relates to electronic technology, and in particular to a calibration method, device, chip, equipment, medium, and product for data processing. Background Art

[0002] With the rapid development of electronic technology, the computing power of various electronic devices is also rapidly increasing. Taking High Bandwidth Memory (HBM) chips as an example, data transmission speeds can reach 2Gbps using a 16nm process, 2.4Gbps using a 7nm process, and 3.2Gbps or even 3.6Gbps using a 5nm process.

[0003] Efficient data transmission also requires a higher operating frequency. For example, HBM PHY can reach a maximum integrated operating frequency of approximately 1.8 GHz. At such a high operating frequency, even slight changes in the operating environment of electronic devices can cause clock drift within the device, leading to pessimistic data eye diagrams and a significantly increased likelihood of data processing errors.

[0004] In this regard, relevant technologies have not yet provided an effective solution. Summary of the Invention

[0005] The embodiments of the present application provide a data processing calibration method, device, chip, electronic device, computer-readable storage medium and computer program product, which can perform clock calibration in a timely manner when clock drift occurs, thereby improving the accuracy of data processing and avoiding errors.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] The present invention provides a data processing calibration method, including:

[0008] During data processing, measurement processing is performed based on the clock measurement unit to obtain multiple measurement clock cycles; wherein the measurement clock cycle is used to represent the multiple clock measurement units;

[0009] determining, based on the number of clock measurement units respectively represented by the multiple measurement clock cycles, whether there is clock drift between the multiple measurement clock cycles;

[0010] When clock drift exists between the multiple measurement clock cycles, determining a delay parameter for the clock drift according to at least a portion of the measurement clock cycles with the latest measurement time among the multiple measurement clock cycles;

[0011] A clock calibration process is performed during the data processing according to the delay parameter.

[0012] The present invention provides a data processing calibration device, comprising:

[0013] A measurement module, configured to perform measurement processing based on the clock measurement unit during data processing to obtain a plurality of measurement clock cycles; wherein the measurement clock cycle is used to represent a plurality of the clock measurement units;

[0014] a drift determination module, configured to determine whether there is clock drift between the plurality of measurement clock cycles according to the number of clock measurement units respectively represented by the plurality of measurement clock cycles;

[0015] a parameter determination module configured to, when clock drift exists between the plurality of measurement clock cycles, determine a delay parameter for the clock drift based on at least a portion of the measurement clock cycles having the latest measurement time among the plurality of measurement clock cycles;

[0016] A clock calibration module is used to perform clock calibration processing during the data processing according to the delay parameter.

[0017] An embodiment of the present application provides a chip, which includes at least one of a programmable logic circuit and an executable instruction. The chip runs in an electronic device to implement the data processing calibration method provided in the embodiment of the present application.

[0018] An embodiment of the present application provides an electronic device, including:

[0019] a memory for storing executable instructions;

[0020] The processor is used to implement the data processing calibration method provided in the embodiment of the present application when executing the executable instructions stored in the memory.

[0021] An embodiment of the present application provides a computer-readable storage medium storing executable instructions for causing a processor to execute the calibration method for data processing provided in the embodiment of the present application.

[0022] An embodiment of the present application provides a computer program product, including executable instructions, which, when executed by a processor, implement the data processing calibration method provided in the embodiment of the present application.

[0023] The embodiments of the present application have the following beneficial effects:

[0024] During data processing, measurement processing is performed based on clock measurement units, and the number of clock measurement units is used to represent clock cycles, achieving accurate measurement of clock cycles. When clock drift exists between multiple measured clock cycles, a delay parameter is determined based on at least a portion of the multiple measured clock cycles with the latest measured time, thereby performing clock calibration. This improves data processing accuracy and effectively avoids data processing errors caused by clock drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the data processing calibration system provided in an embodiment of the present application;

[0026] Figure 2 This is a schematic diagram of the architecture of a terminal device provided in an embodiment of the present application;

[0027] Figure 3A 1 is a flow chart of a calibration method for data processing provided in an embodiment of the present application;

[0028] Figure 3B 1 is a flow chart of a calibration method for data processing provided in an embodiment of the present application;

[0029] Figure 3C 1 is a flow chart of a calibration method for data processing provided in an embodiment of the present application;

[0030] Figure 3D 1 is a flow chart of a calibration method for data processing provided in an embodiment of the present application;

[0031] Figure 4 1 is a timing diagram of a read operation in a chip provided in an embodiment of the present application;

[0032] Figure 5 This is a timing diagram of a write operation in a chip provided in an embodiment of the present application;

[0033] Figure 6 Schematic diagram of the relationship between the degree of voltage and / or temperature drift and chip internal delay provided by an embodiment of the present application;

[0034] Figure 7 Schematic diagram of the relationship between voltage and measurement clock period provided in an embodiment of the present application;

[0035] Figure 8 is a schematic diagram of measuring a clock period provided in an embodiment of the present application;

[0036] Figure 9 is a schematic diagram of measuring a clock period provided in an embodiment of the present application;

[0037] Figure 10This is a schematic diagram of measuring a clock period provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limiting this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0039] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] In the following description, the terms "first, second, and third" are used merely to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the specific order or sequence of "first, second, and third" can be interchanged where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In the following description, the term "plurality" refers to at least two.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0042] The relevant data collection and processing in the embodiments of this application should be strictly in accordance with the requirements of relevant laws and regulations when applied in examples, and the informed consent or separate consent of the personal information subject should be obtained. Subsequent data use and processing should be carried out within the scope of authorization of laws and regulations and the personal information subject.

[0043] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0044] 1) Data processing: This refers to a data processing process implemented by an electronic device, such as a data processing process within a chip or electronic device. The data processing process may include at least one of data reading and data writing.

[0045] 2) Clock measurement unit: used to measure clock cycles during data processing. The specific form of the clock measurement unit is not limited in this embodiment of the present application; for example, it may be a logic circuit, such as combinational logic implemented using NAND gates. In this embodiment of the present application, the measured clock cycle (i.e., the measured clock cycle) can be represented by the number of clock measurement units.

[0046] 3) Delay parameter: This parameter is used to adjust the data sampling signal to address clock drift during data processing. The data sampling signal can be used to read or write data.

[0047] 4) Artificial Intelligence (AI): The theories, methods, technologies and application systems that use digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to achieve the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new type of intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that the machines have the functions of perception, reasoning and decision-making. In the embodiments of the present application, the principles of artificial intelligence can be applied to the data processing process to achieve automated clock calibration. Taking the data processing process within the chip as an example, the AIization of the chip can be realized.

[0048] 5) Intelligent Traffic System (ITS): Also known as the Intelligent Transportation System, it effectively integrates advanced science and technology (information technology, computer technology, data communication technology, sensor technology, electronic control technology, automatic control theory, operations research, artificial intelligence, etc.) into transportation, service control, and vehicle manufacturing, strengthening the connection between vehicles, roads, and users, thereby forming an integrated transportation system that ensures safety, improves efficiency, improves the environment, and saves energy. The embodiments of the present application can be applied to intelligent transportation systems to achieve smart transportation. For example, the embodiments of the present application can be applied during the data processing process of the intelligent transportation system to improve the accuracy of data processing.

[0049] The present invention provides a data processing calibration method, device, chip, electronic device, computer-readable storage medium, and computer program product, which can improve the accuracy of data processing and effectively avoid processing errors caused by clock drift. The following describes exemplary applications of the electronic device provided by the present invention. The electronic device provided by the present invention can be implemented as various types of terminal devices or as a server.

[0050] See also Figure 1 , Figure 1 This is an architectural diagram of a data processing calibration system 100 provided in an embodiment of the present application, wherein a terminal device 400 is connected to a server 200 via a network 300, wherein the network 300 may be a wide area network or a local area network, or a combination of the two.

[0051] In some embodiments, taking the electronic device as a terminal device as an example, the calibration method for data processing provided in the embodiment of the present application can be implemented by the terminal device. For example, in the data processing process inside the terminal device 400, measurement processing is performed based on the clock measurement unit to obtain multiple measurement clock cycles; wherein the measurement clock cycle is used to represent multiple clock measurement units; according to the number of clock measurement units represented by the multiple measurement clock cycles, it is determined whether there is clock drift between the multiple measurement clock cycles; when there is clock drift between the multiple measurement clock cycles, a delay parameter for the clock drift is determined according to at least part of the measurement clock cycles with the latest measurement time in the multiple measurement clock cycles; clock calibration processing is performed during the data processing process according to the delay parameter. It is worth noting that the data processing process can be used to support the stand-alone operation of the terminal device 400, and can also be used to support the online operation of the terminal device 400. For example, based on the connection between the terminal device 400 and other electronic devices (such as the server 200 or other terminal devices), relevant data processing needs to be performed to achieve specific functions.

[0052] It is worth noting that the data processing process inside the terminal device 400 may refer to the data processing process inside a specific electronic device in the terminal device 400, such as the data processing process inside a chip, where the chip provides data computing capabilities in the terminal device 400.

[0053] In some embodiments, taking the electronic device as a server as an example, the calibration method for data processing provided in the embodiment of the present application can also be implemented by the server. For example, the calibration method for data processing provided in the embodiment of the present application can be applied to the server 200. It is worth noting that the data processing process can be used to support the stand-alone operation of the server 200, and can also be used to support the online operation of the server 200. For example, based on the connection between the server 200 and other electronic devices (such as the terminal device 400 or other servers), relevant data processing needs to be performed to achieve specific functions.

[0054] It is worth noting that the data processing process inside the server 200 may refer to the data processing process inside a specific electronic device in the server 200, such as the data processing process inside a chip, where the chip is used to provide data computing capabilities in the server 200.

[0055] In some embodiments, various results involved in the data processing calibration process (such as measured clock cycles, delay parameters, etc.) can be stored in the blockchain. Due to the tamper-proof nature of the blockchain, the accuracy of the data in the blockchain can be guaranteed. Electronic devices can send query requests to the blockchain to query the data stored in the blockchain.

[0056] In some embodiments, the terminal device 400 or the server 200 can implement the data processing calibration method provided in the embodiments of the present application by running a computer program. For example, the computer program can be a native program or software module in the operating system; it can be a native application (APP, Application), that is, a program that needs to be installed in the operating system to run; it can also be a small program, that is, a program that can be run by simply downloading it into a browser environment; it can also be a small program that can be embedded in any APP. In short, the above-mentioned computer program can be an application, module or plug-in in any form.

[0057] In some embodiments, the server 200 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. The terminal device 400 can be a smart phone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, car terminal, smart TV, etc., but is not limited to this. The terminal device and the server can be directly or indirectly connected via wired or wireless communication, which is not limited in the embodiments of the present application.

[0058] Taking the electronic device provided in the embodiment of the present application as an example, it can be understood that in the case where the electronic device is a server, Figure 2 Some of the structures shown in FIG (such as the user interface, presentation module, and input processing module) may be omitted. Figure 2 , Figure 2 is a schematic diagram of the structure of the terminal device 400 provided in an embodiment of the present application. Figure 2 The terminal device 400 shown includes: at least one processor 410, a memory 450, at least one network interface 420, and a user interface 430. The various components in the terminal device 400 are coupled together via a bus system 440. It is understood that the bus system 440 is used to achieve connection and communication between these components. In addition to including a data bus, the bus system 440 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 440 is not shown in FIG. Figure 2 Various buses are labeled as bus system 440 .

[0059] The processor 410 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0060] The user interface 430 includes one or more output devices 431 that enable presentation of media content, including one or more speakers and / or one or more visual display screens. The user interface 430 also includes one or more input devices 432, including user interface components that facilitate user input, such as a keyboard, mouse, microphone, touch screen display, camera, other input buttons and controls.

[0061] The memory 450 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard drives, optical drives, etc. The memory 450 may optionally include one or more storage devices that are physically remote from the processor 410.

[0062] The memory 450 includes volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be a read-only memory (ROM), and the volatile memory may be a random access memory (RAM). The memory 450 described in the embodiments of the present application is intended to include any suitable type of memory.

[0063] In some embodiments, the memory 450 can store data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof, as exemplified below.

[0064] Operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, and driver layer, which are used to implement various basic services and process hardware-based tasks;

[0065] A network communication module 452 is used to reach other electronic devices via one or more (wired or wireless) network interfaces 420. Exemplary network interfaces 420 include Bluetooth, Wi-Fi, and Universal Serial Bus (USB).

[0066] a presentation module 453 for enabling presentation of information via one or more output devices 431 (e.g., a display screen, a speaker, etc.) associated with the user interface 430 (e.g., a user interface for operating peripheral devices and displaying content and information);

[0067] The input processing module 454 is configured to detect one or more user inputs or interactions from one of the one or more input devices 432 and to translate the detected inputs or interactions.

[0068] In some embodiments, the data processing calibration device provided in the embodiments of the present application can be implemented in a software manner. Figure 2 A calibration device 455 for processing data stored in memory 450 is shown. This device can be software in the form of a program or plug-in, and includes the following software modules: a measurement module 4551, a drift determination module 4552, a parameter determination module 4553, and a clock calibration module 4554. These modules are logical and can be arbitrarily combined or further separated according to the functions they implement. The functions of each module will be described below.

[0069] The calibration method for data processing provided in the embodiment of the present application will be described in conjunction with the exemplary application and implementation of the electronic device provided in the embodiment of the present application.

[0070] See also Figure 3A , Figure 3A This is a flow chart of the calibration method for data processing provided in the embodiment of the present application, which will be combined with Figure 3A The steps shown are explained.

[0071] In step 101 , measurement processing is performed based on a clock measurement unit during data processing to obtain a plurality of measurement clock cycles; wherein the measurement clock cycle is used to represent a plurality of clock measurement units.

[0072] With the rapid development of electronic technology, electronic devices have developed features such as high precision and high operating frequency. Taking chips as an example, metal interconnects are typically used to connect various components within a chip. With the advancement of modern processes, the line widths between interconnects have become increasingly narrow, increasing the coupling effect and interference noise between the wires. Furthermore, because chips support high-bandwidth data processing, electronic devices such as chips are easily affected by the operating environment, resulting in problems such as clock drift, which can lead to data processing errors. Clock drift refers to the discrepancy between the actual clock period and the set clock period (i.e., the ideal clock period).

[0073] To address this, in an embodiment of the present application, automatic calibration is implemented during data processing based on artificial intelligence principles. First, during data processing, measurement processing is continuously performed using clock measurement units as units to obtain multiple measurement clock cycles, each of which is used to represent multiple clock measurement units.

[0074] It is worth noting that different measurement clock cycles are measured at different times. In addition, due to the delay inherent in the measurement process, a measurement performed at a certain time may not measure the clock cycle at that time, but rather the clock cycles of several times before that time.

[0075] It is worth noting that the embodiment of the present application does not limit the specific form of the clock measurement unit. For example, it can be a combinational logic implemented based on NAND.

[0076] In some embodiments, the above-mentioned measurement processing based on the clock measurement unit during data processing to obtain multiple measurement clock cycles can be achieved in the following manner: the following processing is performed during the data processing: a pulse that meets the set clock cycle is generated by the first clock; clock delay processing is performed on the second clock based on the clock measurement unit to move the clock rising edge of the second clock; and the measurement clock cycle is determined based on the number of clock measurement units used to move the clock rising edge from the first edge of the pulse to the second edge.

[0077] Here is an example of measurement processing during data processing. First, a pulse that meets the set clock cycle is generated by the first clock, for example, a high-level pulse with a duration of one set clock cycle is generated, wherein the high level and the low level are logic levels, the high level is digital logic 1, and the low level is digital logic 0. Then, the second clock is continuously subjected to clock delay processing based on the clock measurement unit to move the clock rising edge of the second clock from the first edge of the pulse (such as the left edge) to the second edge (such as the right edge). In this way, the number of clock measurement units used during the period of moving the clock rising edge of the second clock from the first edge of the pulse to the second edge is used as the number of clock measurement units represented by the measuring clock cycle, thereby realizing the measurement of the clock cycle. In the above manner, accurate measurement of the clock cycle can be achieved, which is helpful for subsequent precise calibration.

[0078] In step 102, it is determined whether clock drift exists between the multiple measurement clock cycles according to the number of clock measurement units respectively represented by the multiple measurement clock cycles.

[0079] Since each measurement clock cycle is used to represent multiple clock measurement units, it is possible to determine whether there is clock drift between multiple measurement clock cycles by the number of clock measurement units represented by each measurement clock cycle, that is, to determine whether the difference between multiple measurement clock cycles meets the clock drift standard.

[0080] In step 103 , when clock drift exists between multiple measurement clock cycles, a delay parameter for the clock drift is determined based on at least a portion of the measurement clock cycles with the latest measurement time among the multiple measurement clock cycles.

[0081] For example, when clock drift is determined to exist between multiple measurement clock cycles, a delay parameter for addressing the clock drift is determined based on the number of clock measurement units represented by at least a portion of the measurement clock cycles with the latest measurement time among the multiple measurement clock cycles. Because at least a portion of the measurement clock cycles with the latest measurement time is more consistent with the real-time conditions of the data processing process, the validity of the determined delay parameter can be guaranteed.

[0082] The number of at least a portion of the latest measurement clock cycles can be set based on the actual application scenario, for example, it can be one or more. When the at least a portion of the latest measurement clock cycles includes multiple clock cycles, a statistical process can be performed on the number of clock measurement units represented by the at least a portion of the latest measurement clock cycles to obtain a statistical quantity, and then the delay parameter is determined based on the statistical quantity. Methods for statistical process include, but are not limited to, averaging, taking the maximum value, taking the minimum value, and taking the mode.

[0083] In some embodiments, after step 102 , the method further includes: when there is no clock drift between the multiple measurement clock cycles, discarding at least part of the measurement clock cycles with the earliest measurement time among the multiple measurement clock cycles, and continuing to perform measurement processing based on the clock measurement unit.

[0084] Here, when it is determined that there is no clock drift between multiple measurement clock cycles, at least a portion of the measurement clock cycles with the earliest measurement time among the multiple measurement clock cycles is discarded (deleted), and measurement processing based on the clock measurement unit continues. Because the reference value of at least a portion of the measurement clock cycles with the earliest measurement time is relatively small, discarding at least a portion of the measurement clock cycles with the earliest measurement time can improve the accuracy of subsequent judgments on whether clock drift exists, and at the same time, storage space can also be saved. The number of at least a portion of the measurement clock cycles with the earliest measurement time can be set according to the actual application scenario, for example, it can be one or more.

[0085] In step 104, clock calibration is performed during data processing according to the delay parameter.

[0086] For example, the data sampling signal during the data processing process is delayed (adjusted) according to the delay parameter to align the data sampling signal with the center of the data eye diagram. This ensures that the data sampling signal can be correctly sampled, thereby resolving the clock drift problem that exists in the data processing process. The data sampling signal can be used to read data or write data.

[0087] It is worth noting that the object of delay processing can be the timing parameters of the data sampling signal, which include but are not limited to the relationship between the data sampling signal and the clock signal, the time the data sampling signal continues at a high level, and the time the data sampling signal continues at a low level.

[0088] like Figure 3A As shown, the embodiment of the present application accurately identifies clock drift based on the clock measurement unit during data processing and performs targeted clock calibration processing, thereby improving the accuracy of data processing.

[0089] In some embodiments, see Figure 3B , Figure 3B This is a flow chart of a calibration method for data processing provided in an embodiment of the present application. Figure 3A Step 102 shown can be implemented through steps 201 to 203 , which will be described in conjunction with each step.

[0090] In step 201 , a quantity variation range is determined according to the quantity of clock measurement units respectively represented by a plurality of measurement clock cycles.

[0091] Here, the magnitude of the change in the number of clock measurement units represented by multiple measurement clock cycles can be determined. The larger the magnitude of the change in the number, the greater the difference between the multiple measurement clock cycles, and the more likely clock drift is to occur. The embodiment of the present application does not limit the type of determination of the magnitude of the change in the number, for example, it can be the rate of change (ROC), the absolute value of the rate of change, the variance, the standard deviation, etc.

[0092] In some embodiments, the above-mentioned determination of the magnitude of the quantity change according to the number of clock measurement units respectively represented by multiple measurement clock cycles can be achieved in the following manner: sliding sampling processing is performed on the multiple measurement clock cycles according to the sampling number to obtain multiple sampling windows; wherein the number of measurement clock cycles in the sampling window is equal to the sampling number, and the sampling number is an integer greater than one; quantitative statistical processing is performed on the number of clock measurement units respectively represented by the multiple measurement clock cycles in the sampling window to obtain a statistical quantity; and the magnitude of the quantity change between the statistical quantities corresponding to the multiple sampling windows is determined.

[0093] For example, sliding sampling can be performed on multiple measurement clock cycles according to the number of samples in descending order of measurement time to obtain multiple sampling windows. The number of measurement clock cycles in each sampling window is equal to the number of samples, and the number of samples is an integer greater than one. The number of slides in the sliding sampling process is not limited and can be one or more.

[0094] For example, in order of measurement time from earliest to latest, measurement clock cycles 1, 2, 3, 4, and 5 are obtained in sequence, the number of samples is 4, and the number of slides is 1. Then, during the first sampling, measurement clock cycles 1, 2, 3, and 4 are added to sampling window 1; during the second sampling, the sampled measurement clock cycle slides backward by one position, that is, measurement clock cycles 2, 3, 4, and 5 are added to sampling window 2.

[0095] After obtaining multiple sampling windows, a statistical process is performed on the number of clock measurement units represented by multiple measurement clock cycles in each sampling window to obtain a statistical quantity for the sampling window. Methods for statistical processing include, but are not limited to, averaging, maximum value, minimum value, and mode. Because the statistical quantity is obtained by integrating multiple measurement clock cycles, it is more authoritative and effective.

[0096] Finally, the magnitude of the quantity change between the statistical quantities corresponding to the multiple sampling windows is determined. Taking the magnitude of the quantity change as the change rate, and the sampling windows include sampling windows 1 and 2 as an example, the magnitude of the quantity change = (the statistical quantity corresponding to sampling window 2 - the statistical quantity corresponding to sampling window 1) / the statistical quantity corresponding to sampling window 1, wherein the statistical time of sampling window 2 is later than the statistical time of sampling window 1, wherein the statistical time of the sampling window can be obtained by performing time statistical processing on the measurement times corresponding to the multiple measurement clock cycles in the sampling window, and the time statistical processing methods include but are not limited to averaging, taking the maximum value, and taking the minimum value. When the number of sampling windows is greater than three, the change rate between the sampling window with the earliest statistical time and the sampling window with the latest statistical time can be directly determined as the magnitude of the quantity change; the change rate between two sampling windows with adjacent statistical times can also be determined, and all the obtained change rates are averaged to obtain the magnitude of the quantity change.

[0097] By adopting the above method, the effectiveness of the obtained quantity variation range can be improved, that is, the quantity variation range can effectively represent the difference between multiple measurement clock cycles.

[0098] In some embodiments, the above-mentioned determination of the delay parameter for clock drift based on at least a portion of the measurement clock cycles with the latest measurement time among multiple measurement clock cycles can be achieved in the following manner: time statistical processing is performed on the measurement times corresponding to multiple measurement clock cycles in the sampling window to obtain statistical time; and the delay parameter for clock drift is determined based on the statistical number corresponding to a sampling window with the latest statistical time among the multiple sampling windows.

[0099] Under the premise of determining the magnitude of quantity variation based on the sampling window, when clock drift is determined between multiple measurement clock cycles, the sampling window with the latest statistical time is closer to the real-time status of the data processing process, and the statistical quantity is more stable than the measurement time of a single measurement clock cycle (individual measurement clock cycles may experience sudden anomalies). Therefore, the delay parameter for clock drift can be determined based on the statistical quantity corresponding to the latest statistical time. This can further improve the accuracy and effectiveness of the delay parameter.

[0100] In step 202 , when the magnitude of the quantity change is greater than the magnitude threshold, it is determined that clock drift exists between the plurality of measurement clock cycles.

[0101] Here, when the magnitude of the quantity change is greater than the magnitude threshold, it is determined that the difference between the multiple measured clock cycles is too large, and thus it is determined that clock drift exists.

[0102] In some embodiments, the method further includes: performing measurement processing based on a clock measurement unit during sample data processing to obtain multiple sample measurement clock cycles; wherein, there is environmental parameter drift during the sample data processing, and the environmental parameters include at least one of voltage and temperature; determining the sample quantity change amplitude based on the number of clock measurement units respectively represented by the multiple sample measurement clock cycles; and using the sample quantity change amplitude as an amplitude threshold.

[0103] In an embodiment of the present application, the amplitude threshold value can be pre-set or obtained in a specific way. For the latter, an example is provided here. For example, in the process of processing sample data in the presence of environmental parameter drift, measurement processing is performed based on the clock measurement unit to obtain multiple measurement clock cycles (named as sample measurement clock cycles for ease of distinction). Among them, the environmental parameters include at least one of voltage and temperature, and the standard of environmental parameter drift can be set according to the actual application scenario. For example, the voltage change amplitude in the sample data processing process is greater than the voltage change amplitude threshold, and the temperature change amplitude is greater than the temperature change amplitude threshold. The calculation method of the voltage change amplitude and the temperature change amplitude is similar to the quantitative change amplitude above. The environmental parameter drift in the sample data processing process can be generated by adjusting the environment outside the electronic device (for example, adjusting the external temperature) or increasing the data processing pressure inside the electronic device (for example, causing the electronic device to overheat due to continuous high-speed operation).

[0104] After obtaining multiple sample measurement clock cycles, the number change amplitude (named "sample number change amplitude for ease of distinction") is determined based on the number of clock measurement units represented by the multiple sample measurement clock cycles. The sample number change amplitude is then used as the amplitude threshold. This approach enables automatic determination of the amplitude threshold, and the amplitude threshold can be used to accurately determine whether clock drift exists.

[0105] In step 203 , when the magnitude of the quantity change is less than or equal to the magnitude threshold, it is determined that there is no clock drift between the multiple measurement clock cycles.

[0106] Here, when the magnitude of the quantity change is less than or equal to the magnitude threshold, it is determined that the difference between the plurality of measured clock cycles is insufficient to meet the criterion of clock drift, and thus it is determined that there is no clock drift.

[0107] like Figure 3B As shown, the embodiment of the present application determines the quantity change amplitude based on the number of clock measurement units represented by multiple measurement clock cycles, and judges whether there is clock drift according to the size of the quantity change amplitude, which can improve the accuracy of judgment and achieve effective calibration.

[0108] In some embodiments, see Figure 3C , Figure 3CThis is a flow chart of a calibration method for data processing provided in an embodiment of the present application. Figure 3A Step 103 shown may be updated to step 301. In step 301, when clock drift exists between multiple measurement clock cycles, delay parameters corresponding to multiple data positions are determined based on at least a portion of the measurement clock cycles with the latest measurement time among the multiple measurement clock cycles.

[0109] In an embodiment of the present application, the data processing process can be used to process data at multiple data locations. Taking an HBM chip as an example, the data processing process in the HBM chip is used to process 128-bit data. In this case, when clock drift is determined between multiple measurement clock cycles, delay parameters corresponding to the multiple data locations are determined based on at least a portion of the measurement clock cycles with the latest measurement time among the multiple measurement clock cycles. For example, the delay parameters corresponding to the multiple data locations are determined based on the statistical quantity corresponding to the sampling window with the latest statistical time among the multiple sampling windows.

[0110] exist Figure 3C middle, Figure 3A The illustrated step 104 may be updated to step 302 , in which a delay process is performed on a data sampling signal of any data position during the data processing process according to a delay parameter corresponding to any data position.

[0111] Here, for each of the multiple data positions, a data sampling signal of the data position during data processing is delayed according to a delay parameter corresponding to the data position, and the data sampling signal is used to read data or write data at the data position.

[0112] like Figure 3C As shown, the embodiment of the present application can implement clock calibration at each data position to ensure the accuracy of data processing (data reading / data writing) at each data position.

[0113] In some embodiments, see Figure 3D , Figure 3D This is a flow chart of a calibration method for data processing provided in an embodiment of the present application. Figure 3C Step 101 shown can be updated to step 401. In step 401, the main delay path performs measurement processing based on the clock measurement unit during data processing to obtain multiple measurement clock cycles; wherein the measurement clock cycle is used to represent multiple clock measurement units.

[0114] In an embodiment of the present application, clock calibration during data processing can be implemented based on multiple delay paths (or delay control paths), wherein the delay path can be a control circuit, but the implementation form is not limited to this.

[0115] For example, the delay path can be configured in a one-master-multiple-slave mode, where one master delay path corresponds to multiple slave delay paths. During data processing, the master delay path performs measurement processing based on the clock measurement unit to obtain multiple measurement clock cycles.

[0116] exist Figure 3D middle, Figure 3C Step 102 shown may be updated to step 402 , in which the main delay path determines whether clock drift exists between the multiple measurement clock cycles according to the number of clock measurement units respectively represented by the multiple measurement clock cycles.

[0117] Here, the main delay path determines whether clock drift exists between the multiple measurement clock cycles according to the number of clock measurement units respectively represented by the multiple measurement clock cycles.

[0118] exist Figure 3D middle, Figure 3C Step 301 shown can be implemented through steps 403 and 404. In step 403, when clock drift exists between multiple measurement clock cycles, the master delay path notifies the multiple slave delay paths of at least a portion of the measurement clock cycle with the latest measurement time.

[0119] Here, when the master delay path determines that clock drift exists between multiple measurement clock cycles, the master delay path notifies multiple slave delay paths of at least a portion of the measurement clock cycle with the latest measurement time, thereby triggering the multiple slave delay paths to perform clock calibration.

[0120] In some embodiments, before the master delay path notifies multiple slave delay paths of at least a portion of the measurement clock cycle with the latest measurement time, it also includes: performing any of the following processing: configuring slave delay paths that are respectively bound to multiple data positions; encapsulating multiple data positions according to the encapsulation quantity to obtain multiple data position sets, and configuring slave delay paths that are respectively bound to the multiple data position sets; wherein the number of data positions in the data position set is equal to the encapsulation quantity, and the encapsulation quantity is an integer greater than one.

[0121] In the embodiments of this application, there are two ways to configure slave delay paths. The first way is to configure slave delay paths that are bound to multiple data locations. Taking the HBM chip as an example, each bit is bound to a slave delay path, and different bits are bound to different slave delay paths. This method can ensure the independence of each data location.

[0122] The second method is to package multiple data locations according to the package quantity to obtain multiple data location sets, and then configure slave delay paths bound to each of the multiple data location sets. The number of data locations in each data location set is equal to the package quantity, which is an integer greater than one. Taking the HBM chip as an example, the package quantity can be set to 32 bits, that is, each 32 bits is packaged as an independent data location set. This method can reduce the number of slave delay path configurations while maintaining a certain degree of independence, thereby improving calibration efficiency.

[0123] In step 404, the delay path determines the delay parameter corresponding to the bound data position according to the number of clock measurement units represented by the notified measurement clock cycle.

[0124] For each slave delay path, the slave delay path determines a delay parameter corresponding to a data position bound to the slave delay path based on the number of clock measurement units represented by the notified measurement clock cycle, wherein the data position bound to the slave delay path may be one or more.

[0125] exist Figure 3D middle, Figure 3C The illustrated step 104 may be updated to step 405 , in which the data sampling signal of the bound data position during the data processing is delayed according to the delay parameter corresponding to the bound data position from the delay path.

[0126] For each slave delay path, the slave delay path performs delay processing on the data sampling signal of the bound data position during the data processing process according to the delay parameter corresponding to the bound data position.

[0127] like Figure 3D As shown, the embodiment of the present application can improve the calibration efficiency while ensuring the calibration accuracy through the division of labor and cooperation between the main delay path and the slave delay path.

[0128] Below, an exemplary application of an embodiment of the present application in a practical application scenario will be described. For ease of understanding, an HBM chip will be used as an example.

[0129] First, let's introduce HBM. HBM is a high-bandwidth memory that supports multiple read and write commands and enables continuous data reading and writing. In an embodiment of the present application, the HBM PHY may include multiple delay paths (or delay control paths) for calibrating the sampling signal (i.e., the data sampling signal) to the middle position of the data eye diagram. In this way, even in a narrow data eye diagram, the delay path can ensure that the sampling signal can sample the correct read and write data.

[0130] After the HBM power-up sequence is completed, the HBM controller can send various read and write commands to the HBM particles. As an example, the present application embodiment provides the following Figure 4 The timing diagram of a read operation in HBM is shown in Figure 4 In the process, the HBM controller sends a read (READ) command, which contains the address information of BANK and COLUNM. Among them, BANK is the storage array in the memory, and COLUNM refers to the specific column. The READ operation can support concurrent operations of 2 or 4 lengths. Figure 4 It involves the read bidirectional data control pin (Read Bi-directional Data Strobe, RDQS) signal, RDQS signal (ie Figure 4 The timing parameters related to the read signal (also called the sampling signal for reading data) shown in FIG. 1 are described as follows:

[0131] 1) First delay: tDQSCK (min / max), used to describe the timing requirements between the rising edge of the clock (or the falling edge of the clock) and the rising edge of the read signal (or the falling edge of the read signal). For example, the allowable range of delay of the rising edge of the read signal relative to the rising edge and the falling edge of the clock (the first delay is a value within this allowable range). The rising edge of the clock is CK_c, the falling edge of the clock is CK_t, the rising edge of the read signal is RDQS_c, and the falling edge of the read signal is RDQS_t.

[0132] 2) First duration: tQSH, which is used to describe the duration that the read signal remains high.

[0133] 3) Second duration: tQSL, used to describe the duration that the read signal remains at a low level;

[0134] 4) First range value: tLZ(max), used to describe the maximum value of the allowable range of the read signal transitioning from the output high impedance state to the low impedance state relative to the clock signal;

[0135] 5) Second range value: tLZ(min), used to describe the minimum value of the allowable range of the read signal transition from the output high impedance state to the low impedance state relative to the clock signal;

[0136] 6) Second delay: tDQSQ, which is used to describe the delay from the rising or falling edge of the read signal to the earliest valid data.

[0137] 7) Third delay: tQH, used to describe the delay from the rising or falling edge of the read signal to the earliest time the read data becomes invalid;

[0138] 8) The third range value: tHZ(max), which is used to describe the maximum value of the allowable range of the read signal transitioning from low impedance to output high impedance relative to the clock signal;

[0139] 9) The fourth range value: tHZ(min), is used to describe the minimum value of the allowable range of the read signal transitioning from a low impedance state to an output high impedance state relative to the clock signal.

[0140] It is worth noting that tDQSCK may span multiple clock cycles; Figure 4 The case where the burst length is 4 is used as an example for description, but the actual application scenario is not limited to this.

[0141] It is worth mentioning that Figure 4 The figure shows the read data latency (RL) of odd (corresponding to odd bytes) and even (corresponding to even bytes) read data cases, which are further divided into three cases: last data valid, first data no longer valid, and all outputs collectively. In addition, Figure 4 The original data in is not valid data, but only the data when the read output transitions from high impedance to low impedance. Valid data 1 is the valid data read out for the first time in a concurrent read operation, and valid data 2, valid data 3, and valid data 4 are read in the same order.

[0142] As an example, the present application provides the following embodiments: Figure 5 The timing diagram of a write operation in HBM is shown in Figure 5 In the process, the HBM controller sends a write (WRITE) command. Similar to the READ command, the WRITE command contains the address information of BANK and COLUNM. The WRITE operation can also support concurrent operations of 2 or 4 lengths. Figure 5 Involves the write bidirectional data control pin (Write Bi-directional Data Strobe, WDQS) signal, WDQS signal (ie Figure 5 The timing parameters related to the write signal (also called the sampling signal for writing data) shown in FIG. 1 are described as follows:

[0143] 1) Fourth delay: tDQSS (min / max), used to describe the timing requirements between the rising edge of the write signal (or the falling edge of the write signal) and the rising edge (or the falling edge) of the clock. For example, the allowable range of delay of the rising edge of the write signal relative to the rising edge or the falling edge of the clock (the fourth delay is a value within this allowable range). The rising edge of the write signal is WDQS_c, and the falling edge of the write signal is WDQS_t.

[0144] 2) The third duration: tDQSH, which is used to describe the duration of the write signal remaining high.

[0145] 3) The fourth duration: tDQSL, which is used to describe the duration of the write signal remaining at a low level;

[0146] 4) First setup time: tDSS, which is used to describe the setup time between the falling edge of the write signal and the rising edge of the clock;

[0147] 5) First hold time: tDSH, used to describe the hold time between the falling edge of the write signal and the rising edge of the clock;

[0148] 6) Second setup time: tDS, used to describe the setup time for writing data;

[0149] 7) Second hold time: tDH, used to describe the hold time of write data;

[0150] 8) Pulse Width Delay: tDPW, used to describe the pulse width delay of the write signal.

[0151] It is worth mentioning that Figure 5 The data writing scenarios are shown when the fourth delay is respectively the minimum value (min), the maximum value (max), and the nominal value.

[0152] according to Figure 4 and Figure 5 It can be determined that during the data reading process, the delay path can align the RDQS signal to the center of the read data eye diagram by changing the delay parameters, thereby ensuring the correctness of the HBM read data; during the data writing process, the delay path can align the WDQS signal to the center of the write data eye diagram by changing the delay parameters, thereby ensuring the correctness of the HBM write data.

[0153] In HBM chips, metal interconnects are usually used to connect various components. With the development of modern technology, the line width between interconnect wires is getting narrower and narrower, and the coupling effect and interference noise between wires are increasing. At the same time, since HBM supports high-bandwidth data reading and writing, the heat dissipation problem of HBM chips is more challenging. Figure 6As shown in Figure 1, when the voltage and / or temperature of the HBM chip drift slightly, the delay circuit inside the HBM PHY will also change. Figure 6 The horizontal axis represents the degree of voltage and / or temperature drift, and the vertical axis represents the delay inside the HBM PHY.

[0154] Voltage and / or temperature drift also affects the clock accuracy of the HBM's internal clock generator. This effect is exacerbated when the HBM operates at higher frequencies. For example, a 10nm phase-locked loop (PLL) with a clock frequency of 2.4GHz has a clock period of 417 picoseconds (ps). Voltage and / or temperature drift can affect the clock in three ways:

[0155] 1) The static phase variation of the clock is about 7.5ps;

[0156] 2) The dynamic phase variation of the clock is about 50 ps;

[0157] 3) At the same time, the clock duty cycle will also change by about 1%, which is about 4.17ps.

[0158] These three components add up to 7.5 + 4.17 * 2 + 50 = 65.84 ps. Therefore, it can be determined that when the HBM chip's voltage and / or temperature drift, there will be a 7.5 / 65.84 = 11.39% adverse impact. When the clock changes, the HBMPHY delay parameters based on the original clock frequency become significantly inaccurate, increasing the probability of data read and write errors by 24.16%.

[0159] In response to this, an embodiment of the present application provides an automatic calibration mechanism for automatically adjusting the clock and related configuration parameters to recover from voltage and / or temperature drift and ensure the correctness of data reading and writing, while ensuring the efficiency of HBM data reading and writing. In an embodiment of the present application, automatic calibration can be achieved based on multiple delay paths, and these delay paths follow the master-slave configuration mode, that is, one master and multiple slaves. The master delay path is used to measure how many basic delay units (corresponding to the clock measurement unit above) exist in a complete clock cycle, that is, the basic delay unit is similar to a ruler, which is used to realize the measurement of the clock cycle, wherein the basic delay unit can be set according to the actual application scenario, for example, it can be based on NAND combination logic, and under the 5nm process, the delay (duration) of the basic delay unit can be 4.1633ps. The formulas involved are as follows:

[0160] T cycle =N*T delayelement

[0161] Among them, T cycleRepresents a measurement clock period, T delayelement Represents the delay of a basic delay unit, T cycle Can be achieved through N T delayelement To express.

[0162] In a continuously running HBM chip, the main delay path continuously calculates N represented by each measurement clock cycle and records at least 4 consecutive N values, namely N k 、N k+1 、N k+2 、N k+3 The actual value ultimately assigned to the slave delay path for clock and related configuration parameter calculations is obtained using the average value of N over four consecutive measurement clock cycles (hereinafter referred to as the average N value for ease of distinction, corresponding to the statistical quantity mentioned above):

[0163]

[0164] by Figure 7 For example, Figure 7 The operating voltage of the HBM chip in the middle decreases slowly from time T0 to time T3. The N values ​​calculated by the main delay path are N k 、N k+1 、N k+2 、N k+3 , a slow rise occurred.

[0165] Calibration of the main delay path is ongoing throughout the HBM operation. As voltage and / or temperature drift, the clock changes, and therefore the N calculated by the main delay path changes. Here, the amount of change is defined as ΔN. The rate of change of the delay along the main delay path (corresponding to the magnitude of the change in the quantity mentioned above) can be expressed as:

[0166]

[0167] Where σ represents the rate of change of delay on the main delay path, N i+1 Represents the average N value calculated at time i+1, N i Represents the average N value calculated at time i.

[0168] The slave delay path calculates the delay parameters of each slave delay path based on the average N value provided by the master delay path and configures them to each module in the HBM chip (corresponding to the data position set above) to align the sampling signals of the read and write data to the center position of the data eye diagram. Among them, each slave delay path corresponds to a module. For example, the HBM chip processes a total of 128 bits of data. In the embodiment of the present application, each 32-bit read and write control can be encapsulated into an independent module for processing, that is, bit0~bit31 belongs to the DWORD0 module, bit32~bit63 belongs to the DWORD1 module, bit64~bit95 belongs to the DWORD2 module, and bit96~bit127 belongs to the DWORD3 module. Of course, this does not constitute a limitation of the embodiment of the present application. For example, each slave delay path can also correspond to one bit.

[0169] The process of obtaining the average N value from the main delay path and performing calculations and configurations by the slave delay path takes 1.6 milliseconds (ms) to complete. During this process, HBM cannot complete normal data read and write operations. In the actual HBM read and write process, it is not possible to frequently obtain the average N value provided by the main delay path from the slave delay path and perform calculations and configurations, which will greatly reduce efficiency. If the slave delay path is not triggered to re-acquire a new average N value for a long time, the sampling signal will deviate from the center position of the data eye diagram, thereby affecting the correctness of data reading and writing, which is even more harmful. Therefore, in the embodiment of the present application, a suitable time point is determined as a compromise to trigger the slave delay path to re-acquire the average N value from the main delay path.

[0170] For example, the master delay path can continuously compare σ with a programmable amplitude threshold configured in advance on the chip. The default amplitude threshold can be 37.14%, corresponding to a variation of approximately 13 basic delay units. The amplitude threshold can be reconfigured based on the chip's worst-case voltage and / or temperature drift, and is not limited to 37.14%. When σ exceeds the amplitude threshold, the master delay path triggers the slave delay path to calculate the HBM delay parameters using the most recently calculated average N value. This ensures both efficient and accurate data reading and writing.

[0171] For ease of understanding, the following three cases are used as examples: ideal Indicates the expected ideal value (similar to N above i ), Indicates the actual calculated average N value (similar to the N above i+1 ).

[0172] 1) Continuous oscillation. Figure 8 As shown, N k 、N k+1、N k+2 、N k+3 There are continuous oscillations. In this case, N average Almost the same as N ideal If the σ value is small, it will not trigger self-calibration and data reading and writing will not cause errors.

[0173] 2) Slow growth (or slow decrease). Figure 9 As shown, N k 、N k+1 、N k+2 、N k+3 A slow increase occurs. In this case, the σ value is small, self-calibration is not triggered, and data reading and writing will not cause errors.

[0174] 3) Drastic growth (or dramatic decrease). Figure 10 As shown, N k 、N k+1 、N k+2 、N k+3 A dramatic increase occurs. In this case, the σ value is greater than the amplitude threshold set in advance, and there is a risk of error in data reading and writing, so automatic calibration is triggered.

[0175] In summary, the embodiments of the present application provide an automatic calibration mechanism that, while ensuring HBM read and write efficiency, adjusts the clock and related configuration parameters (i.e., delay parameters) to recover from extreme voltage and / or temperature drift. This reduces the probability of data read and write errors from 24.16% to 0, fully ensuring the accuracy of data read and write. In addition to the automatic calibration mechanism, in the embodiments of the present application, the HBM chip's software can access hardware observation registers to identify abnormal voltage and / or temperature operating conditions, analyze the changes through software, and gradually manually configure the relevant registers to restore HBM data read and write accuracy.

[0176] The following continues to describe the exemplary structure of the data processing calibration device 455 provided in the embodiment of the present application implemented as a software module. In some embodiments, such as Figure 2As shown, the software modules in the data processing calibration device 455 stored in the memory 450 may include: a measurement module 4551, which is used to perform measurement processing based on the clock measurement unit during the data processing process to obtain multiple measurement clock cycles; wherein the measurement clock cycle is used to represent multiple clock measurement units; a drift judgment module 4552, which is used to determine whether there is clock drift between multiple measurement clock cycles based on the number of clock measurement units respectively represented by the multiple measurement clock cycles; a parameter determination module 4553, which is used to determine the delay parameter for the clock drift based on at least part of the measurement clock cycles with the latest measurement time in the multiple measurement clock cycles when clock drift exists between the multiple measurement clock cycles; a clock calibration module 4554, which is used to perform clock calibration processing during the data processing process based on the delay parameter.

[0177] In some embodiments, the drift judgment module 4552 is also used to: determine the amplitude of the quantity change based on the number of clock measurement units represented by multiple measurement clock cycles; when the amplitude of the quantity change is greater than the amplitude threshold, determine that there is clock drift between multiple measurement clock cycles; when the amplitude of the quantity change is less than or equal to the amplitude threshold, determine that there is no clock drift between multiple measurement clock cycles.

[0178] In some embodiments, the drift judgment module 4552 is further used to: perform sliding sampling processing on multiple measurement clock cycles according to the sampling number to obtain multiple sampling windows; wherein the number of measurement clock cycles in the sampling window is equal to the sampling number, and the sampling number is an integer greater than one; perform quantitative statistical processing on the number of clock measurement units represented by the multiple measurement clock cycles in the sampling window to obtain a statistical number; and determine the magnitude of the quantitative change between the statistical numbers corresponding to the multiple sampling windows.

[0179] In some embodiments, the parameter determination module 4553 is also used to: perform time statistical processing on the measurement times corresponding to multiple measurement clock cycles in the sampling window to obtain statistical time; and determine the delay parameter for clock drift based on the statistical quantity corresponding to the sampling window with the latest statistical time among the multiple sampling windows.

[0180] In some embodiments, the data processing calibration device 455 also includes a threshold determination module, which is used to: perform measurement processing based on the clock measurement unit during the sample data processing process to obtain multiple sample measurement clock cycles; wherein there is environmental parameter drift in the sample data processing process, and the environmental parameters include at least one of voltage and temperature; determine the sample quantity change amplitude based on the number of clock measurement units represented by the multiple sample measurement clock cycles; and use the sample quantity change amplitude as the amplitude threshold.

[0181] In some embodiments, the data processing process is used to process data at multiple data locations; the parameter determination module 4553 is also used to determine the delay parameters corresponding to the multiple data positions based on at least a portion of the measurement clock cycles with the latest measurement time in the multiple measurement clock cycles; the clock calibration module 4554 is also used to perform the following processing for any one of the multiple data positions: according to the delay parameter corresponding to any one of the data positions, delay processing is performed on the data sampling signal of any one of the data positions during the data processing process.

[0182] In some embodiments, the parameter determination module 4553 is further used to: notify at least a portion of the latest measurement clock cycle of the measurement time to multiple slave delay paths through the master delay path, so that any slave delay path can determine the delay parameter corresponding to the data position bound to any slave delay path based on the number of clock measurement units represented by the notified measurement clock cycle; wherein, any slave delay path is used to delay the data sampling signal of the bound data position during the data processing process based on the delay parameter corresponding to the bound data position.

[0183] In some embodiments, the parameter determination module 4553 is also used to perform any of the following processing: configuring a slave delay path that is respectively bound to multiple data locations; encapsulating multiple data locations according to the encapsulation quantity to obtain multiple data position sets, and configuring a slave delay path that is respectively bound to the multiple data position sets; wherein the number of data positions in the data position set is equal to the encapsulation quantity, and the encapsulation quantity is an integer greater than one.

[0184] In some embodiments, the measurement module 4551 is also used to perform the following processing during the data processing process: generating a pulse that meets the set clock period through the first clock; performing clock delay processing on the second clock based on the clock measurement unit to move the clock rising edge of the second clock; and determining the measurement clock period based on the number of clock measurement units used to move the clock rising edge from the first edge of the pulse to the second edge.

[0185] In some embodiments, the measurement module 4551 is further configured to: when there is no clock drift between multiple measurement clock cycles, discard at least part of the measurement clock cycles with the earliest measurement time among the multiple measurement clock cycles, and continue to perform measurement processing based on the clock measurement unit.

[0186] An embodiment of the present application provides a chip (such as the HBM chip described above), which includes a programmable logic circuit and at least one of executable instructions. The chip runs in an electronic device to implement the data processing calibration method provided in the embodiment of the present application.

[0187] The present invention provides a computer program product or computer program, which includes computer instructions (i.e., executable instructions) stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the data processing calibration method described in the present invention.

[0188] An embodiment of the present application provides a computer-readable storage medium having executable instructions stored therein. When the executable instructions are executed by a processor, the processor will execute the calibration method for data processing provided by the embodiment of the present application.

[0189] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or various devices including one or any combination of the above memories.

[0190] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0191] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (for example, files storing one or more modules, subroutines, or code portions).

[0192] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0193] The above are merely examples of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and scope of the present application are included in the scope of protection of the present application.

Claims

1. A calibration method for data processing, characterized in that: The method comprises: The following processing is performed during data processing: generating a pulse that meets a set clock period using a first clock; performing clock delay processing on a second clock based on a clock measurement unit to shift a rising edge of the second clock; determining a measured clock period based on the number of clock measurement units used to shift the rising edge of the clock from a first edge of the pulse to a second edge; wherein the measured clock period is used to represent a plurality of the clock measurement units; determining, based on the number of clock measurement units respectively represented by the plurality of measurement clock cycles, whether there is clock drift between the plurality of measurement clock cycles; When clock drift exists between the multiple measurement clock cycles, determining a delay parameter for the clock drift according to at least a portion of the measurement clock cycles with the latest measurement time among the multiple measurement clock cycles; A clock calibration process is performed during the data processing according to the delay parameter.

2. The method according to claim 1, characterized in that The determining whether there is clock drift between the multiple measurement clock cycles according to the number of clock measurement units respectively represented by the multiple measurement clock cycles includes: determining a quantity variation amplitude according to the quantities of clock measurement units respectively represented by the plurality of measurement clock cycles; When the magnitude of the quantity change is greater than a magnitude threshold, determining that there is clock drift between the plurality of measurement clock cycles; When the magnitude of the quantity change is less than or equal to the magnitude threshold, it is determined that there is no clock drift between the multiple measurement clock cycles.

3. The method according to claim 2, characterized in that The determining the quantity change range according to the quantity of clock measurement units respectively represented by the multiple measurement clock cycles includes: Performing sliding sampling processing on the multiple measurement clock cycles according to the sampling number to obtain multiple sampling windows; wherein the number of measurement clock cycles in the sampling window is equal to the sampling number, and the sampling number is an integer greater than one; Performing quantitative statistical processing on the number of clock measurement units respectively represented by a plurality of measurement clock cycles in the sampling window to obtain a statistical number; Determine the magnitude of the change between the statistical quantities corresponding to the multiple sampling windows.

4. The method according to claim 3, characterized in that The determining, based on at least a portion of the measurement clock cycles having the latest measurement time among the multiple measurement clock cycles, a delay parameter for the clock drift includes: Performing time statistical processing on the measurement times corresponding to the plurality of measurement clock cycles in the sampling window to obtain statistical time; Determine a delay parameter for the clock drift according to a statistical quantity corresponding to a sampling window with the latest statistical time among the multiple sampling windows.

5. The method according to claim 2, characterized in that The method further comprises: During the sample data processing process, measurement processing is performed based on the clock measurement unit to obtain a plurality of sample measurement clock cycles; wherein the sample data processing process has environmental parameter drift, and the environmental parameter includes at least one of voltage and temperature; determining a sample quantity variation amplitude according to the number of clock measurement units respectively represented by the plurality of sample measurement clock cycles; The amplitude of the change in the number of samples is used as the amplitude threshold.

6. The method according to claim 1, wherein The data processing process is used to process data at multiple data locations; and determining a delay parameter for the clock drift based on at least a portion of the measurement clock cycles having the latest measurement time among the multiple measurement clock cycles includes: determining delay parameters corresponding to the plurality of data positions respectively according to at least a portion of the measurement clock cycles having the latest measurement time among the plurality of measurement clock cycles; The performing clock calibration processing during the data processing according to the delay parameter includes: For any one of the plurality of data locations, the following processing is performed: Delay processing is performed on the data sampling signal of the arbitrary data position during the data processing according to the delay parameter corresponding to the arbitrary data position.

7. The method according to claim 6, characterized in that The determining, based on at least a portion of the measurement clock cycles having the latest measurement time among the multiple measurement clock cycles, delay parameters corresponding to the multiple data positions respectively includes: The master delay path notifies the plurality of slave delay paths of at least a portion of the measurement clock cycle of the latest measurement time, so that Any slave delay path determines, according to the number of clock measurement units represented by the notified measurement clock cycle, a delay parameter corresponding to the data position bound to the any slave delay path; Wherein, any one of the slave delay paths is used to perform delay processing on the data sampling signal of the bound data position during the data processing process according to the delay parameter corresponding to the bound data position.

8. The method according to claim 7, characterized in that The method further comprises: Perform any of the following: configuring slave delay paths respectively bound to the plurality of data locations; The multiple data positions are encapsulated according to the encapsulation quantity to obtain multiple data position sets, and slave delay paths respectively bound to the multiple data position sets are configured; wherein the number of data positions in the data position set is equal to the encapsulation quantity, and the encapsulation quantity is an integer greater than one.

9. The method according to any one of claims 1 to 8, characterized in that The method further comprises: When there is no clock drift between the multiple measurement clock cycles, discard at least part of the measurement clock cycles with the earliest measurement time among the multiple measurement clock cycles, and Continue to perform measurement processing based on the clock measurement unit.

10. A calibration device for data processing, characterized in that: The device comprises: A measurement module is configured to perform the following processing during data processing: generating a pulse that conforms to a set clock period using a first clock; performing clock delay processing on a second clock based on a clock measurement unit to shift a rising edge of the second clock; and determining a measurement clock period based on the number of clock measurement units used to shift the rising edge of the clock from a first edge of the pulse to a second edge of the pulse. a drift determination module, configured to determine whether there is clock drift between a plurality of measurement clock cycles according to the number of clock measurement units respectively represented by the plurality of measurement clock cycles; a parameter determination module configured to, when clock drift exists between the plurality of measurement clock cycles, determine a delay parameter for the clock drift based on at least a portion of the measurement clock cycles having the latest measurement time among the plurality of measurement clock cycles; A clock calibration module is used to perform clock calibration processing during the data processing according to the delay parameter.

11. The device according to claim 10, characterized in that The drift judgment module is further used to: determining a quantity variation amplitude according to the quantities of clock measurement units respectively represented by the plurality of measurement clock cycles; When the magnitude of the quantity change is greater than a magnitude threshold, determining that there is clock drift between the plurality of measurement clock cycles; When the magnitude of the quantity change is less than or equal to the magnitude threshold, it is determined that there is no clock drift between the multiple measurement clock cycles.

12. The device according to claim 11, characterized in that The drift judgment module is further used to: Performing sliding sampling processing on the multiple measurement clock cycles according to the sampling number to obtain multiple sampling windows; wherein the number of measurement clock cycles in the sampling window is equal to the sampling number, and the sampling number is an integer greater than one; Performing quantitative statistical processing on the number of clock measurement units respectively represented by a plurality of measurement clock cycles in the sampling window to obtain a statistical number; Determine the magnitude of the change between the statistical quantities corresponding to the multiple sampling windows.

13. The device according to claim 12, characterized in that The parameter determination module is further used to: Performing time statistical processing on the measurement times corresponding to the plurality of measurement clock cycles in the sampling window to obtain statistical time; Determine a delay parameter for the clock drift according to a statistical quantity corresponding to a sampling window with the latest statistical time among the multiple sampling windows.

14. A chip, characterized in that: The chip includes at least one of a programmable logic circuit and an executable instruction, and the chip runs in an electronic device to implement the data processing calibration method according to any one of claims 1 to 9.

15. An electronic device, characterized in that: The electronic device comprises: a memory for storing executable instructions; A processor, configured to implement the data processing calibration method according to any one of claims 1 to 9 when executing the executable instructions stored in the memory.

16. A computer-readable storage medium storing executable instructions, characterized in that: When the executable instructions are executed by a processor, the data processing calibration method according to any one of claims 1 to 9 is implemented.

17. A computer program product comprising executable instructions, characterized in that When the executable instructions are executed by a processor, the data processing calibration method according to any one of claims 1 to 9 is implemented.

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