Front-end chip of a data transmission system

Abstract

The present invention relates to a front-end chip of a data transmission system. The chip includes a receiving, transmitting, controlling, and switching circuit. The receiving circuit operates at a first voltage and is used to receive a first data signal. The transmitting circuit operates at the first voltage. In the normal mode of the chip, the control circuit operates at a second voltage and is used to generate a second data signal based on the first data signal to the transmitting circuit. The control circuit includes a clock pulse source, which is used to provide a clock pulse signal in the normal mode, wherein the control circuit operates based on the clock pulse signal. In the normal mode, the switching circuit operates at the first voltage and is used to control the second voltage to be suspended from being supplied to the control circuit to make the chip enter the sleep mode of the chip. The switching circuit also controls the second voltage to be supplied to the control circuit based on the first data signal in the sleep mode to make the chip return to the normal mode. The first voltage is higher than the second voltage.

Description

Technical Field

[0001] This application relates to a chip, and particularly to a chip that operates in a normal mode or a sleep mode according to a received signal. Background Art

[0002] In current technologies, due to cost considerations, many input / output devices use only one transmission protocol for communication at their transmission interfaces. Therefore, an additional front-end chip is generally used to convert the transmission protocol or expand the number of input / output ports according to the application of the system. However, the widespread application of front-end chips often causes an increase in the overall power consumption of the system, which has become an urgent problem to be solved in this field. Summary of the Invention

[0003] This application provides a chip for reducing the power consumption of a data transmission system, which includes an analog receiving circuit, an analog transmitting circuit, a digital control circuit, and a switching circuit. The analog receiving circuit operates at a first reference voltage and is used to receive a first data signal. The analog transmitting circuit operates at the first reference voltage. In the normal mode of the chip, the digital control circuit operates at a second reference voltage and is used to generate a second data signal to the analog transmitting circuit according to the first data signal. The digital control circuit includes a first clock pulse source. The first clock pulse source is used to provide a first clock pulse signal in the normal mode, and the digital control circuit operates according to the first clock pulse signal. In the normal mode of the chip, the switching circuit operates at the first reference voltage, and the switching circuit is used to control the second reference voltage to be suspended from being supplied to the digital control circuit so that the chip enters the sleep mode of the chip. The switching circuit also controls the second reference voltage to be supplied to the digital control circuit according to the first data signal in the sleep mode to return to the normal mode. The first reference voltage is higher than the second reference voltage.

[0004] This application provides a chip for reducing the power consumption of a data transmission system, which includes a digital control circuit and a switching circuit. In the normal mode of the chip, the digital control circuit operates at a first reference voltage. The digital control circuit includes a first clock pulse source. The first clock pulse source is used to generate a first clock pulse signal, and the digital control circuit is used to operate according to the first clock pulse signal. The switching circuit operates at a second reference voltage, where in the normal mode of the chip, the switching circuit is used to control the first reference voltage to be suspended from being supplied to the digital control circuit so that the chip enters the sleep mode of the chip. And in the sleep mode of the chip, the switching circuit controls the first reference voltage to be supplied to the digital control circuit according to a hot plug signal so that the chip returns to the normal mode. The second reference voltage is higher than the first reference voltage. The hot plug signal is generated by connecting the chip to an electronic device.

[0005] The chip of this application can reduce the overall power consumption of the chip in the sleep mode and maintain the function of waking up the chip from the sleep mode back to the normal mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A variety of forms of the present application can be better understood when reading the following embodiments and the drawings. It should be noted that, according to the standard operating habits in the art, the various features in the drawings are not drawn to scale. In fact, in order to clearly describe, the dimensions of some features may be deliberately enlarged or reduced.

[0007] Figure 1 FIG. is a schematic diagram of a data transmission system shown according to some embodiments.

[0008] Figure 2 FIG. is a schematic diagram of a front-end chip for a data transmission system shown according to some embodiments.

[0009] Figure 3 FIG. is a schematic diagram of a data transmission system shown according to other embodiments.

[0010] Figure 4 FIG. is a schematic diagram of a data transmission system shown according to other embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] Please refer to Figure 1 . In the data transmission system 10 of the present application, the front-end chip 200 can be switched between a normal mode and a sleep mode, and can be switched to the sleep mode to reduce power consumption when the front-end chip 200 is idle. The details are described as follows.

[0012] The data transmission system 10 includes a transmission device 100, a front-end chip 200, and a receiving device 300. The front-end chip 200 is coupled between the transmission device 100 and the receiving device 300. When the communication protocol used by the receiving device 300 is different from the communication protocol used by the transmission device 100, the front-end chip 200 is used to convert the signal format so that the receiving device 300 can receive the signal from the transmission device 100.

[0013] In this embodiment, the front-end chip 200 and the transmission device 100 and the receiving device 300 include interfaces for transmitting high-speed signals and low-speed signals. As Figure 1 shown, the high-speed signals include a data signal S1 transmitted through a channel CH1a between the transmission device 100 and the front-end chip 200, and a data signal S2 transmitted through a channel CH1b between the receiving device 300 and the front-end chip 200. The low-speed signals include an auxiliary signal AS1 transmitted through a channel CH2a between the transmission device 100 and the front-end chip 200, and an auxiliary signal AS2 transmitted through a channel CH2b between the receiving device 300 and the front-end chip 200. The low-speed signals also include a hot-plug signal HS generated when the receiving device is connected to the chip 200. The hot-plug signal HS is transmitted through channels CH3a and CH3b.

[0014] For example, the transmission device 100 is a personal computer that only uses the High Definition Multimedia Interface (HDMI) transmission protocol, and the receiving device 300 is a screen that only uses the DisplayPort (DP) transmission protocol. When the screen is connected to the front-end chip 200, a hot plug signal HS is generated and transmitted to the front-end chip 200. Then, the front-end chip 200 transmits the hot plug signal HS to the personal computer to notify that the screen has been connected. The personal computer then transmits the HDMI data signal S1 including the display content to the front-end chip 200, and the front-end chip 200 converts the HDMI signal S1 into a data signal S2 in the DP transmission protocol and transmits it to the screen, so that the screen can receive the data signal S2 and present the display content.

[0015] For another example, auxiliary signals (e.g., AS1, AS2) are used to communicate the transmission speed and other information of high-speed signals (e.g., S1, S2) under a specific communication protocol. Generally, devices (e.g., 100, 300) cannot determine the transmission protocol through the channels of the auxiliary signals (i.e., CH2a, CH2b). In some embodiments, the screen is connected to the computer through the front-end chip 200 and generates a hot plug signal HS to the computer. The computer and the screen adjust the high-speed signals through the auxiliary signals (e.g., determine the transmission speed or the number of transmission channels), and the computer sends the high-speed signals (including the display content) to the screen through the high-speed channel. In some embodiments, the auxiliary signal AS1 and the auxiliary signal AS2 are also referred to as sideband signals.

[0016] The front-end chip 200 includes an analog receiving circuit 201, an analog transmitting circuit 202, a digital control circuit 220, and a switching circuit 240. The analog receiving circuit 201 is used to transmit the data signal S1 and the auxiliary signal AS1, and the analog transmitting circuit 202 is used to transmit the data signal S2 and the auxiliary signal AS2, where the analog receiving circuit 201 and the analog transmitting circuit 202 belong to the physical layer of the front-end chip 200. The digital control circuit 220 is coupled between the analog receiving circuit 201 and the analog transmitting circuit 202, and is used to convert the data signal S1 into the data signal S2, and to convert the auxiliary signal AS1 into the auxiliary signal AS2 or convert the auxiliary signal AS2 into the auxiliary signal AS1. The digital control circuit 220 is further used to directly receive the hot plug signal HS. In other words, the hot plug signal HS is not transmitted through the analog receiving circuit 201 and the analog transmitting circuit 202.

[0017] The switching circuit 240 is coupled to and used to control the analog receiving circuit 201, the analog transmitting circuit 202, and the digital control circuit 220 to operate in a normal mode or a sleep mode. In the normal mode, the data signal S1 is continuously transmitted to the front-end chip 200, and the functions and power supplies of the analog receiving circuit 201, the analog transmitting circuit 202, and the digital control circuit 220 are all fully turned on to convert the data signal S1 and generate the data signal S2. When no signal is transmitted into the front-end chip 200 (i.e., idle), the switching circuit 240 will control the analog receiving circuit 201, the analog transmitting circuit 202, and the digital control circuit 220 to enter the sleep mode, completely stopping the power supply to the digital control circuit 220. The switching circuit 240 determines whether to leave the sleep mode based on at least one of the data signal S1, the auxiliary signal AS1, the auxiliary signal AS2, and the hot plug signal HS.

[0018] In data transmission system 10, the front-end chip 200 operates at reference voltages VDD1 and VDD2, where reference voltage VDD1 (in some embodiments, the core voltage, with a voltage value of approximately 1.0V or 1.1V) is lower than reference voltage VDD2 (in some embodiments, the pad voltage, with a voltage value of approximately 3.3V). The digital control circuit 220 operates entirely at reference voltage VDD1, and the switching circuit 240 operates at reference voltage VDD2. In other words, when the reference voltage VDD1 is suspended from being supplied to the digital control circuit 220, the digital control circuit 220 is completely turned off. The analog receiving circuit 201 includes a first part 201_1 and a second part 201_2; the analog transmitting circuit 202 includes a first part 202_1 and a second part 202_2. Among them, the first part 201_1 and the first part 202_1 operate at reference voltage VDD2 (i.e., the pad voltage); the second part 201_2 and the second part 202_2 operate at reference voltage VDD1 (i.e., the core voltage). The reference voltage VDD2 is used to provide power for the first part 201_1 to receive the data signal S1 and the auxiliary signal AS1 from the transmission device 100, and for the first part 202_1 to receive the auxiliary signal AS2 from the receiving device 300 or transmit the data signal S2 and the auxiliary signal AS2 to the receiving device 300. The reference voltage VDD1 is used to provide power for the second part 201_2 to transmit the data signal S1 and the auxiliary signal AS1 to the digital control circuit 220, or to receive the auxiliary signal AS1 from the digital control circuit 220; the reference voltage VDD1 is used to provide power for the second part 202_2 to receive the data signal S2 and the auxiliary signal AS2 from the control circuit 220, or to transmit the auxiliary signal AS2 to the digital control circuit 220. The switching circuit 240 is used to control whether the reference voltage VDD1 (i.e., the core voltage) is supplied to the digital control circuit 220 to perform the conversion between the normal mode and the sleep mode. The process details are described as follows.

[0019] Please refer to Figure 2 The digital control circuit 220 in the front-end chip 200 includes a processing unit 221, a clock pulse source 222, a signal conversion unit 223, an auxiliary control unit 224, and a hot plug detector 225, and the switching circuit 240 in the front-end chip 200 includes a signal detector 241, a processing unit 242, a clock pulse source 243, a storage unit 244, a potential converter 245, and a resetter 246.

[0020] In the normal mode, the clock pulse source 222 generates a clock pulse signal CLK1 and supplies it to the processing unit 221. The clock pulse signal CLK1 is a high-speed clock pulse signal, for example, a high-speed clock pulse signal with a frequency on the order of megahertz (MHz), but not limited thereto. The processing unit 221 controls the signal conversion unit 223 (not shown in the connection diagram) to convert the received data signal S1 into a data signal S2 according to the clock pulse signal CLK1, and controls the auxiliary control unit 224 (not shown in the connection diagram) to transmit the auxiliary signal AS1 and the auxiliary signal AS2. The processing unit 221 also controls the hot plug detector 225 to receive and transmit the hot plug signal HS.

[0021] In the sleep mode, since the reference voltage VDD1 is suspended from being supplied to the digital control circuit 220, the clock pulse source 222 stops generating the clock pulse signal CLK1, causing the processing unit 221 to stop working. In some embodiments, the processing unit 221 and the clock pulse source 222 are the components with the highest power consumption in the front-end chip 200. Therefore, when the digital control circuit 220 is completely turned off, the power consumption of the front-end chip 200 can be significantly reduced, for example, from the milliwatt (mW) level to the micro-watt (μW) level.

[0022] In the switching circuit 240, the processing unit 242 is coupled to the signal detector 241, the clock pulse source 243, the storage unit 244, and the potential converter 245, and the potential converter 245 is further coupled to the resetter 246. In the present application, the reference voltage VDD2 is continuously supplied to the front-end chip 200 in both the normal mode and the sleep mode. Therefore, the switching circuit 240 in the front-end chip 200 does not stop operating due to switching to the sleep mode.

[0023] The clock pulse source 243 generates a clock pulse signal CLK2 and supplies it to the processing unit 242. The clock pulse signal CLK2 is a low-speed clock pulse signal, for example, a low-speed clock pulse signal with a frequency on the order of kilohertz (KHz), but not limited thereto. In other words, the clock pulse signal CLK2 has a lower frequency than the clock pulse signal CLK1. Generally speaking, the higher the frequency of the generated clock pulse, the greater the power consumption. Therefore, the power consumption of the clock pulse source 243 is lower than that of the clock pulse source 222.

[0024] In the normal mode, the processing unit 242 controls the potential converter 245 according to the relatively low-speed clock pulse signal CLK2, so that the potential converter 245 converts the operation information OD1 transmitted from the digital control circuit 220 from the voltage domain of the reference voltage VDD1 to the voltage domain of the reference voltage VDD2. The converted operation information OD2 is stored in the storage unit 244. Since the digital control circuit 220 operates continuously in the normal mode, the potential converter 245 continuously converts the operation information OD1 and updates the operation information OD2 stored in the storage unit 244. In some embodiments, the storage unit 244 may be implemented by a register latch module, but not limited thereto.

[0025] When the front-end chip 200 needs to switch from the normal mode to the sleep mode, the digital control circuit 220 notifies the processing unit 242 in the switching circuit 240 to perform the mode switching. More specifically, the digital control circuit 220 transmits the operation information OD1 with the sleep information SD1 to the potential converter 245, and the potential converter 245 converts the operation information OD1 into the operation information OD2 (the content is the same as the operation information OD1) and stores it in the storage unit 244. The processing unit 242 can then perform the operation of switching from the normal mode to the sleep mode according to the sleep information SD1 (included in the operation information OD2) in the storage unit 244. In some embodiments, it can be implemented by transmitting a lock signal LOCK and an unlock signal UNLOCK.

[0026] In some embodiments, the digital control circuit 220 and the potential converter 245 are connected by at least two channels. The first channel is used to transmit information including the unlock signal UNLOCK, and the second channel is used to transmit other information in the operation information OD1 except the unlock signal UNLOCK, but not limited thereto. After the processing unit 242 accesses the sleep information SD1 (through the storage unit 244), the processing unit 242 can transmit the lock signal LOCK to the potential converter 245 to close the second channel. The potential converter 245 will no longer receive information other than the unlock signal UNLOCK, so that other information in the operation information OD2 except the unlock signal UNLOCK will no longer be updated. This action is to prevent the potential converter 245 from receiving unknown signals from the circuit in the corresponding block of the reference voltage VDD1 after the reference voltage VDD1 is turned off.

[0027] Subsequently, the processing unit 242 generates a reset signal RS1 and a reset signal RS2 and transmits them to the analog receiving circuit 201 and the analog transmitting circuit 202 respectively. After the analog receiving circuit 201 and the analog transmitting circuit 202 receive the reset signal RS1 and the reset signal RS2 respectively, the analog receiving circuit 201 turns off the function of the second part 201_2, and the analog transmitting circuit 202 turns off the function of the second part 202_2.

[0028] Thereafter, the processing unit 242 controls the reference voltage VDD1 to suspend supply to the front-end chip 200. For example, but not limited to, controlling a voltage regulator on a printed circuit board (PCB), controlling a power switch on the printed circuit board, or a power switch reference voltage VDD1 (i.e., the core voltage) inside the front-end chip 200, so that the digital control circuit 220, the second part 201_2 of the analog receiving circuit 201, and the second part 202_2 of the analog transmitting circuit 202 are turned off.

[0029] It should be understood that the resetter 246 can generate a status signal SS to the potential converter 245 in response to the power supply state of the reference voltage VDD1 (i.e., the core voltage). In some embodiments, when the reference voltage VDD1 is not supplied to the digital control circuit 220, the resetter 246 generates a status signal SS with a first value to the potential converter 245. The potential converter 245 closes the second channel connected to the digital control circuit 220 according to the status signal SS with the first value, so that the potential converter 245 does not receive all information (including the unlock signal UNLOCK). Thus, the operation information OD2 in the storage unit 244 remains unchanged, and the front-end chip 200 thus enters the sleep mode.

[0030] In the sleep mode, since the reference voltage VDD1 is suspended from being supplied to the front-end chip 200, the digital control circuit 220 is turned off, but the first part 201_1 of the analog receiving circuit 201 operating at the reference voltage VDD2 can still receive the data signal S1 and the auxiliary signal AS1, and the first part 202_1 of the analog transmitting circuit 202 operating at the reference voltage VDD2 can still receive the auxiliary signal AS2. The signal detector 241 can detect any of the foregoing signals. Additionally, in some embodiments, the signal detector 241 can also directly receive the hot plug signal HS without passing through the analog transmitting circuit 202. In some embodiments, the foregoing data signal S1, auxiliary signal AS1, auxiliary signal AS2, and hot plug signal HS are referred to as wake-up conditions. Therefore, in the sleep mode, the signal detector 241 can generate a control signal CS to the processing unit 242 according to the wake-up conditions (e.g., when any of the above signal potentials change) to execute the program to leave the sleep mode.

[0031] In the sleep mode, the front-end chip 200 of the present application can completely cut off the supply of the reference voltage VDD1 to reduce the power consumption of the front-end chip 200 (e.g., reduce it to the power consumption level of microamperes (uA)), and maintain the ability to wake up the front-end chip 200 to return to the normal mode. The process of the front-end chip 200 returning from the sleep mode to the normal mode is described as follows.

[0032] When the front-end chip 200 wants to switch from the sleep mode to the normal mode, in response to the control signal CS of the signal detector 241, the processing unit 242 updates the sleep information SD1 stored in the storage unit 244 to the wake-up information SD2. According to the wake-up information SD2 in the storage unit 244, the processing unit 242 can control the restoration of the supply of the reference voltage VDD1 (i.e., the core voltage) to the front-end chip 200 (e.g., controlling the voltage regulator, power switch on the printed circuit board, or the power switch inside the front-end chip). In response to the restoration of the power supply of the reference voltage VDD1, the resetter 246 generates a status signal SS with a second value to the potential converter 245, and the potential converter 245 releases the blocking state of the unlock signal UNLOCK according to the status signal SS with the second value. Then, after the power supply of the reference voltage VDD1 is restored, the digital control circuit 220 transmits the unlock signal UNLOCK to the potential converter 245, and then the potential converter 245 transmits it to the storage unit 244. After receiving the unlock signal UNLOCK, the processing unit 242 determines that after the storage unit 244 receives the unlock signal UNLOCK, it will control the potential converter 245 to convert the operation information OD2 stored in the storage unit 244 from the voltage domain of the reference voltage VDD2 to the voltage domain of the reference voltage VDD1, and output it as the operation information OD1 to the digital control circuit 220. The digital control circuit 220 returns to the working state before entering the sleep mode according to the operation information OD1, so that the front-end chip 200 returns to the normal mode. It is worth mentioning that the digital control circuit 220 first obtains the supply of the reference voltage VDD1 (i.e., the core voltage) and then restores the working power, and then receives the operation information OD1, so there will be no floating state where the operation information OD1 is received first without power supply.

[0033] When switching from the sleep mode to the normal mode, after the reference voltage VDD1 is restored to the supply of the front-end chip 200, the processing unit 242 stops transmitting the reset signal RS1 and the reset signal RS2, so that the analog receiving circuit 201 and the analog transmitting circuit 202 restore the functions of the second part 201_2 and the second part 202_2. Since the analog receiving circuit 201 and the analog transmitting circuit 202 are enabled after obtaining the supply of the reference voltage VDD1 first, there will be no floating state where they are enabled first without power supply.

[0034] The settings of the data transmission system 10 provided above are for illustrative purposes only. Settings of various different data transmission systems 10 are within the scope of consideration of this application. For example, please refer to Figure 3 and Figure 4 data transmission systems 30 and 40.

[0035] In some embodiments, such as Figure 3 data transmission system 30, the front-end chip 200 is disposed in the transmission device 100 and coupled to the processor 105 of the transmission device 100 and is controlled by the processor 105. Since the processor 105 can know whether the transmission device 100 is to transmit the data signal S1 or the auxiliary signal AS1, the processor 105 can directly notify the front-end chip 200 of the operating state. When the transmission device 100 does not need to transmit the data signal S1, the processor 105 can control the front-end chip 200 to enter the sleep mode. In the sleep mode, when the transmission device 100 is ready to transmit the data signal S1, the processor 105 can control the front-end chip 200 to return to the normal mode, that is, the front-end chip 200 does not need to detect the data signal S1 and the auxiliary device AS1 from the transmission device 100.

[0036] In some embodiments, when the receiving device 300 is not yet connected to the front-end chip 200 in the transmission device 100, the front-end chip 200 is in the sleep mode. In this case, the front-end chip 200 determines whether the receiving device 300 is connected thereto based on the hot plug signal HS. When the front-end chip 200 detects the hot plug signal HS, it means that the receiving device 300 has been connected, so the front-end chip is returned to the normal mode to transmit the data signal S1.

[0037] In other embodiments, when the receiving device 300 has been connected to the front-end chip 200 in the transmission device 100, but the receiving device 300 is turned off and cannot receive the data signal S2, the front-end chip 200 is in the sleep mode because it does not need to convert the data signal S1 to the data signal S2. In this case, the front-end chip 200 determines whether the receiving device 300 is ready to receive the data signal S2 based on the auxiliary signal AS2. When the front-end chip 200 detects the auxiliary signal AS2 transmitted after the receiving device 300 is turned on, it means that the receiving device 300 can receive the data signal S2, so the front-end chip 200 is returned to the normal mode. The processor 105 can then transmit the data signal S1.

[0038] In some embodiments, such as Figure 4For the data transmission system 40, the front-end chip 200 is disposed in the receiving device 300 and coupled to the processor 305 of the receiving device 300, and is controlled by the processor 305. Since the processor 305 can know whether the receiving device 300 is to transmit the auxiliary signal AS2, the processor 305 can directly notify the front-end chip 200 of the operation status. The front-end chip 200 can receive the hot plug signal HS from the receiving device 300, but the hot plug signal HS needs to be transmitted to the transmission device 100 only when the transmission device 100 is connected. The auxiliary signal is a signal generated after the transmission device 100 is connected. Therefore, in the sleep mode, the front-end chip 200 only needs to detect the data signal S1 and the auxiliary signal AS1 from the transmission device 100 to determine whether the front-end chip 200 returns to the normal mode.

[0039] The foregoing description briefly presents the features of certain embodiments of the present application, enabling those of ordinary skill in the art to which the present application pertains to more comprehensively understand the various forms of the present application. Those of ordinary skill in the art to which the present application pertains can understand that they can easily use the content of the present application as a basis to design or change other processes and structures to achieve the same purpose and / or the same advantages as the implementation here. Those of ordinary skill in the art to which the present application pertains should understand that these equivalent implementations still fall within the spirit and scope of the content of the present application, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of the content of the present application.

[0040] Description of Reference Numerals

[0041] 10: Data transmission system

[0042] 30: Data transmission system

[0043] 40: Data transmission system

[0044] 100: Transmission device

[0045] 105: Processor

[0046] 300: Receiving device

[0047] 305: Processor

[0048] 200: Front-end chip

[0049] 201: Analog receiving circuit

[0050] 202: Analog transmission circuit

[0051] 201_1: First part

[0052] 201_2: Second part

[0053] 202_1: First part

[0054] 202_2: Second part

[0055] 220: Digital control circuit

[0056] 221: Processing unit

[0057] 222: Clock pulse source

[0058] 223: Signal conversion unit

[0059] 224: Auxiliary control unit

[0060] 225: Hot plug detector

[0061] 240: Switching circuit

[0062] 241: Signal detector

[0063] 242: Processing unit

[0064] 243: Clock pulse source

[0065] 244: Storage unit

[0066] 245: Potential converter

[0067] 246: Resetter

[0068] CH1a: Channel

[0069] CH1b: Channel

[0070] CH2a: Channel

[0071] CH2b: Channel

[0072] CH3a: Channel

[0073] CH3b: Channel

[0074] S1: Data signal

[0075] S2: Data signal

[0076] AS1: Auxiliary signal

[0077] AS2: Auxiliary signal

[0078] HS: Hot plug signal

[0079] RS1: Reset signal

[0080] RS2: Reset signal

[0081] CS: Control signal

[0082] SS: Status Signal

[0083] OD1: Operation Information

[0084] OD2: Operation Information

[0085] SD1: Sleep Information

[0086] SD2: Wake-up Information

[0087] CLK1: Clock Pulse Signal

[0088] CLK2: Clock Pulse Signal

[0089] VDD1: Reference Voltage

[0090] VDD2: Reference Voltage

[0091] LOCK: Locking Signal

[0092] UNLOCK: Unlock Signal

Claims

1. A chip for reducing the power consumption of a data transmission system, comprising: an analog receiving circuit operating at a first reference voltage and for receiving a first data signal; an analog transmitting circuit operating at the first reference voltage; a digital control circuit which, in the normal mode of the chip, operates at a second reference voltage and is for generating a second data signal based on the first data signal and supplying it to the analog transmitting circuit, wherein the digital control circuit includes a first clock pulse source for providing a first clock pulse signal in the normal mode, and wherein the digital control circuit operates based on the first clock pulse signal; and a switching circuit which, in the normal mode, operates at the first reference voltage, and the switching circuit is for controlling the suspension of the supply of the second reference voltage to the digital control circuit to cause the chip to enter the sleep mode of the chip, and the switching circuit also controls the supply of the second reference voltage to the digital control circuit based on the first data signal in the sleep mode to cause the chip to return to the normal mode, wherein the first reference voltage is higher than the second reference voltage.

2. The chip according to claim 1, wherein, the switching circuit includes: a signal detector for detecting the first data signal and generating a control signal when the chip is in the sleep mode; a storage unit for storing the operation information of the digital control circuit; a second clock pulse source for providing a second clock pulse signal, wherein the frequency of the second clock pulse signal is lower than the frequency of the first clock pulse signal; and a processing unit for controlling the supply of the second reference voltage to the digital control circuit based on the second clock pulse signal and the control signal to cause the chip to return to the normal mode when the chip is in the sleep mode, and for controlling the suspension of the supply of the second reference voltage to the digital control circuit based on the second clock pulse signal and the operation information to cause the chip to enter the sleep mode when the chip is in the normal mode.

3. The chip according to claim 2, wherein, the switching circuit further includes: a potential converter for converting the operation information of the digital control circuit from the second reference voltage to the first reference voltage and storing it in the storage unit, wherein when the chip is in the sleep mode, the processing unit is further for controlling the potential converter based on the operation information to keep the operation information stored in the storage unit unchanged, wherein when the chip enters the normal mode from the sleep mode, the processing unit is further for controlling the potential converter to convert the operation information from the first reference voltage to the second reference voltage for transmission to the digital control circuit; and A resetter, wherein when the second reference voltage changes from being supplied to the digital control circuit to being suspended from being supplied to the digital control circuit, the resetter generates a status signal to the potential converter, the status signal having a first value, wherein the potential converter receives the status signal having the first value and transmits first information in the operation information stored in the storage unit to the processing unit, wherein the first information is used to enable the processing unit to control the potential converter to keep the operation information stored in the storage unit unchanged. Wherein when the second reference voltage changes from being suspended from being supplied to the digital control circuit to being supplied to the digital control circuit, the resetter generates the status signal to the potential converter, the status signal having a second value, wherein the potential converter receives the status signal having the second value and transmits second information in the operation information stored in the storage unit to the processing unit, wherein the second information is used to enable the processing unit to control the potential converter to stop keeping the operation information stored in the storage unit unchanged.

4. The chip according to claim 2, characterized in that, the analog receiving circuit also operates at the second reference voltage and is used to transmit the first data signal to the digital control circuit, and the analog transmitting circuit also operates at the second reference voltage to receive the second data signal. Wherein before the chip enters the sleep mode, the processing unit is further used to generate a first reset signal to the analog receiving circuit and generate a second reset signal to the analog transmitting circuit, wherein the first reset signal is used to prevent the analog receiving circuit from transmitting the first data signal to the digital control circuit, and the second reset signal is used to prevent the analog transmitting circuit from receiving the second data signal from the digital control circuit.

5. The chip according to claim 1, characterized in that, the analog receiving circuit is further used to receive an auxiliary signal, and the switching circuit is further used to control the supply of the second reference voltage to the digital control circuit according to the auxiliary signal when the chip is in the sleep mode so that the chip returns to the normal mode, wherein the auxiliary signal includes information about the type of the first data signal, and the transmission speed of the auxiliary signal is less than the transmission speed of the first data signal.

6. A chip for reducing the power consumption of a data transmission system, comprising: A digital control circuit, when the chip is in the normal mode, the digital control circuit operates at a first reference voltage, wherein the digital control circuit includes a first clock pulse source for generating a first clock pulse signal, and wherein the digital control circuit operates according to the first clock pulse signal; and A switching circuit that operates at a second reference voltage. When the chip is in the normal mode, the switching circuit is used to control the suspension of the supply of the first reference voltage to the digital control circuit so that the chip enters the sleep mode. When the chip is in the sleep mode, the switching circuit controls the supply of the first reference voltage to the digital control circuit according to a hot-swap signal so that the chip returns to the normal mode. Wherein the second reference voltage is higher than the first reference voltage, and the hot-swap signal is generated when the chip is connected to an electronic device. Wherein the switching circuit further includes: A signal detector for detecting the hot-swap signal and generating a control signal when the chip is in the sleep mode. A storage unit for storing the operation information of the digital control circuit. A second clock pulse source for providing a second clock pulse signal. And A processing unit for controlling the supply of the first reference voltage to the digital control circuit according to the second clock pulse signal and the control signal so that the chip returns to the normal mode when the chip is in the sleep mode, and for controlling the suspension of the supply of the first reference voltage to the digital control circuit according to the second clock pulse signal and the operation information so that the chip enters the sleep mode when the chip is in the normal mode. Wherein the frequency of the first clock pulse signal is higher than that of the second clock pulse signal. A potential converter for converting the operation information of the digital control circuit from the first reference voltage to the second reference voltage and storing it in the storage unit. Wherein when the chip is in the sleep mode, the processing unit is further used to control the potential converter according to the operation information so that the potential converter keeps the operation information stored in the storage unit unchanged. Wherein when the chip enters the normal mode from the sleep mode, the processing unit is further used to control the potential converter to convert the operation information from the second reference voltage to the first reference voltage for transmission to the digital control circuit.

7. The chip according to claim 6, Characterized in that The switching circuit further includes: A resetter. When the supply of the first reference voltage to the digital control circuit changes from being supplied to being suspended, the resetter generates a status signal to the potential converter. The status signal has a first value. The potential converter receives the status signal with the first value and transmits the first information in the operation information stored in the storage unit to the processing unit. The first information is used to enable the processing unit to control the potential converter so that the potential converter keeps the operation information stored in the storage unit unchanged. When the first reference voltage changes from being suspended from being supplied to the digital control circuit to being supplied to the digital control circuit, the reseter generates the status signal to the potential converter, the status signal having a second value, wherein the potential converter receives the status signal having the second value and transmits second information in the operation information stored in the storage unit to the processing unit, wherein the second information is used to cause the processing unit to control the potential converter to stop keeping the operation information stored in the storage unit unchanged.

8. The chip according to claim 6, characterized in that it further comprises: an analog transmission circuit, operating at the second reference voltage, for receiving a first auxiliary signal, wherein, when the chip is in the sleep mode, the switching circuit is further configured to control the supply of the first reference voltage to the digital control circuit according to the first auxiliary signal so that the chip returns to the normal mode; and an analog reception circuit, operating at the second reference voltage, for receiving a first data signal, wherein the analog reception circuit also operates at the first reference voltage when the chip is in the normal mode and transmits the first data signal to the digital control circuit, wherein the digital control circuit generates a second data signal to the analog transmission circuit according to the first data signal, wherein the analog transmission circuit also operates at the first reference voltage when the chip is in the normal mode and transmits the first auxiliary signal to the digital control circuit, wherein the digital control circuit generates a second auxiliary signal to the analog reception circuit according to the first auxiliary signal, wherein the transmission speed of the first auxiliary signal is less than the transmission speed of the first data signal.

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