A highly energy-efficient dedicated processor for multi-level digital halftoning

Abstract

The present invention belongs to the field of integrated circuit design, and discloses a high-performance dedicated processor for multi-level halftone, which adopts SIMD-VLIW architecture and includes data memory, code memory, line cache memory, lookup table memory, register stack and instruction pipeline; the characteristics are: the data memory is used for software stack; the code memory is used for processor instruction fetch operation; the line cache memory is used to save errors; the lookup table memory is used to store lookup table; the instruction pipeline adopts a three-level pipeline, which is an instruction fetch pipeline, a decoding pipeline and an execution pipeline. The dedicated multi-level halftone processor designed by the present invention has higher execution efficiency, and compared with the basic RISC-V integer instruction set, the performance is improved by 4 times and the area is increased by 34%.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a high-performance and low-power consumption dedicated multi-level halftone processor (Application Specific Instruction Set Processor, ASIP). Background Art

[0002] Digital halftoning is a key link in modern printing. It can simulate continuous tone images with fewer colors. The generated image is closer to the original image visually. Halftoning generally refers to the process of binarizing the original image, and the output is only black and white. Multi-level halftoning is an extension of halftoning. The output has multiple color levels, which can effectively improve the similarity between the quantized image and the original image, and gradually become a research hotspot in the field of halftoning. The image quality generated by different halftoning methods is very different. Order dithering simply compares pixels with thresholds to determine whether the output is white or black. This method has high parallelism and is very convenient for hardware implementation, but its image quality often cannot meet actual needs; Direct binary search generates the best image quality, but it has high computational complexity and is not conducive to hardware implementation; Error diffusion can achieve a good compromise between image quality and speed. The algorithm is simple, efficient and widely used.

[0003] At present, the multi-level halftone processing of printers is mainly implemented based on ASIC (Application-specific Integrated Circuit), which lacks certain flexibility and scalability. It is of great significance to study high-performance, flexible and configurable multi-level halftone processing and its key technologies. High-performance, flexible and configurable multi-level halftone processors involve many key technologies, mainly including architecture design and instruction set design. Summary of the invention

[0004] In order to solve the above technical problems existing in the prior art, the object of the present invention is to provide a high-performance dedicated processor for multi-level halftone. The specific technical solution is as follows:

[0005] A high-performance special processor for multi-level halftone, adopting SIMD-VLIW architecture, including data memory, code memory, line cache memory, lookup table memory, register stack and instruction pipeline; the data memory is used for software stack; the code memory is used for processor instruction fetch operation; the line cache memory is used to save errors; the lookup table memory is used to store lookup table; the instruction pipeline adopts a three-stage pipeline, namely, instruction fetch pipeline, decoding pipeline and execution pipeline.

[0006] Furthermore, the register stack includes 32-bit scalar registers, 32-bit vector registers and a program counter, the 32-bit scalar registers include 1 constant zero register (ZERO), 1 link register (LR) and 1 stack pointer register (SP), and the 32-bit vector registers are divided into 4 groups, each group contains a different number of vector registers.

[0007] Furthermore, the 32-bit vector register grouping includes V type, VD type, VQ type and VO type.

[0008] Furthermore, the SIMD-VLIW architecture model includes four instruction slots, namely slot0, slot1, slot2 and slot3. Four instructions are executed in parallel in each cycle. Each instruction slot contains different instruction types and supports SIMD instructions. Slot0 accesses the data memory and code memory through the DM read-write interface and the PM read-write interface respectively. Slot1 and slot2 are used to access the line cache memory through a group of LM read-write interfaces respectively. Slot3 accesses the lookup table memory through the TM read interface.

[0009] Furthermore, the instruction set classification adopted by the processor includes scalar instruction classification and vector instruction classification.

[0010] The beneficial effects of the present invention are as follows: the dedicated multi-level halftone processor designed by the present invention has higher execution efficiency, and compared with the basic RISC-V integer instruction set, the performance is improved by 4 times and the area is increased by 34%. The necessity of formulating dedicated instructions for intensive and frequent computing operations is verified, and the resource overhead is not increased much, but the performance is significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is an example diagram of the storage architecture of the multi-level halftone processor of the present invention;

[0012] Figure 2 is an example diagram of a lookup table memory of the present invention;

[0013] Figure 3 is an example diagram of grouping of vector registers of the present invention;

[0014] Figure 4 is an example diagram of the SIMD-VLIW architecture of the present invention;

[0015] Figure 5 This is an example diagram of the instruction set classification of the present invention. DETAILED DESCRIPTION

[0016] The structure of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0017] The high-performance dedicated processor for multi-level halftone of the present invention adopts SIMD-VLIW architecture, fully utilizes the characteristics of instruction-level parallelism and data-level parallelism, and increases the amount of processed data as much as possible within a unit instruction cycle to achieve acceleration effect.

[0018] The high-performance dedicated processor for multi-level halftone is mainly composed of a data memory, a code memory, a line cache memory, a lookup table memory, a register stack and an instruction pipeline; wherein the data memory is mainly used for a software stack; the code memory is mainly used for a processor instruction fetch operation; considering that the error diffusion mode needs to save the error of the previous line, a line cache memory is introduced to save the error; considering that the ordered dithering mode requires a threshold matrix, a lookup table memory is introduced to store the lookup table; the register stack is mainly composed of 32 32-bit scalar registers (indicated by X), 32 32-bit vector registers (indicated by V) and 1 program counter, the 32 32-bit scalar registers include 1 constant zero register (ZERO), 1 link register (LR) and 1 stack pointer register (SP), and the 32 32-bit vector registers can be divided into 4 groups, each group includes a different number of vector registers, such as Figure 3 shown.

[0019] The instruction pipeline adopts a three-stage pipeline, namely the instruction fetch pipeline, the decoding pipeline and the execution pipeline; this processor contains general scalar instructions and customized special instructions. The extended special instruction unit mainly includes 4 customized instructions.

[0020] The instruction vcmp obtains the source operands specified by src1 and the source operands specified by src2, and performs unsigned vector comparison according to a specific bit width, supporting 8-bit / 10-bit / 16-bit comparisons; the source register can be a V-type vector register, a VD-type vector register, a VQ-type vector register, and a VO-type vector register, and saves the comparison results to specific bits of the destination register; taking 8-bit as an example, the instruction vcmp.8b supports 8-bit data comparison. When src1 and src2 are V-type vector registers, bits 0 to 7, bits 8 to 15, bits 16 to 23, and bits 24 to 31 are compared as 4 independent elements, and the comparison results are saved to bits 0, 8, 16, and 24 in the destination vector register. One instruction cycle can get 4 comparison results; when src1 and src2 are VD-type vector registers, one instruction cycle can get 8 comparison results; when src1 and src2 are VQ-type vector registers, one instruction cycle can get 16 comparison results;

[0021] The instruction vsumd obtains the source operand specified by src, and performs vector summation according to a specific bit width, supporting 8-bit / 10-bit / 16-bit summation; the source register can be a V-type vector register, a VD-type vector register, a VQ-type vector register, and a VO-type vector register, and the summation result is saved to the destination register; taking 8-bit as an example, the instruction vsumd.8b supports 8-bit data summation. When src is a V-type vector register, bits 0 to 7, bits 8 to 15, bits 16 to 23, and bits 24 to 31 are summed as 4 independent elements, and the summation result is saved to the destination vector register. The summation result of 4 elements can be obtained in one instruction cycle; when src1 and src2 are VD-type vector registers, the summation result of 8 elements can be obtained in one instruction cycle; when src1 and src2 are VQ-type vector registers, the summation result of 16 elements can be obtained in one instruction cycle;

[0022] The instruction vadd obtains the source operands specified by src1 and the source operands specified by src2, and performs unsigned vector summation according to a specific bit width, supporting 8-bit / 10-bit / 16-bit summation; the source register can be a V-type vector register, a VD-type vector register, a VQ-type vector register, and a VO-type vector register, and the summation result is saved to the destination register; taking 8-bit as an example, the instruction vadd.8b supports 8-bit vector summation. When src1 and src2 are V-type vector registers, bits 0 to 7, bits 8 to 15, Bits 16 to 23 and bits 24 to 31 are treated as 4 independent elements respectively, each summation result is extended to 16 bits, and the summation result is saved in the destination vector VD type register, and 4 summation results can be obtained in one instruction cycle; when src1 and src2 are VD type vector registers, 8 summation results can be obtained in one instruction cycle, and the summation results are saved in the destination vector VQ type register; when src1 and src2 are VQ type vector registers, 16 summation results can be obtained in one instruction cycle, and the summation results are saved in the destination vector VO type register;

[0023] The instruction vwmulu obtains the source operand specified by src1 and the source operand specified by src2, and performs unsigned vector product according to a specific bit width, supporting 8-bit / 10-bit / 16-bit products; the source register can be a V-type vector register, a VD-type vector register, a VQ-type vector register, and a VO-type vector register, and the sum result is saved to the destination register; taking 8-bit as an example, the instruction vwmulu.8b supports 8-bit unsigned vector product. When src1 and src2 are V-type vector registers, bit 0 to bit 7, bit 8 to bit 15. Bits 16 to 23 and bits 24 to 31 are treated as 4 independent elements respectively. Each product result is extended to 16 bits and saved in the destination vector VD type register. One instruction cycle can get 4 product results; when src1 and src2 are VD type vector registers, one instruction cycle can get 8 product results and save the product results in the destination vector VQ type register; when src1 and src2 are VQ type vector registers, one instruction cycle can get 16 product results and save the product results in the destination vector VO type register;

[0024] The data memory DM address space is defined at 0x0000-0x1FFF, with a size of 8KB; the code memory PM address space is defined at 0x2000-0x3FFF, with a size of 8KB; the line cache memory LM address space is defined at 0x4000-0x7FFF, with a size of 16KB; the lookup table memory TM address space is defined at 0x8000-0xBFFF, with a size of 16KB. Example

[0025] like Figure 1 As shown in the figure, the storage architecture model of the high-performance dedicated processor of the present invention, the ASIP core core can access different memories through corresponding interfaces, the data memory DM address space is defined at 0x0000-0x1FFF, the size is 8KB; the code memory PM address space is defined at 0x2000-0x3FFF, the size is 8KB; the line cache memory LM address space is defined at 0x4000-0x7FFF, the size is 16KB; the lookup table memory TM address space is defined at 0x8000-0xBFFF, the size is 16KB.

[0026] like Figure 2 As shown, a hardware model of a lookup table memory is taken as an example, where each table entry is an 8-bit or 10-bit value for supporting an ordered dithering mode.

[0027] The register file mainly consists of 32 32-bit scalar registers (represented by X), 32 32-bit vector registers (represented by V) and 1 program counter. The 32 32-bit scalar registers include 1 constant zero register (X[0]), 1 link register (X[1]) and 1 stack pointer register (X[2]).

[0028] like Figure 3 As shown, a vector register grouping model is taken as an example, each group contains different numbers of vector registers, and the grouping includes V type, VD type, VQ type and VO type. The V type includes 32 vector registers, and each register has a bit width of 32 bits; the VD type includes 16 vector registers, each register is spliced ​​by 2 V type registers, and the bit width is 64 bits; the VQ type includes 8 vector registers, each register is spliced ​​by 4 V type registers, and the bit width is 128 bits; the VO type includes 4 vector registers, each register is spliced ​​by 8 V type registers, and the bit width is 256 bits;

[0029] like Figure 4 As shown, a SIMD-VLIW architecture model is taken as an example, which includes 4 instruction slots, namely slot0, slot1, slot2 and slot3. Four instructions can be executed in parallel in each cycle. Each instruction slot contains different instruction types and supports SIMD instructions. Slot0 can access the data memory and code memory through the DM read-write interface and the PM read-write interface respectively. Slot1 and slot2 are two identical sets of hardware, each with a set of LM read-write interfaces for accessing the line cache memory. Slot3 can access the lookup table memory through the TM read interface.

[0030] like Figure 5As shown, an instruction set classification of the high-performance special-purpose processor is given as an example, including scalar instruction classification and vector instruction classification, majOP instruction type includes scalar addition instruction, subtraction instruction, multiplication instruction, division instruction, shift instruction and logical operation instruction, majOP_IMM instruction type adds immediate function on the basis of majOP instruction type, majLOAD instruction type supports data reading according to byte, halfword and word, majSTORE instruction type supports data writing according to byte, halfword and word, majCOMP instruction type includes vector comparison instruction, vector addition instruction, vector multiplication instruction and vector summation instruction, majBRANCH instruction type includes conditional branch jump instruction, majJAL instruction type and majJALR instruction type include unconditional branch jump instruction, majCUSTOM0 instruction type and majCUSTOM1 instruction type have no actual instruction classification, which is mainly for the expansion of subsequent processor instruction sets.

[0031] Finally, the high-performance dedicated processor for multi-level halftones was verified and performance analyzed. The multi-level halftone algorithm was implemented and run on the processor designed by the present invention and the basic RISC-V integer instruction set processor model respectively. By comparison, it was found that the high-performance dedicated processor for multi-level halftones of the present invention has an average performance improvement of 4 times and an area increase of 34% compared with the RISC-V integer instruction set processor, which significantly improves the execution efficiency of the multi-level halftone algorithm. This verifies that the instruction set extension of the present invention for the multi-level halftone algorithm does accelerate the execution process of the multi-level halftone algorithm, and the new processor model does not significantly improve the resource overhead.

Claims

1. A high-performance dedicated processor for multi-level halftone, adopting SIMD-VLIW architecture, including data memory, code memory, line cache memory, lookup table memory, register file and instruction pipeline; characterized in that: The data memory is used for software stack; the code memory is used for processor instruction fetch operation; the line cache memory is used to store errors; the lookup table memory is used to store the lookup table; the instruction pipeline adopts a three-stage pipeline, namely, an instruction fetch pipeline, a decoding pipeline and an execution pipeline; The SIMD-VLIW architecture includes four instruction slots, namely slot0, slot1, slot2 and slot3. Four instructions are executed in parallel in each cycle. Each instruction slot contains different instruction types and supports SIMD instructions. Slot0 accesses the data memory and code memory through the DM read-write interface and the PM read-write interface respectively. Slot1 and slot2 are used to access the line cache memory through a group of LM read-write interfaces respectively. Slot3 accesses the lookup table memory through the TM read interface.

2. The high-performance dedicated processor for multi-level halftones as claimed in claim 1, characterized in that: The register stack includes 32-bit scalar registers, 32-bit vector registers and a program counter. The 32-bit scalar registers include a constant zero register ZERO, a link register LR and a stack pointer register SP. The 32-bit vector registers are divided into 4 groups, each group including a different number of vector registers.

3. The high performance dedicated processor for multi-level halftone as claimed in claim 2, characterized in that: The 32-bit vector register grouping includes V type, VD type, VQ type and VO type.

4. The high performance dedicated processor for multi-level halftone according to claim 1, characterized in that: The instruction set classification adopted by the processor includes scalar instruction classification and vector instruction classification.

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