A method for transfer and heterogeneous integration of an array of flip-chip GaN HEMT devices and array of devices thereof

Abstract

The present application relates to a kind of flip GaN HEMT device array transfer and heterogeneous integration method and its device array, which is by setting up GaN HEMT device array structure containing heavily doped GaN sacrificial layer and high resistance layer of blocking leakage current path, covering passivation insulating layer on the surface of device to protect device, by opening via hole on passivation insulating layer to expose source drain and gate and then bond it to target substrate by bonding metal, further combined with specific electrochemical etching method, release HEMT array from rigid substrate, realize the lossless peeling of device array, release the stress inside material, effectively solve the problem of buffer layer and substrate leakage, greatly improve the performance of HEMT device, provide new channel for the heterogeneous integration of HEMT device and target substrate, greatly widen the use range of electronic power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of GaN HEMT, and particularly relates to a transfer and heterogeneous integration method of a flip GaN HEMT device array and a device array thereof. BACKGROUND

[0002] In recent years, with the rapid development of semiconductor material preparation technology, semiconductor process manufacturing technology, microelectronic technology and power integration technology, electronic power technology has made great progress in high power, high frequency, miniaturization, intelligence and energy efficiency conversion. Among them, power devices, as the core components of electronic power technology, play a crucial role in realizing power conversion and improving energy conversion efficiency. Among them, three-five nitride, as a representative of the third generation of wide bandgap semiconductor materials, has the advantages of wide bandgap, high temperature resistance and high breakdown field. The AlGaN / AlN / GaN heterojunction has a polarization characteristic, which forms a high electron mobility and high surface density of two-dimensional electron gas (2DEG) on the GaN side, and is widely used in high-performance radio frequency devices and electronic power devices.

[0003] However, in order to reduce the lattice matching and thermal mismatch of the substrate and the epitaxial material, the selection of the epitaxial substrate usually requires that the substrate is similar to the epitaxial material in crystal structure, lattice constant and stable physical and chemical properties. GaN can only be epitaxied to rigid substrates (Si, sapphire), which greatly limits its application field. At the same time, as for the present stage GaN HEMT device stripping technology, it is difficult to obtain large-area, device structure complete components, which cannot be integrated with the present stage integrated circuit technology route. As for the present stage stripping technology, it is still difficult to achieve non-destructive stripping of GaN HEMT array, and there are problems of incomplete stripping and large structure damage. And the existing bonding technology is more arranged in the processing of the film after stripping, which has the problems of large operation difficulty, low yield and many other technical problems that have not been solved. SUMMARY

[0004] In view of the technical problems existing in the prior art, the primary object of the present application is to provide a transfer and hetero-integration method of flip-chip GaN HEMT device array and the device array thereof, which realizes complete and intact peeling and transfer of the device array, effectively solves the problems of substrate and buffer layer leakage and target layer self-heating, and solves the problem of incomplete peeling and large damage to the epitaxial wafer by the current peeling method. In the GaN HEMT device, by setting the sacrifice layer and the high-resistance layer and utilizing the difference in electrical conductivity between the epitaxial layers, a specific electrochemical peeling method is adopted to realize the bonding of the flip-chip GaN HEMT array device and the target substrate, and to realize the intact and efficient peeling of the device and the array transfer of the device. The buffer layer leakage problem in the traditional HEMT device is effectively solved, the self-heating effect of the device is alleviated, a new scheme for integrating the circuit technology with the target substrate (such as a Si substrate) is provided, and the market application of the GaN HEMT device array is greatly widened. Based on the above object, the present application at least provides the following technical solutions.

[0005] In one aspect, the present application provides a transfer and hetero-integration method of flip-chip GaN HEMT device array, comprising the following steps: epitaxially growing an epitaxial stack comprising a heavily doped GaN sacrifice layer, a high-resistance layer, an AlGaN / AlN / GaN target layer and a cap layer on a growth substrate in sequence;

[0006] patterning the cap layer; forming a source electrode and a drain electrode on the target layer; depositing a gate dielectric layer; patterning the gate dielectric layer to form a gate electrode in contact with the cap layer; depositing a passivation insulating layer and patterning the passivation insulating layer to form a window exposing the source electrode, the drain electrode and the gate electrode; depositing a first bonding metal layer in the window; etching the epitaxial stack to the sacrifice layer to form a GaN HEMT device array; depositing a second bonding metal layer on a predetermined region of a target substrate;

[0007] aligning the second bonding metal layer with the first bonding metal layer, and obtaining a hetero-bonding stack after heating and bonding; selecting an electrochemical etching process to etch the sacrifice layer in the bonding stack to release the growth substrate, and realizing the transfer of the flip-chip GaN HEMT array.

[0008] The high-resistance layer is a p-type GaN high-resistance layer with a thickness of 100-200 nm and a doping concentration of 1-2×10 18 cm -3 , and the doping element is Fe or Mg element; the cap layer is a p-type GaN cap layer with a thickness of 100-200 nm and a width of 1-2 μm, and the doping concentration is 3-5×10 19 cm -3 . The thickness of the heavily doped GaN sacrifice layer is selected to be 300-400 nm, and the doping concentration is 1.0-2.0×10 19cm -3 .

[0009] The epitaxial stack further comprises a GaN buffer layer between the growth substrate and the heavily doped GaN sacrificial layer, the thickness of the GaN buffer layer is 1000-15000 nm, the GaN buffer layer comprises a nucleation layer, a lightly doped and an undoped GaN layer, the doping concentration of the lightly doped GaN layer is 3-5*10 18 cm -3 .

[0010] The AlGaN / AlN / GaN target layer comprises an AlGaN barrier layer with a thickness of 20-25 nm, an AlN interlayer with a thickness of 1-2 nm and a GaN buffer layer with a thickness of 600-900 nm, wherein the Al component in the AlGaN barrier layer is 0.3-0.4.

[0011] The area of the window is smaller than the area of the source, drain and gate.

[0012] The first bonding metal layer is selected as a Ti / Au layer, wherein the thickness of the Ti layer is selected as 10 nm and the thickness of the Au layer is selected as 50 nm; the second bonding metal layer is selected as a Ti / Au layer, wherein the thickness of the Ti layer is selected as 10 nm and the thickness of the Au layer is selected as 50 nm. The bonding temperature range is selected as 300-500℃, and the heating time is 2-3 hours.

[0013] The interval between adjacent array unit regions is 10-20 μm.

[0014] The electrochemical etching solution is selected as an oxalic acid solution, the concentration of which is selected as 0.3 Mol / L, the etching voltage is selected as 10-15 V, and the etching time is selected as 2-3 h; preferably, the etching voltage is selected as 10 V and the etching time is selected as 2 h.

[0015] The source and drain electrodes are selected as a Ti / Al / Ni / Au layer, and the gate electrode is selected as a Ni / Au layer.

[0016] The gate dielectric layer is selected as a Si3N4 layer, and a Si3N4 layer with a thickness of 100-200 nm is deposited at 300-400℃ by plasma enhanced chemical vapor deposition (PECVD).

[0017] The passivation insulating layer is preferably SiO2. An atomic layer deposition process is used to deposit a 10-20 nm thick SiO2 layer on the entire epitaxial array surface to protect the device target layer and play a passivation role.

[0018] After the step of forming a GaN HEMT device array, before the step of depositing a second bonding metal layer, the method further comprises selecting an array unit region and etching the edge of the array unit region to the sacrificial layer.

[0019] Another aspect of the present application provides a flip-chip GaN HEMT device array, comprising, a hetero-target substrate, an array unit region on the hetero-target substrate, the array unit region comprising a bonding metal layer region on the hetero-target substrate, a GaN HEMT device array on the bonding metal layer region, the device comprising a drain in contact with the bonding metal layer region, a gate, and a source, a cap layer in contact with the gate, an AlGaN / AlN / GaN target layer in contact with the drain, the cap layer, and the source, and a high-resistance layer on the target layer, wherein the bonding metal layer region comprises a first bonding metal layer region and a second bonding metal layer region in a stacked bonding manner, the first bonding metal layer region in contact with the source, the gate, and the drain, and the second bonding metal layer region in contact with the hetero-target substrate.

[0020] The hetero-target substrate is further provided with a component in interconnection with the GaN HEMT device.

[0021] The present application further provides a flip-chip GaN HEMT device array obtained by the above-mentioned transfer and hetero-integration method.

[0022] Compared with the prior art, the present application has at least the following beneficial effects:

[0023] The GaN HEMT device designed by the present application releases the target layer HEMT array from the rigid substrate by setting a heavily doped GaN sacrificial layer, setting a high-resistance layer on the sacrificial layer as a current blocking layer to block the leakage current path, and utilizing the difference in conductivity between epitaxial layers, combining a specific electrochemical etching method and setting a passivation insulating layer as a protective layer, realizes the lossless peeling of the GaN HEMT array, releases the stress inside the material, effectively solves the problem of leakage of the buffer layer and the substrate, and greatly improves the basic performance of the HEMT device. Further, the present application exposes the source and drain and the gate by opening a through hole on the passivation insulating layer and then bonds them to the target substrate by a bonding metal using a hot-press bonding process, realizes the hetero-bonding of the GaN HEMT array and the target substrate, combines the electrochemical etching method, realizes the transfer of the GaN HEMT array, provides a new channel for the hetero-integration of HEMT, greatly relieves the self-heating effect of the device, and greatly widens the use range of electronic power devices. The method of the present application is simple, low in cost, and strong in repeatability, and has a wide application prospect in the development and hetero-integration of semiconductor flexible optoelectronic devices. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is an embodiment of the present application GaN HEMT device epitaxial structure schematic diagram.

[0025] Figure 2Schematic diagram of flip-chip GaN HEMT device array for an embodiment of the present application.

[0026] Figure 3 Schematic diagram of GaN HEMT array device for an embodiment of the present application.

[0027] Figure 4 Schematic diagram of heterojunction bonding of GaN HEMT array device for an embodiment of the present application.

[0028] Figure 5 Schematic diagram of electrochemical exfoliation for an embodiment of the present application.

[0029] Figure 6 Schematic diagram of integration of flip-chip GaN HEMT array device for an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application. In the following embodiments, the experimental methods are conventional methods unless otherwise specified, and the reagents and materials are commercially available unless otherwise specified.

[0031] Spatial relative terms such as "under", "below", "lower", "on", "above", "upper" and the like, are used herein for ease of description to explain the positioning of one element relative to a second element. Except for different orientations than those shown in the figures, these terms are intended to encompass different orientations of the device.

[0032] In addition, terms such as "first", "second" and the like are used to describe various elements, layers, regions, sections and the like, and are not intended to be limiting. "Have", "contain", "include", "comprise" and the like are open terms, indicating the presence of the stated elements or features, but not excluding additional elements or features. Unless the context clearly dictates otherwise.

[0033] The purpose of the present application is to provide a flip-chip GaN HEMT device preparation and its array transfer and heterojunction integration method, to realize overall exfoliation, effectively solve the problems of substrate and buffer layer leakage, target layer self-heating effect, and solve the problem of incomplete exfoliation and large damage to epitaxial wafer.

[0034] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0035] Figure 1 is a schematic diagram of an epitaxial structure of a GaN HEMT device provided by an embodiment of the present application. As shown in the diagram, the device includes an epitaxial substrate and an epitaxial stack stacked on the epitaxial substrate. The epitaxial stack includes, from bottom to top, a first GaN buffer layer, a heavily doped GaN sacrificial layer, a high resistance layer, a second GaN buffer layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer. A source electrode and a drain electrode are disposed on the AlGaN barrier layer and located on both sides of the GaN cap layer. A gate dielectric layer is filled between the source electrode and the drain electrode and the GaN cap layer. A gate electrode is disposed on the GaN cap layer. A passivation insulating layer covers the surface of the device. The second GaN buffer layer, the AlN insertion layer, and the AlGaN barrier layer form an AlGaN / AlN / GaN target layer of the device.

[0036] Figure 2 is a schematic diagram of an inverted GaN HEMT device array provided by an embodiment of the present application. As shown in the diagram, the device array includes a hetero-target substrate, which can be a Si substrate for example. A bonding metal layer is disposed on the hetero-target substrate. A GaN HEMT device is disposed on the bonding metal layer. The GaN HEMT device includes an AlGaN / AlN / GaN target layer, a p-type GaN cap layer disposed on the target layer, a source electrode and a drain electrode disposed on both sides of the cap layer, a gate dielectric layer filled between the source electrode, the drain electrode, and the cap layer, and a gate electrode disposed on the cap layer. A passivation insulating layer covers the surface of the device. A via is formed in the passivation insulating layer to expose the source electrode, the drain electrode, and the gate electrode. The area of the via is smaller than the area of the source electrode, the drain electrode, and the gate electrode.

[0037] The bonding metal layer includes a first bonding metal layer and a second bonding metal layer bonded together. The first bonding metal layer is disposed on the surface of the source electrode, the drain electrode, and the gate electrode in the via. The second bonding metal layer is disposed on the surface of the hetero-target substrate.

[0038] In an embodiment, in order to improve the quality of the epitaxial layer, a sapphire substrate is selected as the epitaxial substrate. The first GaN buffer layer has a thickness of 1000-1500 nm and includes a nucleation layer, a lightly doped GaN layer, and an undoped GaN layer. The doping concentration of the lightly doped GaN layer is preferably 5×10 18 cm -3 The heavily doped GaN sacrificial layer has a thickness of 300 nm and a doping concentration of 2.0×10 19 cm -3 The high resistance layer is preferably a p-type GaN high resistance layer. The high resistance layer has a thickness of 100 nm and a doping concentration of 1×10 18 cm -3 The doping element is Fe.

[0039] The second GaN buffer layer, the AlN interlayer and the AlGaN barrier layer form an AlGaN / AlN / GaN target layer. The thickness of the second GaN buffer layer is selected to be 900 nm, the thickness of the AlN interlayer is selected to be 1.25 nm, and the thickness of the AlGaN barrier layer is selected to be 20 nm, wherein the Al component is selected to be 0.3. A p-type GaN cap layer is located on the AlGaN barrier layer, the thickness of the p-type GaN cap layer is selected to be 100 nm, and the doping concentration is selected to be 3×1019cm-3. 19 cm -3 The p-type GaN cap layer is patterned by using an inductively coupled plasma (ICP) etching method, and the width of the p-type GaN cap layer in this embodiment is about 1 μm.

[0040] A source-drain electrode layer is formed on the surface of the AlGaN / AlN / GaN target layer. The electrode layer includes a source electrode, a drain electrode and a gate electrode. First, a source metal layer and a drain metal layer are deposited by using an electron beam evaporation (EBL) process, and then annealing treatment is performed at 850°C for 30 s. The source metal layer and the drain metal layer are selected to be a Ti / Al / Ni / Au layer stacked from bottom to top, wherein the thickness of the Ti layer is selected to be 20 nm, the thickness of the Al layer is selected to be 130 nm, the thickness of the Ni layer is selected to be 50 nm, and the thickness of the Au layer is selected to be 100 nm.

[0041] A gate dielectric layer is deposited by using a plasma enhanced chemical vapor deposition (PECVD) process, and the gate dielectric layer is selected to be a Si3N4 gate dielectric layer, the deposition temperature is 350°C, and the deposition thickness is selected to be 150 nm. Next, a gate electrode pattern region is formed on the p-type GaN cap layer region by using a photolithography process, and a gate electrode is formed by evaporating an Au layer and a Ni layer from bottom to top by using an electron beam evaporation process, the thickness of the Au layer is selected to be 100 nm, and the thickness of the Ni layer is selected to be 30 nm.

[0042] A passivation insulating layer is deposited on the entire device surface by using an atomic layer deposition (ALD) process, and the passivation insulating layer is selected to be a SiO2 layer, and the thickness of the passivation insulating layer is selected to be 10 nm. The passivation insulating layer can also be used as a protective layer for subsequent electrochemical etching. Next, a through hole is formed on the passivation insulating layer. As a specific embodiment, a photoresist is used for patterning, and then a plasma etching process is used to etch a square through hole, and the area of the through hole is smaller than the area of the electrode, and the purpose is to expose the electrode layer, so as to facilitate the thermal pressure bonding of the device and the metal on the target substrate.

[0043] Next, a bonding metal layer is deposited in the through hole exposing the electrode layer, and the bonding metal layer is selected to be a Ti / Au layer. The purpose is to increase the electrical contact between the device electrode and the subsequently bonded substrate, and to facilitate the subsequent bonding process of the device.

[0044] Then, the array structure is designed, and the GaN HEMT array device is etched. Specifically, a mask layer is deposited, and ultraviolet exposure is performed by using the designed mask plate and ultraviolet lithography technology, and the dose of the ultraviolet exposure is selected as 15 mJ / s, and the exposure time is selected as 1.8 s. Then, the array device mask pattern is obtained after the sample is soaked in AZ400K developing solution for 60 s and dried. The epitaxial layer is etched to the heavily doped GaN sacrificial layer by using the pattern as a mask, and the purpose is to form a GaN HEMT array device, which is an intermediate product of the obtained flip-chip GaN HEMT array device. In the plasma etching process, the gas used is a mixed gas of SF6 and CHF3, the flow rate of SF6 is 25 sccm, the flow rate of CHF3 is 60 sccm, the power is 900 W, the pressure is 5 mTorr, the time is 3 min, and the temperature is 120°C.

[0045] Optionally, according to the design needs, the array unit region is selected, and preferably, 5-6 HEMT devices are contained in one array unit. The edge of the array unit region is etched by using inductive coupled plasma, and the depth reaches the surface of the sacrificial layer. As shown in the figure. Figure 3 In particular, each region is spaced apart by 10-20 μm. The purpose is to improve the efficiency of array peeling and transfer in the subsequent transfer process.

[0046] The silver paste is spin-coated on the edge of the epitaxial wafer as a contact electrode of the epitaxial wafer, and the silver paste is located on the surface of the sacrificial layer and the growth substrate and does not contact the GaN HEMT array device formed by etching. Preferably, the spin-coating region accounts for 1 / 3 of the region spacing.

[0047] A target substrate with the same size as the epitaxial wafer is selected, and the electrode region is patterned on the substrate by using a photolithography method. The patterned electrode region is the same as the electrode position of the epitaxial wafer, and the area is larger than the device electrode. Then, the bonding metal Ti / Au layer is evaporated on the patterned electrode region by using an electron beam evaporation process, the thickness of the Ti layer is selected as 10 nm, and the thickness of the Au layer is selected as 50 nm. The bonding metal of the epitaxial array is aligned and fixed with the target substrate by using a stainless steel clamp, and is placed in a constant temperature device, the temperature is set as 500°C, and heating is performed for 3 hours to realize the heterojunction bonding of the flip-chip GaN HEMT array device array and the target substrate, as shown in the figure. Figure 4

[0048] The bonded sample is peeled and transferred by using an electrochemical corrosion method. The electrolyte is selected as 0.3 mol / L oxalic acid, the voltage is preferably 10 V, and the corrosion time is 2 h. During the corrosion process, the epitaxial wafer is immersed in the oxalic acid solution, and preferably, 1 / 3 of the epitaxial wafer is immersed in the electrolyte, and the bonded stack is used as an anode, and a platinum plate is used as a cathode. The reaction schematic diagram is as shown in the figure. Figure 5 ​As shown. After electrochemical corrosion, the epitaxial substrate is separated from the target layer, and then the separated epitaxial substrate is cleaned with deionized water to remove the residual oxalic acid solution on the surface, thereby realizing the preparation and transfer of the flip-chip GaN HEMT array device, as shown. Figure 2 The present application releases the HEMT array from the rigid substrate, realizes the lossless peeling of the GaN HEMT array, releases the stress inside the material, effectively solves the problem of buffer layer and substrate leakage, and greatly improves the basic performance of the HEMT device.

[0049] The target substrate bonded by the flip-chip GaN HEMT structure can be selected from substrates such as SiC and Si having better thermal conductivity. Other components such as LEDs, transistors, etc. are also arranged on the target substrate. After hetero-bonding with the GaN HEMT device and array transfer, gold wire ball bonding is used to lead out from the PAD, interconnect with the original components on the target substrate, and realize the heterogeneous integration application of the flip-chip GaN HEMT array device, as shown. Figure 6 The present application further realizes the hetero-bonding of GaN HEMT and Si substrate by means of thermal compression bonding, and realizes the array transfer of GaN HEMT by combining electrochemical corrosion, which provides a new channel for the heterogeneous integration of HEMT with Si substrate, and greatly relieves the self-heating effect of the device, greatly widening the use range of electronic power devices.

[0050] The above embodiments are the preferred embodiments of the present application, but the embodiments of the present application are not limited by the above embodiments, and any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present application should be equivalent replacement methods, which are all included in the protection scope of the present application.

Claims

1. A method for transferring and heterogeneously integrating flip-chip GaN HEMT device arrays, characterized in that, Includes the following steps: An epitaxial stack comprising a heavily doped GaN sacrificial layer, a p-type GaN high-resistivity layer, an AlGaN / AlN / GaN target layer, and a cap layer is sequentially epitaxially grown on a growth substrate. The thickness of the heavily doped GaN sacrificial layer is 300–400 nm, and its doping concentration is 1.0–2.0 × 10⁻⁶ nm. 19 cm -3 The thickness of the p-type GaN high-resistivity layer is 100~200 nm, and the doping concentration is 1~2×10⁻⁶. 18 cm -3 The doping element is Fe or Mg. Pattern the cap layer; Source and drain electrodes are formed on the target layer; A gate dielectric layer is deposited, which fills the space between the source, drain, and cap layer. The gate dielectric layer is patterned to form a gate that contacts the cap layer; A passivation insulating layer is deposited and patterned to form windows exposing the source, drain, and gate. A first Ti / Au bonded metal layer is deposited in the window; The epitaxial stack is etched down to the sacrificial layer to form a GaN HEMT device array; Select an array cell region and etch the edge of the array cell region down to the sacrificial layer; A Ti / Au second bonded metal layer is deposited in a predetermined region on the target substrate; Align the second bonding metal layer with the first bonding metal layer, heat at 300~500℃ for 2~3 hours, and obtain a heterogeneous bonding stack after heat bonding; An electrochemical etching process is used to etch the sacrificial layer in the bonded stack, releasing the growth substrate and realizing the transfer of the flip-chip GaN HEMT array. The etching solution in the electrochemical etching process is an oxalic acid solution with a concentration of 0.3 Mol / L, an etching voltage of 10~15V, and an etching time of 2~3h.

2. The transfer and heterogeneous integration method according to claim 1, characterized in that, The cap layer is a p-type GaN cap layer with a thickness of 100~200 nm and a doping concentration of 3~5×10⁻⁶. 19 cm -3 ; A buffer layer is also provided between the growth substrate and the heavily doped GaN sacrificial layer.

3. The transfer and heterogeneous integration method according to claim 1 or 2, characterized in that, The area of ​​the window is smaller than the area of ​​the source, drain, and gate.

4. The transfer and heterogeneous integration method according to claim 1 or 2, characterized in that, The adjacent array cell regions are spaced 10~20μm apart.

5. The transfer and heterogeneous integration method according to claim 1 or 2, characterized in that, The first bonding metal layer has a Ti layer thickness of 10 nm and an Au layer thickness of 50 nm; the second bonding metal layer has a Ti layer thickness of 10 nm and an Au layer thickness of 50 nm.

6. The transfer and heterogeneous integration method according to claim 1 or 2, characterized in that, The corrosion voltage was 10V and the corrosion time was 2 hours.

7. A flip-chip GaN HEMT device array obtained by the transfer and heterogeneous integration method according to any one of claims 1 to 6, characterized in that, It includes a heterogeneous target substrate, an array cell region located on the heterogeneous target substrate, the array cell region including a bonding metal layer region located on the heterogeneous target substrate, a GaN HEMT device array located on the bonding metal layer region, the device including a drain, a gate, and a source in contact with the bonding metal layer region, a cap layer in contact with the gate, a gate dielectric layer located between the drain, cap layer, and source, an AlGaN / AlN / GaN target layer in contact with the drain, cap layer, gate dielectric layer, and source, and a p-type GaN high-resistivity layer located on the target layer, wherein the bonding metal layer region includes a first bonding metal layer region and a second bonding metal layer region stacked and bonded, the first bonding metal layer region in contact with the source, gate, and drain, and the second bonding metal layer region in contact with the heterogeneous target substrate.

8. The device array according to claim 7, characterized in that, The heterogeneous target substrate is also provided with components that are interconnected with the GaN HEMT device.

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