A semiconductor device and a manufacturing method thereof

Abstract

This invention provides a semiconductor device and its manufacturing method. The semiconductor device includes a substrate, a first insulating stack stacked on the substrate, and a second insulating stack stacked on the first insulating stack. A first contact hole is formed in the first insulating stack, and a stacked contact plug is filled from bottom to top within the first contact hole, but the stacked contact plug does not completely fill the first contact hole. A second contact hole communicating with the first contact hole is formed in the second insulating stack. The device also includes a lower electrode formed above the second insulating stack, which extends downwards sequentially into the second and first contact holes to contact the stacked contact plug. Extending the lower electrode formed above the two insulating stacks further downwards into the first and second contact holes to contact the remaining stacked contact plug creates an anchor-like structure on the portion of the lower electrode in contact with the stacked contact plug, supporting the entire lower electrode and preventing it from tilting. This increases the surface area of ​​the lower electrode, thereby improving the capacitance of the capacitor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] A capacitor is a component that can store electrical charge and energy. Different voltages can be applied to the two electrodes of a capacitor, causing it to store different amounts of charge. Based on this, capacitors can be used to store different types of data. Therefore, the quality of a capacitor directly affects the data storage performance of semiconductor devices.

[0003] To improve memory drive performance, the capacitance of capacitors needs to be increased. A common way to increase capacitor capacitance is to increase the capacitor's height. However, increasing the capacitor's height leads to an increase in its aspect ratio. An increased aspect ratio can cause problems such as capacitor tilting, bending, or even collapse during the wet cleaning process. Summary of the Invention

[0004] This invention provides a semiconductor device and its manufacturing method, which can effectively increase the charge storage capacity of a capacitor and effectively prevent the capacitor from tilting, bending or collapsing.

[0005] In a first aspect, the present invention provides a semiconductor device comprising a substrate, a first insulating stack stacked on the substrate, and a second insulating stack stacked on the first insulating stack. A first contact hole is formed in the first insulating stack, and a stacked contact plug is filled from bottom to top within the first contact hole, but the stacked contact plug does not completely fill the first contact hole. A second contact hole communicating with the first contact hole is formed in the second insulating stack. The semiconductor device further includes a lower electrode formed above the second insulating stack, and the lower electrode extends downwards sequentially into the second contact hole and the first contact hole to contact the stacked contact plug.

[0006] In the above scheme, by removing the conductor film and the landing pad (LP) in contact with the conductor film in the second contact hole, and also removing part of the buried contact (BC) in the first contact hole, the lower electrode formed above the two insulating layers extends downward into the first and second contact holes to contact the remaining buried contact. This creates an anchor-like structure on the lower electrode in contact with the buried contact, supporting the entire lower electrode and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode, the anchor-like structure in the lower electrode prevents bending deformation, thus preventing capacitor collapse. Furthermore, the portion of the lower electrode extending into the first and second contact holes increases the surface area of ​​the lower electrode, thereby increasing the capacitor's charge storage capacity, capacitance, and storage performance. Furthermore, the lower electrode extends downwards to directly contact the retained stacked contact plugs through the first and second contact holes, replacing the previous method where the lower electrode contacted the stacked contact plugs via landing pads and conductive films. This reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode supports the entire lower electrode, the capacitor structure is more robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase capacitance and further improve storage performance.

[0007] In one specific embodiment, the lower electrode extending to the hole walls of the second contact hole and the first contact hole is deposited on the hole walls of the first contact hole and the second contact hole, and the lower electrode extending to the upper end face of the stacked contact plug is deposited on the upper end face of the stacked contact plug, so as to improve the contact strength between the lower electrode and the hole walls of the contact hole and the stacked contact plug, and improve the support effect on the entire lower electrode.

[0008] In one specific embodiment, the lower electrode is formed in a cylindrical shape; wherein the bottom wall of the lower electrode is deposited on the upper end surface of the stacked contact plug; the sidewalls of the lower electrode are partially deposited on the walls of the first and second contact holes, and partially exposed outside the first and second contact holes. By using a cylindrical lower electrode, the surface area of ​​the lower electrode is increased, the charge storage capacity of the capacitor is increased, and the capacitance of the capacitor is increased.

[0009] In one specific embodiment, an upper electrode and a dielectric layer insulating the lower electrode from the upper electrode are formed on the bottom wall, inner side wall, and outer side wall of the lower electrode, which are exposed outside the first and second contact holes. By providing capacitor structures on both the inner and outer sides of the lower electrode, the charge storage capacity of the capacitor is increased, the capacitance of the capacitor is increased, and the storage effect is improved.

[0010] In one specific embodiment, the height of the stacked contact plug is h1, and the height of the first contact hole is h2, wherein 20% × h2 ≤ h1 ≤ 80% × h2. This ensures that the portion of the lower electrode extending into the first contact hole has a large contact surface with the sidewall of the first contact hole, guaranteeing the anchor-like structure's support effect on the entire lower electrode. Simultaneously, the height of the stacked contact plug is maintained to ensure a relatively stable adhesion between the stacked contact plug and the lower electrode.

[0011] In one specific embodiment, an etch barrier layer is further deposited on the second insulating stack, and the second contact via extends through the etch barrier layer. By depositing an etch barrier layer on the second insulating stack, subsequent etching or cleaning operations can be prevented from affecting the substrate, ensuring the quality of the substrate and the insulating stack.

[0012] In one specific implementation, the semiconductor device is a dynamic random access memory (DRAM) to prevent the capacitor in the DRAM from collapsing due to tilting, bending, or other reasons related to the lower electrode.

[0013] Secondly, the present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0014] Provide a base;

[0015] An insulating layer is stacked on the substrate;

[0016] Contact holes are provided in the insulating layer;

[0017] The contact hole is filled with a stacked contact plug and a landing pad electrically connected to the stacked contact plug;

[0018] Remove the landing pads;

[0019] Remove part of the stacked contact plug from top to bottom;

[0020] A lower electrode is formed above the insulating layer, and the lower electrode extends downward into the contact hole to contact the retained stacked contact plug.

[0021] In the above solution, by removing the landing pads and part of the stacked contact plugs within the contact hole, the lower electrode formed above the insulating layer extends downwards into the contact hole to contact the remaining stacked contact plugs. This creates an anchor-like structure on the lower electrode, supporting it and preventing tilting. In subsequent processes, when depositing the dielectric layer and upper electrode on the lower electrode, the anchor-like structure prevents bending and deformation, thus preventing capacitor collapse. Furthermore, extending the lower electrode into the contact hole increases its surface area, thereby increasing the capacitor's charge storage capacity, capacitance, and storage performance. Extending the lower electrode downwards to directly contact the remaining stacked contact plugs, instead of the previous method of contacting the lower electrode through landing pads, conductive films, and stacked contact plugs, reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode supports the entire lower electrode, the capacitor structure is relatively robust. The aspect ratio of the stacked capacitors can be appropriately increased to increase the capacitance and further improve storage performance.

[0022] In one specific embodiment, the landing pad, which is electrically connected to the stacked contact plug and fills the contact hole, specifically comprises: filling the contact hole with the stacked contact plug; filling the contact hole with a conductive film in contact with the stacked contact plug; and filling the contact hole with a landing pad in contact with the conductive film. After removing the landing pad and before removing a portion of the stacked contact plug from top to bottom, the manufacturing method further comprises: removing the conductive film.

[0023] In one specific implementation, removing the landing pads, conductive film, and part of the stacked contact plugs involves using a wet etching process or a remote plasma dry cleaning process to remove the landing pads, conductive film, and part of the stacked contact plugs from the contact holes from top to bottom. This process removes them without affecting other film materials.

[0024] In one specific embodiment, after filling the contact hole with a stacked contact plug and a landing pad electrically connected to the stacked contact plug, and before removing the landing pad, the manufacturing method further includes: stacking a sacrificial film layer on an insulating layer; and forming a capacitor hole in the sacrificial film layer that communicates with the landing pad. Forming a lower electrode above the insulating layer, and extending downwards into the contact hole to contact the retained portion of the stacked contact plug, specifically involves forming a lower electrode that contacts the retained stacked contact plug on the walls of the capacitor hole and the contact hole, and on the upper surface of the retained portion of the stacked contact plug.

[0025] In one specific embodiment, forming a lower electrode that contacts the retained stacked contact plug on the walls of the capacitor hole and contact hole, and on the upper surface of the retained portion of the stacked contact plug, specifically involves: depositing a lower electrode material layer on the surface of the sacrificial film layer, the walls of the capacitor hole and contact hole, and the upper surface of the retained portion of the stacked contact plug; removing the lower electrode material layer from the surface of the sacrificial film layer to form the lower electrode that contacts the retained stacked contact plug. This facilitates the formation of the lower electrode and improves the contact strength between the lower electrode and the walls of the contact hole and the upper surface of the retained stacked contact plug, thereby enhancing the support effect on the entire lower electrode.

[0026] In one specific embodiment, after forming the lower electrode above the insulating layer, the manufacturing method further includes removing the sacrificial film layer to facilitate the subsequent formation of capacitor structures on both the inner and outer sides of the lower electrode, thereby increasing the capacitance of the capacitor and improving its storage performance. Attached Figure Description

[0027] Figure 1a This is a schematic diagram of one step in the manufacturing process of a capacitor in the prior art;

[0028] Figure 1b This is a schematic diagram of another step in the manufacturing process of capacitors in the prior art;

[0029] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0034] Figures 1a-1b Figure labels in the diagram:

[0035] 1-Substrate 2-Sacrificial film 3-Capacitor via 4-Landing pad 5-Lower electrode

[0036] Figures 2-6 Figure labels in the diagram:

[0037] 10-Substrate 21-First insulating layer 211-Stacked contact plug 212-Insulating part

[0038] 22-Second insulating layer; 221-Conductor film; 222-Landing pad; 223-Isolation section

[0039] 31-First contact hole; 32-Second contact hole; 40-Lower electrode; 50-Sacrificial film layer

[0040] 60 - Capacitor via; 70 - Etching barrier layer; 80 - Support layer; 81 - Support structure Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] To facilitate understanding of the semiconductor device provided in the embodiments of the present invention, the application scenario of the semiconductor device provided in the embodiments of the present invention will be described first. This semiconductor device is applied in a memory with capacitors. The semiconductor device will then be described in detail with reference to the accompanying drawings.

[0043] refer to Figure 2 The semiconductor device provided in this embodiment of the invention includes a substrate 10, a first insulating stack 21 stacked on the substrate 10, and a second insulating stack 22 stacked on the first insulating stack 21. The first insulating stack 21 has a first contact hole 31, which is filled from bottom to top with a stacked contact plug 211, but the stacked contact plug 211 does not completely fill the first contact hole 31. The second insulating stack 22 has a second contact hole 32 communicating with the first contact hole 31. The semiconductor device also includes a lower electrode 40 formed above the second insulating stack 22, and the lower electrode 40 extends downwards sequentially into the second contact hole 32 and the first contact hole 31 to contact the stacked contact plug 211.

[0044] In the above-described scheme, by removing the conductor film 221 and the landing pad 222 in contact with the conductor film 221 within the second contact hole 32, and also removing a portion of the stacked contact plug 211 within the first contact hole 31, the lower electrode 40 formed above the two insulating layers extends downwards into the first and second contact holes 31 and 32 to contact the remaining stacked contact plug 211. This creates an anchor-like structure in contact with the stacked contact plug 211, supporting the entire lower electrode 40 and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the anchor-like structure in the lower electrode 40 further prevents bending and deformation, thus preventing capacitor collapse. Furthermore, the portion of the lower electrode 40 extending into the first and second contact holes 31 and 32 increases the surface area of ​​the lower electrode 40, thereby increasing the capacitor's charge storage capacity, capacitance, and storage performance. Furthermore, the lower electrode 40 extends downwards to directly contact the retained stacked contact plug 211 through the first contact hole 31 and the second contact hole 32, replacing the previous method where the lower electrode 40 contacts the stacked contact plug 211 through the landing pad 222 and the conductor film 221. This reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively robust, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance and further improve storage performance. The following is a detailed description of the above-mentioned structural configurations in conjunction with the accompanying drawings.

[0045] When setting the substrate 10, the substrate 10 can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, etc. The substrate 10 can also be a stacked structure with partially formed semiconductor structures. For example, the substrate 10 can at least include a semiconductor substrate, a transistor, a bit line structure, etc. The transistor can be formed on the semiconductor substrate of the semiconductor device. The bit line structure can be formed above the transistor.

[0046] refer to Figure 2 A first insulating layer 21 is stacked above the substrate 10. A first contact hole 31 is formed in the first insulating layer 21, connecting its upper and lower surfaces. A stacked contact plug 211 fills the first contact hole 31 from bottom to top, but does not completely fill it. Specifically, the stacked contact plug 211 is located at the lower end of the first contact hole 31 and does not completely fill it. In application, the stacked contact plug 211 contacts the source or drain region of the transistor. (Reference) Figure 2An insulating portion 212 is also formed in the first insulating layer 21 to isolate two adjacent stacked contact plugs 211, and the stacked contact plugs 211 and the insulating portion 212 are formed between adjacent bit line structures.

[0047] Continue to refer to Figure 2 A second insulating layer 22 is stacked above the first insulating layer 21. A second contact hole 32 communicating with the first contact hole 31 is formed in the second insulating layer 22. That is, the second contact hole 32 penetrates both the upper and lower surfaces of the second insulating layer 22, and its lower end communicates with the first contact hole 31. The edges of the first contact hole 31 and the second contact hole 32 can overlap, making the opening sizes at the connection point equal and their edges overlapping. The edges of the first contact hole 31 and the second contact hole 32 can also at least partially intersect, allowing at least partial communication between them. Alternatively, at the connection point, one contact hole can have a larger opening and the other a smaller opening, with the smaller opening fitting inside the larger opening.

[0048] like Figure 2 As shown, when the lower electrode 40 is set, the lower electrode 40 mainly includes two parts. One part is formed above the second insulating stack, which is exposed outside the first contact hole 31 and the second contact hole 32. The other part is a part that extends downwards into the second contact hole 32 and the first contact hole 31 and contacts the stacked contact plug 211. This part is located inside the first contact hole 31 and the second contact hole 32.

[0049] Existing methods for manufacturing capacitors include: Figures 1a-1b As shown, for reference Figure 1a First, a sacrificial film layer 2 is deposited on substrate 1; then, the sacrificial film layer 2 is etched to form capacitor holes 3, which are connected to landing pads 4 in substrate 1; then, a lower electrode material layer is deposited on the sacrificial film layer 2, the inner wall of the capacitor holes 3, and the upper surface of the landing pads 4; then, a reference electrode material layer is deposited. Figure 1b Remove the lower electrode material layer outside capacitor hole 3 to form lower electrode 5; then, refer to Figure 1b The sacrificial film layer 2 is removed; subsequently, a dielectric layer and an upper electrode are deposited on the lower electrode 5 to form a capacitor. For example... Figure 1b In the semiconductor device shown, the lower electrode 5 only contacts the landing pad 4 at its lower end, resulting in a relatively small contact area. This makes the lower electrode 5 have a poor foundation and prone to tilting, falling over, or even bending. After removing the sacrificial film layer 2, the lower electrode 5 is prone to tilting or even falling over. When depositing the dielectric layer and the upper electrode on the lower electrode 5, the lower electrode 4 is prone to bending due to the weight of the dielectric layer and the upper electrode, causing the entire capacitor to collapse.

[0050] Compared to existing technologies Figure 1b The solution in this application removes the conductor film 221 and the landing pad 222 in contact with the conductor film 221 within the second contact hole 32, and also removes a portion of the stacked contact plug 211 within the first contact hole 31. The lower electrode 40, formed above the two insulating layers, extends downward into the first contact hole 31 and the second contact hole 32 to contact the remaining stacked contact plug 211. This creates an anchor-like structure in contact with the stacked contact plug 211, supporting the entire lower electrode 40 and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the anchor-like structure in the lower electrode 40 further prevents bending and deformation, thus preventing capacitor collapse. Furthermore, the portion of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 increases the surface area of ​​the lower electrode 40, thereby increasing the charge storage capacity, capacitance, and storage performance of the capacitor. Furthermore, the lower electrode 40 extends downwards to directly contact the retained stacked contact plug 211 through the first contact hole 31 and the second contact hole 32, replacing the previous method where the lower electrode 40 contacts the stacked contact plug 211 through the landing pad 222 and the conductor film 221. This reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively robust, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance and further improve storage performance.

[0051] More specifically, when the portion of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 contacts the stacked contact plug 211, the portion of the lower electrode 40 extending into the upper surface of the stacked contact plug 211 can be deposited on the upper surface of the stacked contact plug 211, thereby increasing the contact strength between the lower electrode 40 and the stacked contact plug 211 and improving the support effect for the entire lower electrode 40. Simultaneously, the portion of the lower electrode 40 extending into the walls of the first contact hole 31 and the second contact hole 32 can also be deposited on the walls of the first contact hole 31 and the second contact hole 32. That is, the portion of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 not only contacts the stacked contact plug 211 but also contacts the walls of the first contact hole 31 and the second contact hole 32, with the contact method being deposition. This increases the contact area and contact strength between the lower electrode 40 and the two contact holes and the stacked contact plug 211, thereby improving the support effect for the entire lower electrode 40.

[0052] When setting the lower electrode 40, the shape of the lower electrode 40 can be a hollow cylindrical structure, which includes a thin-walled bottom and a sidewall communicating with the bottom. The bottom wall of the lower electrode 40 can be deposited on the upper end surface of the stacked contact plug 211, that is, the bottom of the lower electrode 40 is deposited on the upper end surface of the stacked contact plug 211. A portion of the sidewall of the lower electrode 40 is deposited on the walls of the first contact hole 31 and the second contact hole 32, and a portion is exposed outside the first contact hole 31 and the second contact hole 32. That is, the portion of the sidewall of the lower electrode 40 located inside the first contact hole 31 and the second contact hole 32 is deposited on the walls of the first contact hole 31 and the second contact hole 32, and the portion exposed outside the first contact hole 31 and the second contact hole 32 stands vertically above the second insulating stack 22. By using a cylindrical lower electrode 40, the surface area of ​​the lower electrode 40 is increased, the charge storage capacity of the capacitor is increased, and the capacitance of the capacitor is increased.

[0053] When forming the dielectric layer and the upper electrode on the lower electrode 40, the upper electrode and the dielectric layer insulating and isolating the lower electrode 40 from the upper electrode can be formed on the bottom wall, the inner side wall, and the outer side wall of the portion exposed outside the first contact hole 31 and the second contact hole 32 of the lower electrode 40, thereby completing the manufacture of the capacitor. That is, on the portion of the lower electrode 40 located at the first contact hole 31 and the second contact hole 32, the dielectric layer and the upper electrode are formed only on the inner side wall and the bottom wall; on the portion of the lower electrode 40 exposed outside the first contact hole 31 and the second contact hole 32, the dielectric layer and the upper electrode are formed not only on the inner side wall but also on the outer side wall. By providing a capacitor structure on both the inner and outer sides of the lower electrode 40, the charge storage capacity of the capacitor is increased, the capacitance of the capacitor is increased, and the storage effect is improved. It should be understood that the method of setting the dielectric layer and the upper electrode is not limited to the above method; other methods can also be used. For example, a dielectric layer and an upper electrode may be formed only on the inner sidewall and bottom wall of the lower electrode 40, and no dielectric layer and upper electrode may be formed on the outer sidewall of the lower electrode 40.

[0054] When determining the height of the stacked contact plug 211 relative to the entire first contact hole 31, it can be assumed that the height of the stacked contact plug 211 is h1, that is, the vertical distance between the lower surface and the upper surface of the stacked contact plug 211 is h1; and the height of the first contact hole 31 is h2, that is, the vertical distance between the upper edge and the lower edge of the first contact hole 31 is h2. It can be set that: 20% × h2 ≤ h1 ≤ 80% × h2. Specifically, the height h1 of the stacked contact plug 211 can be set to any value between 20% and 80% of the height h2 of the first contact hole 31, such as h1 = 20% × h2, h1 = 25% × h2, h1 = 30% × h2, h1 = 35% × h2, h1 = 40% × h2, h1 = 45% × h2, h1 = 50% × h2, h1 = 55% × h2, h1 = 60% × h2, h1 = 65% × h2, h1 = 70% × h2, h1 = 75% × h2, h1 = 80% × h2. This ensures that the portion of the lower electrode 40 extending into the first contact hole 31 has a large contact surface with the sidewall of the first contact hole 31, ensuring the anchor-like structure provides support for the entire lower electrode 40. Simultaneously, the height of the stacked contact plug 211 is maintained to ensure a relatively stable adhesion between the stacked contact plug 211 and the lower electrode 40.

[0055] In addition, such as Figure 2 As shown, the second contact hole 32 can be shaped to be larger at the top, smaller in the middle, and larger at the bottom. The first contact hole 31 can be shaped to have the same size opening at the bottom of the second contact hole 32. The openings at the top and bottom of the first contact hole 31 can be of equal size, and the outer edge of the first contact hole 31 coincides with the outer edge of the second contact hole 32. By adopting the above arrangement, the surface area of ​​the lower electrode 40 in contact with the sidewall of the second contact hole 32 is increased, thereby improving the support effect of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32 on the entire lower electrode 40. Furthermore, the larger bottom of the first contact hole 31 can increase the contact area between the lower electrode 40 and the stacked contact plug 211, reducing the resistance of interlayer current transmission. The larger top of the second contact hole 32 allows the lower electrode 40 exposed outside the first contact hole 31 and the second contact hole 32 to have a larger surface area, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. Of course, both the first contact hole 31 and the second contact hole 32 can be configured as hollow cylindrical through holes.

[0056] refer to Figure 2An etch barrier layer 70 may be deposited on the second insulating stack 22, with the second contact hole 32 penetrating through the etch barrier layer 70. By depositing the etch barrier layer 70 on the second insulating stack 22, subsequent etching or cleaning operations can be prevented from affecting the substrate 10 and the two insulating stacks, ensuring the quality of the substrate 10 and the insulating stacks. When determining the material of the etch barrier layer 70, SiN, SiBN, or SiCN can be selected to improve the barrier effect during etching.

[0057] The first insulating layer 21 and the second insulating layer 22 can be in direct contact. Alternatively, an etch stop layer can be deposited between the first insulating layer 21 and the second insulating layer 22, meaning that the first insulating layer 21 and the second insulating layer 22 are not directly stacked together, but an etch stop layer is deposited between them. Correspondingly, contact holes are also formed on the etch stop layer between the first insulating layer 21 and the second insulating layer 22, connecting the first contact hole 31 and the second contact hole 32. Furthermore, the portion of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 is also deposited on the sidewall of the contact hole formed on the etch stop layer. By depositing an etch stop layer between them, the etch stop layer protects the first insulating layer 21 and the substrate 10 during the manufacturing process, preventing subsequent etching or cleaning operations from affecting the substrate 10 and the two insulating layers, thus ensuring the quality of the substrate 10 and the insulating layers.

[0058] like Figure 2 As shown, a support structure 81 for supporting the lower electrode 40 can also be provided above the etching barrier layer 70. The support structure 81 surrounds the outer wall of the lower electrode 40 to improve the support effect on the lower electrode 40. Specifically, when setting the support structure 81, the support structure 81 can be set at the upper end of the lower electrode 40 or at the middle position of the lower electrode 40, and support structures 81 can be set at different positions of the lower electrode 40 at the same time.

[0059] When determining the type of semiconductor device, it can be a dynamic random access memory (DRAM) to prevent capacitor collapse caused by tilting or bending of the lower electrode 40. The semiconductor device can also be a static random-access memory (SRAM), flash memory, or other memory that uses capacitors as storage cells.

[0060] By removing the conductor film 221 and the landing pad 222 in contact with the conductor film 221 within the second contact hole 32, and also removing a portion of the stacked contact plug 211 within the first contact hole 31, the lower electrode 40 formed above the two insulating layers extends further downward into the first and second contact holes 31 and 32 to contact the remaining stacked contact plug 211. This creates an anchor-like structure in contact with the stacked contact plug 211, supporting the entire lower electrode 40 and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the anchor-like structure in the lower electrode 40 further prevents bending and deformation, thus preventing capacitor collapse. Furthermore, the portion of the lower electrode 40 extending into the first and second contact holes 31 and 32 increases the surface area of ​​the lower electrode 40, thereby increasing the capacitor's charge storage capacity, capacitance, and storage performance. Furthermore, the lower electrode 40 extends downwards to directly contact the retained stacked contact plug 211 through the first contact hole 31 and the second contact hole 32, replacing the previous method where the lower electrode 40 contacts the stacked contact plug 211 through the landing pad 222 and the conductor film 221. This reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively robust, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance and further improve storage performance.

[0061] In addition, embodiments of the present invention also provide a method for manufacturing a semiconductor device, the method comprising:

[0062] Step 1: Provide a substrate 10;

[0063] Step 2: Lay an insulating layer on the substrate 10;

[0064] Step 3: Contact holes are formed in the insulating layer;

[0065] Step 4: Fill the contact hole with a stacked contact plug 211 and a landing pad 222 that is electrically connected to the stacked contact plug 211;

[0066] Step 5: Remove landing pad 222;

[0067] Step 6: Remove part of the stacked contact plug 211 from top to bottom;

[0068] Step 7: A lower electrode 40 is formed above the insulating layer, and the lower electrode 40 extends downward into the contact hole to contact the retained stacked contact plug 211.

[0069] In the above-described scheme, by removing the landing pad 222 within the contact hole and also removing a portion of the stacked contact plug 211 within the contact hole, the lower electrode 40 formed above the insulating layer extends downward into the contact hole to contact the remaining stacked contact plug 211. This creates an anchor-like structure on the portion of the lower electrode 40 in contact with the stacked contact plug 211, supporting the entire lower electrode 40 and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the anchor-like structure in the lower electrode 40 further prevents bending and deformation of the entire lower electrode 40, thereby preventing capacitor collapse. Furthermore, the portion of the lower electrode 40 extending into the contact hole increases the surface area of ​​the lower electrode 40, thereby increasing the capacitor's charge storage capacity, capacitance, and storage performance. Furthermore, the lower electrode 40 extends downwards to directly contact the retained stacked contact plug 211 through the contact hole, replacing the previous method where the lower electrode 40 contacts the stacked contact plug 211 via the landing pad 222 and the conductor film 221. This reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is more robust, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance and further improve storage performance. The specific operation of each of the above steps will be described in detail below with reference to the accompanying drawings.

[0070] First, refer to Figure 3 A substrate 10 is provided, which can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, etc. The substrate 10 can also be a stacked structure with partially formed semiconductor structures. For example, the substrate 10 can include at least a semiconductor substrate, a transistor, a bit line structure, etc. The transistor can be formed on the semiconductor substrate of the semiconductor device. The bit line structure can be formed above the transistor.

[0071] Next, an insulating layer is laminated on the substrate 10. (Reference) Figure 3 The insulating layer can be a layer structure formed by a single deposition, or it can be a layer structure formed by two depositions of the first insulating stack 21 and the second insulating stack 22, as mentioned in the description of the semiconductor device section. Of course, the insulating layer can also be a layer structure composed of the first insulating stack 21, the second insulating stack 22, and the etch barrier layer between them. In this case, the insulating layer is formed by at least three depositions.

[0072] Next, contact holes are formed in the insulating layer. These contact holes can be through-holes formed in a single deposition of the insulating layer, or through-holes formed in at least two depositions. (Reference) Figure 3When the insulating layer is formed by stacking the aforementioned first insulating layer 21 and second insulating layer 22, the contact hole includes a first contact hole 31 located at the bottom and a second contact hole 32 located at the top.

[0073] Next, refer to Figure 3 The contact hole is filled with a stacked contact plug 211 and a landing pad 222 electrically connected to the stacked contact plug 211. For details, refer to... Figure 3 First, a stacked contact plug is filled into the contact hole; then, a conductive film that contacts the stacked contact plug is filled into the contact hole; finally, a landing pad that contacts the conductive film is filled into the contact hole. That is, the contact plug 211, conductive film 221, and landing pad 222 are sequentially filled into the contact hole from bottom to top. The conductive film 221 can be made of metal silicide, and the landing pad 222 can be made of metal to increase the conductivity between the landing pad 24 and the stacked contact plug 11.

[0074] like Figure 3 The substrate 10 shown has a stacked contact plug 211 that fills the first contact hole 31, and a conductor film 221 and a landing pad 222 that fill the second contact hole 32, with the conductor film 221 and landing pad 222 also filling the second contact hole 32. The conductor film 221 is in contact with the stacked contact plug 211, and the landing pad 222 is in contact with the conductor film 221.

[0075] In application, the stacked contact plug 211 contacts the source or drain region of the transistor. Each landing pad 222 is formed on a corresponding stacked contact plug 211. The landing pad 222 is electrically connected to the source or drain region of the transistor via the conductive film 221 and the stacked contact plug 211. (Reference) Figure 3 An insulating portion 212 is also formed in the first insulating stack 21 to isolate two adjacent stacked contact plugs 211, and the stacked contact plugs 211 and the insulating portion 212 are formed between adjacent bit line structures. An isolation portion 223 is also formed in the second insulating stack 22 to isolate two adjacent landing pads 222.

[0076] Next, refer to Figure 4 Remove landing pad 222. Landing pad 222 can be removed using wet etching or remote plasma dry cleaning processes to remove it without affecting other film layers. (Reference) Figure 5 When the contact hole is filled from bottom to top with the stacked contact plug 211, conductor film 221 and landing pad 222, the conductor film 221 can also be removed. When removing the conductor film 221, wet etching or remote plasma dry cleaning process can be used to remove the conductor film 221 without affecting other film materials.

[0077] Next, refer to Figure 6 The contact plugs 211 are removed from top to bottom. Specifically, wet etching or remote plasma dry cleaning processes can be used to remove the portion of the contact plugs 211 within the contact holes from top to bottom, without affecting other film components. When removing the contact plugs 211 within the contact holes, a portion of the contact plugs 211 should be retained at the bottom of the contact holes so that the subsequently formed lower electrode 40 can contact the retained contact plugs 211.

[0078] Next, refer to Figure 2 A lower electrode 40 is formed above the insulating layer, and the lower electrode 40 extends downward into the contact hole to contact the retained stacked contact plug 211. For details, refer to... Figure 3 After the contact hole is filled with a stacked contact plug 211 and a landing pad 222 electrically connected to the stacked contact plug 211, and before the landing pad 222 is removed, a sacrificial film layer 50 can be stacked on the insulating layer. The sacrificial film layer 50 has a capacitor hole 60 communicating with the landing pad 222. When depositing the sacrificial film layer 50 on the insulating layer, it can be deposited directly on the insulating layer. Alternatively, an etching barrier layer 70 can be deposited between the sacrificial film layer 50 and the insulating layer. In this case, the capacitor hole 60 penetrates the sacrificial film layer 50 and the etching barrier layer 70 and communicates with the landing pad 222. By depositing the etching barrier layer 70 between the sacrificial film layer 50 and the insulating layer, the etching barrier layer 70 can prevent subsequent etching or cleaning operations from affecting the substrate 10 and the insulating layer after the sacrificial film layer 50 is removed in subsequent processes, ensuring the quality of the substrate 10 and the insulating layer.

[0079] like Figure 3 As shown, at least one support layer 80 can also be formed inside or above the sacrificial film layer 50. In this case, the capacitor hole 60 not only penetrates the sacrificial film layer 50 and the etching barrier layer 70, but also penetrates each support layer 80 and connects to the landing pad 222. After the lower electrode 40 is formed in the subsequent process, during the removal of the sacrificial film layer 50, a portion of the support layer 80 is also removed, and the remaining portion of the support layer 80 serves as a support structure 81 to support the lower electrode 40.

[0080] When forming the lower electrode 40 above the insulating layer, the lower electrode 40, which contacts the stacked contact plug 211, can be formed on the walls of the capacitor hole 60 and the contact hole, as well as on the upper surface of the retained portion of the stacked contact plug 211. Specifically, firstly, a lower electrode material layer can be deposited on the surface of the sacrificial film layer 50, the walls of the capacitor hole 60 and the contact hole, and the upper surface of the retained portion of the stacked contact plug 211. Then, the lower electrode material layer on the surface of the sacrificial film layer 50 is removed to form the lower electrode 40 that contacts the retained portion of the stacked contact plug 211. Specifically, the lower electrode material layer on the surface of the sacrificial film layer 50 can be removed using plasma etching or wet etching. Figure 6 As shown, if a support layer 80 is deposited above the sacrificial film layer 50, then the lower electrode material layer is not deposited on the surface of the sacrificial film layer 50, but on the surface of the top support layer 80. Similarly, the lower electrode material layer on the surface of the sacrificial film layer 50 is not removed, but on the surface of the top support layer 80. By forming the lower electrode 40 through deposition, the lower electrode 40 is facilitated, and the contact strength between the lower electrode 40 and the hole wall of the contact hole and the upper end face of the stacked contact plug 211 is improved, thereby enhancing the support effect on the entire lower electrode 40.

[0081] After forming the lower electrode 40, the sacrificial film layer 50 can be removed to form a structure like... Figure 2 The semiconductor device shown. Specifically, the sacrificial film layer 50 can be removed by plasma etching or wet etching. When at least one support layer 80 is formed in the sacrificial film layer 50, it is also necessary to remove a portion of the support layer 80 of each support layer 80, and retain the portion of the support layer 80 connected to the outer wall of the lower electrode 40 in each layer, as a support structure 81 for supporting the lower electrode 40, and the support structure 81 surrounds at least one ring around the outer wall of the lower electrode 40.

[0082] By removing the landing pad 222 within the contact hole and a portion of the stacked contact plug 211, the lower electrode 40 formed above the insulating layer extends further downward into the contact hole to contact the remaining stacked contact plug 211. This creates an anchor-like structure on the lower electrode 40 in contact with the stacked contact plug 211, supporting the entire lower electrode 40 and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the anchor-like structure in the lower electrode 40 further prevents bending and deformation, thus preventing capacitor collapse. Furthermore, the portion of the lower electrode 40 extending into the contact hole increases its surface area, thereby increasing the capacitor's charge storage capacity, capacitance, and storage performance. Furthermore, the lower electrode 40 extends downwards to directly contact the retained stacked contact plug 211 via the contact hole, replacing the previous method where the lower electrode 40 contacts the stacked contact plug 211 via the landing pad 222 and the conductor film 221. This reduces the number of contacts between different layers and lowers the resistance of interlayer current transmission. In application, because the anchor-like structure in the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is more robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase the capacitance and further improve storage performance.

[0083] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate including transistors and bit line structures, the bit line structures being formed above the transistors; A first insulating stack is stacked on the substrate, and a first contact hole is formed in the first insulating stack; wherein, the first contact hole is filled from bottom to top with a stacked contact plug, the stacked contact plug is in contact with the source region or drain region of the transistor, and the stacked contact plug does not completely fill the first contact hole; an insulating portion is also formed in the first insulating stack to isolate two adjacent stacked contact plugs, the stacked contact plug and the insulating portion are formed between adjacent bit line structures; A second insulating layer is stacked on the first insulating layer, and the second insulating layer has a second contact hole that communicates with the first contact hole; A lower electrode is formed above the second insulating layer, and the lower electrode extends downward in sequence into the second contact hole and the first contact hole to contact the stacked contact plug; The height of the stacked contact plug is h1, and the height of the first contact hole is h2, wherein 20%×h2≤h1≤80%×h2.

2. The semiconductor device as claimed in claim 1, characterized in that, The lower electrode, extending to the hole walls of the second contact hole and the first contact hole, is deposited on the hole walls of the first contact hole and the second contact hole; The lower electrode, extending to the upper end face of the stacked contact plug, is deposited on the upper end face of the stacked contact plug.

3. The semiconductor device as described in claim 1, characterized in that, The lower electrode is cylindrical in shape; the bottom wall of the lower electrode is deposited on the upper end surface of the stacked contact plug; the side wall of the lower electrode is partially deposited on the hole walls of the first contact hole and the second contact hole, and partially exposed outside the first contact hole and the second contact hole.

4. The semiconductor device as claimed in claim 1, characterized in that, An upper electrode and a dielectric layer that insulates and isolates the lower electrode from the upper electrode are formed on the bottom wall, inner side wall, and outer side wall of the lower electrode that are exposed outside the first contact hole and the second contact hole.

5. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a transistor and a bit line structure, the bit line structure being formed above the transistor; An insulating layer is stacked on the substrate; Contact holes are formed in the insulating layer; The contact hole is filled with a stacked contact plug and a landing pad that is electrically connected to the stacked contact plug. The stacked contact plug is in contact with the source region or drain region of the transistor. The insulating layer includes a first insulating stack, in which an insulating portion is formed to isolate two adjacent stacked contact plugs. The stacked contact plug and the insulating portion are formed between adjacent bit line structures. A sacrificial film layer is stacked on the insulating layer; A capacitor hole communicating with the landing pad is formed in the sacrificial film layer; Remove the landing pad; Remove a portion of the stacked contact plug from top to bottom; A lower electrode is formed above the insulating layer, and the lower electrode extends downward into the contact hole to contact the reserved portion of the stacked contact plug; Specifically, the landing pad that fills the contact hole with a stacked contact plug and is electrically connected to the stacked contact plug is: The contact hole is filled with stacked contact plugs; A conductor film that contacts the stacked contact plug is filled into the contact hole; The contact hole is filled with a landing pad that contacts the conductor film; After removing the landing pads and before removing a portion of the stacked contact plugs from top to bottom, the manufacturing method further includes removing the conductor film.

6. The manufacturing method as described in claim 5, characterized in that, The removal of the landing pads, conductor film, and part of the stacked contact plugs specifically involves using a wet etching process or a remote plasma dry cleaning process to remove the landing pads, conductor film, and part of the stacked contact plugs from the contact holes from top to bottom.

7. The manufacturing method as described in claim 5, characterized in that, The formation of a lower electrode above the insulating layer, and the lower electrode extending downward into the contact hole to contact the reserved portion of the stacked contact plug, specifically refers to: A lower electrode is formed on the hole wall of the capacitor hole and the contact hole, and on the upper end surface of the retained portion of the stacked contact plug, to contact the retained stacked contact plug.

8. The manufacturing method as described in claim 7, characterized in that, Specifically, the lower electrode, which contacts the retained stacked contact plug, is formed on the hole walls of the capacitor hole and the contact hole, and on the upper end surface of the retained portion of the stacked contact plug. A lower electrode material layer is deposited on the surface of the sacrificial film layer, the walls of the capacitor holes and contact holes, and the upper surface of the retained portion of the stacked contact plug; Remove the lower electrode material layer from the surface of the sacrificial film layer to form a lower electrode that contacts the retained stacked contact plug.

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