Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to the field of semiconductor technology, providing a semiconductor structure and its manufacturing method. The semiconductor structure includes: a transistor structure and a capacitor structure arranged along a first direction, the capacitor structure extending along the first direction; and a word line staircase structure arranged at intervals from the transistor structure along a second direction, the word line staircase structure extending along the first direction, the first direction intersecting the second direction, and the word line staircase structure and the transistor structure being electrically connected. Using a plane perpendicular to the second direction as a reference plane, the orthographic projection of the transistor structure onto the reference plane is a first projection, the orthographic projection of the capacitor structure onto the reference plane is a second projection, and the orthographic projection of the word line staircase structure onto the reference plane is a third projection. The third projection covers the first projection, and the third projection partially overlaps with the second projection. This disclosure at least helps to improve the integration density of the transistor structure and capacitor structure in the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] As semiconductor structures continue to evolve and their critical dimensions shrink, limitations in lithography machines restrict further reduction. Therefore, achieving higher storage density chips on a single wafer remains a key research focus for many researchers and semiconductor professionals. In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Thus, the integration density of two-dimensional or planar semiconductor devices is determined by the area occupied by each memory cell. This integration density is significantly influenced by the technology used to form intricate patterns, limiting the potential for further increases in integration density. Consequently, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, the current arrangement of functional devices in three-dimensional semiconductor devices requires a completely new design. For example, while ensuring that the functional devices do not affect each other, the existing layout space should be fully utilized to improve the integration density of three-dimensional semiconductor devices. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least improves the integration density of transistor and capacitor structures in the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a transistor structure and a capacitor structure arranged along a first direction, the capacitor structure extending along the first direction; a word line staircase structure arranged at intervals from the transistor structure along a second direction, the word line staircase structure extending along the first direction, the first direction intersecting the second direction, the word line staircase structure and the transistor structure being electrically connected; wherein, taking a plane perpendicular to the second direction as a reference plane, the orthographic projection of the transistor structure on the reference plane is a first projection, the orthographic projection of the capacitor structure on the reference plane is a second projection, the orthographic projection of the word line staircase structure on the reference plane is a third projection, the third projection covering the first projection, and the third projection partially overlapping the second projection.

[0006] In some embodiments, the transistor structure, the capacitor structure, and the word line ladder structure constitute a memory structure, two adjacent memory structures along the first direction are centrally symmetrical, and the word line ladder structure of one of the two memory structures and the capacitor structure of the other are arranged at intervals along the first direction.

[0007] In some embodiments, the transistor structure includes a plurality of sub-transistor structures spaced apart along a third direction, and the third direction, the second direction, and the first direction intersect each other; the capacitor structure includes a plurality of sub-capacitor structures spaced apart along a third direction, each sub-capacitor structure including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer stacked sequentially; the word line staircase structure includes a plurality of step structures spaced apart along the third direction, each step structure extending along the first direction, and the lengths of the plurality of step structures in the first direction being different; wherein, the sub-transistor structures are connected one-to-one with the sub-capacitor structures, and the sub-transistor structures are connected one-to-one with the step structures.

[0008] In some embodiments, the semiconductor structure further includes a support structure located between adjacent sub-capacitor structures in the capacitor structure, and the support structure surrounds a portion of the sidewall of the sub-capacitor structure extending in the first direction to support the capacitor structure.

[0009] In some embodiments, the transistor structure, the capacitor structure, and the word line ladder structure constitute a memory structure, and the memory structures are arranged at intervals along both the first direction and the second direction; the semiconductor structure further includes a support structure shared by multiple memory structures, the support structure extending along the second direction and surrounding the capacitor structure located in the multiple memory structures arranged in the second direction.

[0010] In some embodiments, a first gap exists between the stepped structure of one of two adjacent storage structures along the first direction and the capacitor structure of the other; the support structure includes: a first support layer extending along the second direction and surrounding a portion of the sidewall of the lower electrode layer extending along the first direction, the first support layer being located in the first gap.

[0011] In some embodiments, the sub-transistor structure includes: a portion of a semiconductor channel extending along the first direction, and a gate structure surrounding a sidewall of the semiconductor channel extending along the first direction; the lower electrode layer includes a portion of the semiconductor channel extending along the first direction; the support structure further includes: a second support layer extending along the second direction and surrounding a portion of the sidewall of the semiconductor channel, the second support layer being located between the gate structure and the capacitor structure and between adjacent step structures; and a third support layer extending along the second direction and surrounding a portion of the sidewall of the semiconductor channel in the lower electrode layer, the third support layer being located on the side of the first support layer away from the second support layer.

[0012] In some embodiments, along the first direction, the semiconductor channel includes a first region, a second region, and a third region, the gate structure surrounds the sidewall of the first region, the second support layer surrounds the sidewall of the second region, the lower electrode layer includes the third region and a sub-lower electrode layer surrounding a portion of the sidewall of the third region, and the first support layer and the third support layer surround the remaining sidewall of the third region.

[0013] In some embodiments, the semiconductor structure further includes: a plurality of first conductive pillars extending along the third direction, each of the first conductive pillars corresponding to one of the stepped structures, and the first conductive pillars being in contact with the stepped structures; and a plurality of second conductive pillars extending along the third direction, the second conductive pillars being in contact with the upper electrode layer.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, including: forming a transistor structure and a capacitor structure arranged along a first direction, the capacitor structure extending along the first direction; forming a word line staircase structure, the word line staircase structure and the transistor structure being arranged at intervals along a second direction, and the word line staircase structure extending along the first direction, the first direction intersecting the second direction, the word line staircase structure and the transistor structure being electrically connected; wherein, taking a plane perpendicular to the second direction as a reference plane, the orthographic projection of the transistor structure on the reference plane is a first projection, the orthographic projection of the capacitor structure on the reference plane is a second projection, the orthographic projection of the word line staircase structure on the reference plane is a third projection, the third projection covering the first projection, and the third projection partially overlapping the second projection.

[0015] In some embodiments, the word line ladder structure and the transistor structure are formed using the same fabrication steps.

[0016] In some embodiments, the capacitor structure includes a plurality of sub-capacitor structures arranged along a third direction, and the manufacturing method further includes: forming a support structure located between adjacent sub-capacitor structures in the capacitor structure, and the support structure surrounding a portion of the sidewall of the sub-capacitor structure to support the capacitor structure.

[0017] In some embodiments, the support structure includes a first support layer, and the step of forming the first support layer includes: forming a first stacked structure and a second stacked structure spaced apart and staggered along a first direction, wherein the first stacked structure and the second stacked structure are spaced apart and staggered along a second direction; forming a first sacrificial layer, wherein the first sacrificial layer fills a first gap between the first stacked structure and the second stacked structure; wherein, along a third direction, both the first stacked structure and the second stacked structure include alternately stacked first semiconductor layers and second semiconductor layers, and the third direction, the second direction, and the first direction intersect each other; forming a first mask layer having a first opening, wherein the first opening extends along the second direction and exposes a portion of the first sacrificial layer; using the first mask layer as a mask, etching the first sacrificial layer exposed by the first opening and the first semiconductor layer facing the first opening to form a first hole; and forming a first support layer, wherein the first support layer fills the first hole.

[0018] In some embodiments, the step of forming the first stacked structure and the second stacked structure includes: forming an initial first semiconductor layer and an initial second semiconductor layer that are stacked sequentially upward along the third party; and graphically representing the initial first semiconductor layer and the initial second semiconductor layer to form the first stacked structure and the second stacked structure.

[0019] In some embodiments, the second semiconductor layer in the first stacked structure is a semiconductor channel, and along the first direction, the semiconductor channel includes a first region, a second region, and a third region; the support structure further includes a second support layer and a third support layer; the step of forming the first mask layer further includes: forming a first mask layer having a second opening and a third opening, wherein the second opening extends along the second direction and exposes the second region and the first sacrificial layer in contact with the second region, the third opening extends along the second direction and exposes a portion of the first sacrificial layer between adjacent first stacked structures; the step of forming the second support layer includes: using the first mask layer as a mask, etching the first sacrificial layer exposed by the second opening and the first semiconductor layer facing the second opening to form a second hole; forming a second support layer that fills the second hole; the step of forming the third support layer includes: using the first mask layer as a mask, etching the first sacrificial layer exposed by the third opening and the first semiconductor layer facing the third opening to form a third hole; forming a third support layer that fills the third hole.

[0020] In some embodiments, the step of forming the transistor structure includes: using the second semiconductor layer and the support structure as masks, removing the remaining first semiconductor layer and the first sacrificial layer to form a fourth hole; forming a second sacrificial layer to fill the fourth hole; forming a second mask layer located on the third region of the semiconductor channel; using the second mask layer as a mask, removing the second sacrificial layer in contact with the first region of the semiconductor channel and removing the second sacrificial layer in contact with the second stacked structure; forming a gate structure and a conductive layer, the gate structure surrounding the sidewall of the first region of the semiconductor channel, the conductive layer surrounding the sidewall of the second semiconductor layer in the second stacked structure, the transistor structure including the gate structure and the first region, the conductive layer and the second semiconductor layer in the second stacked structure forming an initial word line staircase structure.

[0021] In some embodiments, along the third upward direction, there is a second spacing between the gate structures surrounding different sidewalls of the first region, and a third spacing between the conductive layers surrounding the sidewalls of the first semiconductor layer in different second stacked structures; the manufacturing method further includes: forming a first dielectric layer, the first dielectric layer filling the second spacing and the third spacing.

[0022] In some embodiments, the step of forming the capacitor structure includes: forming a third mask layer having a fourth opening located on the third region of the semiconductor channel; using the third mask layer as a mask to remove the second sacrificial layer in contact with the third region to form a fifth hole; forming a sub-lower electrode layer surrounding the semiconductor channel sidewall exposed by the fifth hole; forming a capacitor dielectric layer surrounding the sidewall of the sub-electrode layer away from the semiconductor channel; and forming an upper electrode layer filling the remaining fifth holes; wherein the semiconductor channel of the third region and the sub-lower electrode layer constitute the lower electrode layer, and the lower electrode layer, the capacitor dielectric layer, and the upper electrode layer constitute the capacitor structure.

[0023] In some embodiments, the step of forming the word line staircase structure includes: performing local etching on the initial word line staircase structure and the first semiconductor layer in the second stacked structure multiple times to form the word line staircase structure, the word line staircase structure including a plurality of step structures spaced apart along the third direction, and the plurality of step structures having different lengths along the first direction.

[0024] In some embodiments, the manufacturing method further includes: forming a plurality of first conductive posts extending along the third direction, wherein each first conductive post corresponds to a step structure and is in contact with the step structure; and forming a plurality of second conductive posts extending along the third direction, wherein the second conductive posts are in contact with the capacitor structure.

[0025] The technical solution provided in this disclosure has at least the following advantages:

[0026] The transistor structure has opposing first and second sides along the first direction, and opposing third and fourth sides along the second direction. The capacitor structure is located on the first or second side, and the word line ladder structure is located on the third or fourth side. This arrangement, by placing the transistor structure and the word line ladder structure adjacent to each other to facilitate electrical connection, also helps reduce the overall layout length of the transistor structure, capacitor structure, and word line ladder structure in the first direction. Furthermore, it is understood that the layout length of the semiconductor structure in the first direction is generally determined by the layout length of the capacitor structure in the first direction. The portion of the word line ladder structure extending along the first direction is directly opposite the capacitor structure. This allows for a reduction in the layout length of the word line ladder structure in the second direction while maximizing its placement along the first direction, thereby increasing the length of the area directly opposite the capacitor structure. This achieves efficient use of layout space and reduces the total layout area of ​​the semiconductor structure. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a partial three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0029] Figure 2 This is a partial top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0030] Figure 3 for Figure 1 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1.

[0031] Figure 4 for Figure 3 A magnified structural diagram of region IV in the middle.

[0032] Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step of the manufacturing method of a semiconductor structure provided in another embodiment of this disclosure. Detailed Implementation

[0033] As can be seen from the background technology, the integration density of semiconductor structures needs to be improved.

[0034] This disclosure provides a semiconductor structure and its manufacturing method. In the semiconductor structure, along a first direction, a transistor structure is adjacent to a capacitor structure, and along a second direction, a transistor structure is adjacent to a word line ladder structure. This facilitates electrical connection between the transistor structure and the word line ladder structure while reducing the overall layout length of the transistor structure, capacitor structure, and word line ladder structure in the first direction. Furthermore, it is understood that the layout length of the semiconductor structure in the first direction is generally determined by the layout length of the capacitor structure in the first direction. The portion of the word line ladder structure extending along the first direction is directly opposite the capacitor structure. This allows for a reduction in the layout length of the word line ladder structure in the second direction while maximizing its placement along the first direction. This increases the length of the area directly opposite the word line ladder structure and the capacitor structure, achieving efficient use of layout space and reducing the total layout area of ​​the semiconductor structure, thereby increasing the integration density of the transistor and capacitor structures in the semiconductor structure.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] This disclosure provides a method for manufacturing a semiconductor structure according to an embodiment. The method for manufacturing a semiconductor structure according to an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 This is a partial three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a partial top view of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 for Figure 1 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1. Figure 4 for Figure 3 A magnified structural diagram of region IV in the middle.

[0037] refer to Figure 1 The semiconductor structure includes: a transistor structure 100 and a capacitor structure 101 arranged along a first direction X, the capacitor structure 101 extending along the first direction X; a word line staircase structure 102, arranged at intervals from the transistor structure 100 along a second direction Y, and the word line staircase structure 102 extending along the first direction X, the first direction X intersecting the second direction Y, and the word line staircase structure 102 and the transistor structure 100 being electrically connected; wherein, taking a plane perpendicular to the second direction Y as a reference plane, the orthographic projection of the transistor structure 100 on the reference plane is the first projection, the orthographic projection of the capacitor structure 101 on the reference plane is the second projection, and the orthographic projection of the word line staircase structure 102 on the reference plane is the third projection, the third projection covering the first projection, and the third projection partially overlapping the second projection.

[0038] Understandably, reference Figure 1 The transistor structure 100 and capacitor structure 101 are arranged in the first direction X, and the transistor structure 100 and word line staircase structure 102 are arranged in the second direction Y. The extension directions of the word line staircase structure 102 and capacitor structure 101 are both in the first direction X. Generally, the increased demand for capacitor structure 101 with large capacitance results in capacitor structure 101 occupying a larger layout length in the first direction X. Therefore, the layout length of the semiconductor structure in the first direction X is generally determined by the layout length of capacitor structure 101 in the first direction X. Thus, in one embodiment of this disclosure, the arrangement of transistor structure 100, capacitor structure 101, and word line staircase structure 102 is beneficial for increasing the area directly opposite the word line staircase structure 102 and capacitor structure 101, i.e., increasing the overlap area between the third projection and the second projection, in order to reduce the overlap area of ​​word line staircase structure 102 in the first direction Y. While increasing the layout length in the Y direction, the word line ladder structure 102 is arranged as much as possible along the X direction. This is beneficial to reduce the layout length of the semiconductor structure in the Y direction without increasing the layout length of the semiconductor structure in the X direction. This reduces the layout length of the semiconductor structure in the Y direction, thereby making reasonable use of the layout space and reducing the total layout area of ​​the semiconductor structure. This allows for the integration of more transistor structures 100, capacitor structures 101, and word line ladder structures 102 within a certain layout area, thereby increasing the integration density of the semiconductor structure.

[0039] The following combination Figures 1 to 4 The semiconductor structure is described in detail.

[0040] In some embodiments, reference Figure 2The transistor structure 100, the capacitor structure 101, and the word line ladder structure 102 constitute the memory structure 103. Two adjacent memory structures 103 along the first direction X are centrally symmetrical, and the word line ladder structure 102 of one of the two memory structures 103 and the capacitor structure 101 of the other are arranged at intervals along the first direction X.

[0041] It is understood that, for a single memory structure 103, the word line staircase structure 102 protrudes relative to the transistor structure 100 and the capacitor structure 101 in the second direction Y. Furthermore, due to the high capacitance requirement of the capacitor structure 101, in the first direction X, the layout length of the capacitor structure 101 is greater than the layout length of the word line staircase structure 102, resulting in a portion of the area directly opposite the capacitor structure 101 along the extension direction of the word line staircase structure 102 being vacant. The word line staircase structure 102 may have only a step structure in the first direction X, or it may have step structures in both the first direction X and the second direction Y, thereby increasing the number of step structures in the same area. In one embodiment of this disclosure, two adjacent memory structures 103 are centrally symmetrical along the first direction X. The aforementioned vacant area of ​​one of the two memory structures 103 can correspond to the vacant area of ​​the other, meaning that the vacant area of ​​one of the two memory structures 103 without the word line staircase structure 102 can be used to arrange the capacitor structure 101 of the other, thereby increasing the layout density of the memory structures 103.

[0042] Furthermore, the word line ladder structure 102 of one of the two memory structures 103 and the capacitor structure 101 of the other are arranged at intervals along the first direction X. Thus, the layout length of the two memory structures 103 in the second direction Y is the same as the layout length of one memory structure 103 in the second direction Y. That is, the word line ladder structure 102 of one of the two memory structures 103 and the capacitor structure 101 of the other are arranged in the same row, which is beneficial to further improve the layout density of the memory structures 103, thereby improving the integration density of the semiconductor structure.

[0043] In this configuration, a first gap exists between the word line ladder structure 102 of one of the two memory structures 103 and the capacitor structure 101 of the other. Without considering the layout length of this first gap in the first direction X, the layout length of the two memory structures 103 in the first direction X is equivalent to the sum of the layout length of one memory structure 103 and the layout length of one word line ladder structure 102 in the first direction X. This helps to reduce the layout length of the two memory structures 103 along the first direction X, thereby further increasing the layout density of the memory structures 103.

[0044] It should be noted that, Figure 2Taking the arrangement of two storage structures 103 spaced apart along the first direction X and three storage structures 103 spaced apart along the second direction Y as an example, for a total of six storage structures 103, in practical applications, there are no restrictions on the number of storage structures 103 spaced apart along the first direction X and the second direction Y, as long as two adjacent storage structures 103 along the direction X are centrally symmetrical.

[0045] In some embodiments, reference Figure 3 and Figure 4 The semiconductor structure may further include a substrate 160 located directly below the transistor structure 100, the capacitor structure 101, and the word line ladder structure 102 along the third direction Z, serving as a support base for the transistor structure 100, the capacitor structure 101, and the word line ladder structure 102.

[0046] In some embodiments, reference Figure 1 , Figure 3 and Figure 4 The transistor structure 100 may include multiple sub-transistor structures 110 spaced apart along a third direction Z, and the third direction Z, the second direction Y, and the first direction X intersect each other; the capacitor structure 101 includes multiple sub-capacitor structures 111 spaced apart along a third direction Z, and each sub-capacitor structure 111 includes a lower electrode layer 121, a capacitor dielectric layer 131, and an upper electrode layer 141 stacked sequentially; the word line staircase structure 102 includes multiple step structures 112 spaced apart along a third direction Z, each step structure 112 extending along the first direction X, and the lengths of the multiple step structures 112 in the first direction X are different; wherein, the sub-transistor structures 110 and the sub-capacitor structures 111 are connected in a one-to-one correspondence, and the sub-transistor structures 110 and the step structures 112 are connected in a one-to-one correspondence.

[0047] It is understandable that multiple sub-transistor structures 110 and multiple sub-capacitor structures 111 can be arranged along the third direction Z. A sub-transistor structure 110 can be used as a transistor unit, and a sub-capacitor structure 111 can be used as a capacitor unit. A transistor unit and a capacitor unit can constitute a memory cell. In this way, it is beneficial to increase the layout density of memory cells in the semiconductor structure by stacking sub-transistor structures 110 and sub-capacitor structures 111 along the third direction Z, thereby increasing the integration density of the semiconductor structure.

[0048] Furthermore, the sub-transistor structures 110 and the step structures 112 are connected in a one-to-one correspondence, and the lengths of the multiple step structures 112 in the first direction X are different. Thus, different sub-transistor structures 110 can be controlled by different step structures 112 to achieve independence between different sub-transistor structures 110. In some embodiments, the lengths of the multiple step structures 112 in the first direction X can increase sequentially along the direction from the sub-transistor structure 110 to the substrate 160.

[0049] In some embodiments, continue to refer to Figure 3 and Figure 4 Along the first direction X, the semiconductor channel 113 includes a first region 123, a second region 133, and a third region 143. The sub-transistor structure 110 includes the semiconductor channel 113 of the first region 123 and a gate structure 120, wherein the gate structure 120 surrounds a sidewall of the first region 123 extending along the first direction X. In one example, along the third direction Z, the gate structure 120 includes a gate dielectric layer 130 and a gate conductive layer 140 stacked sequentially, wherein the gate dielectric layer 130 surrounds a sidewall of the first region 123 extending along the first direction X, and the gate conductive layer 140 surrounds a sidewall of the gate dielectric layer 130 away from the first region 123 and extending along the first direction X. It is understood that the material of the gate conductive layer 140 can be at least one of conductive materials such as titanium nitride, tungsten, or silver, and the material of the gate dielectric layer 130 can be at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0050] Furthermore, in some embodiments, the lower electrode layer 121 in the sub-capacitor structure 111 includes a semiconductor channel 113 of the third region 143 and a sub-lower electrode layer 151, wherein the sub-lower electrode layer 151 surrounds a portion of the sidewall of the third region 143 extending in the first direction X; the capacitor dielectric layer 131 surrounds the sidewall of the sub-lower electrode layer 151 away from the third region 143 and extending in the first direction X; the upper electrode layer 141 surrounds the sidewall of the sub-capacitor dielectric layer 131 away from the sub-lower electrode layer 151 and extending in the first direction X; the sub-capacitor structure 111 and the sub-transistor structure 110 are electrically connected through the second region 133, that is, the signal in the sub-transistor structure 110 is transmitted to the sub-capacitor structure 111 for storage through the second region 133, or the signal stored in the sub-capacitor structure 111 is transmitted to the sub-transistor structure 110 through the second region 133.

[0051] In some embodiments, the upper electrode layer 141 may include a diffusion barrier layer (not shown) and a sub-upper electrode layer (not shown) stacked sequentially. The diffusion barrier layer surrounds a sidewall of the capacitor dielectric layer 131 that is away from the sub-lower electrode layer 151 and extends along a first direction X. The sub-upper electrode layer surrounds a sidewall of the diffusion barrier layer that is away from the capacitor dielectric layer 131 and extends along the first direction X. The diffusion barrier layer helps to prevent the diffusion of conductive material in the sub-upper electrode layer into the capacitor dielectric layer 131, thereby ensuring good insulation performance of the capacitor dielectric layer 131 and good conductivity performance of the sub-upper electrode layer. In one example, the material of the diffusion barrier layer may be titanium nitride, and the materials of the sub-upper electrode layer and the sub-lower electrode layer 151 may be at least one of conductive materials such as polycrystalline silicon, titanium nitride, or tungsten. The material of the capacitor dielectric layer 131 may be a dielectric material with a high dielectric constant such as hafnium oxide, chromium oxide, or zirconium oxide.

[0052] In some embodiments, reference Figure 3 The upper electrode layers 141 in the multiple sub-capacitor structures 111 can be in contact with each other. In practical applications, multiple sub-capacitor structures 111 in the same memory structure 103 can share a single upper electrode layer 141. The material of the upper electrode layer 141 may include polycrystalline silicon or germanium silicon.

[0053] In some embodiments, reference Figure 2 The semiconductor structure may further include an electrical connection layer 150 extending along a second direction Y, wherein one end of the electrical connection layer 150 is in contact with the transistor structure 100 and the other end is in contact with the word line ladder structure 102 along the second direction Y. It is understood that the word line ladder structure 102 and the transistor structure 100 are electrically connected through the electrical connection layer 150.

[0054] In some embodiments, the stepped structure 112 may include a support layer 153, a dielectric layer 132, and a conductive layer 122. The support layer 153 and the semiconductor channel 103 may be integrally formed, the dielectric layer 132 and the gate dielectric layer 130 may be integrally formed, and the conductive layer 122 and the gate conductive layer 140 may be integrally formed. In one example, the electrical connection layer 150 is in contact with and on the same layer as the gate conductive layer 140 in the transistor structure 100, and is also in contact with and on the same layer as the conductive layer 122 in the word line stepped structure 102. Thus, the conductive layer 122 and the gate conductive layer 140 are electrically connected through the electrical connection layer 150, thereby achieving the electrical connection between the stepped structure 112 and the sub-transistor structure 110.

[0055] In other embodiments, the stepped structure may consist of only a conductive layer, which is electrically connected to the gate conductive layer through an electrical connection layer, and the conductive layer and the sub-transistor structure are on the same layer.

[0056] In some embodiments, continue to refer to Figure 3 and Figure 4 The semiconductor structure may further include: a first dielectric layer 107 located between adjacent sub-transistor structures 110 to achieve electrical insulation between adjacent sub-transistor structures 110; the first dielectric layer 107 is also located between adjacent step structures 112 to achieve electrical insulation between adjacent step structures 112; along the second direction Y, adjacent memory structures 103 are spaced together, and the first dielectric layer 107 is also located in the space. It is understood that the width of the electrical connection layer 150 in the second direction Y is equal to the width of the space in the second direction Y.

[0057] It should be noted that the electrical connection layer 150 corresponds one-to-one with the sub-transistor structure 110, that is, multiple electrical connection layers 150 are arranged sequentially at intervals along the third direction Z. The first dielectric layer 107 is also used to achieve insulation between the multiple electrical connection layers 150.

[0058] In some embodiments, reference Figures 1 to 4 The semiconductor structure also includes a support structure 104, which is located between adjacent sub-capacitor structures 111 in the capacitor structure 101, and the support structure 104 surrounds a portion of the sidewall of the sub-capacitor structure 111 extending along the first direction X to support the capacitor structure 101.

[0059] Understandably, reference Figure 1 Due to the increased demand for capacitor structures 101 with large capacitance, the layout length of capacitor structures 101 in the first direction X is relatively large. Therefore, the support structure 104 surrounds the sidewall of the sub-capacitor structure 101 extending along the first direction X to fix and support the longer capacitor structure 101, preventing its collapse and improving the stability of the semiconductor structure. Furthermore, refer to... Figure 4 The sub-capacitor structure 111 includes a semiconductor channel 113 in the third region 143, and the support structure 104 and the sub-lower electrode layer 151 together cover the sidewall of the third region 143 extending along the first direction X.

[0060] It should be noted that, Figure 1 Taking the support structure 104 as an example, which includes three support layers, in practical applications, the support structure 104 may include only one support layer, which surrounds the side wall of the sub-capacitor structure 111 in the middle part; or the support structure 104 may include only two or four support layers, with multiple support layers surrounding part of the side wall of the sub-capacitor structure 111, and the multiple support layers are evenly distributed along the layout length of the sub-capacitor structure 111 along the first direction X. That is, in one embodiment of this disclosure, the number and distribution of support layers included in the support structure 104 are not limited, and can be adjusted according to actual needs.

[0061] The following combination Figures 1 to 4 The support structure 104 is described in detail.

[0062] In some embodiments, reference Figure 2 The transistor structure 100, the capacitor structure 101, and the word line ladder structure 102 constitute the memory structure 103. The memory structure 103 is arranged at intervals along the first direction X and the second direction Y. The semiconductor structure also includes a support structure 104 shared by multiple memory structures 103. The support structure 104 extends along the second direction Y and surrounds the capacitor structure 101 located in the multiple memory structures 103 arranged in the second direction Y.

[0063] It is understandable that multiple memory structures 103 extending along the second direction Y can share a support structure 104, so that one support structure 104 can simultaneously position and support multiple capacitor structures 101, thereby improving the overall stability of the semiconductor structure.

[0064] In some embodiments, reference Figures 1 to 4 The stepped structure 112 of one of two adjacent storage structures 103 along the first direction X has a first gap with the capacitor structure 101 of the other; the support structure 104 includes: a first support layer 114, the first support layer 114 extends along the second direction Y and surrounds a portion of the sidewall of the lower electrode layer 121 extending along the first direction X, the first support layer 114 is located in the first gap, and the first support layer 114 is also used to isolate the two adjacent storage structures 103.

[0065] It is understood that the portion of the sidewall extending along the first direction X around the lower electrode layer 121 by the first support layer 114 refers to the portion of the sidewall exposed in the third region 143 of the lower electrode layer 121. In one example, the first support layer 114 can fill the first gap, providing support and fixation for the capacitor structure 101 while achieving electrical isolation between the stepped structure 112 of one of the two adjacent memory structures 103 and the capacitor structure 101 of the other, thus avoiding electrical interference between adjacent memory structures 103.

[0066] In some embodiments, reference Figure 4The sub-transistor structure 110 includes: a portion of semiconductor channel 113 extending along a first direction X, and a gate structure 120 surrounding a sidewall of semiconductor channel 113 extending along the first direction X; the lower electrode layer 121 includes a portion of semiconductor channel 113 extending along the first direction X; the support structure 104 further includes: a second support layer 124 extending along a second direction Y and surrounding a portion of the sidewall of semiconductor channel 113, the second support layer 124 being located between the gate structure 120 and the capacitor structure 101 and between adjacent step structures 112; and a third support layer 134 extending along the second direction Y and surrounding a portion of the sidewall of semiconductor channel 113 in the lower electrode layer 121, the third support layer 134 being located on the side of the first support layer 114 away from the second support layer 124.

[0067] As described above, along the third direction Z, the gate structure 120 may include a gate dielectric layer 130 and a gate conductive layer 140 stacked sequentially.

[0068] It is understood that the first support layer 114, the second support layer 124, and the third support layer 134 are distributed around the sidewalls of different regions of the semiconductor channel 113 to provide support for the semiconductor channel 113. In addition, since the second support layer 124 surrounds multiple stacked structures arranged along the second direction Y, the second support layer 124 surrounds part of the sidewall of the support layer 153 in the stepped structure 112 while surrounding the sidewall of the second region.

[0069] The first support layer 114, the second support layer 124, and the third support layer 134 will be explained in detail below with a specific example.

[0070] In one example, refer to Figure 4 Along the first direction X, the semiconductor channel 113 includes a first region 123, a second region 133 and a third region 143. The gate structure 120 surrounds the sidewall of the first region 123, the second support layer 124 surrounds the sidewall of the second region 133, the lower electrode layer 121 includes the third region 143 and a sub-lower electrode layer 151 surrounding a portion of the sidewall of the third region 143, and the first support layer 114 and the third support layer 134 surround the remaining sidewall of the third region 143.

[0071] It should be noted that the sidewalls of the first region 123, the second region 133, and the third region 143 all refer to the sidewalls of the semiconductor channel 113 extending along the first direction X. It can be understood that the second support layer 124 surrounds the sidewall of the second region 133, enabling the second support layer 124 to simultaneously fix and support the transistor structure 100 and the capacitor structure 101, and to achieve electrical isolation between the gate structure 120 and the lower electrode layer 151 and the upper electrode layer 141; the first support layer 114, the third support layer 134, and the lower electrode layer 151 together surround and cover the sidewall of the third region 143 extending along the first direction X, wherein the first support layer 114 and the third support layer 134 together fix and support the capacitor structure 101.

[0072] In some embodiments, reference Figure 3 The semiconductor structure may further include: a plurality of first conductive pillars 115 extending along a third direction Z, wherein each first conductive pillar 115 corresponds to a step structure 112 and the first conductive pillar 115 is in contact with the step structure 112; and a plurality of second conductive pillars 125 extending along a third direction Z, wherein the second conductive pillars 125 are in contact with the upper electrode layer 141.

[0073] It is understandable that since the stepped structure 112 corresponds one-to-one with the sub-transistor structure 110, the first conductive post 115 also corresponds one-to-one with the sub-transistor structure 110, thereby facilitating the control of different sub-transistor structures 110 through different first conductive posts 115. In one example, the first conductive post 115 is in contact with the conductive layer 122 in the stepped structure 112, and the second conductive post 125 is in contact with the upper electrode layer 141 in the capacitor structure 101.

[0074] It should be noted that, Figure 1 , Figure 3 and Figure 4 Taking the example of three sub-transistor structures 110 stacked along the third direction Z, in practical applications, there is no limit to the number of sub-transistor structures 110 stacked along the third direction Z, and the design can be carried out according to actual needs.

[0075] In some embodiments, reference Figure 3The topmost sub-transistor structure 110 has a first dielectric layer 107, which is also located between the topmost sub-transistor structure 110 and the topmost sub-capacitor structure 111, and may also be located on the surface of the word line ladder structure 102. The semiconductor structure may further include: a second dielectric layer 137, located on the top surface of the first dielectric layer 107 and the topmost sub-capacitor structure 111, to protect the sub-capacitor structure 111; a third dielectric layer 147, located on the top surface of the second dielectric layer 137 and surrounding the sidewalls of the first conductive pillar 115 and the second conductive pillar 125, with the top surface of the third dielectric layer 147, the top surface of the first conductive pillar 115, and the top surface of the second conductive pillar 125 flush, wherein the first conductive pillar 115 and the second conductive pillar 125 both penetrate the second dielectric layer 137 and the third dielectric layer 147.

[0076] It is understandable that the second dielectric layer 137 and the third dielectric layer 147 together support the first conductive pillar 115 and the second conductive pillar 125 and make the overall semiconductor structure planarize.

[0077] In some embodiments, reference Figure 1 The semiconductor structure may further include a bit line 135, which is contacted and connected to the side of the transistor structure 100 away from the capacitor structure 101 to achieve an electrical connection between the bit line 135 and the transistor structure 100. The bit line 135 may extend in a third direction Z.

[0078] In summary, along the first direction X, the transistor structure 100 is adjacent to the capacitor structure 101, and along the second direction Y, the transistor structure 100 is adjacent to the word line ladder structure 102. This facilitates electrical connection between the transistor structure 100 and the word line ladder structure 102 while reducing the overall layout length of the transistor structure 100, capacitor structure 101, and word line ladder structure 102 along the first direction X. Furthermore, the portion of the word line ladder structure 102 extending along the first direction X directly faces the capacitor structure 101. This allows for a reduction in the layout length of the word line ladder structure 102 along the second direction Y while maximizing its placement along the first direction X. This increases the length of the area directly opposite the word line ladder structure 102 and the capacitor structure 101, achieving efficient use of layout space and reducing the overall layout area of ​​the semiconductor structure, thereby increasing the integration density of the transistor structure 100 and the capacitor structure 101 within the semiconductor structure.

[0079] Another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, used to prepare the semiconductor structure provided in the foregoing embodiments. The following will be combined with... Figures 1 to 16 A method for manufacturing a semiconductor structure according to another embodiment of this disclosure will be described in detail. Figures 5 to 16This is a schematic diagram of the structure corresponding to each step of a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be described again here.

[0080] refer to Figures 5 to 16 The method for manufacturing a semiconductor structure includes: forming a transistor structure 100 and a capacitor structure 101 arranged along a first direction X, wherein the capacitor structure 101 extends along the first direction X; forming a word line staircase structure 102, wherein the word line staircase structure 102 and the transistor structure 100 are arranged at intervals along a second direction Y, and the word line staircase structure 102 extends along the first direction X, wherein the first direction X intersects the second direction Y, and the word line staircase structure 102 and the transistor structure 100 are electrically connected; wherein, taking a plane perpendicular to the second direction Y as a reference plane, the orthographic projection of the transistor structure 100 on the reference plane is a first projection, the orthographic projection of the capacitor structure 101 on the reference plane is a second projection, and the orthographic projection of the word line staircase structure 102 on the reference plane is a third projection, wherein the third projection covers the first projection, and the third projection partially overlaps with the second projection.

[0081] In some embodiments, the word line ladder structure 102 and the transistor structure 100 are formed using the same fabrication steps. This simplifies the semiconductor structure fabrication process and reduces the fabrication cost of the semiconductor structure. The following sections will describe in detail how the word line ladder structure 102 and the transistor structure 100 are formed using the same fabrication steps, with reference to specific embodiments.

[0082] In some embodiments, reference Figure 3 The capacitor structure 101 includes a plurality of sub-capacitor structures 111 arranged along a third direction Z. The manufacturing method may further include: forming a support structure 104, the support structure 104 being located between adjacent sub-capacitor structures 111 in the capacitor structure 101, and the support structure 104 surrounding a portion of the sidewall of the sub-capacitor structures 111 to support the capacitor structure 101. The formation of the support structure 103 will be described in detail later with reference to specific embodiments.

[0083] In some embodiments, the support structure 104 includes a first support layer 114, and forming the first support layer 114 may include the following steps:

[0084] refer to Figure 5 and Figure 6 A first stacked structure 116 and a second stacked structure 126 are formed and spaced apart and staggered along the first direction X, and the first stacked structure 116 and the second stacked structure 126 are spaced apart and staggered along the second direction Y.

[0085] It should be noted that two adjacent first stacked structures 116 are centrally symmetrical, and two adjacent second stacked structures 126 are centrally symmetrical. The first stacked structures 116 are used to subsequently form transistor and capacitor structures, and the second stacked structures 126 are used to subsequently form word line step structures.

[0086] In some embodiments, the step of forming the first stacked structure 116 and the second stacked structure 126 may include: referring to Figure 5 An initial first semiconductor layer 136 and an initial second semiconductor layer 146 are formed by sequentially stacking along the third direction Z, wherein the materials of the initial first semiconductor layer 136 and the initial second semiconductor layer 146 are different. In one example, the material of the initial first semiconductor layer 156 is silicon germanide, and the material of the initial second semiconductor layer 146 is silicon.

[0087] In some embodiments, prior to forming the initial first semiconductor layer 136 and the initial second semiconductor layer 146, the method further includes providing a substrate 160, on which the initial first semiconductor layer 136 and the initial second semiconductor layer 146 are subsequently formed.

[0088] refer to Figure 5 , Figure 6 and Figure 7 The initial first semiconductor layer 136 and the initial second semiconductor layer 146 are patterned to form a first stacked structure 116 and a second stacked structure 126. In one example, the initial first semiconductor layer 136 and the initial second semiconductor layer 146 are patterned using a fourth mask layer 189 having a fifth opening 179 as a mask to form a first semiconductor layer 156 and a second semiconductor layer 166. Thus, along the third direction Z, both the first stacked structure 116 and the second stacked structure 126 include alternately stacked first semiconductor layers 156 and second semiconductor layers 166. The region where the first semiconductor layer 156 is located is subsequently used to form the gate structure in the sub-transistor structure and the sub-lower electrode layer, capacitor dielectric layer and upper electrode layer in the sub-capacitor structure. The second semiconductor layer 166 is subsequently used to form a semiconductor channel.

[0089] Understandably, the top view of the fourth mask layer 189 is also as follows. Figure 6 As shown, the fifth opening 179 is as follows Figure 6 The spacing between the first stacked structure 116 and the second stacked structure 126 is shown.

[0090] in, Figure 7 for Figure 6 The diagram shows a partial cross-sectional view of the semiconductor structure along the first cross-sectional direction AA1 and the second cross-sectional direction BB1. It should be noted that... Figure 6The diagram only shows 6 first stacked structures 116 and 6 second stacked structures. In practical applications, the number of first stacked structures 116 and second stacked structures 126 can be reasonably designed according to the final requirements of the transistor structure. Figure 5 and Figure 7 This example only uses the first semiconductor layer 156 and the second semiconductor layer 166, both comprising three layers, in the first stacked structure 116 and the second stacked structure 126. In practical applications, the number of layers in the first semiconductor layer 156 and the second semiconductor layer 166 can be reasonably designed according to the final requirements of the transistor structure; subsequent... Figures 8 to 16 All are in Figure 6 and Figure 7 Further manufacturing processes are carried out based on this.

[0091] refer to Figure 8 A first sacrificial layer 117 is formed, which fills the first gap 108 between the first stacked structure 116 and the second stacked structure 126 (see reference). Figure 6 As described above, along the third direction Z, both the first stacked structure 116 and the second stacked structure 126 may include alternating stacked first semiconductor layer 156 and second semiconductor layer 166, and the third direction Z, the second direction Y and the first direction X intersect each other.

[0092] Continue to refer to Figure 8 A first mask layer 119 is formed having a first opening 109 extending along the second direction Y, and the first opening 109 exposes a portion of the first sacrificial layer 117. It is understood that the first opening 109 and the first spacing 108 (see reference) are... Figure 6 The area extending along the second direction Y is directly opposite, and along the second direction Y, the first opening 109 exposes a portion of the multiple first stacked structures 116.

[0093] Reference Figure 8 and Figure 9 Using the first mask layer 119 as a mask, the first sacrificial layer 117 exposed by the first opening 109 and the first semiconductor layer 156 opposite to the first opening 109 are etched to form the first hole 118. It is understood that the material of the first semiconductor layer 156 is different from the material of the second semiconductor layer 166. Therefore, the materials of the first sacrificial layer 117 and the first semiconductor layer 156 can be removed by the same etching process. However, this etching process will not remove the second semiconductor layer 166. Therefore, after etching the first sacrificial layer 117 exposed by the first opening 109, a portion of the first semiconductor layer 156 opposite to the first opening 109 is exposed. This portion of the first semiconductor layer 156 can then be removed to form the first hole 118. The first hole 118 exposes the sidewall of the third region 143 opposite to the first opening 109.

[0094] refer to Figure 10 This forms the first support layer 114, which fills the first cavity 118.

[0095] In some embodiments, reference Figures 8 to 10 The second semiconductor layer 166 in the first stacked structure 116 is a semiconductor channel 113, which extends along the first direction X. The semiconductor channel 113 includes a first region 123, a second region 133, and a third region 143 (see reference). Figure 4 The support structure 104 also includes a second support layer 124 and a third support layer 134.

[0096] refer to Figure 8 The step of forming the first mask layer 119 may further include: forming a first mask layer 119 having a second opening 129 and a third opening 139, wherein the second opening 129 extends along the second direction Y and exposes the second region 133 and the first sacrificial layer 117 in contact with the second region 133, and the third opening 139 extends along the second direction Y and exposes a portion of the first sacrificial layer 117 between adjacent first stacked structures 116.

[0097] In the second stacked structure 126, the second semiconductor layer 166 can serve as the support layer 153 in the subsequent stepped structure, and the second opening 129 exposes part of the support layer 153.

[0098] refer to Figures 9 to 10 The formation of the second support layer 124 includes the following steps:

[0099] refer to Figure 9 Using the first mask layer 119 as a mask, the first sacrificial layer 117 exposed by the second opening 129 and the first semiconductor layer 156 opposite to the second opening 129 are etched to form the second hole 128. It can be understood that after etching the first sacrificial layer 117 exposed by the second opening 129, the etching process can expose a portion of the first semiconductor layer 156 opposite to the second opening 129, and then further remove this portion of the first semiconductor layer 156 to form the second hole 128. The second hole 128 exposes the sidewall of the second region 133 opposite to the second opening 129.

[0100] refer to Figure 10 This forms a second support layer 124 that fills the second cavity 128.

[0101] refer to Figures 9 to 10 The formation of the third support layer 134 includes the following steps:

[0102] refer to Figure 9Using the first mask layer 119 as a mask, the first sacrificial layer 117 exposed by the third opening 139 and the first semiconductor layer 156 facing the third opening 139 are etched to form the third hole 138. It can be understood that after etching the first sacrificial layer 117 exposed by the third opening 139, the etching process can expose a portion of the first semiconductor layer 156 facing the third opening 139, and then further remove this portion of the first semiconductor layer 156 to form the third hole 138. The third hole 138 exposes the sidewall of the third region 143 facing the third opening 139.

[0103] refer to Figure 10 This forms a third support layer 134 that fills the third cavity 138.

[0104] It is understandable that the formation of the first cavity 118, the second cavity 128 and the third cavity 138 can be carried out simultaneously, as can the formation of the first scaffold layer 114, the second scaffold layer 124 and the third scaffold layer 134, in order to simplify the process steps for preparing the scaffold structure 104.

[0105] In some embodiments, forming the transistor structure 100 may include the following steps:

[0106] Reference Figure 10 and Figure 11 Using the second semiconductor layer 166 and the support structure 104 as a mask, the remaining first semiconductor layer 156 and the first sacrificial layer 117 are removed to form the fourth hole 148. It is understood that in this step, the support structure 194 surrounds a portion of the sidewalls of the second semiconductor layer 166, so the second semiconductor layer 166 will not collapse when the first semiconductor layer 156 and the first sacrificial layer 117 are removed.

[0107] refer to Figure 12 This forms the second sacrificial layer 127, which fills the fourth cavity 148.

[0108] refer to Figure 13 A second mask layer 149 is formed, which is located on the third region 143 of the semiconductor channel 113 and is used to protect the second sacrificial layer 127 opposite to the third region 143 from being etched. Using the second mask layer 149 as a mask, the second sacrificial layer 127 in contact with the first region 123 of the semiconductor channel 113 and the second sacrificial layer 127 in contact with the second stacked structure 126 are removed.

[0109] refer to Figure 14 A gate structure 120 and a conductive layer 122 are formed. The gate structure 120 surrounds the sidewall of the first region 123 of the semiconductor channel 113, and the conductive layer 122 surrounds the second stacked structure 126 (see reference). Figure 8The second semiconductor layer 166 in the transistor structure 100 includes a gate structure 120 and a first region 123. The conductive layer 122 and the second semiconductor layer 166 in the second stacked structure 126 constitute an initial word line ladder structure 142.

[0110] A dielectric layer 132 is further provided between the conductive layer 122 and the second semiconductor layer 166 in the second stacked structure 126. The second semiconductor layer 166 in the second stacked structure 126 serves as a support layer 153. The dielectric layer 132 and the gate dielectric layer 130 are integrally formed, and the conductive layer 122 and the gate conductive layer 140 are integrally formed. The steps of forming the gate structure 120, the conductive layer 122, and the dielectric layer 132 include: forming the conductive layer 122 and the gate conductive layer 140, and conformally covering the conductive layer 122 and the gate conductive layer 140. Figure 13 The second semiconductor layer 166 exposes a sidewall extending along the first direction X; a dielectric layer 132 and a gate dielectric layer 130 are formed, and the dielectric layer 132 and the gate dielectric layer 130 conformally cover the sidewalls of the conductive layer 122 and the gate conductive layer 140 extending along the first direction X.

[0111] In this structure, the semiconductor channel 113 and gate structure 120 of the first region 123 constitute a sub-transistor structure 110, and the second semiconductor layer 166, dielectric layer 132 and conductive layer 122 in the second stacked structure 126 constitute an initial word line ladder structure 142. Multiple sub-transistor structures 110 arranged along the third direction Z constitute a transistor structure 100.

[0112] In some embodiments, continue to refer to Figure 14 Along the third direction Z, there is a second spacing 158 between the gate structures 120 surrounding the sidewalls of different first regions 123, and a third spacing 168 between the conductive layers 122 surrounding the sidewalls of the first semiconductor layer 136 in different second stacked structures 126; the manufacturing method further includes: forming a first dielectric layer 107, the first dielectric layer 107 filling the second spacing 158 and the third spacing 168.

[0113] In some embodiments, reference Figure 15 The step of forming capacitor structure 101 may include: forming a third mask layer 169 having a fourth opening 159, the fourth opening 159 being located in the third region 143 of semiconductor channel 113 (see reference). Figure 13 On top of the structure, to protect the sub-transistor structure 110 and the step structure 112.

[0114] Continue to refer to Figure 15 Using the third mask layer 169 as a mask, the material in the third region 143 (reference) is removed. Figure 9 The second sacrificial layer 127 is in contact with the first sacrificial layer to form the fifth cavity 178.

[0115] It should be noted that, since the first dielectric layer 107 is located on the top surface of the third region 143 when the first dielectric layer 107 is formed, the first dielectric layer 107 located on the top surface of the third region 143 is removed at the same time as the second sacrificial layer 127 is removed, so as to expose all the sidewalls of the third region 143 extending along the first direction X.

[0116] Reference Figure 15 and Figure 16 A sub-lower electrode layer 151 is formed, which surrounds the sidewall of the semiconductor channel 113 exposed by the fifth hole 178; a capacitor dielectric layer 131 is formed, which surrounds the sidewall of the sub-lower electrode layer 151 away from the semiconductor channel 113; and an upper electrode layer 141 is formed, which fills the remaining fifth hole 178. The semiconductor channel 113 and the sub-lower electrode layer 151 in the third region 143 constitute the lower electrode layer 121, and the lower electrode layer 121, the capacitor dielectric layer 131, and the upper electrode layer 141 constitute the capacitor structure 101.

[0117] It is understandable that, for a certain third region 143, the third region 143 and the sub-lower electrode layer 151, capacitor dielectric layer 131 and upper electrode layer 141 that surround the sidewall of the third region 143 in sequence constitute a sub-capacitor structure 111, and multiple sub-capacitor structures are arranged along the third direction Z (reference). Figure 1 The sub-capacitor structures 111 arranged together constitute capacitor structure 101.

[0118] It should be noted that, in the steps of forming the lower sub-electrode layer 151, the capacitor dielectric layer 131, and the upper electrode layer 141, the lower sub-electrode layer 151, the capacitor dielectric layer 131, and the upper electrode layer 141 may also cover the top surface of the remaining first ring layer 107, which will be subsequently planarized to form... Figure 16 The capacitor structure 101 shown is shown.

[0119] In some embodiments, the step of forming the upper electrode layer 141 may include: forming a diffusion barrier layer (not shown) and a sub-upper electrode layer (not shown) stacked sequentially, wherein the diffusion barrier layer surrounds a sidewall of the capacitor dielectric layer 131 that is away from the sub-lower electrode layer 151 and extends along a first direction X; and the sub-upper electrode layer surrounds a sidewall of the diffusion barrier layer that is away from the capacitor dielectric layer 131 and extends along a first direction X.

[0120] In some embodiments, in conjunction with reference Figure 16 and Figure 3The step of forming word line staircase structure 102 may include: performing local etching on the initial word line staircase structure 142 and the first semiconductor layer 136 in the second stacked structure 126 multiple times to form word line staircase structure 102. Word line staircase structure 102 includes multiple step structures 112 arranged at intervals along the third direction Z, and the multiple step structures 112 have different lengths in the first direction X.

[0121] It is understood that the dielectric layer 132 in the word line staircase structure 102 and the gate dielectric layer 130 in the transistor structure 100 are formed using the same fabrication step, and the conductive layer 122 in the word line staircase structure 102 and the gate conductive layer 140 in the transistor structure 100 are formed using the same fabrication step.

[0122] It should be noted that the manufacturing method for forming multiple step structures 112 with different lengths in the first direction X is not limited in the embodiments of this disclosure, and can form such... Figure 3 The character line ladder structure 102 shown is sufficient.

[0123] In some embodiments, reference Figure 3 The manufacturing method may further include: forming a plurality of first conductive posts 115 extending along a third direction Z, wherein each first conductive post 115 corresponds to a step structure 112 and the first conductive post 115 is in contact with the step structure 112; and forming a plurality of second conductive posts 125 extending along a third direction Z, wherein the second conductive posts 125 are in contact with the capacitor structure 101.

[0124] In summary, in the semiconductor structure formed by the above manufacturing method, along the first direction X, the transistor structure 100 is adjacent to the capacitor structure 101, and along the second direction Y, the transistor structure 100 is adjacent to the word line ladder structure 102. This facilitates electrical connection between the transistor structure 100 and the word line ladder structure 102 while reducing the overall layout length of the transistor structure 100, capacitor structure 101, and word line ladder structure 102 along the first direction X. Furthermore, the portion of the word line ladder structure 102 extending along the first direction X directly faces the capacitor structure 101. This allows for a reduction in the layout length of the word line ladder structure 102 along the second direction Y while maximizing its placement along the first direction X. This increases the length of the area directly facing the word line ladder structure 102 and the capacitor structure 101, achieving efficient use of layout space and reducing the overall layout area of ​​the semiconductor structure, thereby increasing the integration density of the transistor structure 100 and the capacitor structure 101 in the semiconductor structure.

[0125] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: A transistor structure and a capacitor structure arranged along a first direction, wherein the capacitor structure extends along the first direction; A word line ladder structure is arranged at intervals with the transistor structure along a second direction, and the word line ladder structure extends along a first direction, the first direction intersects the second direction, and the word line ladder structure and the transistor structure are electrically connected; Wherein, with a plane perpendicular to the second direction as the reference plane, the orthographic projection of the transistor structure on the reference plane is the first projection, the orthographic projection of the capacitor structure on the reference plane is the second projection, and the orthographic projection of the word line staircase structure on the reference plane is the third projection. The third projection covers the first projection, and the third projection partially overlaps with the second projection. The transistor structure, the capacitor structure, and the word line ladder structure constitute a memory structure. Two adjacent memory structures along the first direction are centrally symmetrical, and the word line ladder structure of one memory structure and the capacitor structure of the other are arranged at intervals along the first direction.

2. The semiconductor structure of claim 1, wherein, The transistor structure includes multiple sub-transistor structures spaced apart along a third direction, and the third direction, the second direction, and the first direction intersect each other in pairs; The capacitor structure includes multiple sub-capacitor structures arranged along a third direction, and each sub-capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer stacked sequentially. The letter line staircase structure includes multiple step structures arranged at intervals along the third direction, the step structures extending along the first direction, and the multiple step structures having different lengths in the first direction; The sub-transistor structure is connected to the sub-capacitor structure in a one-to-one correspondence, and the sub-transistor structure is connected to the step structure in a one-to-one correspondence.

3. The semiconductor structure of claim 2, wherein, Also includes: A support structure is located between adjacent sub-capacitor structures in the capacitor structure, and the support structure surrounds a portion of the sidewall of the sub-capacitor structure extending in the first direction to support the capacitor structure.

4. The semiconductor structure as described in claim 2, characterized in that, The transistor structure, the capacitor structure, and the word line ladder structure constitute a memory structure, and the memory structure is arranged at intervals along the first direction and the second direction. The semiconductor structure further includes a support structure shared by the plurality of memory structures, the support structure extending along the second direction and surrounding the capacitor structure located in the plurality of memory structures arranged in the second direction.

5. The semiconductor structure of claim 4, wherein, A first interval exists between the stepped structure of one of two adjacent storage structures along the first direction and the capacitor structure of the other. The support structure includes: a first support layer, the first support layer extending along the second direction and surrounding a portion of the sidewall of the lower electrode layer extending along the first direction, the first support layer being located in the first interval.

6. The semiconductor structure of claim 5, wherein, The sub-transistor structure includes: a portion of a semiconductor channel extending along the first direction, and a gate structure surrounding a sidewall extending along the first direction of the semiconductor channel; the lower electrode layer includes a portion of the semiconductor channel extending along the first direction. The support structure further includes: a second support layer, which extends along the second direction and surrounds a portion of the sidewall of the semiconductor channel, the second support layer being located between the gate structure and the capacitor structure and between adjacent step structures; and a third support layer, which extends along the second direction and surrounds a portion of the sidewall of the semiconductor channel in the lower electrode layer, the third support layer being located on the side of the first support layer away from the second support layer.

7. The semiconductor structure of claim 6, wherein, Along the first direction, the semiconductor channel includes a first region, a second region, and a third region. The gate structure surrounds the sidewall of the first region, the second support layer surrounds the sidewall of the second region, the lower electrode layer includes the third region and a sub-lower electrode layer surrounding a portion of the sidewall of the third region, and the first support layer and the third support layer surround the remaining sidewall of the third region.

8. The semiconductor structure as described in claim 2, characterized in that, Also includes: Multiple first conductive posts extending along the third direction, each first conductive post corresponding to a step structure, and the first conductive post being in contact with the step structure; Multiple second conductive pillars extending along the third direction are in contact with the upper electrode layer.

9. A method of manufacturing a semiconductor structure, characterized by, include: A transistor structure and a capacitor structure are formed along a first direction, wherein the capacitor structure extends along the first direction; A word line ladder structure is formed, wherein the word line ladder structure and the transistor structure are arranged at intervals along the second direction, and the word line ladder structure extends along the first direction, the first direction intersects the second direction, and the word line ladder structure and the transistor structure are electrically connected. Wherein, with a plane perpendicular to the second direction as the reference plane, the orthographic projection of the transistor structure on the reference plane is the first projection, the orthographic projection of the capacitor structure on the reference plane is the second projection, and the orthographic projection of the word line staircase structure on the reference plane is the third projection. The third projection covers the first projection, and the third projection partially overlaps with the second projection. The transistor structure, the capacitor structure, and the word line ladder structure constitute a memory structure. Two adjacent memory structures along the first direction are centrally symmetrical, and the word line ladder structure of one memory structure and the capacitor structure of the other are arranged at intervals along the first direction.

10. The production method according to claim 9, wherein The word line ladder structure and the transistor structure are formed using the same fabrication steps.

11. The production method according to claim 9 or 10, wherein The capacitor structure includes multiple sub-capacitor structures arranged along a third direction. The manufacturing method further includes: forming a support structure, the support structure being located between adjacent sub-capacitor structures in the capacitor structure, and the support structure surrounding a portion of the sidewall of the sub-capacitor structure to support the capacitor structure.

12. The production method according to claim 11, wherein The support structure includes a first support layer, and the steps for forming the first support layer include: A first stack structure and a second stack structure are formed that are spaced apart and staggered along the first direction, and the first stack structure and the second stack structure are spaced apart and staggered along the second direction; A first sacrificial layer is formed, which fills the first gap between the first stacked structure and the second stacked structure; Along the third direction, both the first stacked structure and the second stacked structure include alternating stacked first semiconductor layers and second semiconductor layers, and the third direction and the second direction intersect the first direction in pairs; A first mask layer is formed having a first opening extending along the second direction, and the first opening exposes a portion of the first sacrificial layer. Using the first mask layer as a mask, the first sacrificial layer exposed by the first opening and the first semiconductor layer opposite to the first opening are etched to form a first hole; A first scaffold layer is formed, and the first scaffold layer fills the first cavity.

13. The production method according to claim 12, wherein The steps for forming the first stacked structure and the second stacked structure include: An initial first semiconductor layer and an initial second semiconductor layer are formed, stacked sequentially upwards along the third party; The initial first semiconductor layer and the initial second semiconductor layer are graphically represented to form the first stacked structure and the second stacked structure.

14. The manufacturing method as described in claim 12, characterized in that, The second semiconductor layer in the first stacked structure is a semiconductor channel, and along the first direction, the semiconductor channel includes a first region, a second region, and a third region; the support structure also includes a second support layer and a third support layer; The step of forming the first mask layer further includes: forming the first mask layer having a second opening and a third opening, wherein the second opening extends along the second direction and exposes the second region and the first sacrificial layer in contact with the second region, and the third opening extends along the second direction and exposes a portion of the first sacrificial layer between adjacent first stacked structures; The step of forming the second support layer includes: using the first mask layer as a mask, etching the first sacrificial layer exposed by the second opening and the first semiconductor layer facing the second opening to form a second hole; forming a second support layer that fills the second hole; The step of forming the third support layer includes: using the first mask layer as a mask, etching the first sacrificial layer exposed by the third opening and the first semiconductor layer opposite to the third opening to form a third hole; and forming the third support layer that fills the third hole.

15. The manufacturing method as described in claim 14, characterized in that, The steps for forming the transistor structure include: Using the second semiconductor layer and the support structure as a mask, the remaining first semiconductor layer and the first sacrificial layer are removed to form a fourth hole; A second sacrificial layer is formed to fill the fourth cavity; A second mask layer is formed, the second mask layer being located on the third region of the semiconductor channel; Using the second mask layer as a mask, the second sacrificial layer that is in contact with the first region of the semiconductor channel and the second sacrificial layer that is in contact with the second stacked structure are removed. A gate structure and a conductive layer are formed, the gate structure surrounding the sidewall of the first region of the semiconductor channel, the conductive layer surrounding the sidewall of the second semiconductor layer in the second stacked structure, the transistor structure including the gate structure and the first region, the conductive layer and the second semiconductor layer in the second stacked structure forming an initial word line ladder structure.

16. The production method according to claim 15, wherein Along the third direction upward, the gate structures surrounding different sidewalls of the first region have a second spacing, and the conductive layers surrounding the sidewalls of the first semiconductor layer in different second stacked structures have a third spacing; the manufacturing method further includes: A first dielectric layer is formed, which fills the second and third spacers.

17. The production method according to claim 15, wherein The steps for forming the capacitor structure include: A third mask layer is formed having a fourth opening located on the third region of the semiconductor channel; Using the third mask layer as a mask, the second sacrificial layer in contact with the third region is removed to form a fifth cavity; A sub-lower electrode layer is formed, the sub-lower electrode layer surrounding the semiconductor channel sidewall exposed by the fifth hole; A capacitor dielectric layer is formed, which surrounds the sidewall of the sub-lower electrode layer away from the semiconductor channel; An upper electrode layer is formed, which fills the remaining fifth cavity; The semiconductor channel and the sub-lower electrode layer in the third region constitute the lower electrode layer, and the lower electrode layer, the capacitor dielectric layer, and the upper electrode layer constitute the capacitor structure.

18. The production method according to claim 15, wherein The step of forming the word line staircase structure includes: performing local etching on the initial word line staircase structure and the first semiconductor layer in the second stacked structure multiple times to form the word line staircase structure, wherein the word line staircase structure includes multiple step structures arranged at intervals along the third direction, and the multiple step structures have different lengths along the first direction.

19. The production method according to claim 18, wherein Also includes: Multiple first conductive posts are formed extending along the third direction, each of the first conductive posts corresponding to one of the step structures, and the first conductive posts are in contact with the step structures. Multiple second conductive pillars are formed extending along the third direction, and the second conductive pillars are in contact with the capacitor structure.

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