Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device, comprising: a semiconductor substrate, a capacitor contact part is formed on the semiconductor substrate; a capacitor bottom electrode is formed above the capacitor contact part and is connected with the capacitor contact part; wherein the capacitor bottom electrode comprises a first bottom electrode layer and a second bottom electrode layer which are connected with each other, the first bottom electrode layer comprises a first cylindrical sidewall and a bottom wall, the inner diameter of the first cylindrical sidewall gradually decreases from top to bottom, and the bottom wall contacts the capacitor contact part; and the second bottom electrode layer comprises a second cylindrical sidewall, the second cylindrical sidewall extends upwards from a certain height on the inner side of the first cylindrical sidewall until the height of the second cylindrical sidewall is the same as that of the first cylindrical sidewall. The application can increase the surface area of the bottom electrode plate of the capacitor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] As DRAM device manufacturing processes continue to advance, device dimensions are becoming increasingly smaller. To ensure sufficiently large capacitance in DRAM devices, a common method is to increase the height of the capacitor plates. However, increasing the height of the capacitor plates increases the risk of plate collapse. Therefore, how to maintain capacitor capacitance while keeping plate height relatively low has become a pressing problem to solve. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a semiconductor device and its manufacturing method, which can increase the surface area of ​​the bottom electrode plate of a capacitor.

[0004] In a first aspect, the present invention provides a semiconductor device, comprising:

[0005] A semiconductor substrate, wherein a capacitor contact is formed on the semiconductor substrate;

[0006] The bottom electrode of the capacitor is formed above the capacitor contact portion and connected to the capacitor contact portion;

[0007] The capacitor bottom electrode includes a first bottom electrode layer and a second bottom electrode layer connected to each other. The first bottom electrode layer includes a first cylindrical sidewall and a bottom wall. The inner diameter of the first cylindrical sidewall gradually decreases from top to bottom. The bottom wall contacts the capacitor contact portion. The second bottom electrode layer includes a second cylindrical sidewall. The second cylindrical sidewall extends upward from a certain height inside the first cylindrical sidewall until it is the same height as the first cylindrical sidewall.

[0008] Optionally, the semiconductor substrate includes an etch stop layer, and the bottom of the first cylindrical shape passes through the etch stop layer and connects to the capacitor contact.

[0009] Optionally, the material of the etching termination layer is silicon nitride.

[0010] Optionally, the bottom electrode material of the capacitor is a TiN thin film or a TaN thin film.

[0011] Optionally, it further includes: a capacitor dielectric layer and a top electrode layer on the bottom electrode of the capacitor.

[0012] Optionally, the semiconductor device is DRAM;

[0013] The semiconductor substrate further includes buried channel transistors, bit lines, and memory node contacts;

[0014] The capacitor contact is electrically connected to the storage node contact.

[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0016] A semiconductor substrate is provided, on which a capacitor contact is formed, and an etch stop layer and a first dielectric layer are deposited sequentially.

[0017] An opening is formed in the first dielectric layer and the etching stop layer by photolithography and etching processes to expose the capacitor contact portion, wherein the inner diameter of the opening gradually decreases from top to bottom;

[0018] A first bottom electrode layer is formed, which covers the sidewalls and bottom of the opening and the upper surface of the first dielectric layer;

[0019] Remove the first bottom electrode layer outside the opening, leaving only the first bottom electrode layer inside the opening;

[0020] A second dielectric layer is formed, which covers the upper surface of the first dielectric layer and simultaneously covers the upper parts of the two sidewalls of the retained first bottom electrode layer at intervals.

[0021] A second bottom electrode layer is formed around the upper surface and sidewalls of the second dielectric layer, and the second bottom electrode layer is connected to the first bottom electrode layer retained in the opening;

[0022] Remove the second bottom electrode layer outside the opening, leaving only the second bottom electrode layer inside the opening;

[0023] Remove the remaining second dielectric layer and first dielectric layer.

[0024] Optionally, the material of the second dielectric layer is one of carbon thin film, BPSG, and PSG.

[0025] Optionally, forming the second dielectric layer includes:

[0026] A second dielectric layer material is deposited, which covers the upper surface of the first dielectric layer and fills the top of the opening;

[0027] The second dielectric layer material is etched vertically downwards, causing the second dielectric layer material filling the top of the opening to separate into two parts.

[0028] Optionally, the second dielectric layer material is vertically etched downwards using a dry etching process.

[0029] The semiconductor device provided by the present invention includes a first bottom electrode layer and a second bottom electrode layer as the bottom electrode, forming a branch structure. A gap is formed between the cylindrical sidewall of the first bottom electrode layer and the cylindrical sidewall of the second bottom electrode layer. This structure can increase the surface area of ​​the bottom electrode of the capacitor, thereby reducing the height of the capacitor. Attached Figure Description

[0030] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present invention;

[0031] Figures 2-9 This is a schematic cross-sectional view of each step in the manufacturing method of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0036] This invention provides a semiconductor device, such as... Figure 1As shown, the semiconductor device includes a semiconductor substrate 100, typically a silicon substrate, on which a capacitor contact portion 101 is formed. A capacitor bottom electrode 102 is formed above the capacitor contact portion 101. The material of the capacitor bottom electrode 102 can be a TiN thin film or a TaN thin film. The capacitor bottom electrode 102 is connected to the capacitor contact portion 101. The capacitor bottom electrode 102 includes a first bottom electrode layer 1021 and a second bottom electrode layer 1022. The first bottom electrode layer 1021 and the second bottom electrode layer 1022 are interconnected. Both the first bottom electrode layer 1021 and the second bottom electrode layer 1022 have a cylindrical structure. The second bottom electrode layer 1022 is stacked on top of the first bottom electrode layer 1021.

[0037] Specifically, the first bottom electrode layer 1021 includes a cylindrical sidewall (denoted as the first cylindrical sidewall) and a bottom wall. The inner diameter of the first cylindrical sidewall gradually decreases from top to bottom, and the bottom wall is horizontal and has contact with the capacitor contact portion. The second bottom electrode layer 1022 includes a cylindrical sidewall (denoted as the second cylindrical sidewall). The inner diameter of the second cylindrical sidewall gradually increases from top to bottom. The second cylindrical sidewall extends upward from a certain height inside the first cylindrical sidewall until it reaches the same height as the first cylindrical sidewall. The semiconductor substrate 100 also includes an etch stop layer 103. The bottom of the first cylindrical sidewall passes through the etch stop layer 103 and connects to the capacitor contact portion. The material of the etch stop layer 103 is typically silicon nitride (SiN).

[0038] In one implementation, the semiconductor device in this embodiment is a DRAM. The semiconductor substrate may further include buried channel transistors, bit lines, and memory node contacts; the capacitor contacts are electrically connected to the memory node contacts. A capacitor dielectric layer and a top electrode layer are also included on the bottom electrode of the capacitor.

[0039] The semiconductor device provided in this embodiment includes a first bottom electrode layer and a second bottom electrode layer as the bottom electrode, forming a branch structure. A gap is formed between the cylindrical sidewall of the first bottom electrode layer and the cylindrical sidewall of the second bottom electrode layer. This structure can increase the surface area of ​​the bottom electrode of the capacitor, thereby reducing the height of the capacitor.

[0040] Another embodiment of the present invention provides a manufacturing method for manufacturing the semiconductor device described in the above embodiments. Figures 2-9 The diagram shows a cross-sectional view of the device in each step of the manufacturing process.

[0041] First, such as Figure 2As shown, a semiconductor substrate 200 is provided, on which a capacitor contact 201 is formed. An etch stop layer 202 and a first dielectric layer 203 are sequentially deposited on the semiconductor substrate. The etch stop layer 202 can be silicon nitride, and the first dielectric layer 203 can be made of boron phosphosilicate glass (BPSG) with a thickness of 2.2 μm. The first dielectric layer 203 can be formed by atmospheric pressure chemical vapor deposition or a similar method, and then subjected to chemical mechanical polishing to obtain a smooth surface.

[0042] Then, as Figure 3 As shown, an opening 300 is formed in the first dielectric layer 203 and the etching stop layer 202 through photolithography and etching processes to expose the capacitor contact 201. The inner diameter of the opening 300 gradually decreases from top to bottom. The specific process is as follows: a layer of photoresist is coated, exposed and developed to obtain a photoresist pattern, and dry etching is performed using the photoresist pattern as a mask to form the opening 300 until the capacitor contact 201 is exposed. The specific conditions for dry etching are: reactive ion etching, power supply 1500W, pressure 20mTorr, wafer temperature 20℃, and the reactive gas includes a mixture of C4F6, CHF3, O2, and Ar. Finally, the photoresist is removed.

[0043] Then, as Figure 4 As shown, a first bottom electrode layer 204 is formed, which covers the sidewalls and bottom of the opening 300 and the upper surface of the first dielectric layer 203.

[0044] Then, as Figure 5 As shown, the first bottom electrode layer located outside the opening 300 is removed, leaving only the first bottom electrode layer inside the opening 300. The remaining first bottom electrode layer is connected to the capacitor contact portion 201.

[0045] Then, a second dielectric layer 205 is formed, which covers the upper surface of the first dielectric layer 203 and also covers the upper parts of the sidewalls of the retained first bottom electrode layer 204 at intervals. The material of the second dielectric layer 205 can be carbon thin film, BPSG, PSG, etc. The specific formation method is as follows: Figure 6 As shown, for example, a carbon thin film 205 is formed by plasma chemical vapor deposition (plasma CVD). The formed carbon thin film 205 covers the upper surface of the first dielectric layer 203 and fills the top of the opening 300. During the formation of the carbon thin film 205, the area below the opening 300 is not filled. Then, as... Figure 7As shown, the carbon thin film 205 is etched vertically downwards. In this embodiment, dry etching is used to remove the middle portion of the carbon thin film 205 filling the top of the opening, thus separating the carbon thin films on both sides from each other. The remaining carbon thin film then forms the second dielectric layer. (Reference) Figure 7 Using the obtained second dielectric layer 205 as a mold, a second bottom electrode layer 206 is formed around the upper surface and sidewalls of the second dielectric layer 205. The second bottom electrode layer 206 is connected to the first bottom electrode layer 204 retained in the opening 300. It can be seen that the function of the second dielectric layer 205 is to provide a mold for the preparation of the second bottom electrode layer 206.

[0046] Then, the second bottom electrode layer 206 is etched to remove the second bottom electrode layer located outside the opening 300, leaving only the second bottom electrode layer inside the opening 300. The etched structure is as follows. Figure 8 As shown.

[0047] Then, dry etching is used to remove the remaining second dielectric layer 205 and first dielectric layer 203, yielding the bottom electrode of the capacitor. The etched structure is shown below. Figure 9 As shown, Figure 9 In the final capacitor, the bottom electrode includes a first bottom electrode layer 204 and a second bottom electrode layer 206, forming a branch structure. A gap is formed between the two bottom electrode layers. This structure can increase the surface area of ​​the capacitor bottom electrode, thereby reducing the height of the capacitor.

[0048] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0049] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, on which a capacitor contact is formed, and an etch stop layer and a first dielectric layer are deposited sequentially. An opening is formed in the first dielectric layer and the etching stop layer by photolithography and etching processes to expose the capacitor contact portion, wherein the inner diameter of the opening gradually decreases from top to bottom; A first bottom electrode layer is formed, which covers the sidewalls and bottom of the opening and the upper surface of the first dielectric layer; Remove the first bottom electrode layer outside the opening, leaving only the first bottom electrode layer inside the opening; A second dielectric layer is formed, which covers the upper surface of the first dielectric layer and simultaneously covers the upper parts of the two sidewalls of the retained first bottom electrode layer at intervals. A second bottom electrode layer is formed around the upper surface and sidewalls of the second dielectric layer, and the second bottom electrode layer is connected to the first bottom electrode layer retained in the opening; Remove the second bottom electrode layer outside the opening, leaving only the second bottom electrode layer inside the opening; Remove the remaining second dielectric layer and first dielectric layer.

2. The method according to claim 1, characterized in that, The material of the second dielectric layer is one of carbon thin film, BPSG and PSG.

3. The method according to claim 1, characterized in that, The formation of the second dielectric layer includes: A second dielectric layer material is deposited, which covers the upper surface of the first dielectric layer and fills the top of the opening; The second dielectric layer material is etched vertically downwards, causing the second dielectric layer material filling the top of the opening to separate into two parts.

4. The method according to claim 3, characterized in that, The second dielectric layer material is etched vertically downwards using a dry etching process.

5. A semiconductor device, characterized in that, The semiconductor device is obtained by the method described in any one of claims 1 to 4, comprising: A semiconductor substrate, wherein a capacitor contact is formed on the semiconductor substrate; The bottom electrode of the capacitor is formed above the capacitor contact portion and connected to the capacitor contact portion; The capacitor bottom electrode includes a first bottom electrode layer and a second bottom electrode layer connected to each other. The second bottom electrode layer is stacked on top of the first bottom electrode layer. The first bottom electrode layer includes a first cylindrical sidewall and a bottom wall. The inner diameter of the first cylindrical sidewall gradually decreases from top to bottom. The bottom wall contacts the capacitor contact portion. The second bottom electrode layer includes a second cylindrical sidewall. The inner diameter of the second cylindrical sidewall gradually increases from top to bottom. The second cylindrical sidewall extends upward from a certain height inside the first cylindrical sidewall until it is the same height as the first cylindrical sidewall.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor substrate includes an etch stop layer, and the bottom of the first cylindrical sidewall passes through the etch stop layer and connects to the capacitor contact.

7. The semiconductor device according to claim 6, characterized in that, The material of the etching termination layer is silicon nitride.

8. The semiconductor device according to claim 5, characterized in that, The bottom electrode material of the capacitor is a TiN thin film or a TaN thin film.

9. The semiconductor device according to claim 5, characterized in that, Further includes: The capacitor has a dielectric layer and a top electrode layer on its bottom electrode.

10. The semiconductor device according to any one of claims 5 to 9, characterized in that, The semiconductor device is a DRAM; The semiconductor substrate further includes buried channel transistors, bit lines, and memory node contacts; The capacitor contact is electrically connected to the storage node contact.

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