Display panel and display device

Abstract

The embodiment of the present disclosure provides a display panel and a display device, which relates to the technical field of display, and can improve the under-screen sensing effect. The display panel has a first area including a first display area and a second display area; the first display area includes a first sub-area and a second sub-area. The display panel includes a substrate, a plurality of light emitting devices, a plurality of pixel circuits and a plurality of signal lines. The plurality of light emitting devices includes a first light emitting device located in the first display area and a second light emitting device located in the second display area. The plurality of pixel circuits includes a first pixel circuit coupled with the first light emitting device and located outside the first display area, and a second pixel circuit coupled with the second light emitting device and located in the second display area. The plurality of signal lines provide working signals to the plurality of pixel circuits coupled therewith; at least one signal line in the plurality of signal lines is coupled with at least one first pixel circuit; the orthogonal projection of the at least one signal line on the substrate has an overlap with the second sub-area and no overlap with the first sub-area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the advent of the "full screen" era, high screen-to-body ratio has become a new development trend for electronic devices such as mobile phones and laptops. Screen-to-body ratio refers to the ratio of the screen area of ​​the display to the area of ​​the entire front of the display. The display is designed as a special-shaped display with a groove area (Notch area), such as a bangs screen, a water drop screen, etc. The groove area can be used to accommodate sensors of the display, such as a camera, light sensor, etc., to increase the screen-to-body ratio of the screen. However, the above-mentioned special-shaped display screen is not a true "full screen", and the groove area of ​​the display screen cannot realize display, which reduces the screen-to-body ratio.

[0003] In some related technologies, a sensor is placed under the display screen, for example, a camera is placed under the display screen, so that the area of ​​the display screen above the sensor can realize both sensing function and display, thereby increasing the screen-to-body ratio. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel and a display device, which can improve under-screen sensing effects.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a display panel is provided. The display panel has a first area. The first area includes a first display zone and a second display zone. The first display zone includes a first sub-zone and a second sub-zone. The display panel includes a substrate, a plurality of light-emitting devices, a plurality of pixel circuits, and a plurality of signal lines. The plurality of light-emitting devices are disposed on the substrate. The plurality of light-emitting devices include a first light-emitting device located in the first display zone and a second light-emitting device located in the second display zone. The plurality of pixel circuits are disposed on the substrate. The plurality of pixel circuits include a first pixel circuit coupled to the first light-emitting device and a second pixel circuit coupled to the second light-emitting device. The first pixel circuit is located outside the first display zone; the second pixel circuit is located within the second display zone.

[0007] The plurality of signal lines are disposed on the substrate. The plurality of signal lines are coupled to the plurality of pixel circuits. The plurality of signal lines are configured to provide operating signals to the plurality of pixel circuits. At least one of the plurality of signal lines is coupled to at least one first pixel circuit. An orthographic projection of the at least one signal line on the substrate overlaps with the second sub-region and does not overlap with the first sub-region.

[0008] In some embodiments, the display panel further has a second region and a bending region. The first region and the second region are connected through the bending region. The display panel is configured to bend through a portion located at the bending region, and bend a portion located at the second region to a back of a portion located at the first region.

[0009] At least one first pixel circuit is located in the second region. In a case where a portion located at the second region in the display panel is bent to a back of a portion located at the first region, a projection of the at least one first pixel circuit on the first region in the substrate has no overlap with the first display area.

[0010] In some embodiments, the at least one signal line has at least one opening, and the at least one opening is located in the bending region.

[0011] In some embodiments, the at least one signal line includes a first pattern, a second pattern, and a third pattern. The first pattern is located in the bending region. The second pattern is located in the first region, and the second pattern is coupled with the second pixel circuit and the first pattern. The third pattern is located in the second region, and the third pattern is coupled with the first pixel circuit and the first pattern. A tensile modulus of the first pattern is greater than a tensile modulus of the second pattern and a tensile modulus of the third pattern, respectively.

[0012] In some embodiments, the plurality of signal lines includes a first signal line and a second signal line. The first signal line includes the first pattern, the second pattern, and the third pattern. The first pattern is made of the same material as the second signal line.

[0013] In some embodiments, the display panel further includes a plurality of connection leads. The plurality of connection leads are disposed on the substrate. One first light emitting device is coupled with one first pixel circuit through one connection lead. At least a portion of at least one connection lead located in the first display area is transparent.

[0014] In some embodiments, the at least one connection lead includes a fourth pattern and a fifth pattern. The fourth pattern is located in the first display area, and the fourth pattern is coupled with the first light emitting device. The fifth pattern is located outside the first display area, and the fifth pattern is coupled with the fourth pattern and the first pixel circuit. A tensile modulus of the fifth pattern is greater than a tensile modulus of the fourth pattern.

[0015] In some embodiments, in a case where the at least one signal line includes a second signal line, the fifth pattern is made of the same material as the second signal line.

[0016] In some embodiments, the portion of the display panel located in the second region comprises a transparent portion. The first pixel circuit has no overlap with the transparent portion in the orthographic projection of the first pixel circuit on the substrate. The portion of the display panel located in the second region is bent to the back of the portion of the display panel located in the first region, and the first sub-region is located in the area where the orthographic projection of the transparent portion on the portion of the substrate located in the first region is located.

[0017] In some embodiments, the plurality of light emitting devices further comprises a third light emitting device. The third light emitting device is located on the transparent portion. The plurality of pixel circuits further comprises a third pixel circuit. The third pixel circuit is located in the second region. The third pixel circuit is coupled with the third light emitting device. The third pixel circuit has no overlap with the orthographic projection of the transparent portion on the substrate.

[0018] In the case where the portion of the display panel located in the second region is bent to the back of the portion of the display panel located in the first region, the orthographic projection of the third light emitting device on the portion of the substrate located in the first region is located in the first display area and has no overlap with the orthographic projection of the first light emitting device on the substrate.

[0019] In some embodiments, in the case where the portion of the display panel located in the second region is bent to the back of the portion of the display panel located in the first region, the arrangement of the whole of the first light emitting device and the third light emitting device is the same as the arrangement of the second light emitting device.

[0020] In some embodiments, the display panel further comprises a transparent conductor. The transparent conductor is disposed on the substrate. The third light emitting device is coupled with the third pixel circuit through the transparent conductor.

[0021] In some embodiments, the transparent portion is an opening, and the depth direction of the opening is perpendicular to the plane where the portion of the substrate located in the second region is located.

[0022] In some embodiments, the plurality of pixel circuits located in the second region are arranged in an array, and in the row direction of the pixel circuit arrangement, the plurality of pixel circuits are located on at least one side of the transparent portion.

[0023] In some embodiments, in the column direction of the pixel circuit arrangement, the width of the whole of the plurality of pixel circuits located in the second region is less than or equal to the width of the first display area.

[0024] In some embodiments, the plurality of pixel circuits in the second region are divided into at least two groups. Different groups are arranged along a row direction of the pixel circuits, and each group includes at least one row of pixel circuits. Each row of pixel circuits in the at least two groups corresponds to one row of pixel circuits in the second display area. Each row of pixel circuits in each group and the corresponding row of pixel circuits in the second display area are coupled to at least one same signal line.

[0025] In some embodiments, the display panel further includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer covers the plurality of pixel circuits and the plurality of light emitting devices. The second encapsulation layer is farther away from the substrate than the first encapsulation layer, and the second encapsulation layer covers the second pixel circuit. The third encapsulation layer is between the first encapsulation layer and the second encapsulation layer, and the third encapsulation layer covers the plurality of light emitting devices.

[0026] In some embodiments, in a case where the plurality of light emitting devices include a third light emitting device, the second encapsulation layer further covers the third light emitting device.

[0027] In some embodiments, the display panel further has a bonding area. In a case where the display panel has a second region and a bending region, the bonding area is located on a side of the second region that is farther away from the bending region; or the bonding area is located on a side of the first region that is farther away from the bending region.

[0028] In another aspect, a display device is provided. The display device includes a display panel as described in any of the above embodiments and a sensor. The sensor is disposed on a back surface of a portion of the display panel located in a first display area. A direct projection of the sensor on the display panel is located in a first sub-area in the first display area.

[0029] Therefore, the display panel and the display device provided by the embodiments of the present disclosure set the first pixel circuit coupled with the first light emitting device outside the first display area, so that the first display area has no pixel circuit, so that the light passing through the first display area is not blocked by the pixel circuit, the light transmittance and the aperture ratio of the first display area are improved, and the light transmittance of the first display area is greater than that of the second display area. In this way, the first display area has more space to set the light emitting device, and the PPI of the first display area can be improved, so that the PPI of the first display area is equal to that of the second display area, so that the display effects of the first display area and the second display area are more uniform, and the display effect of the display panel is improved. Moreover, the orthographic projection of the at least one signal line on the substrate overlaps with the second sub-area and does not overlap with the first sub-area, and the signal line also does not block the first sub-area, so that the transmittance of the first sub-area is greater than that of the second sub-area, thereby improving the transmittance of the first sub-area, and the light passing through the first sub-area is not blocked by the signal line, thereby avoiding diffraction of the light. In this case, the sensor (such as a camera or a light sensor) is arranged on the back of the part of the display panel located in the first sub-area, which can better sense the light signal, thereby improving the effect of the display panel in realizing under-screen sensing. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the product involved in the embodiments of the present disclosure.

[0031] FIG. 1A A structural diagram of a display device according to some embodiments;

[0032] FIG. 1B A structural diagram of a display panel according to some embodiments;

[0033] FIG. 2A A flat state diagram of a display panel according to some embodiments;

[0034] FIG. 2B A bending state diagram of a display panel according to some embodiments;

[0035] FIG. 3 Another structural diagram of a display panel according to some embodiments;

[0036] FIG. 4A A structural diagram of a pixel circuit according to some embodiments;

[0037] FIG. 4B is a driving timing diagram of a pixel circuit according to some embodiments;

[0038] FIG. 5 is a structural diagram of a light emitting device according to some embodiments;

[0039] FIG. 6 is another structural diagram of a display panel according to some embodiments;

[0040] FIG. 7 is another structural diagram of a display panel according to some embodiments;

[0041] FIG. 8A is a structural diagram of a signal line according to some embodiments;

[0042] FIG. 8B is another structural diagram of a signal line according to some embodiments;

[0043] FIG. 9A is another structural diagram of a display panel according to some embodiments;

[0044] FIG. 9B for FIG. 9A A cross-sectional view of the display panel along the D-D' direction;

[0045] FIG. 10A is another structural diagram of a display panel according to some embodiments;

[0046] FIG. 10B for FIG. 10A A cross-sectional view of the display panel along the EE' direction;

[0047] FIG. 10C is another structural diagram of a display panel according to some embodiments;

[0048] FIG. 10D is another structural diagram of a display panel according to some embodiments;

[0049] FIG. 11 is another structural diagram of a display panel according to some embodiments;

[0050] FIG. 12A is another structural diagram of a display panel according to some embodiments;

[0051] FIG. 12B is another structural diagram of a display panel according to some embodiments;

[0052] FIG. 13A is another structural diagram of a display panel according to some embodiments;

[0053] FIG. 13B forFIG. 13A FIG. 1 is a structural diagram of a display panel according to some embodiments;

[0054] FIG. 14 FIG. 2 is another structural diagram of a display panel according to some embodiments;

[0055] FIG. 15A FIG. 3 is yet another structural diagram of a display panel according to some embodiments;

[0056] FIG. 15B FIG. 4 is still another structural diagram of a display panel according to some embodiments;

[0057] FIG. 15C FIG. 5 is a connection relationship diagram of a first pixel circuit and a second pixel circuit according to some embodiments;

[0058] FIG. 15D FIG. 6 is a connection relationship diagram of a first pixel circuit and a first light emitting device according to some embodiments;

[0059] FIG. 15E FIG. 7 is another connection relationship diagram of a first pixel circuit and a second pixel circuit according to some embodiments;

[0060] FIG. 16A FIG. 8 is yet another structural diagram of a display panel according to some embodiments;

[0061] FIG. 16B FIG. 9 is still another structural diagram of a display panel according to some embodiments;

[0062] FIG. 16C FIG. 10 is yet another structural diagram of a display panel according to some embodiments;

[0063] FIG. 17A FIG. 11 is still another structural diagram of a display panel according to some embodiments;

[0064] FIG. 17B FIG. 12 is yet another structural diagram of a display panel according to some embodiments;

[0065] FIG. 18 FIG. 13 is another structural diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0067] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an open, inclusive sense, as opposed to a closed or exclusive sense, that is as "including, but not limited to." As used herein in the description of the embodiments of the disclosure, the terms "one embodiment," "some embodiments," "exemplary embodiments," "an example," "a specific example," or "some examples" are not necessarily to be construed as excluding the presence of other embodiments or examples. Also, terms such as "first" and "second" are used herein only to describe one or more features, and do not imply relative importance or a limitation on the number of features. Thus, the features defined with "first" or "second" can include one or more of the features explicitly or implicitly. In the description of embodiments of the disclosure, the meaning of "a plurality" is two or more, unless otherwise specified.

[0068] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" can include one or more of the features explicitly or implicitly. In the description of embodiments of the disclosure, the meaning of "a plurality" is two or more, unless otherwise specified.

[0069] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. For example, the term "connected" can be used to mean that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to mean that two or more components are in direct physical or electrical contact with each other. However, the terms "coupled" or "communicatively coupled" can also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the context.

[0070] The use of "adapted for" or "configured for" herein means open and inclusive language that does not exclude additional tasks or steps.

[0071] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and for purposes of illustration only. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that would be formed by a given manufacturing technique and are intended to be merely an illustration of the regions formed in exemplary embodiments. Thus, exemplary embodiments should not be limited to the precise shapes of regions illustrated herein but are intended to include regions having variations in shapes resulting, for example, from manufacturing.

[0072] Embodiments of the present disclosure provide a display device 200, as shown in FIG. 1A The display device 200 includes a display panel 100 and a sensor 300. The display device 200 can be a display, or a product including a display, such as a television, a computer (all-in-one or desktop), a tablet computer, a mobile phone, an electronic picture screen, and the like. The display panel 100 can be a Light Emitting Diode (LED) display panel, or an Organic Light Emitting Diode (OLED) display panel. The sensor 300 can be an optical sensor, such as a camera or a light sensor, and the like. The camera can be a front camera of the display device.

[0073] It should be noted that the number of sensors can be designed according to actual conditions, which is not limited herein. For example, the sensor can be one or more.

[0074] Embodiments of the present disclosure provide a display panel 100, as shown in FIG. 1B The display panel 100 has a first region A.

[0075] As shown in FIG. 1BAs shown, the first area A includes a first display area A1 and a second display area A2. It should be noted that the number of the first display area, the shape of the first display area and the positional relationship of the second display area can be designed according to actual conditions, and are not limited here. For example, the first display area can be one or more. For example, the second display area A2 can be located on at least one side of the first display area A1, for example, the second display area A2 can surround the first display area A1; or, when the first display area A1 is a quadrilateral, the second display area A2 can be located outside three continuously distributed edges of the first display area A1. For example, the shapes of the first display area A1 and the second display area A2 are both rectangular (or rounded rectangles). In this case, one side edge of the second display area A2 can have a concave portion (the concave direction is the direction in which the edge of the display panel 100 points to the center), and the first display area A1 is located in the concave area. For example, the area of ​​the first display area A1 is less than or equal to the area of ​​the second area A2.

[0076] In related art, pixels are arranged in both the first and second display areas. The pixel arrangement density of the first display area is lower than that of the second display area (i.e., PPI (Pixels Per Inch)), resulting in a lower resolution in the first display area. This can improve the transmittance of the first display area by reducing the pixel arrangement density in the first display area, but this will result in uneven display effects between the first and second display areas of the display panel, thereby reducing the display quality.

[0077] like FIG. 1B As shown, the display panel 100 in the embodiment of the present disclosure includes a substrate 110, a plurality of light-emitting devices 120, a plurality of pixel circuits 130, and a plurality of signal lines 140. The plurality of light-emitting devices 120 and the plurality of pixel circuits 130 are both disposed on the substrate 110. The plurality of signal lines 140 are disposed on the substrate 110. At least one signal line 140 among the plurality of signal lines 140 is coupled to at least one first pixel circuit 131.

[0078] A plurality of signal lines 140 are coupled to the plurality of pixel circuits 130. The plurality of signal lines 140 are configured to provide operating signals to the plurality of pixel circuits 130 so that the plurality of pixel circuits 130 output drive signals. Exemplarily, the plurality of pixel circuits 130 output drive signals in response to the operating signals transmitted on the plurality of signal lines 140 to drive the plurality of light-emitting devices 120 to emit light. For example, the plurality of pixel circuits 130 generate drive signals (such as drive currents) in response to the operating signals transmitted on the plurality of signal lines 140, transmit the drive signals to the plurality of light-emitting devices 120, and drive the plurality of light-emitting devices 120 to emit light. The plurality of signal lines 140 include gate lines and data lines, etc. For example, the material of the plurality of signal lines 140 includes metal.

[0079] Exemplarily, the at least one first pixel circuit and the at least one second pixel circuit can be coupled to the same signal line. For example, in a case where the plurality of light emitting devices in the first region are arranged in an array, the first pixel circuit and the second pixel circuit coupled to the light emitting devices in a row are coupled to one signal line, and the light emitting devices in the row emit light synchronously; and the first pixel circuit and the second pixel circuit coupled to the light emitting devices in a column are coupled to one signal line.

[0080] Exemplarily, the substrate 110 can include a flexible substrate such as a PI (Polyimide) substrate, and can further include a thin film such as a buffer layer disposed on the flexible substrate.

[0081] It should be noted that the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, and the pixel circuit can be designed according to actual conditions. Exemplarily, the pixel circuit is composed of electronic devices such as a TFT (Thin Film Transistor) and a C (Capacitance). For example, the pixel circuit can be a 2T1C structure pixel circuit composed of two TFTs (one switching transistor and one driving transistor) and one C; of course, the pixel circuit can also be a pixel circuit composed of more than two TFTs (a plurality of switching transistors and one driving transistor) and at least one C, for example, refer to FIG. 4A The pixel circuit 130 can include a Cst and a 7T1C pixel circuit composed of seven transistors (six switching transistors (M1, M2, M3, M5, M6, M7) and one driving transistor M4).

[0082] Exemplarily, as shown in FIG. 4A , the control electrode (gate) of a part of the switching transistors (for example, M1, M7) is used to receive a reset signal Reset as shown in FIG. 4B , the control electrode of another part of the switching transistors (for example, M2, M3) is used to receive a gate driving signal Gate as shown in FIG. 4B , and the control electrode of still another part of the switching transistors (for example, M5, M6) is used to receive an emission control signal EM as shown in FIG. 4B , wherein the working process of the pixel circuit as shown in FIG. 4A includes FIG. 4BThe three stages shown are the first stage ①, the second stage ② and the third stage ③. For example, in the first stage ①, in response to the reset signal Reset, the transistor M1 and the transistor M7 are turned on. The initial signal Initial is transmitted to the control electrode (g) of the driving transistor M4 and the anode of the light-emitting device 120 through the transistor M1 and the transistor M7, respectively, to achieve the purpose of resetting the anode of the light-emitting device 120 and the control electrode of the driving transistor M4. In the second stage ②, under the control of the gate drive signal Gate, the transistor M2 is turned on, the control electrode g of the driving transistor M4 is coupled to the drain (d), and the driving transistor M4 is in a diode conduction state. At this time, the data signal Data is written to the source (s) of the driving transistor M4 through the transistor M2, and the threshold voltage (Vth) of the driving transistor M4 is compensated. In the third stage ③, under the control of the light-emitting control signal EM, the transistor M5 and the transistor M6 are turned on, and the current path between the first power supply signal VDD and the second power supply signal VSS is turned on. The driving current (I sd ) is transmitted to the light-emitting device 120 through the above-mentioned current path to drive the light-emitting device 120 to emit light.

[0083] Furthermore, the light emitting device may be a current driven light emitting device such as LED or OLED. FIG. 5 As shown, the light-emitting device 120 includes a cathode 1202 and an anode 1201, and a light-emitting functional layer 1203 located between the cathode 1202 and the anode 1201. The light-emitting functional layer 1203 may include, for example, a light-emitting layer EL, a hole transporting layer (HTL) located between the light-emitting layer EL and the anode 1201, and an electron transporting layer (ETL) located between the light-emitting layer EL and the cathode 1202. Of course, in some embodiments, as needed, a hole injection layer (HIL) may be provided between the hole transporting layer HTL and the anode, and an electron injection layer (EIL) may be provided between the electron transporting layer ETL and the cathode 1202.

[0084] For example, the anode can be formed of a transparent conductive material with a high work function, and its electrode materials may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum zinc oxide (AZO), and carbon nanotubes. The cathode can be formed of a material with high conductivity and low work function, and its electrode materials may include alloys such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl), or single metals such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag). The material of the light-emitting layer can be selected based on the color of the light it emits. For example, the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material. For example, in at least one embodiment of the present disclosure, the light-emitting layer can adopt a doping system, that is, a doping material is mixed into the main light-emitting material to obtain a usable light-emitting material. For example, the main light-emitting material can be a metal compound material, anthracene derivatives, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, biphenylenediamine derivatives, and triarylamine polymers.

[0085] Among them, such as FIG. 1B As shown, the plurality of light-emitting devices 120 include a first light-emitting device 121 and a second light-emitting device 122. The first light-emitting device 121 is located in the first display area A1, and the second light-emitting device 122 is located in the second display area A2. The plurality of pixel circuits 130 include a first pixel circuit 131 and a second pixel circuit 132. The first pixel circuit 131 is coupled to the first light-emitting device 121, and the second pixel circuit 132 is coupled to the second light-emitting device 122. The first pixel circuit 131 is located outside the first display area A1, and the second pixel circuit 132 is located within the second display area A2.

[0086] And, as FIG. 1B As shown, the first display area A1 includes a first sub-area A11 and a second sub-area A12. Exemplarily, the second sub-area A12 is located at least on one side of the first sub-area A11. For example, the second sub-area A12 is located around the first sub-area A11. The orthographic projection of at least one signal line 140 on the substrate 110 overlaps with the second sub-area A12 but does not overlap with the first sub-area A11.

[0087] Exemplarily, the first region further includes a peripheral region outside the first display region and the second display region. The first pixel circuit may be located within the peripheral region. For example, a signal line coupled to a row of second pixel circuits among the plurality of signal lines may have its orthographic projection on the substrate not overlap with the first sub-region, i.e., it bypasses the first sub-region and couples to the first pixel circuit via the second sub-region. A signal line coupled to a column of second pixel circuits among the plurality of signal lines may couple to the first pixel circuit via the second sub-region.

[0088] For example, the driving modes of the first pixel circuit 131 and the second pixel circuit 132 are the same, for example, in the case of pixel circuit array arrangement, the second pixel circuit 132 is driven row by row from the first row to the last row, and the first pixel circuit 131 is also driven row by row from the first row to the last row. For example, the pixel circuits in the first region and the pixel circuits in the second region are driven by the same scan driving circuit (such as a gate driving circuit). In this way, the display algorithm of the display panel can be changed to realize picture display.

[0089] It can be understood that the pixel circuit coupled with the first light emitting device in the first display area is arranged outside the first display area, so that the first display area has no pixel circuit, so that the light passing through the first display area will not be blocked by the pixel circuit, thereby improving the light transmittance and aperture ratio of the first display area, so that the light transmittance of the first display area is greater than that of the second display area. In this way, the first display area has more space to arrange the light emitting device, which can improve the PPI of the first display area, so that the PPI of the first display area is equal to that of the second display area, thereby making the display effect of the first display area and the second display area more uniform, and improving the display effect of the display panel. Moreover, the orthogonal projection of the at least one signal line on the substrate has an overlap with the second sub-area and no overlap with the first sub-area. At this time, the signal line will not block the first sub-area, so that the transmittance of the first sub-area is greater than that of the second sub-area, thereby improving the transmittance of the first sub-area.

[0090] In this way, the sensor (such as a camera or a light sensor) is arranged on the back of the part of the display panel located in the first sub-area, that is, the sensor is arranged on the side away from the display of the display panel, and the orthogonal projection of the sensor on the display panel is located in the first sub-area. Since there is no pixel circuit and signal line in the first sub-area to block the light, the light transmittance is improved, and the light passing through the first sub-area will not be blocked by the signal line, thereby avoiding diffraction of the light. Therefore, the sensor can better sense the light signal, thereby improving the effect of realizing under-screen sensing of the display panel. Moreover, since there is no pixel circuit in the second sub-area, there is sufficient space for wiring in the second sub-area, thereby improving the wiring space.

[0091] It should be noted that the wiring mode of the plurality of signal lines 140 can be designed according to actual conditions, such as the positional relationship between the first sub-area and the second sub-area, without limitation. For example, as shown in FIG. 13B, the second sub-area A12 is located around the first sub-area A11, and the plurality of signal lines 140 can be respectively wired from the opposite two outer sides of the first sub-area A11. FIG. 1B

[0092] ​Therefore, in the display panel provided by the embodiments of the present disclosure, the first pixel circuit coupled to the first light-emitting device is disposed outside the first display area, so that the first display area is free of pixel circuits. This prevents light passing through the first display area from being blocked by the pixel circuits, thereby improving the transmittance and aperture ratio of the first display area and making the transmittance of the first display area greater than that of the second display area. This provides more space for the light-emitting device in the first display area, thereby improving the PPI of the first display area, making the PPI of the first display area equal to that of the second display area. This results in a more uniform display effect between the first and second display areas, thereby improving the display quality of the display panel. Furthermore, the orthographic projection of at least one signal line on the substrate overlaps with the second sub-area but not with the first sub-area. The signal line does not block the first sub-area, resulting in a greater transmittance of the first sub-area than the second sub-area, thereby improving the transmittance of the first sub-area. Light passing through the first sub-area is not blocked by the signal line, thereby preventing light diffraction. In this case, placing a sensor (such as a camera or light sensor) on the back side of the portion of the display panel located in the first sub-area can better sense the light signal, thereby improving the display panel's ability to achieve under-screen sensing.

[0093] In some embodiments, as FIG. 2A and FIG. 2B As shown, the display panel 100 further has a second region B and a bending region F. The bending region F is located between the first region A and the second region B, and the first region A and the second region B are connected via the bending region F. The display panel 100 is configured to bend the portion located in the bending region F, thereby bending the portion located in the second region B to the back of the portion located in the first region A.

[0094] It should be noted that the positions and sizes of the first region A, second region B, and bending region F can be designed based on actual conditions and are not limited here. For example, the area of ​​the first region A can be larger than that of the second region B and also larger than that of the bending region F. The area of ​​the second region B can also be larger than that of the bending region F. For example, the bending region F can be located on one side of the first region A, and the second region B can be located on the side of the bending region F away from the first region A.

[0095] The display panel 100 is a flexible display panel. The back side of the portion of the display panel 100 located in the first area A refers to the side of the portion of the display panel 100 located in the first area A away from the display surface (or light emitting surface) of the display panel 100.

[0096] like FIG. 3As shown, at least one first pixel circuit 131 is located in the second region B. For example, all first pixel circuits 131 are located in the second region B. Furthermore, when the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the orthographic projection of the first pixel circuit 131 on the portion of the substrate 110 located in the first region A does not overlap with the first display area A1.

[0097] In this way, by setting at least one first pixel circuit in the second area, the number of pixel circuits set outside the first display area in the first area and the space they occupy can be reduced, and the size of the peripheral area of ​​the first area can be reduced. Moreover, when multiple sensors are set on the back of the display panel, the area of ​​the second area can be increased to set more pixel circuits. There is no need for a large space in the peripheral area of ​​the first area, and the size of the peripheral area can be reduced. Moreover, the portion of the display panel located in the second area is bent to the back of the portion located in the first area, which does not increase the frame of the display panel. The frame of the display panel can be reduced, making it easier for the display panel to achieve a narrow frame. For example, FIG. 6 As shown, the plurality of signal lines 140 are connected to a row of second pixel circuits 132 (e.g., along FIG. 6 The signal lines 140 coupled to the second pixel circuits 132 (arranged in a row in the X direction) have an orthographic projection on the substrate 110 that does not overlap with the first sub-area A11, that is, bypass the first sub-area A11, extend through the second sub-area A12 and the bending area F to the second area B, and are coupled to the first pixel circuits 131; the signal lines 140 coupled to a column of the second pixel circuits 132 (for example, along the FIG. 6 The signal line 140 coupled to the second pixel circuits arranged in a row in the Y direction can extend through the second sub-area A12 and the bending area F to the second area B and couple to the first pixel circuit 131.

[0098] For example, in the second sub-area A12, the orthographic projection of at least one signal line 140 on the substrate 110 overlaps with the orthographic projection of at least one first light-emitting device 121 on the substrate 110. In this way, the at least one first light-emitting device 121 blocks the at least one signal line 140, thereby increasing the aperture ratio of the first display area A1 and improving the transmittance of the first display area A1.

[0099] It should be noted that the routing of the plurality of signal lines 140 can be designed according to actual conditions, such as the positional relationship between the first sub-area and the second sub-area, and is not limited here. FIG. 7 As shown, the second sub-area A12 is located around the first sub-area A11, and multiple signal lines 140 can be routed from two opposite outer sides of the first sub-area A11. For example, in the second sub-area A12, the distance between at least two adjacent signal lines 140 is smaller than the distance between two adjacent light-emitting devices 120.

[0100] In some embodiments, as shown in FIG. 8A and FIG. 8B At least one signal line 140 has at least one opening 14 located at the bending area F. In this case, the stress on the at least one signal line 140 during bending can be reduced, and the signal line 140 can be prevented from being broken at the bending area F during bending of the display panel 100.

[0101] Exemplarily, as shown in FIG. 8A At the location of the opening 14, the signal line 140 has a first edge M1 and a second edge M2, which are opposite in the width direction (for example, the X direction in FIG. 8A ) of the signal line 140. The first edge M1 and the second edge M2 each have a fold line segment and an arc line segment, and the fold line segment and the arc line segment of each edge are connected to each other and arranged alternately in the extension direction of the signal line 140. For example, the fold line segment of the first edge M1 and the fold line segment of the second edge M2 are arranged in a staggered manner in the width direction of the signal line 140, and the arc line segment of the first edge M1 and the arc line segment of the second edge M2 are arranged in a staggered manner. For example, the fold line segment of the first edge M1 and the arc line segment of the second edge M2 are opposite in the width direction of the signal line 140, and the arc line segment of the first edge M1 and the fold line segment of the second edge M2 are opposite.

[0102] It should be noted that the opening can be designed according to actual conditions, which is not limited herein. The specific number of openings is not limited, for example, the opening can be one, three or five, etc. The arrangement manner of the opening is not limited, for example, as shown in FIG. 8A , a plurality of openings can be arranged in register in the extension direction (for example, along the Y direction) of the signal line 140, that is, the geometric centers of the plurality of openings are sequentially connected to obtain a straight line; or as shown in FIG. 8B , a plurality of openings can be arranged in a staggered manner, that is, the geometric centers of the plurality of openings are sequentially connected to obtain a fold line. The shape of the opening is not limited, for example, the planar shape (for example, the shape of the orthographic projection on the substrate) of the opening can be circular, elliptical or quadrilateral, etc.

[0103] In some embodiments, as shown in FIG. 9A and FIG. 9BAs shown, the at least one signal line 140 includes a first pattern 1401, a second pattern 1402, and a third pattern 1403. The first pattern 1401 is located at the folding region F, the second pattern 1402 is located at the first region A, and the third pattern 1403 is located at the second region B. The second pattern 1402 is coupled with the second pixel circuit 122 and the first pattern 1401, and the third pattern 1403 is coupled with the first pixel circuit 121 and the first pattern 1401.

[0104] The tensile modulus of the first pattern 1401 is greater than the tensile modulus of the second pattern 1402 and the tensile modulus of the third pattern 1403, respectively, the ductility of the first pattern 1401 is greater than the ductility of the second pattern 1402 and the ductility of the third pattern 1403, respectively, and the flexibility of the first pattern 1401 is greater than the flexibility of the second pattern 1402 and the flexibility of the third pattern 1403, respectively. In this case, during the folding of the display panel 100, the signal line 140 can be prevented from breaking at the folding region F, thereby ensuring that the signal line 140 can work normally, prolonging the service life, and improving the performance of the display panel 100.

[0105] It should be noted that the tensile modulus described herein is the elasticity of the pattern (e.g., the first pattern and the second pattern) during stretching, for example, the tensile modulus of the pattern (e.g., the first pattern and the second pattern) is the ratio of the force required to stretch a unit length of the pattern along its central axis to its cross-sectional area.

[0106] Exemplarily, the first pattern 1401 can extend beyond the folding region F and be coupled with the second pattern 1402 and the third pattern 1403. The orthographic projection of the second pattern 1402 and the third pattern 1403 on the substrate 110 does not overlap with the folding region F. Exemplarily, the first pattern 1401 is coupled with the second pattern 1402 through a via penetrating between the film layers where the two patterns are located, and the first pattern 1401 is also coupled with the third pattern 1403 through a via penetrating between the film layers where the two patterns are located. Exemplarily, the second pattern 1402 and the third pattern 1403 are disposed in the same layer and are made of the same material, i.e., the second pattern 1402 and the third pattern 1403 can be formed synchronously, for example, by patterning from the same film layer, thereby simplifying the production process and saving costs.

[0107] It should be noted that, for the convenience of description, each pixel circuit in the figure is schematically shown with one transistor (e.g., the first pixel circuit 121 and the second pixel circuit 122 are each schematically shown with one transistor). FIG. 9B and the following FIG. 10B to 10D and FIG. 16A to FIG. 16C ).

[0108] In some embodiments, as shown in FIG. 6 , the plurality of signal lines 140 includes a first signal line 141 and a second signal line 142. As shown in FIG. 9BAs shown, the first signal line 141 includes a first pattern 1401, a second pattern 1402, and a third pattern 1403.

[0109] The first pattern 1401 is made of the same material as the second signal line 142. For example, the first pattern 1401 and the second signal line 142 are arranged in the same layer, and the first pattern 1401 and the second signal line 142 can be formed by the same film layer patterning, that is, the first pattern 1401 and the second signal line 142 can be formed synchronously, which can simplify the production process and save costs.

[0110] For example, the first signal line 141 can include a gate line, a reset signal line, or a light-emitting control signal line, etc., wherein the gate line is configured to transmit a gate driving signal (Gate), the reset signal line is configured to transmit a reset signal (Reset), and the light-emitting control signal line is configured to transmit a light-emitting control signal (EM). For example, the reset signal line coupled to the current row of pixel circuits can be the gate line coupled to the next row of pixel circuits. For example, the material of the second pattern 1402 and the material of the third pattern 1403 in the first signal line 141 are the same, for example, both can use a metal containing molybdenum (Mo) or the like.

[0111] The second signal line 142 can include a data line, an initial signal line, a first power signal line, or a second power signal line, etc., wherein the data line is configured to transmit a data signal (Data), the initial signal line is configured to transmit an initial signal (Initial), the first power signal line is configured to transmit a first power signal (VDD), for example, the first power signal is a direct current high level signal, and the second power signal line is configured to transmit a second power signal (VSS), for example, the second power signal is a direct current low level signal. For example, the material of the second signal line 142 can use a metal containing titanium (Ti) and aluminum (Al) or the like. For example, the second signal line 142 can be a three-layer structure (Ti-Al-Ti), that is, a three-layer structure composed of two layers of titanium material and an aluminum material layer sandwiched between the two layers of titanium material. For example, the first pattern 1401 and the second signal line 142 include the same type of material and have the same material composition structure. For example, the first pattern 1401 can also use a metal containing titanium (Ti) and aluminum (Al) or the like, and the first pattern 1401 can also be the above-mentioned Ti-Al-Ti three-layer structure.

[0112] In some embodiments, as FIG. 10A and FIG. 10BAs shown, the display panel 100 further comprises a plurality of connection leads 150. The plurality of connection leads 150 are disposed on the substrate 110. One first light emitting device 121 is coupled with one first pixel circuit 131 through one connection lead 150. It can be understood that the first pixel circuit 131 transmits a driving signal (e.g. driving current) to the first light emitting device 121 through the connection lead 150, so as to drive the first light emitting device 121 to work, i.e. the first light emitting device 121 emits light in response to the driving signal transmitted by the connection lead 150. For example, the drain of the driving transistor in the first pixel circuit is connected with the anode of the light emitting device through the connection lead.

[0113] In addition, the first pattern 1401 and the second signal line 142 can also be disposed in different layers, for example, the first pattern 1401 is closer to the substrate 110 than the second signal line 142. In this way, the wiring space can be expanded, and the first pattern 1401 and the second signal line 142 are prevented from crossing each other.

[0114] At least a portion of at least one connection lead 150 located in the first display area A1 is transparent. In this way, the connection lead 150 can be prevented from affecting the transmittance of the first display area A1. For example, at least one connection lead 150 can be entirely transparent. Exemplarily, the material of the transparent portion of at least one connection lead 150 can be a transparent conductive material, for example, the transparent conductive material can be an oxide including ITO, IZO or AZO, or can be a thin transparent metal including Ag, or can be a combination of oxide and metal including ITO and Ag.

[0115] In the description, the transparent structure refers to a structure having a relatively high transmittance to light, for example, the transmittance can be greater than or equal to about 80%, and the structure can be colored or colorless.

[0116] It should be noted that the wiring of the plurality of connection leads 150 can be designed according to the actual situation of the display panel 100, for example, considering the size of the wiring space of the display panel 100, the position of the first pixel circuit 131 or the position of the first light emitting device 121, etc. For example, in the bending area F, the distance between two adjacent connection leads 150 is less than the distance between two adjacent light emitting devices 120. For example, in order to prevent the plurality of connection leads 150 from crossing each other, the connection lead 150 can pass through the second display area A2, i.e. the orthogonal projection of the connection lead 150 on the substrate 110 can overlap with the second display area A2.

[0117] For example, multiple connecting leads can be provided on the same layer, that is, multiple connecting leads 150 can be formed simultaneously (for example, by patterning the same film layer), which can simplify the production process and reduce production costs. For example, multiple connecting leads can be provided on multiple layers to avoid the connecting leads from crossing each other.

[0118] In some embodiments, as FIG. 10C As shown, at least one connecting lead 150 includes a fourth pattern 151 and a fifth pattern 152. The fourth pattern 151 is located in the first display area A1, and the fifth pattern 152 is located outside the first display area A1. The fourth pattern 151 is coupled to the first light-emitting device 121. The fifth pattern 152 is coupled to the fourth pattern 151 and the first pixel circuit 131.

[0119] The orthographic projection of the fifth pattern 152 on the substrate 110 does not overlap with the first display area A1, but overlaps with the bending area F and the second area B. When the first display area A1 includes a first sub-area A11 and a second sub-area A12, the orthographic projection of the fifth pattern 152 on the substrate 110 does not overlap with the first sub-area A11, but overlaps with the second sub-area A12. The orthographic projection of the fourth pattern 151 on the substrate 110 overlaps with the first sub-area A11.

[0120] For example, when at least one signal line 140 includes a second signal line 142, the fifth pattern 152 is made of the same material as the second signal line 142. For example, while ensuring that the fifth pattern 152 does not cross the second signal line 142, the fifth pattern 152 and the second signal line 142 can be provided on the same layer (e.g., FIG. 10C Alternatively, for example, the fifth pattern 152 and the second signal line 142 are located in different pattern layers, for example, as shown in FIG. FIG. 10D As shown, the fifth pattern 152 is further away from the substrate 110 than the second signal line 142, and closer to the substrate 110 than the fourth pattern 151. The fourth and fifth patterns 151 and 152 can be connected via vias that penetrate the film layer between them. For example, the material of the fifth pattern 152 includes a metal such as Ti or Al. For example, the fifth pattern 152 can have a three-layer structure of Ti-Al-Ti. For example, the material of the fourth pattern is a transparent conductive material such as ITO or IZO. As such, the fifth pattern 152 has higher ductility than the fourth pattern 151, with a tensile modulus greater than that of the fourth pattern 151, and a greater flexibility than that of the fourth pattern 151. This prevents the connecting lead 150 from breaking in the bend region F. Furthermore, the resistance of the fifth pattern 152 is lower than that of the fourth pattern 151, thereby reducing the resistance of the connecting lead 150 and preventing loss of electrical signals transmitted through the connecting lead 150.

[0121] Exemplarily, the fourth pattern 151 is a single-layer structure, the fifth pattern 152 includes three sub-patterns, and the second sub-pattern among the three sub-patterns is located between the first sub-pattern and the third sub-pattern, and the third sub-pattern is farther away from the substrate than the first sub-pattern. Among them, the first sub-pattern is arranged in the same layer as the fourth pattern and is of the same material, and the third sub-pattern is of the same material as the first sub-pattern. For example, the materials of the fourth pattern, the first sub-pattern and the third sub-pattern all adopt transparent conductive materials including ITO or IZO, and the material of the second sub-pattern adopts metal materials including silver (Ag) or aluminum (Al). For example, the materials of the first sub-pattern and the third sub-pattern adopt ITO, and the material of the second sub-pattern is Ag, at this time, the fifth pattern is in a three-layer structure of ITO-Ag-ITO. Among them, the fourth pattern and the first sub-pattern in the fifth pattern are formed synchronously and connected as an integrated structure, that is, the fourth pattern is served by the first sub-pattern in the fifth pattern. In the process, for example, a three-layer conductive thin film can be formed on the substrate, such as an ITO thin film, an Ag thin film and an ITO thin film stacked in sequence, and the three-layer conductive thin film is patterned, and the first layer of the conductive thin film located in the region to be formed into the fourth pattern and the region to be formed into the fifth pattern, and the third layer of the conductive thin film and the second layer of the conductive thin film located in the region to be formed into the fifth pattern are reserved, to obtain the fifth pattern and the fourth pattern.

[0122] It can be understood that the fourth pattern 151 is transparent, which can improve the transmittance of the first display area A1. Moreover, the fifth pattern 152 has higher ductility than the fourth pattern 151, the tensile modulus of the fifth pattern 152 is greater than that of the fourth pattern 151, and the flexibility of the fifth pattern 152 is greater than that of the fourth pattern 151. It can be avoided that the connecting lead 150 is broken in the bending area F.

[0123] Exemplarily, the fifth pattern 152 is of the same material as the light emitting device 120. For example, the anode 1201 of the light emitting device 120 can also be in a three-layer structure of ITO-Ag-ITO. In this way, when the fifth pattern 152 and the anode 1201 are prepared in the process, the same material can be used in the film forming process, such as using the same target material, so as to reduce the production cost.

[0124] It should be noted that, for the convenience of description, FIG. 10A to FIG. 10D The first pixel circuit 131 in the first display area A1 is schematically shown by one transistor.

[0125] Exemplarily, the display panel further includes a first conductive layer and a second conductive layer, with the first conductive layer being located on a side of the second conductive layer closer to the substrate. The first pattern is located in the first conductive layer, the fifth pattern is located in the second conductive layer, and the second signal line can be located in either the first conductive layer or the second conductive layer. This prevents the lines from crossing each other. For example, the first pattern, the fifth pattern, and the second signal line are all made of the same material.

[0126] In addition, the display panel also includes a third conductive layer and a fourth conductive layer, and the fourth conductive layer is located on the side of the third conductive layer close to the substrate. Among them, the control electrode of each transistor in the pixel circuit can be located in the fourth conductive layer, the first electrode of the capacitor can be located in the fourth conductive layer, and the second electrode of the capacitor can be located in the third conductive layer. The second pattern and the third pattern in the above-mentioned first signal line can be located in the fourth conductive layer or the third conductive layer. For example, the first electrode and the second electrode of the capacitor, the control electrode of each transistor in the pixel circuit, and the second pattern and the third pattern in the first signal line are all made of the same material.

[0127] Exemplarily, the plurality of signal lines further include a third signal line and a fourth signal line located within the second display area, wherein the pixel circuit coupled to the third signal line and the fourth signal line is the second pixel circuit. The third signal line is made of the same material and disposed in the same layer as the second and third patterns in the first signal line, and the fourth signal line is made of the same material and disposed in the same layer as the second signal line.

[0128] In some embodiments, as FIG. 11 As shown, the portion of the display panel 100 located in the second region B includes a transparent portion 160. The orthographic projection of the first pixel circuit 131 on the substrate 110 does not overlap with the transparent portion 160. For example, there is no non-transparent film layer in the transparent portion 160, for example, the non-transparent film layer includes a metal layer and a semiconductor layer. For example, the transparent portion 160 includes a transparent film layer located on the substrate 110, such as an insulating layer. For example, referring to FIG. 10B to FIG. 10D The insulating layer may include a buffer layer (Buffer), a gate insulating layer (GI), an interlayer dielectric layer (ILD) or a planar layer (PLN), etc. For example, the planar layer may have multiple layers (PLN1, PLN2, PLN3).

[0129] The portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A. When the first display area A1 includes the first sub-area A11, the first sub-area A11 is located in the area where the positive projection of the transparent portion 160 on the portion of the substrate 110 located in the first area A is located.

[0130] In this case, the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A. Light passes through the first sub-area A11 and then the transparent portion 160 without being blocked by the first pixel circuit 131, thereby improving transmittance. Thus, when the sensor is located in the first sub-area A11, the sensor's sensitivity to light can be improved, thereby enhancing the sensing effect.

[0131] For example, when the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the first display area A1 is located within the region where the orthographic projection of the transparent portion 160 on the portion of the substrate 110 located in the first region A is located. In this way, light passing through the first display area A1 will not be blocked by the first pixel circuit 131, thereby improving transmittance.

[0132] For example, in the second region B, the orthographic projection of at least one signal line 140 (such as the first signal line 141) on the substrate 110 does not overlap with the orthographic projection of the transparent portion 160 on the substrate 110. For example, in the case where there are multiple first pixel circuits 131, the multiple first pixel circuits 131 can be respectively located in the transparent portion 160 in the row direction of the pixel circuit arrangement (for example, FIG. 11 For example, the plurality of first pixel circuits coupled to a row of first light-emitting devices are divided into two parts, one of the first pixel circuits in the two parts is located on one of the two opposite sides, and the other of the first pixel circuits in the two parts is located on the other side of the two opposite sides. The two first pixel circuits are respectively coupled to two first signal lines, which transmit synchronous signals and are also located on opposite sides. One of the first pixel circuits in the two parts is coupled to one of the two first signal lines, and the other of the first pixel circuits in the two parts is coupled to the other of the two first signal lines.

[0133] It should be noted that the row direction of the pixel circuit arrangement described in the article can be the arrangement direction of multiple pixel circuits responding to synchronized signals. For example, multiple pixel circuits that synchronously write data signals in response to synchronized gate drive signals are a row of pixel circuits.

[0134] In some embodiments, as FIG. 12A 、 FIG. 12B and FIG. 13AAs shown, the plurality of light emitting devices 120 further includes a third light emitting device 123. The third light emitting device 123 is located on the transparent portion 160. The plurality of pixel circuits 130 further includes a third pixel circuit 133. The third pixel circuit 133 is located in the second region B. The third pixel circuit 133 is coupled with the third light emitting device 123. The third pixel circuit 133 has a footprint on the substrate 110 that does not overlap with a footprint of the transparent portion 160 on the substrate 110.

[0135] It can be understood that the third pixel circuit 133 does not block light passing through the transparent portion 160, i.e., the third pixel circuit 133 does not block light passing through the first sub-region A11, and thus the transmittance of the first sub-region A11 can be improved. In addition, the third pixel circuit 133 does not block light passing through the first display region A1, and thus the transmittance of the first display region A1 can be improved.

[0136] In a case where the portion of the display panel 100 located in the second region B is bent to the back of the portion of the display panel 100 located in the first region A, the third light emitting device 123 has a footprint on the portion of the substrate 110 located in the first region A that is located within the first display region A1 and does not overlap with a footprint of the first light emitting device 121 on the substrate 110.

[0137] Exemplarily, in a case where the first display region A1 includes the first sub-region A11, the third light emitting device 123 has a footprint on the portion of the substrate 110 located in the first region A that is located within the first sub-region A11 and does not overlap with a footprint of the first light emitting device 121 on the substrate 110.

[0138] Exemplarily, the third pixel circuit 133 is coupled with a plurality of signal lines 140. For example, in a case where the footprint of the third light emitting device 123 on the portion of the substrate 110 located in the first region A is within a range of a footprint of a row of light emitting devices on the substrate 110, the first pixel circuit 131 and the third pixel circuit 133 are coupled with a signal line 140 (e.g., the first signal line 141). For example, in a case where the footprint of the third light emitting device 123 on the portion of the substrate 110 located in the first region A is within a range of a footprint of a column of light emitting devices on the substrate 110, the first pixel circuit 131 and the third pixel circuit 133 are coupled with a signal line 140 (e.g., the second signal line 142).

[0139] In this case, since part of the light-emitting devices originally located in the first display area A1 are set in the second area B, that is, the third light-emitting device 123 is set in the second area B, and the corresponding pixel circuit is also located in the second area B, the connecting line between the third light-emitting device 123 and the third pixel circuit 133 can not pass through the first display area A1 and the bending area F, thereby reducing the number of wiring in the first display area A1 and the bending area F, simplifying the wiring, and reducing the wiring difficulty.

[0140] In some embodiments, when the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A, as shown in FIG. FIG. 13B As shown, the arrangement of the first light emitting device 121 and the third light emitting device 123 is the same as the arrangement of the second light emitting device 122 .

[0141] In which, when the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A, the arrangement of the orthographic projections of the first light-emitting device 121 and the third light-emitting device 123 on the portion of the substrate 110 located in the first area A is the same as the arrangement of the orthographic projection of the second light-emitting device 122 on the substrate 110, and the orthographic projections of the first light-emitting device 121, the second light-emitting device 122 and the third light-emitting device 123 meet the arrangement of multiple light-emitting devices 120 in the display panel 100.

[0142] For example, FIG. 13A As shown, the second light emitting devices 122 are arranged in an array, as shown in FIG. FIG. 13B As shown, when the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A, the first light emitting devices 121 and the third light emitting devices 123 are arranged in an array.

[0143] For example, for the direction along the column of pixel circuits (refer to FIG. 13A In the Y direction of the display panel 100, there are n rows (or n devices) of third light-emitting devices in a column. When the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, in the orthographic projection of the third light-emitting devices in the column on the portion of the substrate 110 located in the first region A, the orthographic projection of the third light-emitting devices in the i-th row is located in the (n+1-i)-th row of the orthographic projection of the third light-emitting devices in the n-th row; n is a positive integer, i≤n and i is a positive integer. For example, when there are six rows of third light-emitting devices in a column (i.e., n=6), when the display panel 100 is in a flat state (refer to FIG. 13A ) is located in the first row (i.e., i=1), the portion of the third light emitting device located in the second region B of the display panel 100 is bent to the back of the portion located in the first region A (refer to FIG. 13BIn the case where the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A (for reference

[0144] Exemplarily, in the case where the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A, the third light emitting device is arranged in the same row as the first light emitting device on the substrate, and the third pixel circuit coupled to the third light emitting device is arranged in the same row as the first pixel circuit coupled to the first light emitting device. For example, in the case where there are six rows of third light emitting devices in one column, there are also six rows of third pixel circuits in the corresponding column, and the third light emitting device in the first row is coupled to the third pixel circuit in the sixth row. For example, in the case where the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A (for reference FIG. 13B ), the third light emitting device is arranged in the same row as the first light emitting device on the substrate in a six-row and six-column array (for reference FIG. 13B ), and the third light emitting device in the first row is arranged in the same row as the first light emitting device in the sixth row on the substrate 110 (i.e., the sixth row), and the third pixel circuit coupled to the third light emitting device in the first row is arranged in the same row as the first pixel circuit coupled to the first light emitting device in the sixth row (e.g., the sixth row), and the third pixel circuit and the first pixel circuit in the same row are responsive to a synchronous signal (e.g., a gate driving signal).

[0145] It should be noted that the embodiments of the present disclosure do not limit the arrangement of the light emitting devices, which can be designed according to actual conditions. For example, the plurality of light emitting devices can be arranged in an array; or the plurality of light emitting devices can be arranged in a Pentile arrangement. For example, in the case where the light emitting devices are arranged in an array, the adjacent two rows of light emitting devices and the adjacent two columns of light emitting devices can be arranged in alignment, or the adjacent two rows of light emitting devices and the adjacent two columns of light emitting devices can be arranged in misalignment, which is not limited by the embodiments of the present disclosure.

[0146] In some embodiments, the number of the third light emitting devices 123 is less than the number of the first light emitting devices 121. It can be understood that, in the case that the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the light emitted by the third light emitting device 123 will pass through the portion of the substrate 110 located in the first display area A1 and be emitted from the side of the first light emitting device 121 away from the substrate 110, the light emitted by the first light emitting device 121 is emitted from the side of the first light emitting device 121 away from the substrate 110, and the light emitted by the second light emitting device 122 is emitted from the side of the second light emitting device 122 away from the substrate 110, that is, the light emitted by the third light emitting device 123 will pass through the film layer located on the side of the first light emitting device 121 and the second light emitting device 122 close to the substrate, therefore, the number of the film layers through which the light emitted by the third light emitting device 123 passes is greater than the number of the film layers through which the light emitted by the first light emitting device 121 and the second light emitting device 122 passes, and thus the light emitting effect of the third light emitting device 123 is lower than the light emitting effects of the first light emitting device 121 and the second light emitting device 122. In this case, the number of the third light emitting device 123 is less than the number of the first light emitting device 121, which can reduce the influence of the light emitting effect of the third light emitting device 123 on the display panel 100 and avoid the non-uniform light emission of the first display area A1 and the second display area A2 after the display panel 100 is bent, so as to ensure the uniformity of the display effects of the first display area A1 and the second display area A2 and the display uniformity of the display panel 100.

[0147] In some embodiments, as shown in FIGS. 1C and 1D, the display panel 100 further includes a transparent conductive line 170. The transparent conductive line 170 is disposed on the substrate 110. The third light emitting device 123 is coupled to the third pixel circuit 133 through the transparent conductive line 170. In this way, in the case that the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the first display area A1 can be transparent, and the transmittance of the first display area A1 can be improved. FIG. 12A FIG. 12B It can be understood that, in the case that the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the light emitted by the third light emitting device 123 will pass through the portion of the substrate 110 located in the first display area A1 and be emitted from the side of the first light emitting device 121 away from the substrate 110, the light emitted by the first light emitting device 121 is emitted from the side of the first light emitting device 121 away from the substrate 110, and the light emitted by the second light emitting device 122 is emitted from the side of the second light emitting device 122 away from the substrate 110, that is, the light emitted by the third light emitting device 123 will pass through the film layer located on the side of the first light emitting device 121 and the second light emitting device 122 close to the substrate, therefore, the number of the film layers through which the light emitted by the third light emitting device 123 passes is greater than the number of the film layers through which the light emitted by the first light emitting device 121 and the second light emitting device 122 passes, and thus the light emitting effect of the third light emitting device 123 is lower than the light emitting effects of the first light emitting device 121 and the second light emitting device 122. In this case, the number of the third light emitting device 123 is less than the number of the first light emitting device 121, which can reduce the influence of the light emitting effect of the third light emitting device 123 on the display panel 100 and avoid the non-uniform light emission of the first display area A1 and the second display area A2 after the display panel 100 is bent, so as to ensure the uniformity of the display effects of the first display area A1 and the second display area A2 and the display uniformity of the display panel 100.

[0148] It can be understood that, in the case that the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the light emitted by the third light emitting device 123 will pass through the portion of the substrate 110 located in the first display area A1 and be emitted from the side of the first light emitting device 121 away from the substrate 110, the light emitted by the first light emitting device 121 is emitted from the side of the first light emitting device 121 away from the substrate 110, and the light emitted by the second light emitting device 122 is emitted from the side of the second light emitting device 122 away from the substrate 110, that is, the light emitted by the third light emitting device 123 will pass through the film layer located on the side of the first light emitting device 121 and the second light emitting device 122 close to the substrate, therefore, the number of the film layers through which the light emitted by the third light emitting device 123 passes is greater than the number of the film layers through which the light emitted by the first light emitting device 121 and the second light emitting device 122 passes, and thus the light emitting effect of the third light emitting device 123 is lower than the light emitting effects of the first light emitting device 121 and the second light emitting device 122. In this case, the number of the third light emitting device 123 is less than the number of the first light emitting device 121, which can reduce the influence of the light emitting effect of the third light emitting device 123 on the display panel 100 and avoid the non-uniform light emission of the first display area A1 and the second display area A2 after the display panel 100 is bent, so as to ensure the uniformity of the display effects of the first display area A1 and the second display area A2 and the display uniformity of the display panel 100.

[0149] It can be understood that, in the case that the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the light emitted by the third light emitting device 123 will pass through the portion of the substrate 110 located in the first display area A1 and be emitted from the side of the first light emitting device 121 away from the substrate 110, the light emitted by the first light emitting device 121 is emitted from the side of the first light emitting device 121 away from the substrate 110, and the light emitted by the second light emitting device 122 is emitted from the side of the second light emitting device 122 away from the substrate 110, that is, the light emitted by the third light emitting device 123 will pass through the film layer located on the side of the first light emitting device 121 and the second light emitting device 122 close to the substrate, therefore, the number of the film layers through which the light emitted by the third light emitting device 123 passes is greater than the number of the film layers through which the light emitted by the first light emitting device 121 and the second light emitting device 122 passes, and thus the light emitting effect of the third light emitting device 123 is lower than the light emitting effects of the first light emitting device 121 and the second light emitting device 122. In this case, the number of the third light emitting device 123 is less than the number of the first light emitting device 121, which can reduce the influence of the light emitting effect of the third light emitting device 123 on the display panel 100 and avoid the non-uniform light emission of the first display area A1 and the second display area A2 after the display panel 100 is bent, so as to ensure the uniformity of the display effects of the first display area A1 and the second display area A2 and the display uniformity of the display panel 100.

[0150] ​In some embodiments, the transparent part 160 is an opening, and a depth direction of the opening is perpendicular to a plane in which the portion of the substrate 110 located in the second region B is located. In this case, the opening penetrates the substrate 110 in a direction perpendicular to the portion of the substrate 110 located in the second region B. That is, the display panel 100 is a through hole in the region where the transparent part 160 is located. For example, the opening can be obtained by removing the film layers (such as metal layers, semiconductor layers, inorganic material layers, and organic material layers) and the substrate 110 (for example, the substrate 110 includes PI) in the region of the transparent part 160 by a laser cutting process, which is similar to an AAH (Active Area Hole, AA region through hole, display region through hole) process (that is, a process of forming a through hole in the AA region by using a laser). In this way, the light transmittance of the display panel can be improved, and in the case where the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the number of film layers through which the light passes can be reduced, thereby improving the under-screen sensing effect of the display panel 100.

[0151] In some embodiments, referring to FIG. 11 and FIG. 12A to FIG. 12B , the plurality of pixel circuits 130 located in the second region B are arranged in an array. Along a row direction of the pixel circuit arrangement (for example, the X direction in FIG. 11 , the plurality of pixel circuits 130 are located on at least one side of the transparent part 160. In this way, the plurality of pixel circuits in the second region B can be uniformly distributed, and the wires coupled to the plurality of pixel circuits can also be uniformly distributed. For example, along the row direction of the pixel circuit arrangement, the plurality of pixel circuits 130 are located on one side of the transparent part 160, or a part of the plurality of pixel circuits 130 are located on one side of the transparent part 160, and the other part are located on the other side of the transparent part 160.

[0152] For example, in the case where the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the orthographic projection of the third light emitting device 123 on the portion of the substrate 110 located in the first region A and the orthographic projection of the first light emitting device 121 on the substrate 110 are arranged in a row along the row direction of the pixel circuit arrangement, and at this time, the third pixel circuit 133 coupled to the third light emitting device 123 and the first pixel circuit 131 coupled to the first light emitting device 121 are in the same row of pixel circuits, and the same row of pixel circuits can be partially located on one side of the transparent part 160 and partially located on the other side of the transparent part 160. At this time, at least one signal line coupled to the same row of pixel circuits can be two sub-line segments, and the two sub-line segments are located on opposite sides of the transparent part 160 and synchronously drive a row of pixel circuits.

[0153] In some embodiments, as FIG. 14As shown, in the column direction (such as FIG. 14 In the Y direction (in the Y direction), the width W1 of the entire structure formed by the multiple pixel circuits 130 located in the second area B is less than or equal to the width W2 of the first display area A1. This reduces the width of the second area B in the column direction of the pixel circuits 130, and reduces the size of the portion of the display panel 100 located in the second area B. When the portion of the display panel 100 located in the second area B is bent to the back of the portion located in the first area A, the overlapping area between the portion of the display panel 100 located in the second area B and the portion of the display panel 100 located in the first area A is small, reducing the space occupied by the portion of the display panel 100 located in the second area B when it is bent to the back of the portion of the display panel 100 located in the first area A. This ensures sufficient space on the back of the display panel 100 for other devices (such as a camera and a battery).

[0154] In some embodiments, as FIG. 15A to FIG. 15E As shown, the plurality of pixel circuits 130 located in the second region B are divided into at least two groups G. Different groups are arranged along the row direction of the pixel circuits (eg FIG. 15A to FIG. 15E Each group G includes at least one row of pixel circuits 130. Each row of pixel circuits in at least two groups G corresponds one-to-one to multiple rows of pixel circuits located in the second display area A2.

[0155] For example, in the case where the plurality of pixel circuits 130 located in the second region B are originally arranged in an array of 6 rows and 6 columns, refer to FIG. 15A , can be divided into 3 groups, and the multiple pixel circuits in each group are arranged in an array of 2 rows and 6 columns; or, referring to FIG. 15B , or it can be divided into two groups, with the multiple pixel circuits in each group arranged in three rows and six columns. In this way, the overall width of the pixel circuits in the second region B in the column direction of the pixel circuit arrangement can be reduced, thereby reducing the size of the portion of the display panel 100 located in the second region B. When the portion of the display panel 100 located in the second region B is bent to the back of the portion located in the first region A, the overlapping area between the portion of the display panel 100 located in the second region B and the portion of the display panel 100 located in the first region A is small, reducing the space occupied by the portion of the display panel 100 located in the second region B when it is bent to the back of the portion of the display panel 100 located in the first region A, thereby ensuring sufficient space for arranging other devices (such as a camera and a battery) on the back of the display panel 100.

[0156] Each row of pixel circuits in each group G and the corresponding row of pixel circuits in the second display area A2 are coupled to at least one same signal line 140. In this way, each row of pixel circuits in each group G and the corresponding row of pixel circuits in the second display area A2 respond to signals synchronously. For example, each row of pixel circuits in each group G and the corresponding row of pixel circuits in the second display area A2 can respond to synchronous gate driving signals, and write data signals synchronously. During display, each row of pixel circuits in each group G and the corresponding row of pixel circuits in the second display area A2 can drive the light emitting devices coupled thereto synchronously, i.e., the light emitting devices coupled to each row of pixel circuits in each group G and the light emitting devices coupled to the corresponding row of pixel circuits in the second display area A2 emit light synchronously.

[0157] For example, referring to FIG. 15A , three groups correspond to 6 rows of 6 columns of first light emitting devices in the first display area, and each of the three groups includes 2 rows of 6 columns of pixel circuits. In the first group (e.g., the left group in FIG. 15A ) of the three groups, the first row of pixel circuits is configured to drive the first row of first light emitting devices, and the second row of pixel circuits is configured to drive the second row of first light emitting devices. In the second group (e.g., the middle group in FIG. 15A ) of the three groups, the first row of pixel circuits is configured to drive the third row of first light emitting devices, and the second row of pixel circuits is configured to drive the fourth row of first light emitting devices. In the third group (e.g., the right group in FIG. 15A ) of the three groups, the first row of pixel circuits is configured to drive the fifth row of first light emitting devices, and the second row of pixel circuits is configured to drive the sixth row of first light emitting devices.

[0158] For example, referring to FIG. 15B , two groups correspond to 6 rows of 6 columns of first light emitting devices in the first display area, and each of the two groups includes 3 rows of 6 columns of pixel circuits. In the first group (e.g., the left group in FIG. 15B ) of the two groups, the first row of pixel circuits is configured to drive the first row of first light emitting devices, the second row of pixel circuits is configured to drive the second row of first light emitting devices, and the third row of pixel circuits is configured to drive the third row of first light emitting devices. In the second group (e.g., the right group in FIG. 15B ) of the two groups, the first row of pixel circuits is configured to drive the fourth row of first light emitting devices, the second row of pixel circuits is configured to drive the fifth row of first light emitting devices, and the third row of pixel circuits is configured to drive the sixth row of first light emitting devices.

[0159] For example, the pixel circuits in each column of each group G and the corresponding column of pixel circuits in the second display area A2 are coupled to at least one same signal line 140. For example, each column of pixel circuits in each group G and the corresponding column of pixel circuits in the second display area A2 can receive the same data signal. For example, referring to FIG. 15A the 1st column of pixel circuits in a first group (e.g., the left group in FIG. 15A ), the 1st column of pixel circuits in a second group (e.g., the middle group in FIG. 15A ), and the 1st column of pixel circuits in a third group (e.g., the right group in FIG. 15A ) are coupled to one signal line.

[0160] In some embodiments, as shown in FIG. 16A and FIG. 16B , the display panel 100 further includes a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183. The second encapsulation layer 182 is farther away from the substrate 110 than the first encapsulation layer 181. The third encapsulation layer 183 is between the first encapsulation layer 181 and the second encapsulation layer 182. The first encapsulation layer 181 covers the plurality of pixel circuits 130 and the plurality of light emitting devices 120. The second encapsulation layer 182 covers the second pixel circuit 132. The third encapsulation layer 183 covers the plurality of light emitting devices 120.

[0161] Exemplarily, the material of the first encapsulation layer 181 and the material of the second encapsulation layer 182 each comprises an inorganic material, i.e., the first encapsulation layer 181 and the second encapsulation layer 182 are each an inorganic encapsulation layer. The inorganic material may, for example, be silicon nitride, silicon oxide, silicon oxynitride, etc., and the first encapsulation layer and the second encapsulation layer formed of the inorganic material have high compactness and can prevent the invasion of water and oxygen, etc. For example, the material of the third encapsulation layer comprises an organic material, i.e., the third encapsulation layer 183 is an organic encapsulation layer. The organic material may, for example, be a high-molecular material containing a desiccant or a high-molecular material capable of blocking water vapor, such as a high-molecular resin, etc., to perform a planarization process on the surface of the display panel and can relieve the stress of the first encapsulation layer and the second encapsulation layer. For example, the material of the third encapsulation layer 183 may, for example, further comprise a hygroscopic material, such as an alkali metal (e.g., lithium (Li) and sodium (Na)), an alkaline earth metal (e.g., barium (Ba) and calcium (Ca)), or other moisture-reactive metals (e.g., aluminum (Al) and iron (Fe)); an alkali metal oxide (e.g., lithium oxide (Li2O) and sodium oxide (Na2O)), an alkaline earth metal oxide (e.g., magnesium oxide (MgO), calcium oxide (CaO), and barium oxide (BaO)), a sulfate (e.g., anhydrous magnesium sulfate (MgSO4)), a metal halide (e.g., calcium chloride (CaCl2) or perchlorate (e.g., magnesium perchlorate Mg(ClO4)2), etc., to absorb the water and oxygen, etc., invading the interior.

[0162] In this case, the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 cover the light emitting device 120 and the pixel circuit 130 located in the first region A, and the first encapsulation layer 181 further covers the pixel circuit 130 located in the second region B, so that the invasion of water vapor and oxygen, etc., in the external environment into the interior of the display panel 100 can be avoided, for example, the water vapor and oxygen, etc., react with the light emitting device and the pixel circuit, etc., in the display panel to affect the electrical properties thereof, thereby reducing the performance and the life of the display panel 100.

[0163] In some embodiments, as shown in FIG. 1B, in the case where the plurality of light emitting devices 120 comprises a third light emitting device 123, the second encapsulation layer 182 further covers the third light emitting device 123. FIG. 16C

[0164] ​It can be understood that the first encapsulation layer 181 and the second encapsulation layer 182 both cover the light emitting device 120 and the pixel circuit 130 located in the second area B, and the third encapsulation layer 183 covers the light emitting device 120 (i.e., the third light emitting device 123) located in the second area B. In this case, it can be avoided that water vapor and oxygen in the external environment invade the inside of the display panel 100 from the second area B, for example, the water vapor and oxygen react with the third light emitting device 123, the first pixel circuit 131, and the third pixel circuit 133, etc., to affect the electrical performance thereof, thereby reducing the performance and service life of the display panel 100.

[0165] In some embodiments, as shown in FIG. 17A and FIG. 17B , the display panel 100 also has a bonding area Q. In the case that the display panel 100 has the second area B and the bending area F, as shown in FIG. 17A , the bonding area Q is located on the side of the second area B away from the bending area F, or as shown in FIG. 17B , the bonding area Q is located on the side of the first area A away from the bending area F. Wherein, the display panel 100 is configured to bond a driver IC in the bonding area Q.

[0166] Exemplarily, as shown in FIG. 17A and FIG. 17B , the display panel 100 also includes a plurality of pads 101 arranged in the bonding area Q. The plurality of signal lines 140 extend to the bonding area Q through the plurality of pads 101, and the driver chip is coupled.

[0167] It can be understood that, in the case that the bonding area Q is located on the side of the second area B away from the bending area F, the side of the first area A away from the bending area F has no bonding area Q, and the pads 101 are not arranged either, so that the frame of the display panel 100 on the side of the first area A away from the bending area F can be reduced, the frame of the display panel 100 is not increased, and the display panel 100 is facilitated to realize narrow frame. Moreover, in the process of bending the part of the display panel 100 located in the second area B to the back of the part located in the first area A, the driver chip is also bent to the back of the part of the display panel 100 located in the first area A, that is, the driver chip and the part of the display panel 100 located in the second area B can be bent synchronously, so that the process can be saved.

[0168] In the case that the bonding area Q is located on the side of the first area A away from the bending area F, in the process of bending the driver chip to the back of the display panel 100, the part of the display panel 100 located in the first area A away from the bending area F is also bent, so that the frame of the display panel 100 on the side of the first area A away from the bending area F can be reduced, and the display panel 100 is facilitated to realize narrow frame.

[0169] It should be noted that each wire line shown in FIG. 1B , FIG. 3 , FIG. 6 , FIG. 7 , FIG. 9A , FIG. 10A , FIG. 11 , FIG. 12A , FIG. 12B , FIG. 15A to FIG. 15E , and FIG. 17A to FIG. 17B is only a connection diagram and is not the layout of the actual wire line. In actuality, the wire line mode can be designed under the condition that each wire line does not appear signal interference.

[0170] The display device 200 provided by the embodiment of the present disclosure, as shown in FIG. 18 , further includes a driving chip 210. The driving chip 210 is bonded with the display panel 100.

[0171] It can be understood that the driving chip 210 is bonded in the bonding area Q in the display panel 100. Exemplarily, the driving chip 210 includes a driving IC (Source IC) and is coupled with a plurality of signal lines (for example, the second signal line) in the display panel 100 to provide a data signal to the plurality of signal lines.

[0172] Exemplarily, the driving chip 210 can adopt COF (Chip on Film, Chip on Film), for example, the driving chip 210 is arranged on the FPC (Flexible Printed Circuit Board, Flexible Printed Circuit Board), and the FPC is bonded with the display panel 100; for example, in the case that the display panel 100 includes the pad 101, the pin of the FPC is bonded with the pad 101. Alternatively, exemplarily, the driving chip 210 can be directly arranged on the display panel 100.

[0173] The display device 200 described above can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or pictorial. More particularly, it is contemplated that the embodiments can be implemented in and / or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, display of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0174] The display device described above has the same advantages as the display panel described in some of the embodiments above, which will not be repeated here.

[0175] The above description is merely illustrative of the disclosure, and does not limit the scope of the disclosure. Any modifications and variations that come within the scope of the disclosure are intended to be included within the scope of the disclosure. Accordingly, the scope of the disclosure is to be interpreted in the broadest sense and is not limited to the specific embodiments described above. The disclosure is defined by the claims appended hereto.

Claims

1. A display panel, characterized in that: The display panel has a first area; the first area includes a first display area and a second display area; the first display area includes a first sub-area and a second sub-area; a sensor is arranged on the back of the first display area, and the orthographic projection of the sensor on the display panel is located within the first sub-area; The display panel includes: substrate; a plurality of light-emitting devices disposed on the substrate, the plurality of light-emitting devices including a first light-emitting device located in the first display area and a second light-emitting device located in the second display area; a plurality of pixel circuits disposed on the substrate, the plurality of pixel circuits including a first pixel circuit coupled to the first light-emitting device and a second pixel circuit coupled to the second light-emitting device; the first pixel circuit is located outside the first display area; and the second pixel circuit is located within the second display area; A plurality of signal lines are arranged on the substrate; the plurality of signal lines are coupled to the plurality of pixel circuits; the plurality of signal lines are configured to provide working signals to the plurality of pixel circuits; at least one signal line among the plurality of signal lines is coupled to at least one first pixel circuit; the orthographic projection of the at least one signal line on the substrate overlaps with the second sub-area and does not overlap with the first sub-area.

2. The display panel according to claim 1, wherein: The display panel further comprises a bending region and a second region; the first region and the second region are connected via the bending region; the display panel is configured to bend a portion located in the bending region so as to bend a portion located in the second region to a back side of a portion located in the first region; At least one first pixel circuit is located in the second area; When the portion of the display panel located in the second area is bent to the back of the portion located in the first area, the orthographic projection of the at least one first pixel circuit on the portion of the substrate located in the first area does not overlap with the first display area.

3. The display panel according to claim 2, wherein: The at least one signal line has at least one opening, and the at least one opening is located in the bending area.

4. The display panel according to claim 2, wherein: At least one signal line includes: A first pattern located in the bending area; a second pattern located in the first area; the second pattern is coupled to the second pixel circuit and the first pattern; a third pattern located in the second area; the third pattern is coupled to the first pixel circuit and the first pattern; The tensile modulus of the first pattern is greater than the tensile modulus of the second pattern and the tensile modulus of the third pattern.

5. The display panel according to claim 4, wherein: The plurality of signal lines include a first signal line and a second signal line; The first signal line includes the first pattern, the second pattern and the third pattern; The first pattern and the second signal line are made of the same material.

6. The display panel according to claim 1, wherein: Also includes: A plurality of connecting leads are provided on the substrate; a first light emitting device is coupled to a first pixel circuit via a connecting lead; At least a portion of at least one connecting lead located in the first display area is transparent.

7. The display panel according to claim 6, wherein: The at least one connecting lead comprises: a fourth pattern, located in the first display area; the fourth pattern is coupled to the first light-emitting device; a fifth pattern located outside the first display area; the fifth pattern is coupled to the fourth pattern and the first pixel circuit; The tensile modulus of the fifth pattern is greater than the tensile modulus of the fourth pattern.

8. The display panel according to claim 7, wherein: In a case where the at least one signal line includes a second signal line, the fifth pattern is made of the same material as the second signal line.

9. The display panel according to claim 2, wherein: The portion of the display panel located in the second area includes: a transparent portion; The orthographic projection of the first pixel circuit on the substrate does not overlap with the transparent portion; The portion of the display panel located in the second area is bent to the back of the portion located in the first area, and the first sub-area is located in the area where the orthographic projection of the transparent portion on the portion of the substrate located in the first area is located.

10. The display panel according to claim 9, wherein: The plurality of light emitting devices further includes a third light emitting device; the third light emitting device is located on the transparent portion; The plurality of pixel circuits further includes a third pixel circuit; the third pixel circuit is located in the second area; The third pixel circuit is coupled to the third light-emitting device; an orthographic projection of the third pixel circuit on the substrate does not overlap with an orthographic projection of the transparent portion on the substrate; When the portion of the display panel located in the second area is bent to the back of the portion located in the first area, the orthographic projection of the third light-emitting device on the portion of the substrate located in the first area is located in the first display area and has no overlap with the orthographic projection of the first light-emitting device on the substrate.

11. The display panel according to claim 10, wherein: When the portion of the display panel located in the second area is bent to the back of the portion located in the first area, the arrangement of the first light-emitting device and the third light-emitting device is the same as the arrangement of the second light-emitting device.

12. The display panel according to claim 10, wherein: Also includes: A transparent wire is provided on the substrate; the third light emitting device is coupled to the third pixel circuit via the transparent wire.

13. The display panel according to claim 9, wherein: The transparent portion is an opening, and a depth direction of the opening is perpendicular to a plane where the portion of the substrate located in the second region is located.

14. The display panel according to claim 9, wherein: The plurality of pixel circuits located in the second area are arranged in an array, and along a row direction of the pixel circuits, the plurality of pixel circuits are located on at least one of two opposite sides of the transparent portion.

15. The display panel according to any one of claims 9 to 14, wherein: In the column direction of the pixel circuit arrangement, the width of the entirety of the plurality of pixel circuits located in the second region is less than or equal to the width of the first display area.

16. The display panel according to claim 15, wherein: The plurality of pixel circuits located in the second area are divided into at least two groups; the different groups are arranged along a row direction of the pixel circuits, each group includes at least one row of pixel circuits, and each row of pixel circuits in the at least two groups corresponds one-to-one to the plurality of rows of pixel circuits located in the second display area; Each row of pixel circuits in each group and a corresponding row of pixel circuits in the second display area are coupled to at least one same signal line.

17. The display panel according to any one of claims 1 to 14, wherein: Also includes: a first encapsulation layer, covering the plurality of pixel circuits and the plurality of light-emitting devices; a second encapsulation layer, further away from the substrate than the first encapsulation layer; The second encapsulation layer covers the second pixel circuit; The third encapsulation layer is located between the first encapsulation layer and the second encapsulation layer; the third encapsulation layer covers the plurality of light-emitting devices.

18. The display panel according to claim 17, wherein: In a case where the plurality of light emitting devices include a third light emitting device, the second encapsulation layer further covers the third light emitting device.

19. The display panel according to any one of claims 1 to 14, wherein: The display panel also has a bonding area; In the case that the display panel has a second region and a bending region, the bonding area is located on a side of the second region away from the bending region; or the bonding area is located on a side of the first region away from the bending region.

20. A display device, characterized in that: include: The display panel according to any one of claims 1 to 19; a sensor, disposed on the back of a portion of the display panel located in the first display area; The orthographic projection of the sensor on the display panel is located in a first sub-area of ​​the first display area.

Images