Display panel and display device

Abstract

An embodiment of the present invention provides a display panel and a display device, which relate to the field of display technologies and improve the light transmittance of the optical component setting area. The display panel includes: a display area, the display area includes an optical component setting area, the optical component setting area includes a plurality of pixel areas, and at least some of the adjacent two pixel areas include a light transmission area; a plurality of pixels located in the display area, the pixel includes a pixel circuit and an organic light-emitting element, the pixel circuit includes a plurality of transistors, the plurality of transistors include a first reset transistor, a second reset transistor, and a driving transistor, the first reset transistor resets the gate of the driving transistor in response to its corresponding scan signal, and the second reset transistor resets the first electrode of the organic light-emitting element in response to its corresponding scan signal; wherein, the pixel circuit includes a first pixel circuit located in the optical component setting area, and the gates of the first reset transistor and the second reset transistor in the first pixel circuit are electrically connected.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, full-screen display devices have become one of the hot technologies in the field of display technology. In order to enable the display device to also have a front camera function, under-screen camera technology has come into being.

[0003] For a display panel using under-screen camera technology, the display area of ​​the display panel includes an optical component setting area with a certain light-transmitting area. When the display device is shooting, the external ambient light passes through the optical component setting area and enters the camera component under the screen. The camera component collects the external ambient light and then realizes imaging. However, in the prior art, the light transmittance of the optical component setting area is relatively low, resulting in low imaging quality. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a display panel and a display device to improve the light transmittance of an optical component arrangement area.

[0005] In one aspect, an embodiment of the present invention provides a display panel, including:

[0006] A display area, the display area includes an optical component setting area, the optical component setting area includes a plurality of pixel areas, and at least a portion of the pixel areas between two adjacent pixel areas include a light-transmitting area;

[0007] A plurality of pixels located in a display area, the pixels comprising a pixel circuit and an organic light emitting element, the pixel circuit comprising a plurality of transistors, the plurality of transistors comprising a first reset transistor, a second reset transistor and a driving transistor, the first reset transistor resetting a gate of the driving transistor in response to a corresponding scan signal, the second reset transistor resetting a first electrode of the organic light emitting element in response to a corresponding scan signal;

[0008] The pixel circuit includes a first pixel circuit located in the optical component setting area, and a gate of the first reset transistor and a gate of the second reset transistor in the first pixel circuit are electrically connected.

[0009] On the other hand, an embodiment of the present invention provides a display device, including the above-mentioned display panel.

[0010] One of the above technical solutions has the following beneficial effects:

[0011] In an embodiment of the present invention, the gate of the first reset transistor and the gate of the second reset transistor in the first pixel circuit are electrically connected to each other, and the two receive the same scan signal. Therefore, it is only necessary to set a scan line in the optical component setting area to provide a scan signal to the first reset transistor and the second reset transistor, and there is no need to set two separate scan lines to provide scan signals to the first reset transistor and the second reset transistor respectively. Accordingly, the number of scan lines running through the optical component setting area is reduced, thereby reducing the shielding of the optical component setting area by the scan lines, and increasing the area of ​​the light-transmitting area in the optical component setting area. When the display panel is shooting, more external ambient light will be incident on the camera assembly through the optical component setting area, so that the camera assembly can collect more external ambient light and optimize the imaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 It is a structural schematic diagram of a display panel in the prior art;

[0014] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 3 for Figure 2 A partial enlarged schematic diagram of the middle area A;

[0016] Figure 4 A circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 5 A schematic diagram of a connection between a first reset transistor and a second reset transistor in a first pixel circuit provided by an embodiment of the present invention;

[0018] Figure 6 A schematic diagram of the structure of the optical component arrangement area provided in an embodiment of the present invention;

[0019] Figure 7 Another connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0020] Figure 8 A schematic diagram of the layout of a single pixel area provided by an embodiment of the present invention;

[0021] Fig. 9 for Figure 7 The corresponding layout diagram;

[0022] Fig.10 A schematic diagram of a connection between a first scanning signal transmission line and a first scanning signal line provided by an embodiment of the present invention;

[0023] Fig.11 for Fig.10 The corresponding layout diagram;

[0024] Fig.12 Another schematic diagram of connection between the first scan signal transmission line and the first scan signal line provided by an embodiment of the present invention;

[0025] Fig.13 for Fig.12 The corresponding layout diagram;

[0026] Fig.14 A schematic diagram of the structure of the main display area provided by an embodiment of the present invention;

[0027] Fig.15 A schematic diagram of a connection between a first reset transistor and a second reset transistor in a second pixel circuit provided by an embodiment of the present invention;

[0028] Fig.16 for Fig.15 The corresponding layout diagram;

[0029] Fig.17 Another schematic diagram of the structure of the main display area provided by an embodiment of the present invention;

[0030] Fig.18 Another connection diagram of the first reset transistor and the second reset transistor in the second pixel circuit provided by an embodiment of the present invention;

[0031] Fig.19 for Fig.18 The corresponding layout diagram;

[0032] Fig. 20 A schematic diagram of another connection between the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0033] Fig.21 for Fig. 20 The corresponding layout diagram;

[0034] Fig. 22 for Fig.21 Cross-sectional view along the A1-A2 direction;

[0035] Fig.23A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0036] Fig.24 A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0037] Fig.25 A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0038] Fig.26 for Fig.25 The corresponding layout diagram;

[0039] Fig. 27 Another structural schematic diagram of the first scan signal transmission line and the first reset signal transmission line provided by an embodiment of the present invention;

[0040] Fig.28 A schematic diagram of the structure of a first connecting line provided in an embodiment of the present invention;

[0041] Fig.29 A schematic diagram of the film layer position of the first reset signal transmission line provided by an embodiment of the present invention;

[0042] Fig.30 for Fig.29 Cross-sectional view along the B1-B2 direction;

[0043] like Fig.31 As shown, Fig.31 A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0044] Fig.32 for Fig.31 The corresponding layout diagram;

[0045] Fig.33 A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0046] Fig.34 A schematic diagram of film layer positions of a sixth connecting wire and a seventh connecting wire provided in an embodiment of the present invention;

[0047] Fig.35 for Fig.34 Cross-sectional view along the C1-C2 direction;

[0048] Fig.36A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0049] Fig.37 for Fig.36 The corresponding layout diagram;

[0050] Fig.38 A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0051] Fig.39 A further connection diagram of the first reset transistor and the second reset transistor in the first pixel circuit provided by an embodiment of the present invention;

[0052] Fig.40 for Fig.39 The corresponding layout diagram;

[0053] Fig.41 A schematic diagram of the structure of a second reset signal transmission line and a third reset signal transmission line provided by an embodiment of the present invention;

[0054] Fig.42 Another structural schematic diagram of the second reset signal transmission line and the third reset signal transmission line provided by an embodiment of the present invention;

[0055] Fig.43 A schematic diagram of another structure of the second reset signal transmission line and the third reset signal transmission line provided by the embodiment of the present invention;

[0056] Fig.44 for Fig.43 A cross-sectional view along the D1-D2 direction;

[0057] Fig.45 A schematic diagram of another structure of the first connecting line provided in an embodiment of the present invention;

[0058] Fig.46 A schematic diagram of the structure of a light shielding portion provided by an embodiment of the present invention;

[0059] Fig.47 Another schematic diagram of the structure of the light shielding portion provided by an embodiment of the present invention;

[0060] Fig.48 A schematic diagram of another structure of the light shielding portion provided by an embodiment of the present invention;

[0061] Fig.49 A schematic diagram of another structure of the light shielding portion provided by an embodiment of the present invention;

[0062] Fig.50A schematic diagram of another structure of the light shielding portion provided by an embodiment of the present invention;

[0063] Fig.51 for Fig.50 Cross-sectional view along the E1-E2 direction;

[0064] Fig.52 A schematic diagram of another film layer position of the light shielding portion provided by an embodiment of the present invention;

[0065] Fig.53 A schematic diagram of the film layer positions of various metal layers in a display panel provided by an embodiment of the present invention;

[0066] Fig.54 A schematic diagram of the film layer position of the signal line in the main display area provided by an embodiment of the present invention;

[0067] Fig.55 A schematic diagram of a film layer position of a signal line in an optical component setting area provided in an embodiment of the present invention;

[0068] Fig.56 Another schematic diagram of the film layer position of the signal line in the optical component setting area provided in an embodiment of the present invention;

[0069] Fig.57 Another structural schematic diagram of a storage capacitor provided in an embodiment of the present invention;

[0070] Fig.58 A schematic diagram of the arrangement of various signal transmission lines in the optical component setting area provided in an embodiment of the present invention;

[0071] Fig.59 A schematic diagram of the structure of the main display area and the optical component setting area provided in an embodiment of the present invention;

[0072] Fig.60 A schematic diagram of a partial layout of a main display area and an optical component setting area provided in an embodiment of the present invention;

[0073] Fig.61 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0074] Fig.62 A schematic diagram of the structure of a shielding portion provided by an embodiment of the present invention;

[0075] Fig.63 A schematic structural diagram of a first scanning signal transmission line provided by an embodiment of the present invention;

[0076] Fig.64 A schematic diagram of the shape of the light-transmitting area provided in an embodiment of the present invention;

[0077] Fig.65A schematic diagram of the shape of a pixel area provided in an embodiment of the present invention;

[0078] Fig.66 A schematic diagram of the structure of a dummy routing provided by an embodiment of the present invention;

[0079] Fig.67 Another structural schematic diagram of a dummy routing provided by an embodiment of the present invention;

[0080] Fig.68 A schematic diagram of the structure of a second electrode provided by an embodiment of the present invention;

[0081] Fig.69 A schematic diagram of an arrangement of pixel areas provided by an embodiment of the present invention;

[0082] Fig.70 A schematic diagram of another arrangement of pixel areas provided by an embodiment of the present invention;

[0083] Fig.71 A schematic diagram of a structure of a pixel area provided by an embodiment of the present invention;

[0084] Fig.72 for Fig.71 Cross-sectional view along the G1-G2 direction;

[0085] Fig.73 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0086] Fig.74 for Fig.73 Cross-sectional view along the F1-F2 direction. DETAILED DESCRIPTION

[0087] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0088] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0089] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0090] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0091] It should be understood that although the terms first, second, third, etc. may be used to describe metal layers in embodiments of the present invention, these metal layers should not be limited to these terms. These terms are only used to distinguish metal layers from each other. For example, without departing from the scope of embodiments of the present invention, the first metal layer may also be referred to as the second metal layer, and similarly, the second metal layer may also be referred to as the first metal layer.

[0092] Combined with the analysis in the background technology, for display panels using under-screen camera technology, such as Figure 1 As shown, Figure 1 Schematic diagram of the structure of a display panel in the prior art. A plurality of pixel circuits 1' are arranged in the display area of ​​the panel. To drive the pixel circuits 1' to work normally, the transistors in the pixel circuits 1' are electrically connected to a plurality of signal wirings.

[0093] However, based on the circuit design of the existing pixel circuit 1', the number of signal lines electrically connected to the pixel circuit 1' is relatively large. For example, the scan lines electrically connected to the pixel circuit 1' include at least the first scan signal line Scan1', the second scan signal line Scan2' and the third scan signal line Scan3', and also include the light control signal line Emit', the reference signal line Vref' and the connection signal lines between other pixel circuits 1' (not shown in the figure), which results in a large number of signal lines running through the optical component setting area 2', blocking a large area of ​​the optical component setting area 2', and affecting its light transmittance.

[0094] An embodiment of the present invention provides a display panel, such as Figure 2 and Figure 3 As shown, Figure 2 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 3 for Figure 2A partial enlarged schematic diagram of the middle area A, the display panel includes a display area 1, the display area 1 includes an optical component setting area 2, in the direction perpendicular to the plane where the display panel is located, the optical component setting area 2 and the optical component (such as a camera, an infrared light sensor, etc.) at least partially overlap, the optical component setting area 2 includes a plurality of pixel areas 3, at least part of the adjacent two pixel areas 3 include a light-transmitting area 4. In the case where light passes through the optical component setting area 2, the light transmittance of the optical component setting area 2 can be greater than the light transmittance of the area other than the optical component setting area 2 in the display area 1. Among them, the outer edge shape of the optical component setting area 2 can be circular, square or other shapes, which can be designed according to actual needs, and the present application does not limit this.

[0095] The display panel also includes a plurality of pixels 5 located in the display area 1. The pixels 5 include a pixel circuit 6 and an organic light emitting element 7. The organic light emitting element 7 includes a first electrode and a second electrode (not shown in the figure). The first electrode and the second electrode are respectively one of an anode and a cathode, that is, when the first electrode is an anode, the second electrode is a cathode; when the first electrode is a cathode, the second electrode is an anode. Figure 4 As shown, Figure 4 A circuit schematic diagram of a pixel circuit 6 provided in an embodiment of the present invention, wherein the pixel circuit 6 includes a plurality of transistors, wherein the plurality of transistors include a first reset transistor M1, a second reset transistor M2 and a driving transistor M0, wherein the first reset transistor M1 transmits a voltage at a first electrode of the first reset transistor M1 to a gate of the driving transistor M0 in response to a corresponding scanning signal, thereby resetting the gate of the driving transistor M0, and the second reset transistor M2 transmits a voltage at a first electrode of the second reset transistor M2 to a first electrode of an organic light emitting element 7 in response to a corresponding scanning signal, thereby resetting the first electrode of the organic light emitting element 7.

[0096] It should be noted that Figure 4 The connection method between the gate and the first electrode of the first reset transistor M1 and the signal line, and the connection method between the gate and the first electrode of the second reset transistor M2 and the signal line in the pixel circuit shown in the figure are only schematic illustrations. The connection relationship between the first reset transistor M1 and the second reset transistor M2 and the signal line will be described in detail in the embodiments of the present invention later.

[0097] Among them, Figure 5 As shown, Figure 5This is a connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention. The pixel circuit 6 includes a first pixel circuit 8 located in the optical component setting area 2. The gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the first pixel circuit 8 are electrically connected. That is, the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 respond to the same scanning signal, and the gate of the driving transistor M0 and the first electrode of the organic light emitting element 7 are reset at the same time by the first reset transistor M1 and the second reset transistor M2.

[0098] In the embodiment of the present invention, the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the first pixel circuit 8 are electrically connected to each other, and the two receive the same scan signal. Therefore, only one scan line is required in the optical component setting area 2 to provide the scan signal to the first reset transistor M1 and the second reset transistor M2 at the same time, and there is no need to set two separate scan lines to provide the scan signal to the first reset transistor M1 and the second reset transistor M2 respectively. Accordingly, the number of scan lines running through the optical component setting area 2 is reduced, thereby reducing the shielding area of ​​the optical component setting area 2 by the scan lines, and increasing the area of ​​the light-transmitting area in the optical component setting area 2. When the display panel is taking front-end photos and videos, more external ambient light will be incident on the camera assembly through the optical component setting area 2, so that the camera assembly can collect more external ambient light, thereby optimizing the imaging quality.

[0099] In one embodiment, see again Figure 5 , the pixel area 3 includes at least one first pixel circuit 8, and the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the pixel area 3 are both electrically connected to the first scan signal line Scan1. For two adjacent pixel areas 3 in the first direction, the first scan signal line Scan1 electrically connected to the first pixel circuits 8 in the two pixel areas 3 is electrically connected through the first scan signal transmission line 9, so that the first scan signal transmission line 9 is used to connect the multiple first scan signal lines Scan1 arranged along the first direction in series to form a complete scan line, providing a continuous transmission path for the scan signal, and ensuring that the scan signal is normally written into the multiple first pixel circuits 8 arranged along the first direction.

[0100] Furthermore, if Figure 6~Figure 9 As shown, Figure 6 This is a schematic diagram of the structure of the optical component setting area 2 provided in an embodiment of the present invention. Figure 7 Another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention is shown in FIG. Figure 8A schematic diagram of the layout of a single pixel area 3 provided in an embodiment of the present invention, Fig. 9 for Figure 7 Corresponding layout schematic diagram, the first scan signal line Scan1 includes a first scan line segment Scan11 and a second scan line segment Scan12 located in the pixel area 3; the first scan line segment Scan11 is electrically connected to the gate of the first reset transistor M1, the second scan line segment Scan12 is electrically connected to the gate of the second reset transistor M2, and the first scan line segment Scan11 and the second scan line segment Scan12 are electrically connected through the first connecting wire 10. Optionally, the first scan signal line scan1 can realize the electrical connection between the gate of the first reset transistor M1 and the gate of the second reset transistor M2 through vias.

[0101] It should be noted that, for the sake of clarity, Figure 7 and Fig. 9 Only the first scanning signal transmission lines 9 between the first scanning signal lines Scan1 are illustrated, and transmission lines between other signal lines, such as the light emitting control signal line Emit, the power signal line PVDD, and the data line Data, will be described in detail in subsequent embodiments.

[0102] Combination Figure 8 In the layout of the first pixel circuit 8 shown, the positions of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 are far apart. By making the first scan signal line Scan1 include two routing segments, the first scan line segment Scan11 and the second scan line segment Scan12, in the layout design, the first scan line segment Scan11 can be extended at a position close to the first reset transistor M1, so that it is easier to be electrically connected to the gate of the first reset transistor M1, and at the same time, the second scan line segment Scan12 can be extended at a position close to the second reset transistor M2, so that it is easier to be electrically connected to the gate of the second reset transistor M2. On the one hand, the layout design is simple and compact, and the space utilization rate is high. On the other hand, this setting method does not need to change the setting position of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8, and only needs to adjust the routing design, and the design method is more flexible.

[0103] Also, see again Figure 8 The display panel also includes a virtual anode 90, which is arranged adjacent to a connecting line 92 between the second reset transistor M2 and the first electrode of the light-emitting element 7, and is used to form a coupling capacitor with the connecting line 92, thereby stabilizing the potential of the first electrode of the light-emitting element 7 by using the coupling capacitor, thereby improving the accuracy of the brightness of the light-emitting element 7.

[0104] Optional, please continue to see Figure 8Since there are multiple film layer structures between the first electrode of the light emitting element 7 and the source and drain of the second reset transistor M2, the distance between the two is relatively far along the direction perpendicular to the display panel. When the first electrode is electrically connected to the second reset transistor M2, the contact hole will be relatively deep and have a larger aperture, which will increase the non-transparent area. When the contact hole is deep, the etching process is more difficult than that of a shallow hole. Therefore, a transfer structure 93 can also be set in the third metal layer or the fourth metal layer, and the light emitting element 7 is electrically connected to the transfer structure 93 through the contact hole. The transfer structure 93 is also electrically connected to the second electrode or drain of the second reset transistor M2 through another contact hole. In the direction perpendicular to the plane where the display panel is located, the virtual anode 90 and the corresponding organic light emitting element 7 are electrically connected to the transfer structure 93 at least partially overlap, further stabilizing the potential of the first electrode of the organic light emitting element 7. Optionally, the virtual anode 90 can be electrically connected to the fixed potential signal terminal.

[0105] When the first scan signal line Scan1 includes a first scan line segment Scan11 and a second scan line segment Scan12, and the first scan line segment Scan11 and the second scan line segment Scan12 are electrically connected through the first connecting wiring 10, the first scan signal transmission line 9 can be directly connected to the first scan line segment Scan11, or directly connected to the second scan line segment Scan12, or directly connected to the first connecting wiring 10 to achieve electrical connection between the first scan signal transmission line 9 and the first scan signal line Scan1.

[0106] Moreover, the first scan signal transmission line 9 can also be arranged in the same layer as the first scan line segment Scan11, the second scan line segment Scan12 or the first connection line 10 directly connected thereto. In other words, the first scan signal transmission line 9 and the first scan line segment Scan11, the second scan line segment Scan12 or the first connection line 10 directly connected thereto are formed by the same patterning process.

[0107] For example, Fig.10 and Fig.11 As shown, Fig.10 A schematic diagram of the connection between the first scanning signal transmission line 9 and the first scanning signal line Scan1 provided in an embodiment of the present invention, Fig.11 for Fig.10 In the corresponding layout diagram, the first scanning signal transmission lines 9 on both sides of the pixel area 3 in the first direction are directly connected to the first scanning line segment Scan11 in the pixel area 3, and the first scanning signal transmission lines 9 and the first scanning line segment Scan11 are arranged in the same layer. This not only saves the process, but also realizes the electrical connection between the first scanning signal line Scan1 and the first scanning signal transmission line 9 without setting additional contact holes, thereby reducing the light-transmitting area occupied by the contact holes in the optical device setting area 2.

[0108] Or, if Fig.12 and Fig.13 As shown, Fig.12 Another connection diagram of the first scanning signal transmission line 9 and the first scanning signal line Scan1 provided in an embodiment of the present invention is shown in FIG. Fig.13 for Fig.12 In the corresponding layout diagram, the first scanning signal transmission line 9 on one side of the pixel area 3 in the first direction is directly connected to the first connecting line 10 in the pixel area 3, and the first scanning signal transmission line 9 and the first connecting line 10 are arranged in the same layer; the first scanning signal transmission line 9 on the other side of the pixel area 3 in the first direction is directly connected to the first scanning line segment Scan11 in the pixel area 3, and the first scanning signal transmission line 9 and the first scanning line segment Scan11 are arranged in the same layer. Not only does it save the process, but also, the electrical connection between the first scanning signal line Scan1 and the first scanning signal transmission line 9 can be realized without additionally setting contact holes, reducing the light-transmitting area occupied by the contact holes in the optical device setting area 2.

[0109] In addition, if the first scan signal transmission line 9 and the first scan line segment Scan11, the second scan line segment Scan12 or the first connection line 10 directly connected thereto are arranged in different layers, and the first scan signal transmission line 9 and the first scan line segment Scan11, the second scan line segment Scan12 or the first connection line 10 need to be electrically connected through a via, then there may be a risk of a circuit break caused by the discontinuity of the metal material deposited in the via. However, the first scan signal transmission line 9 and the first scan line segment Scan11, the second scan line segment Scan12 or the first connection line 10 directly connected thereto are in the same layer, and the first scan signal transmission line 9 and the first scan line segment Scan11, the second scan line segment Scan12 or the first connection line 10 connected thereto are formed using the same patterning process, and the two are connected to each other, so the connection reliability is higher and the signal transmission is more stable.

[0110] Further, please see again Figure 8, the two ends of the second scan line segment Scan12 can be electrically connected to the two ends of the first scan line segment Scan11 through a first connecting wire 10 respectively. In other words, along the first direction, a first connecting wire 10 located on one side of the pixel area 3 electrically connects the first end of the first scan line segment Scan11 with the first end of the second scan line segment Scan12; a first connecting wire 10 located on the other side of the pixel area 3 electrically connects the second end of the first scan line segment Scan11 with the second end of the second scan line segment Scan12. Such a setting can not only reduce the overall routing load of the first scan signal line Scan1, but also, when the display panel adopts a shift register for bilateral driving, when the scan signal is transmitted to the two ends of the first scan line segment Scan11, it can be transmitted to the two ends of the second scan line segment Scan12 through two first connecting wires 10 at the same time, and then transmitted from the two ends of the second scan line segment Scan12 to the middle, compared with the scan signal being transmitted from one end of the second scan line segment Scan12 to the other end, the write rate of the scan signal in the second reset transistor M2 can be improved.

[0111] In one embodiment, see again Figure 2 and Figure 3 The display area 1 also includes a main display area 11 arranged adjacent to the optical component setting area 2. For example, the main display area 11 can be arranged around the optical component setting area 2. The pixel circuit 6 also includes a second pixel circuit 12 located in the main display area 11.

[0112] The connection manner between the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the second pixel circuit 12 is exemplarily described below by taking two configuration manners as examples.

[0113] The first setting method:

[0114] like Figure 14~Figure 16 As shown, Fig.14 A schematic diagram of the structure of the main display area provided by an embodiment of the present invention, Fig.15 Schematic diagram of the connection between the first reset transistor M1 and the second reset transistor M2 in the second pixel circuit 12 provided in an embodiment of the present invention. Fig.16 for Fig.15 In the corresponding layout diagram, the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the second pixel circuit 12 are electrically connected. That is, the first reset transistor M1 and the second reset transistor M2 in the second pixel circuit 12 are turned on in response to the effective level of the same scanning signal, and the first reset transistor M1 and the second reset transistor M2 simultaneously reset the gate of the driving transistor M0 and the first electrode of the organic light emitting element 7.

[0115] Based on the above configuration, the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the first pixel circuit 8 and the second pixel circuit 12 both receive the same scan signal. Therefore, when setting the shift register for providing the scan signal, please refer to Fig.14 The scanning signals required by the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the pixel circuit only need to be provided by a set of shift registers 14, which reduces the number of shift registers 14 required to be set in the panel, thereby being more conducive to the narrow frame design of the display panel.

[0116] Further, please see again Fig.15 and Fig.16 , the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the second pixel circuit 12 arranged along the first direction are electrically connected to the second scan signal line Scan2; the second scan signal line Scan2 includes a third scan line segment Scan21 and a fourth scan line segment Scan22 located in the main display area 11, the third scan line segment Scan21 is electrically connected to the gate of the first reset transistor M1, the fourth scan line segment Scan22 is electrically connected to the gate of the second reset transistor M2, and the third scan line segment Scan21 and the fourth scan line segment Scan22 are electrically connected through the second connecting wiring 13.

[0117] Furthermore, for the first pixel circuits 8 and the second pixel circuits 12 arranged in the first direction, the first scanning signal line Scan1 electrically connected to the first pixel circuits 8 and the second scanning signal line Scan2 electrically connected to the second pixel circuits 12 are electrically connected.

[0118] It should be noted that the electrical connection between the second scan signal line Scan2 and the first scan signal line Scan1 can be achieved by directly connecting any one of the third scan line segment Scan21, the fourth scan line segment Scan22 and the second connecting line 13 to any one of the first scan line segment Scan11, the second scan line segment Scan12, the first connecting line 10 and the first scan signal transmission line 9. For example, please refer to Fig.14 When the main display area 11 is adjacent to the pixel area 3, the electrical connection between the second scan signal line Scan2 and the first scan signal line Scan1 can be achieved by directly connecting the third scan line segment Scan21 to the first scan line segment Scan11; when the main display area 11 is adjacent to the light-transmitting area 4, the electrical connection between the second scan signal line Scan2 and the first scan signal line Scan1 can be achieved by directly connecting the third scan line segment Scan21 to the first scan signal transmission line 9.

[0119] Combination Fig.16The layout of the second pixel circuit 12 shown in the figure makes the second scan signal line Scan2 include two routing segments, the third scan line segment Scan21 and the fourth scan line segment Scan22. In the layout design, the third scan line segment Scan21 can be extended at a position close to the first reset transistor M1, so that it is more convenient to be electrically connected to the gate of the first reset transistor M1, and the fourth scan line segment Scan22 can be extended at a position close to the second reset transistor M2, so that it is more convenient to be electrically connected to the gate of the second reset transistor M2. On the one hand, the layout design is simple and compact, and the space utilization rate is high. On the other hand, this setting method does not need to change the setting position of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8, and only needs to adjust the routing design, and the design method is more flexible.

[0120] In addition, to reduce the overall routing load of the second scan signal line Scan2, please refer to Fig.16 , two ends of the fourth scan line segment Scan22 can be electrically connected to two ends of the third scan line segment Scan21 through a second connecting wire 13 respectively.

[0121] The second setting method:

[0122] like Figure 17~Figure 19 As shown, Fig.17 Another structural schematic diagram of the main display area provided by an embodiment of the present invention, Fig.18 Another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the second pixel circuit 12 provided by an embodiment of the present invention is shown in FIG. Fig.19 for Fig.18 The corresponding layout schematic diagram shows that, for two second pixel circuits 12 adjacent to each other in the second direction, the gate of the second reset transistor M2 in the i-th second pixel circuit 12 and the gate of the first reset transistor M1 in the i+1-th second pixel circuit 12 are electrically connected to the fourth scanning signal line Scan4, where i is a positive integer greater than or equal to 1; and, for a plurality of second pixel circuits 12 arranged along the first direction, the gate of the first reset transistor M1 in the second pixel circuit 12 is electrically connected to the same fourth scanning signal line Scan4, and the gate of the second reset transistor M2 in the second pixel circuit 12 is electrically connected to the same fourth scanning signal line Scan4, and the second direction intersects with the first direction. In other words, for two second pixel circuits adjacent to each other in the second direction, the first reset transistor M1 in one of the second pixel circuits 12 can share a fourth scanning signal line Scan4 with the second reset transistor M2 in the other second pixel circuit 12, so that the number of fourth scanning signal lines Scan4 can be reduced, which is beneficial to improving the space utilization of the display panel, making the pixel circuits of the display panel more densely arranged, and improving the resolution of the display panel.

[0123] In addition, for the first pixel circuit 8 and the second pixel circuit 12 arranged along the first direction, the first scanning signal line Scan1 electrically connected to the first pixel circuit 8 and the fourth scanning signal line Scan4 electrically connected to the gate of the first reset transistor M1 in the second pixel circuit 12 are electrically connected, thereby realizing the transmission of the scanning signal and enabling the pixel circuit to work normally.

[0124] It should be noted that the electrical connection between the fourth scan signal line Scan4 and the first scan signal line Scan1 can be achieved by directly connecting the fourth scan signal line Scan4 to any one of the first scan line segment Scan11, the second scan line segment Scan12, the first connecting line 10 and the first scan signal transmission line 9. For example, please refer to Fig.17 When the main display area 11 is adjacent to the pixel area 3, the fourth scan signal line Scan4 can be electrically connected to the first scan signal line Scan1 by directly connecting to the first scan line segment Scan11; when the main display area 11 is adjacent to the light-transmitting area 4, the fourth scan signal line Scan4 can be electrically connected to the first scan signal line Scan1 by directly connecting to the first scan signal transmission line 9.

[0125] Based on the above-mentioned setting method, the driving cycle of the second pixel circuit 12 includes a first reset period and a second reset period. For two second pixel circuits 12 adjacent to each other in the second direction, in the first reset period of the previous second pixel circuit 12, the first reset transistor M1 responds to the scanning signal provided by the fourth scanning signal line Scan4 connected thereto to reset the gate of the driving transistor M0. In the second reset period of the previous second pixel circuit 12, the second reset transistor M2 responds to the scanning signal provided by the fourth scanning signal line Scan4 connected thereto to reset the gate of the driving transistor M0. At the same time, the next second pixel circuit 12 enters the first reset period, and the first reset transistor M1 in the next second pixel circuit 12 responds to the scanning signal to reset the gate of the driving transistor M0, thereby realizing sequential scanning.

[0126] Furthermore, when setting the shift register for providing the scanning signal using the above setting method, please refer to Fig.17 , it is still only necessary to use a group of shift registers 14 to provide the scan signal to the fourth scan signal line Scan4. The number of shift registers 14 required to be set in the display panel is small, and the border width of the panel is correspondingly narrow.

[0127] In one embodiment, Fig. 20 As shown, Fig. 20This is another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention, in which the first electrode of the first reset transistor M1 in the pixel area 3 is electrically connected to the first reset signal line Vref1, and the first electrode of the second reset transistor M2 is electrically connected to the first reset signal line Vref1. In addition, for two adjacent pixel areas 3, the first reset signal line Vref1 electrically connected to the first pixel circuit 8 in the pixel area 3 is electrically connected through the first reset signal transmission line 15. In other words, the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 respond to the same scanning signal, and use the same reset signal to reset the gate of the driving transistor M0 and the first electrode of the organic light emitting element 7 respectively.

[0128] In the above-mentioned setting method, the first electrode of the first reset transistor M1 and the first electrode of the second reset transistor M2 of the first pixel circuit 8 receive the same reset signal. Therefore, only one reset line needs to be set in the optical component setting area 2 to provide a reset signal to the first reset transistor M1 and the second reset transistor M2, thereby further reducing the number of signal lines passing through the optical component setting area 2, reducing the opaque area in the optical component setting area 2, and greatly improving the light transmittance of the optical component setting area 2.

[0129] The structure of the first reset signal line Vref1 is described below by taking two configuration modes as examples.

[0130] The first setting method:

[0131] Combination Fig. 20 ,like Fig.21 As shown, Fig.21 for Fig. 20 Corresponding layout schematic diagram, the pixel area 3 includes a plurality of first pixel circuits 8 arranged along a first direction, the first reset signal line Vref1 extends along a second direction, and the second direction intersects the first direction. The optical component setting area 2 also includes a third connection line 16 and a fourth connection line 17 extending along the first direction, the first electrode of the first reset transistor M1 in the pixel area 3 is electrically connected to the third connection line 16, and the third connection line 16 is electrically connected to the first reset signal line Vref1; the first electrode of the second reset transistor M2 in the pixel area 3 is electrically connected to the fourth connection line 17, and the fourth connection line 17 is also electrically connected to the first reset signal line Vref1.

[0132] It should be noted that, for the sake of clarity, Fig. 20 and Fig.21Only the first scan signal transmission line 9 between the first scan signal lines Scan1 and the first reset signal transmission line 15 between the first reset signal lines Vref1 are illustrated, and other signal lines, such as the transmission lines between the power signal lines PVDD and the data lines Data, will be described in detail in subsequent embodiments.

[0133] Based on this structure, the third connecting line 16 can be extended at a position close to the first reset transistor M1, making it easier to electrically connect the first electrode of the first reset transistor M1, and the fourth connecting line 17 can be extended at a position close to the second reset transistor M2, making it easier to electrically connect the first electrode of the second reset transistor M2. The layout design of this structure is simple and compact, with high space utilization. There is no need to change the setting positions of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8. Only the routing design needs to be adjusted, and the design method is more flexible.

[0134] In addition, it should be noted that in order to reduce the number of connection traces and optimize the layout design, please refer to Fig. 20 and Fig.21 The fourth connecting line 17 electrically connected to the first pixel circuit 8 in the i-th row and the third connecting line 16 electrically connected to the first pixel circuit 8 in the i+1-th row can be reused as one connecting line. At this time, the third connecting line 16 and the fourth connecting line 17 can pass through the light-transmitting area 4 and extend along the first direction in the entire optical component setting area 2. Based on this setting, the first reset signal line Vref1 and the first reset signal transmission line 15 connected in sequence in the second direction constitute a reset line, and the third connection line 16 and the fourth connection line 17 extending along the first direction form a grid structure with the reset line extending along the second direction. This grid structure can reduce the overall routing load of the reset line, thereby reducing the voltage drop of the reset signal when it is transmitted on the first reset signal line Vref1, so that the voltage value of the reset signal when it is transmitted to the gate of the driving transistor M0 and the first electrode of the organic light-emitting element in the first pixel circuit 8 at different positions tends to be consistent, thereby improving the uniformity of the reset degree of the driving transistor M0 and the organic light-emitting element 7 in different first pixel circuits 8, avoiding the difference in charging effect of the pixel circuit due to the voltage drop of the reset signal line, and thus improving the display effect of the display panel.

[0135] Furthermore, if Fig. 22 As shown, Fig. 22 for Fig.21 In the cross-sectional view along the A1-A2 direction, the display panel includes a semiconductor layer 18 and a first metal layer 19 stacked along the light emitting direction of the display panel, the gate g of the transistor is located in the first metal layer 19, the first pole s of the transistor and the second pole d of the transistor are located in the semiconductor layer 18, and the third connecting wiring 16 and the fourth connecting wiring 17 are located in the semiconductor layer 18.

[0136] Compared with metal materials, semiconductor materials have higher light transmittance. Therefore, forming the third connecting wire 16 and the fourth connecting wire 17 with semiconductor materials can improve the light transmittance of the third connecting wire 16 and the fourth connecting wire 17, and part of the ambient light can penetrate the third connecting wire 16 and the fourth connecting wire 17 into the camera assembly, thereby increasing the light transmittance of the optical component setting area and further increasing the amount of light that can be collected by the camera assembly. At the same time, the third connecting wire 16 and the fourth connecting wire 17 are located in the semiconductor layer 16, which can avoid the signal lines in the pixel circuit being concentrated in the metal layer, optimize the layout of the pixel circuit, reduce the space occupied by the pixel circuit, and thus improve the space utilization of the display panel.

[0137] In addition, if Fig.23 As shown, Fig.23 This is another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided by an embodiment of the present invention. The first pixel circuit 8 in each pixel area 3 can be electrically connected to two first reset signal lines Vref1, so that the first reset signal lines Vref1 form a parallel structure, further reducing the load of the reset line. Moreover, the first reset signal line Vref1 can be formed of a metal material with higher conductivity.

[0138] In addition, if Fig.24 As shown, Fig.24 Another connection schematic diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention, the first reset signal line Vref1 and the first reset signal transmission line 15 sequentially connected in the second direction constitute a reset line, the first pixel circuit 8 in the i-th column and the first pixel circuit 8 in the i+1-th column can be connected to the same reset line, wherein i is an odd number. At this time, compared with each column of the first pixel circuit 8 being electrically connected to a reset line, the number of reset lines set in the optical component setting area 2 is reduced, and the layout design is more concise and compact.

[0139] The second setting method:

[0140] like Fig.25 and Fig.26 As shown, Fig.25 This is another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention. Fig.26 for Fig.25Corresponding layout schematic diagram, the first reset signal line Vref1 includes a first reset line segment Vref11 and a second reset line segment Vref12 located in the pixel area 3; the first reset line segment Vref11 is electrically connected to the first electrode of the first reset transistor M1, the second reset line segment Vref12 is electrically connected to the first electrode of the second reset transistor M2, and the second reset line segment Vref12 is electrically connected to the first reset line segment Vref11 through the fifth connecting line 20. The first reset line segment Vref11, the second reset line segment Vref12, the first scan line segment Scan11 and the second scan line segment Scan12 extending in the same direction can be arranged in the same layer.

[0141] It should be noted that, for the sake of clarity, Fig.25 and Fig.26 Only the first scan signal transmission line 9 between the first scan signal lines Scan1 and the first reset signal transmission line 15 between the first reset signal lines Vref1 are illustrated, and other signal lines, such as the transmission lines between the power signal line PVDD and the data line Data, will be described in detail in subsequent embodiments.

[0142] In the above-mentioned setting, the first reset line segment Vref11 extends at a position close to the first reset transistor M1, and the second reset line segment Vref12 extends at a position close to the second reset transistor M2, so that the first reset line segment Vref11 is more convenient to be electrically connected to the first electrode of the first reset transistor M1, and the second reset line segment Vref12 is more convenient to be electrically connected to the first electrode of the second reset transistor M2, thereby reducing the difficulty of connecting the first reset signal line Vref1 with the first reset transistor M1 and the second reset transistor M2.

[0143] Moreover, when the first reset signal line Vref1 includes a first reset line segment Vref11 and a second reset line segment Vref12, and the second reset line segment Vref12 and the first reset line segment Vref11 are electrically connected through the fifth connecting line 20, the first reset signal transmission line 15 can be electrically connected to the first reset signal line Vref11 by directly connecting to the first reset line segment Vref11, or directly connecting to the second reset line segment Vref12, or directly connecting to the fifth connecting line 20.

[0144] Furthermore, the first reset signal transmission line 15 and the first reset line segment Vref11, the second reset line segment Vref12 or the fifth connection line 20 directly connected thereto are arranged on the same layer. Fig.25 and Fig.26The first reset signal transmission lines 15 on both sides of the pixel area 3 in the first direction are directly connected to the fifth connection wiring 20 in the pixel area 3, and the first reset signal transmission lines 15 and the fifth connection wiring 20 are arranged on the same layer.

[0145] The first reset signal transmission line 15 is on the same layer as the first reset line segment Vref11, the second reset line segment Vref12 or the fifth connecting line 20 directly connected thereto. The first reset signal transmission line 15 is formed by the same patterning process as the first reset line segment Vref11, the second reset line segment Vref12 or the fifth connecting line 20 connected thereto. The two are connected to each other, and the connection reliability is higher, avoiding the circuit breakage caused by the discontinuity of the metal material in the connecting via. At the same time, there is no need to set up additional vias, which reduces the opaque area in the optical component setting area and improves the light transmittance.

[0146] In one embodiment, see again Fig.26 The light-transmitting area 4 includes a first main light-transmitting area 21 and a first auxiliary light-transmitting area 22. The first main light-transmitting area 21 and the first auxiliary light-transmitting area 22 are arranged along the second direction, and at least part of the first reset signal transmission line 15 and the first scan signal transmission line 9 extend in the first auxiliary light-transmitting area 22.

[0147] If the light-transmitting area 4 is divided into several scattered light-transmitting areas by the first reset signal transmission line 15 and the first scanning signal transmission line 9 that penetrate through it, the external ambient light is easily diffracted between the lines or at the edges of the lines when it enters the light-transmitting area 4. Based on the above arrangement, the first reset signal transmission line 15 and the first scanning signal transmission line 9 are concentrated and extended in a part of the light-transmitting area 4, thereby centralizing the areas blocked by the lines and the areas not blocked by the lines in the light-transmitting area 4, thereby effectively reducing the diffraction phenomenon.

[0148] It should be noted that when the first reset signal transmission line 15 and the first scanning signal transmission line 9 are concentrated and extended in the first auxiliary light-transmitting area 22, a shading portion can also be set in the first auxiliary light-transmitting area 22 to fully cover the first auxiliary light-transmitting area 22, or to cover the gap between the first reset signal transmission line 15 and the first scanning signal transmission line 9 in the first auxiliary light-transmitting area 22, so as to eliminate diffraction to a greater extent.

[0149] In one embodiment, Fig. 27 As shown, Fig. 27Another structural schematic diagram of the first scanning signal transmission line 9 and the first reset signal transmission line 15 provided in an embodiment of the present invention, the first reset signal transmission line 15 and the first scanning signal transmission line 9 are arranged in different layers, and in the direction perpendicular to the plane where the display panel is located, the projection of the first reset signal transmission line 15 and the projection of the first scanning signal transmission line 9 at least partially overlap, thereby reducing the overall shielding degree of the first reset signal transmission line 15 and the first scanning signal transmission line 9 on the light-transmitting area 4, increasing the area of ​​the area in the light-transmitting area 4 that is not shielded by the wiring, and further improving the light transmittance of the optical component setting area 2. Further, in the direction perpendicular to the plane where the display panel is located, it is also possible to set the gap between the projections of at least two of the multiple signal lines in the light-transmitting area 4 to be at least partially covered by the projection of the third signal line, that is, the signal lines cover and shield each other, so as to eliminate or weaken the light diffraction problem caused by the wiring gap, and improve the imaging effect of the optical component. It can be understood that the wiring that can transmit signals can be understood as signal lines.

[0150] In one embodiment, Fig.28 As shown, Fig.28 A structural schematic diagram of the first connecting wiring 10 provided in an embodiment of the present invention, the first connecting wiring 10 includes a first end 23 and a second end 24, in a direction perpendicular to the plane where the display panel is located, the projection of the first end 23 is located on a side where the projection of the first scanning line segment Scan11 is away from the projection of the second scanning line segment Scan12, and the projection of the second end 24 is located on a side where the projection of the second scanning line segment Scan12 is away from the projection of the first scanning line segment Scan11; in a direction perpendicular to the plane where the display panel is located, the projection of the first end 23 overlaps with the projection of the first reset line segment Vref11, and / or the projection of the second end 24 overlaps with the projection of the second reset line segment Vref12.

[0151] Combination Fig.17Based on the setting mode of the first scan signal line Scan1, the first scan line segment Scan11 and the second scan line segment Scan12 are connected in parallel through the first connecting line 10, which reduces the overall routing load of the first scan signal line Scan1, so that there is a certain difference between the load of the first scan signal line Scan4 in the main display area 11. To this end, by increasing the extension length of the first connecting line 10, the first end 23 of the first connection line overlaps with the first reset line segment Vref11 and / or the second end 24 overlaps with the second reset line segment Vref12, and a coupling capacitor is formed between the first end 23 and the first reset line segment Vref11 and / or the second end 24 and the second reset line segment Vref12. The coupling capacitor can compensate for the load difference between the first scan signal line Scan1 and the fourth scan signal line Scan4, so that the voltage drop of the scan signal transmitted in the main display area 11 and the optical component setting area 2 tends to be consistent.

[0152] In one embodiment, Fig.29 and Fig.30 As shown, Fig.29 A schematic diagram of the film layer position of the first reset signal transmission line 15 provided in an embodiment of the present invention, Fig.30 for Fig.29 In the cross-sectional view along the B1-B2 direction, the display panel includes a semiconductor layer 18 and a first metal layer 19, the gate g of the transistor is located in the first metal layer 19, the first electrode s of the transistor and the second electrode d of the transistor are located in the semiconductor layer 18, and the first reset signal transmission line 15 is located in the semiconductor layer 18.

[0153] Compared with the first reset signal transmission line 15 formed of metal material, the first reset signal transmission line 15 is located in the semiconductor layer 18, which improves the light transmittance of the first reset signal transmission line 15 and reduces the degree of shielding of the light-transmitting area 4 by the first reset signal transmission line 15, thereby allowing more external ambient light to pass through the optical component setting area 2 and enter the camera assembly.

[0154] In one embodiment, Fig.31 As shown, Fig.31This is another connection schematic diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention, wherein the first electrode of the first reset transistor M1 in the pixel area 3 is electrically connected to the second reset signal line Vref2, and the second reset signal line Vref2 connected to the first pixel circuits 8 in two adjacent pixel areas 3 is electrically connected through the second reset signal transmission line 25, and the second reset signal line Vref2 is connected to the first voltage terminal (not shown in the figure); the first electrode of the second reset transistor M2 in the pixel area 3 is electrically connected to the third reset signal line Vref3, and the third reset signal line Vref3 connected to the first pixel circuits 8 in two adjacent pixel areas 3 is electrically connected through the third reset signal transmission line 26, and the third reset signal line Vref3 is connected to the second voltage terminal (not shown in the figure).

[0155] The first voltage terminal and the second voltage terminal are used to provide different reset signals. In an embodiment of the present invention, the voltage of the reset signal provided by the second voltage terminal is smaller than the voltage of the reset signal provided by the first voltage terminal.

[0156] In the above configuration, the first electrode of the first reset transistor M1 and the first electrode of the second reset transistor M2 are electrically connected to different reset signal lines respectively, and the first reset transistor M1 and the second reset transistor M2 transmit different reset signals respectively to reset the gate of the driving transistor M0 and the first electrode of the organic light emitting element 7 respectively. Further, since the voltage of the reset signal received by the second reset transistor M2 is relatively low, a relatively low reset potential can be provided to the first electrode (for example, the anode) of the organic light emitting element 7, so as to avoid raising the voltage of the first electrode of the organic light emitting element 7 due to the influence of the leakage current during the non-light emitting period, so that the potential difference between the first electrode and the second electrode of the organic light emitting element 7 reaches the condition for driving it to emit light, and the relatively low reset signal voltage can ensure that the organic light emitting element 7 does not emit light during the non-light emitting period, and effectively improve the phenomenon of stealing light of the pixel. Since the voltage of the reset signal received by the second reset transistor M2 is slightly higher, it is possible to avoid writing an excessively low reset signal to the gate of the driving transistor M0. In this way, after the gate of the driving transistor M0 is reset, when the data signal is written to the gate of the driving transistor M0, it can be written based on a slightly higher low-level potential, thereby reducing the voltage difference between the initial potential of the gate of the driving transistor M0 and the data signal to be written, thereby allowing the data signal to be written more fully during the charging period.

[0157] The following takes two configuration modes as examples to illustrate the structures of the second reset signal line Vref2 and the third reset signal line Vref3.

[0158] The first setting method:

[0159] Combination Fig.31,like Fig.32 As shown, Fig.32 for Fig.31 Corresponding layout schematic diagram, the pixel area 3 includes a plurality of first pixel circuits 8 arranged along the first direction, the second reset signal line Vref2 and the third reset signal line Vref3 extend along the second direction, and the second direction intersects with the first direction; the optical component setting area 2 also includes a sixth connecting wire 27 and a seventh connecting wire 28 extending along the first direction, the first electrode of the first reset transistor M1 in the pixel area 3 is electrically connected to the sixth connecting wire 27, and the sixth connecting wire 27 is also electrically connected to the second reset signal line Vref2; the first electrode of the second reset transistor M2 in the pixel area 3 is electrically connected to the seventh connecting wire 28, and the seventh connecting wire 28 is also electrically connected to the third reset signal line Vref3.

[0160] It should be noted that, for the sake of clarity, Fig.31 and Fig.32 Only the first scan signal transmission line 9 between the first scan signal lines Scan1, the second reset signal transmission line 25 between the second reset signal lines Vref2, and the third reset signal transmission line 26 between the third reset signal lines Vref3 are illustrated. Other signal lines, such as the transmission lines between the power signal lines PVDD and the data lines Data, will be described in detail in subsequent embodiments.

[0161] Based on this structure, the sixth connecting line 27 can be extended at a position close to the first reset transistor M1, making it easier to electrically connect the first pole of the first reset transistor M1, and the seventh connecting line 28 can be extended at a position close to the second reset transistor M2, making it easier to electrically connect the first pole of the second reset transistor M2. The layout design of this structure is simple and compact, with high space utilization. There is no need to change the setting positions of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8. Only the routing design needs to be adjusted, and the design method is more flexible.

[0162] In addition, the second reset signal line Vref2 and the second reset signal transmission line 25 sequentially connected in the second direction constitute a first reset line, and the third reset signal line Vref3 and the third reset signal transmission line 26 sequentially connected in the second direction constitute a second reset line. Fig.33 As shown, Fig.33This is another connection schematic diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention. The sixth connection wiring 27 and the seventh connection wiring 28 can pass through the light-transmitting area 4 and extend along the first direction in the entire optical component setting area 2. At this time, the sixth connection wiring 27 extending along the first direction and the first reset wiring extending along the second direction form a grid structure, and the seventh connection wiring 28 extending along the first direction and the second reset wiring extending along the second direction form a grid structure. This grid structure can reduce the wiring load of the reset wiring, thereby reducing the voltage drop during the reset signal transmission.

[0163] Further, please see again Fig.33 To further reduce the number of reset signal lines, the first pixel circuit 8 in the i-th column and the first pixel circuit 8 in the i+1-th column are connected to the same first reset line. The first pixel circuit 8 in the i-th column and the first pixel circuit 8 in the i-1-th column are connected to the same second reset line, where i is an even number.

[0164] In one embodiment, Fig.34 and Fig.35 As shown, Fig.34 A schematic diagram of the film layer positions of the sixth connecting wiring 27 and the seventh connecting wiring 28 provided in an embodiment of the present invention, Fig.35 for Fig.34 In the cross-sectional view along the C1-C2 direction, the display panel includes a semiconductor layer 18, the first electrode of the transistor and the second electrode of the transistor are located in the semiconductor layer 18, and the sixth connecting wire 27 and the seventh connecting wire 28 are located in the semiconductor layer 18, thereby improving the transmittance of the sixth connecting wire 27 and the seventh connecting wire 28, and part of the ambient light can pass through the sixth connecting wire 27 and the seventh connecting wire 28 to enter the camera assembly, further increasing the amount of light that can be collected by the camera assembly.

[0165] Further, please see again Fig.31 and Fig.32 The pixel area 3 includes x first pixel circuits 8 arranged along the first direction, the second reset signal line Vref2 is located on the side of the first first pixel circuit 8 away from the second first pixel circuit 8, and the third reset signal line Vref3 is located on the side of the xth first pixel circuit 8 away from the x-1th first pixel circuit 8.

[0166] The light-transmitting area 4 includes a second main light-transmitting area 29 and two second auxiliary light-transmitting areas 30. One second auxiliary light-transmitting area 30, the second main light-transmitting area 29 and another second auxiliary light-transmitting area 30 are arranged along the first direction. At least part of the second reset signal transmission line 25 extends in the second auxiliary light-transmitting area 30, and at least part of the third reset signal transmission line 26 extends in the second auxiliary light-transmitting area 30. At this time, the second reset signal transmission line 25 and the third reset signal transmission line 26 extend on both sides of the light-transmitting area 4, respectively, so that the area in the light-transmitting area 4 that is not blocked by the wiring is centralized, the diffraction phenomenon caused by the external ambient light entering the light-transmitting area 4 is weakened, and the light transmission effect is improved.

[0167] Or, in another embodiment, Fig.36 and Fig.37 As shown, Fig.36 This is another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention. Fig.37 for Fig.36 Corresponding layout schematic diagram, the pixel area 3 includes x first pixel circuits 8 arranged along the first direction; the light-transmitting area 4 includes a third main light-transmitting area 31 and a third auxiliary light-transmitting area 32, the third main light-transmitting area 31 and the third auxiliary light-transmitting area 32 are arranged along the first direction, and at least part of the second reset signal transmission line 25 and the third reset signal transmission line 26 extend in the third auxiliary light-transmitting area 32.

[0168] The second reset signal line Vref2 and the third reset signal line Vref3 are located on the side of the first first pixel circuit 8 away from the second first pixel circuit 8, and the direction of the third auxiliary light-transmitting area 32 pointing to the third main light-transmitting area 31 is the same as the direction of the first first pixel circuit 8 pointing to the second first pixel circuit 8; or, the second reset signal line Vref2 and the third reset signal line Vref3 are located on the side of the x-th first pixel circuit 8 away from the x-1-th first pixel circuit 8, where x is a positive integer greater than or equal to 2, and the direction of the third auxiliary light-transmitting area 32 pointing to the third main light-transmitting area 31 is opposite to the direction of the first first pixel circuit 8 pointing to the second first pixel circuit 8.

[0169] Based on the above arrangement, the second reset signal transmission line 25 and the third reset signal transmission line 26 are both extended on the same side of the light-transmitting area 4, and the areas in the light-transmitting area 4 that are blocked by the wiring and those that are not blocked by the wiring are centralized, effectively reducing the diffraction phenomenon when the external ambient light enters the light-transmitting area 4. Furthermore, the diffraction can be eliminated to a greater extent by arranging a shading portion in the third auxiliary light-transmitting area 32, using the shading portion to cover the third auxiliary light-transmitting area 32, or covering the gap between the second reset signal transmission line 25 and the third reset signal transmission line 26. In addition, the second reset signal line Vref2 and the third reset signal line Vref3 extend on the same side as the second reset signal transmission line 25 and the third reset signal transmission line 26, and the length of the reset wiring formed by the reset signal line and the reset signal transmission line can also be reduced, thereby reducing the voltage drop of the reset signal during transmission.

[0170] The second reset signal line Vref2 and the second reset signal transmission line 25 sequentially connected in the second direction form a first reset line, and the third reset signal line Vref3 and the third reset signal transmission line 26 sequentially connected in the second direction form a second reset line. Fig.38 As shown, Fig.38 Another connection schematic diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention, the sixth connection wiring 27 and the seventh connection wiring 28 can pass through the light-transmitting area 4. At this time, the sixth connection wiring 27 extending along the first direction and the first reset wiring extending along the second direction form a grid structure, and the seventh connection wiring 28 extending along the first direction and the second reset wiring extending along the second direction form a grid structure. This grid structure can reduce the wiring load of the reset wiring, thereby reducing the voltage drop during the reset signal transmission.

[0171] Further, please see again Fig.38 To further reduce the number of reset lines, the first pixel circuit 8 in the i-th column and the first pixel circuit 8 in the i+1-th column are electrically connected to the same first reset line, and the first pixel circuit 8 in the i-th column and the first pixel circuit 8 in the i+1-th column are connected to the same second reset line, where i is an odd number.

[0172] The second setting method:

[0173] like Fig.39 and Fig.40 As shown, Fig.39 This is another connection diagram of the first reset transistor M1 and the second reset transistor M2 in the first pixel circuit 8 provided in an embodiment of the present invention. Fig.40 for Fig.39Corresponding layout schematic diagram, the second reset signal line Vref2 and the third reset signal line Vref3 extend along the first direction in the pixel area 3 respectively. Among them, the second reset signal line Vref2 extends at a position close to the first reset transistor M1, so that it is easier to electrically connect to the gate of the first reset transistor M1, and at the same time, the third reset signal line Vref3 extends at a position close to the second reset transistor M2, so that it is easier to electrically connect to the gate of the second reset transistor M2. Among them, the second reset signal line Vref2, the third reset signal line Vref3, the first scan line segment Scan11 and the second scan line segment Scan12 extending in the same direction can be arranged in the same layer.

[0174] It should be noted that, for the sake of clarity, Fig.39 and Fig.40 Only the first scan signal transmission line 9 between the first scan signal lines Scan1, the second reset signal transmission line 25 between the second reset signal lines Vref2, and the third reset signal transmission line 26 between the third reset signal lines Vref3 are illustrated. Other signal lines, such as the transmission lines between the power signal lines PVDD and the data lines Data, will be described in detail in subsequent embodiments.

[0175] In the above-mentioned setting, the extension direction of the second reset signal line Vref2 and the third reset signal line Vref3 is the same as the arrangement direction of the multiple first pixel circuits 8 in the pixel area 3. The second reset signal line Vref2 can be directly connected to the first electrode of the first reset transistor M1 in the multiple first pixel circuits 8 in the pixel area 3 through multiple vias. When the pixel area 3 includes multiple first pixel circuits 8, the third reset signal line Vref3 can be directly connected to the first electrode of the second reset transistor M2 in the multiple first pixel circuits 8 through multiple vias. There is no need to set a connecting line electrically connected between the second reset signal line Vref2 and the first electrode of the first reset transistor M1, and between the third reset signal line Vref3 and the first electrode of the second reset transistor M2, thereby simplifying the wiring design.

[0176] In one embodiment, Fig.41 As shown, Fig.41Schematic diagram of the structure of the second reset signal transmission line 25 and the third reset signal transmission line 26 provided in an embodiment of the present invention, the light-transmitting area 4 includes a fourth main light-transmitting area 33 and a fourth auxiliary light-transmitting area 34, the fourth auxiliary light-transmitting area 34 and the fourth main light-transmitting area 33 are arranged along the first direction, the fourth main light-transmitting area 33 includes a first sub-area 39, a second sub-area 40 and a third sub-area 41 arranged along the second direction, and the second direction intersects with the first direction; the second reset signal transmission line 25 includes a first reset transmission line segment 35 located in the fourth auxiliary light-transmitting area 34 and a third sub-area 41 located in the fourth auxiliary light-transmitting area 34. In the second reset transmission line segment 36 of the second sub-area 40, the third reset signal transmission line 26 includes a third reset transmission line segment 37 located in the fourth auxiliary light-transmitting area 34 and a fourth reset transmission line segment 38 located in the second sub-area 40; along the direction from the fourth auxiliary light-transmitting area 34 to the fourth main light-transmitting area 33, the spacing between the first reset transmission line segment 35 and the third reset transmission line segment 37 decreases gradually. In other words, the shortest distance between the first reset transmission line segment 35 and the third reset transmission line segment 37 gradually decreases, and the two tend to be centrally arranged in the light-transmitting area 4.

[0177] In this arrangement, while the area in the light-transmitting area 4 that is not blocked by the routing is centralized to reduce diffraction, the first reset transmission line segment 35 and the third reset transmission line segment 37 both extend toward the second sub-area 40 at the middle position of the fourth main light-transmitting area 33, and the extension lengths of the first reset transmission line segment 35 and the third reset transmission line segment 37 tend to be consistent, thereby making the routing loads of the first reset signal transmission line 15 and the second reset signal transmission line 25 tend to be consistent.

[0178] In one embodiment, Fig.42 As shown, Fig.42 Another structural schematic diagram of the second reset signal transmission line 25 and the third reset signal transmission line 26 provided in an embodiment of the present invention, the second reset signal transmission line 25 and the third reset signal transmission line 26 are arranged in a different layer from the first scanning signal transmission line 9, and in the direction perpendicular to the plane where the display panel is located, the projection of the second reset signal transmission line 25 and / or the third reset signal transmission line 26 overlaps with the projection of the first scanning signal transmission line 9, thereby reducing the overall shielding degree of the three parts of the second reset signal transmission line 25, the third reset signal transmission line 26 and the first scanning signal transmission line 9 on the light-transmitting area 4, increasing the area of ​​the light-transmitting area 4 not blocked by the wiring, and further improving the light transmittance of the optical component setting area 2.

[0179] In one embodiment, Fig.43 and Fig.44 As shown, Fig.43 Another structural diagram of the second reset signal transmission line 25 and the third reset signal transmission line 26 provided in an embodiment of the present invention is shown in FIG. Fig.44 for Fig.43In the cross-sectional view along the D1-D2 direction, the display panel includes a semiconductor layer 18 and a first metal layer 19 stacked along the light emitting direction of the display panel, the gate g of the transistor is located in the first metal layer 19, the first pole s of the transistor and the second pole d of the transistor are located in the semiconductor layer 18, and the second reset signal transmission line 25 and the third reset signal transmission line 26 are located in the semiconductor layer 18, thereby improving the transmittance of the second reset signal transmission line 25 and the third reset signal transmission line 26, and reducing the degree of shielding of the light-transmitting area 4 by the second reset signal transmission line 25 and the third reset signal transmission line 26, thereby allowing more external ambient light to pass through the optical component setting area 2 and enter the camera assembly, thereby increasing the amount of external ambient light collected by the camera assembly.

[0180] Furthermore, if Fig.45 As shown, Fig.45 Another structural schematic diagram of the first connecting wiring 10 provided in an embodiment of the present invention, the first connecting wiring 10 includes a first end 23 and a second end 24, in the direction perpendicular to the plane where the display panel is located, the projection of the first end 23 is located on the side where the projection of the first scan line segment Scan11 is away from the projection of the second scan line segment Scan12, and the projection of the second end 24 is located on the side where the projection of the second scan line segment Scan12 is away from the projection of the first scan line segment Scan11; and, in the direction perpendicular to the plane where the display panel is located, the projection of the first end 23 overlaps with the projection of the second reset signal line Vref2, and / or the projection of the second end 24 overlaps with the projection of the third reset signal line Vref3.

[0181] Combination Fig.17 Based on the setting mode of the first scan signal line Scan1, the first scan line segment Scan11 and the second scan line segment Scan12 are connected in parallel through the first connecting wire 10, which reduces the overall routing load of the first scan signal line Scan1, so that there is a certain difference between the load of the first scan signal line Scan4 in the main display area 11. To this end, by increasing the extension length of the first connecting wire 10, the first end 23 of the first connecting wire 10 overlaps with the second reset signal line Vref2 and / or the second end 24 overlaps with the third reset signal line Vref3, and a coupling capacitor is formed between the first end 23 and the second reset signal line Vref2 and / or the second end 24 and the third reset signal line Vref3. The coupling capacitor can compensate for the load difference between the first scan signal line Scan1 and the fourth scan signal line Scan4, so that the voltage drop of the scan signal transmitted in the main display area 11 and the optical component setting area 2 tends to be consistent. Optionally, the line width of the first end 23 and / or the second end 24 may be increased, so that the overlapping area between the first end 23 or the second end 24 and the first scanning signal line scan1 may be increased in a direction perpendicular to the plane where the display panel is located.

[0182] It is understandable that the first pixel circuit 8 includes multiple metal layers for forming transistors, and there are gaps between the multiple metal layers, and there are also gaps between the signal traces included in the metal layers. When the display panel is shooting, part of the external ambient light is easily diffracted when it enters through these gaps, thereby affecting the image quality. For this reason, in one embodiment, Fig.46 and Fig.47 As shown, Fig.46 Schematic diagram of the structure of the light shielding portion 39 provided in an embodiment of the present invention, Fig.47 Another structural schematic diagram of the shading portion 39 provided in an embodiment of the present invention, the display panel further includes a shading portion 39 located in the optical component setting area 2, and in a direction perpendicular to the plane where the display panel is located, the shading portion 39 covers at least a portion of the first pixel circuit 8, so that the shading portion 39 is used to block the gaps between the metal layers to weaken the diffraction phenomenon. Optional, please continue to refer to Fig.46 and Fig.47 The pixel area may include pixels of multiple colors, for example, at least one red pixel (R), one green pixel (G) and one blue pixel (B), or other color pixels that can emit white light in combination.

[0183] In one embodiment, Fig.48 As shown, Fig.48 The present invention provides another structural schematic diagram of the shading portion 39 provided in an embodiment of the present invention. The shading portion 39 is electrically connected to a reset signal terminal (not shown in the figure). The shading portion 39 is also electrically connected to a first electrode of a first reset transistor M1 through a first via 40, and is electrically connected to a first electrode of a second reset transistor M2 through a second via 41. Furthermore, two adjacent shading portions 39 are electrically connected to an eighth connecting wiring 43.

[0184] In this arrangement, the light shielding portion 39 can directly transmit the reset signal to the first electrode of the first reset transistor M1 and the first electrode of the second reset transistor M2, and no additional reset signal line is required in the optical component arrangement area 2, thereby simplifying the structural design of the panel. Moreover, compared with the wiring structure, the light shielding portion 39 with a planar design has a smaller load, thereby also reducing the voltage drop of the reset signal when it is transmitted in the light shielding portion 39.

[0185] Or, in another embodiment, in combination Figure 4 ,like Fig.49 As shown, Fig.49This is another structural schematic diagram of the light shielding portion 39 provided in an embodiment of the present invention, wherein the multiple transistors further include a power supply voltage writing transistor M3, the gate of the power supply voltage writing transistor M3 is electrically connected to the light emission control signal line Emit, and the second electrode of the power supply voltage writing transistor M3 is electrically connected to the first electrode of the driving transistor M0. The light shielding portion 39 is electrically connected to the power supply signal terminal (not shown in the figure), and the light shielding portion 39 is also electrically connected to the first electrode of the power supply voltage writing transistor M3 through a third via 44, and two adjacent light shielding portions 39 are electrically connected through a ninth connecting wire 45 provided on the same layer as the light shielding portion 39.

[0186] In this arrangement, the light shielding portion 39 can directly transmit the power signal to the first electrode of the power voltage writing transistor M3, and no additional power signal line is required in the optical component setting area 2, thereby simplifying the structural design of the panel. Moreover, compared with the wiring structure, the light shielding portion 39 with a planar design has a smaller load, thereby reducing the voltage drop of the power signal when it is transmitted in the light shielding portion 39.

[0187] In one embodiment, Fig.50 and Fig.51 As shown, Fig.50 This is another structural schematic diagram of the light shielding portion 39 provided in an embodiment of the present invention. Fig.51 for Fig.50 In the cross-sectional view along the E1-E2 direction, the display panel includes a semiconductor layer 18 and a first metal layer 19 arranged along the light emitting direction of the display panel, the gate g of the transistor is located in the first metal layer 19, the first pole s of the transistor and the second pole d of the transistor are located in the semiconductor layer 18, and the shading portion 39 is located on the side of the semiconductor layer 18 facing away from the light emitting direction of the display panel.

[0188] At this time, in addition to blocking the gaps between the metal layers to reduce diffraction, the shading portion 39 can also prevent stray light from the bottom of the panel, or ambient light from the top of the panel but reflected back by the bottom from irradiating the semiconductor layer 18, thereby reducing the risk of photogenerated carriers generated by light irradiating the active layer in the semiconductor layer 18 and causing leakage current in the transistor.

[0189] Furthermore, combined with Figure 4 Please see again Fig.50 The multiple transistors also include a threshold compensation transistor M5, a gate of the threshold compensation transistor M5 is electrically connected to the third scan signal line Scan3, a first electrode of the threshold compensation transistor M5 is electrically connected to the second electrode of the driving transistor M0, and a second electrode of the threshold compensation transistor M5 is electrically connected to the gate of the driving transistor M0.

[0190] Since the first reset transistor M1 and the threshold compensation transistor M5 are directly connected to the gate of the driving transistor M0, if the first reset transistor M1 and the threshold compensation transistor M5 generate leakage current, the stability of the potential of the gate of the driving transistor M0 will be greatly affected, thereby affecting the writing of the data voltage, resulting in problems such as incomplete writing of the data signal. Therefore, in the embodiment of the present invention, in the direction perpendicular to the plane where the display panel is located, the projection of the light shielding portion 39 can cover the projection of at least one of the first reset transistor M1, the threshold compensation transistor M5 and the driving transistor M0, thereby avoiding the first reset transistor M1, the threshold compensation transistor M5 and the driving transistor M0 from generating leakage current, and improving the stability of the gate potential of the driving transistor M0.

[0191] Or, in another embodiment, Fig.52 As shown, Fig.52 Another film layer position schematic diagram of the light shielding portion 39 provided in an embodiment of the present invention, the organic light emitting element 7 includes a first electrode 46, a light emitting layer 47 and a second electrode 48 arranged along the light emitting direction of the display panel, the embodiment of the present invention takes the first electrode 46 as an anode and the second electrode 48 as a cathode as an example for illustration, the first electrode 46 of the organic light emitting element 7 is electrically connected to the first electrode of the second reset transistor M2, the light shielding portion 39 is arranged in the same layer as the first electrode 46, wherein there is a gap between the light shielding portion 39 and the first electrode 46 to ensure electrical insulation between the light shielding portion 39 and the first electrode 46. At this time, the light shielding portion 39 is located on the side of the transistor and various signal lines facing the light emitting direction of the display panel, and the connecting vias between the transistor and the signal line do not need to pass through the light shielding portion 39, and the light shielding portion 39 has a larger light shielding area. Moreover, the light shielding portion 39 only needs to be formed by the same composition process as the first electrode 46, which not only simplifies the process flow, but also does not require additional film thickness.

[0192] In one embodiment, in combination Figure 4 and Fig.50 The plurality of transistors further include a power supply voltage writing transistor M3, a data voltage writing transistor M4, a threshold compensation transistor M5 and a light emission control transistor M6.

[0193] Among them, the gate of the power supply voltage write transistor M3 is electrically connected to the light emitting control signal line Emit, the first electrode of the power supply voltage write transistor M3 is electrically connected to the power supply signal line PVDD, and the second electrode of the power supply voltage write transistor M3 is electrically connected to the first electrode of the driving transistor M0; the gate of the data voltage write transistor M4 is electrically connected to the third scanning signal line Scan3, the first electrode of the data voltage write transistor M4 is electrically connected to the data line Data, and the second electrode of the data voltage write transistor M4 is electrically connected to the first electrode of the driving transistor M0; the gate of the threshold compensation transistor M5 is electrically connected to the third scanning signal line Scan3, the first electrode of the threshold compensation transistor M5 is electrically connected to the second electrode of the driving transistor M0, and the second electrode of the threshold compensation transistor M5 is electrically connected to the gate of the driving transistor M0; the gate of the light emitting control transistor M6 is electrically connected to the light emitting control signal line Emit, the first electrode of the light emitting control transistor M6 is electrically connected to the second electrode of the driving transistor M0, and the second electrode of the light emitting control transistor M6 is electrically connected to the first electrode of the organic light emitting element 7.

[0194] In addition, the pixel circuit 6 further includes a storage capacitor Cst, a first plate of the storage capacitor Cst is electrically connected to the power signal line PVDD, and a second plate of the storage capacitor Cst is multiplexed with the gate of the driving transistor M0.

[0195] The working principle of the pixel circuit 6 is described below by taking the electrical connection between the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the pixel circuit 6 as an example:

[0196] The driving period of the pixel circuit 6 includes a first period, a second period and a third period.

[0197] In the first period, the first reset transistor M1 resets the gate of the driving transistor M0 in response to the corresponding scan signal, and the second reset transistor M2 resets the first electrode of the organic light emitting element 7 in response to the corresponding scan signal.

[0198] In the second period, the data voltage write transistor M4 responds to the scan signal provided by the third scan signal line Scan3, and the data line Data writes the data signal to the driving transistor M0 via the turned-on data voltage write transistor M4 and the threshold compensation transistor M5.

[0199] In the third period, the power supply voltage writing transistor M3 and the light emission control transistor M6 respond to the light emission control signal provided by the light emission control signal line Emit to control the organic light emitting element 7 to emit light under the action of the driving current converted from the data signal and the power signal provided by the power supply signal line PVDD.

[0200] Based on the above structure, combined with Figure 2The display area 1 further includes a main display area 11 disposed adjacent to the optical component arrangement area 2, and the pixel circuit 6 includes a second pixel circuit 12 located in the main display area 11. Fig.53 As shown, Fig.53 A schematic diagram of the film layer positions of each metal layer in a display panel provided in an embodiment of the present invention, wherein the display panel includes a semiconductor layer 18, a first metal layer 19, a second metal layer 49, a third metal layer 50 and a fourth metal layer 51 arranged along the light emitting direction of the display panel, wherein the gate g of the transistor is located in the first metal layer 19, the first electrode s of the transistor and the second electrode d of the transistor are located in the semiconductor layer 18, and the first electrode plate C1 of the storage capacitor Cst is located in the second metal layer 49.

[0201] In the main display area 11, as shown Fig.54 As shown, Fig.54 The schematic diagram of the film layer position of the signal line in the main display area 11 provided in an embodiment of the present invention, the first metal layer 19, the third metal layer 50 and the fourth metal layer 51 respectively include at least one of the third scanning signal line Scan3, the light emitting control signal line Emit, the power signal line PVDD and the data line Data.

[0202] For example, see again Fig.54 The light emitting control signal line Emit electrically connected to the second pixel circuit 12 is located in the first metal layer 19 , the second scanning signal line Scan2 and the third scanning signal line Scan3 are located in the third metal layer 50 , and the power signal line PVDD and the data line Data are located in the fourth metal layer 51 .

[0203] In the optical component setting area 2, Fig.55 This is a schematic diagram of the film layer position of the signal line in the optical component setting area 2 provided in an embodiment of the present invention. Fig.56 Another schematic diagram of the film layer position of the signal line in the optical component setting area 2 provided in an embodiment of the present invention, the shading portion 39 is located in the first metal layer 19, or the third metal layer 50, or the fourth metal layer 51, and the shading portion 39 and the third scanning signal line Scan3, the light control signal line Emit, the power signal line PVDD and the data line Data in the optical component setting area 2 are set in different layers.

[0204] For example, see again Fig.55 and Fig.56 The first scanning signal line Scan1, the third scanning signal line Scan3 and the light emitting control signal line Emit electrically connected to the first pixel circuit 8 are located in the first metal layer 19, the power signal line PVDD and the data line Data are located in the third metal layer 50, and the light shielding portion 39 is located in the fourth metal layer 51.

[0205] In addition, when the first electrode of the first reset transistor M1 is electrically connected to the second reset signal line Vref2, and the first electrode of the second reset transistor M2 is electrically connected to the third reset signal line Vref3, please refer to Fig.55 , the second reset signal line Vref2 and the third reset signal line Vref3 may be located in the second metal layer 49. Alternatively, when the first electrode of the first reset transistor M1 and the first electrode of the second reset transistor M2 are electrically connected to the first reset signal line Vref1 extending along the second direction, please refer to Fig.56 The first reset signal line Vref1 is located in the third metal layer 50 , and the third connection line 16 and the fourth connection line 17 electrically connected to the first reset signal line Vref1 are located in the second metal layer 49 .

[0206] By adjusting the film layer positions of each signal line in the optical component setting area 2, a metal layer is reserved in the first metal layer 19, the third metal layer 50 and the fourth metal layer 51 to separately form a shading portion 39. The shading portion 39 does not need to be set on the same layer as other signal lines, so the shading portion 39 does not need to avoid other signal lines and has a larger shading area.

[0207] Please refer again to Fig.55 and Fig.56 To reduce the voltage drop of the power signal, the line width of the power signal line PVDD can be larger than the line width of the data line Data. Fig.57 As shown, Fig.57 Another structural schematic diagram of the storage capacitor Cst provided in an embodiment of the present invention, in addition to including a first electrode plate C1 electrically connected to the power signal line PVDD and a second electrode plate C2 multiplexed with the gate of the first reset transistor M1, the storage capacitor Cst may further include a third electrode plate C3 arranged opposite to the first electrode plate C1, and the third electrode plate C3 is also electrically connected to the power signal line PVDD, for further reducing the load of the power signal line PVDD.

[0208] Further, please see again Fig.55 and Fig.56 The shading portion 39 is located in the fourth metal layer 51. At this time, the shading portion 39 is located on the side of the light emitting direction of the transistor and various signal lines toward the display panel. The connecting vias between the transistor and the signal line do not need to pass through the shading portion 39, and the coverage area of ​​the shading portion 39 is larger.

[0209] Furthermore, if Fig.58 As shown, Fig.58This is a schematic diagram of the arrangement of various signal transmission lines in the optical component setting area 2 provided in an embodiment of the present invention, wherein the light control signal line Emit electrically connected to the first pixel circuit 8 in two adjacent pixel areas 3 is electrically connected via a light signal transmission line 52; the power signal line PVDD electrically connected to the first pixel circuit 8 in two adjacent pixel areas 3 is electrically connected via a power signal transmission line 53; the third scanning signal line Scan3 electrically connected to the first pixel circuit 8 in two adjacent pixel areas 3 is electrically connected via a second scanning signal transmission line 54; and the data line Data electrically connected to the first pixel circuit 8 in two adjacent pixel areas 3 is electrically connected via data signal transmission lines 55, respectively.

[0210] The light-transmitting area 4 includes a fifth main light-transmitting area 56 and a fifth auxiliary light-transmitting area 57 surrounding the fifth main light-transmitting area 56. The light-emitting signal transmission line 52, the power signal transmission line 53, the second scanning signal transmission line 54 and the data signal transmission line 55 extend in the fifth auxiliary light-transmitting area 57. In other words, various signal transmission lines are extended around the fifth main light-transmitting area 56, thereby concentrating the areas blocked by the wiring and the areas not blocked by the wiring in the light-transmitting area 4 to reduce diffraction.

[0211] It should be noted that a shading portion may be provided in the fifth auxiliary light-transmitting area 57 to fully cover the fifth auxiliary light-transmitting area 57 or to cover the gaps between the signal transmission lines in the fifth auxiliary light-transmitting area 57 to eliminate diffraction to a greater extent.

[0212] Based on the specific structure of the above pixel circuit, the structural schematic diagram of the main display area 11 and the optical component setting area 2 is as follows: Fig.59 As shown, the layout diagram of the main display area 11 and the optical component setting area 2 is as shown in Fig.60 shown.

[0213] In addition, if Fig.61 As shown, Fig.61Another structural schematic diagram of the display panel provided by the embodiment of the present invention, when the pixel circuit 6 adopts the above circuit structure, the display panel may include a first scanning shift register 70, a second scanning shift register 71 and a light emitting shift register 72, wherein the first scanning shift register 70 is used to provide a scanning signal to the gate of the first reset transistor M1 and the gate of the second reset transistor M2 in the pixel circuit 6, the second scanning shift register 71 is used to provide a scanning signal to the gate of the data voltage writing transistor M4 and the gate of the threshold compensation transistor M5 in the pixel circuit 6, and the light emitting shift register 72 is used to provide a light emitting control signal to the gate of the power supply voltage writing transistor M3 and the gate of the light emitting control transistor M6 in the pixel circuit 6. The first scanning shift register 70, the second scanning shift register 71 and the light emitting shift register 72 may adopt a single-side driving or double-side driving driving mode, and the working principle of the above shift registers is the same as the working principle of the existing shift registers, which will not be repeated here.

[0214] In one embodiment, Fig.62 As shown, Fig.62 This is a structural schematic diagram of the shielding part 59 provided in an embodiment of the present invention, wherein the multiple transistors further include a threshold compensation transistor M5, a gate of the threshold compensation transistor M5 is electrically connected to the third scan signal line Scan3, a first electrode of the threshold compensation transistor M5 is electrically connected to the second electrode of the driving transistor M0, and a second electrode of the threshold compensation transistor M5 is electrically connected to the gate of the driving transistor M0; the pixel circuit 6 further includes a storage capacitor Cst, a first electrode plate C1 of the storage capacitor Cst is electrically connected to the power signal line PVDD, and a second electrode plate C2 of the storage capacitor Cst is multiplexed with the gate of the driving transistor M0.

[0215] The display panel also includes a shielding portion 59 protruding from the first electrode plate C1. In a direction perpendicular to the plane where the display panel is located, the projection of the shielding portion 59 is arranged adjacent to the projection of the second electrode of the threshold compensation transistor M5, so that the shielding portion 59 is used to shield the interference signal from affecting the second electrode of the threshold compensation transistor M5, that is, the potential of the gate of the driving transistor M0, thereby avoiding fluctuations in the gate potential of the driving transistor M0. At the same time, the shielding portion 59 can be arranged in the same layer as the first electrode plate C1 of the storage capacitor Cst and electrically connected. In a direction perpendicular to the plane where the display panel is located, the shielding portion 59 at least partially overlaps with the third scan line scan3, which can increase the capacitance of the storage capacitor Cst electrically connected to the driving transistor M0 and improve the stability of the gate potential of the driving transistor M0.

[0216] In one embodiment, Fig.63 As shown, Fig.63The schematic diagram of the structure of the first scanning signal transmission line 9 provided in an embodiment of the present invention, the first scanning signal transmission line 9 includes at least two connected zigzag routing segments, or the first scanning signal transmission line 9 includes at least two connected arc routing segments. In this case, the edge of the first scanning signal transmission line 9 is a zigzag edge or a wavy edge, which breaks the periodic interference of the external ambient light and eliminates diffraction to a greater extent.

[0217] Alternatively, in another embodiment, the shape of the light-transmitting area 4 may be adjusted so that the edge of the light-transmitting area 4 is a non-linear edge, thereby effectively eliminating diffraction.

[0218] For example, Fig.64 As shown, Fig.64 The schematic diagram of the shape of the light-transmitting area 4 provided in the embodiment of the present invention is a circular or elliptical shape. It should be noted that when the shape of the light-transmitting area 4 is circular or elliptical, the shape of the pixel area 3 can still be rectangular. In this case, the shape of the light-transmitting area 4 can be defined by the light-shielding portion.

[0219] Or, if Fig.65 As shown, Fig.65 This is a schematic diagram of the shape of the pixel area 3 provided in an embodiment of the present invention. The shape of the pixel area 3 is circular or quasi-circular. In this case, the edge of the light-transmitting area 4 between two adjacent pixel areas 3 is a non-straight edge.

[0220] In one embodiment, Fig.66 As shown, Fig.66 This is a structural schematic diagram of a dummy routing line 62 provided in an embodiment of the present invention, wherein the display panel includes a semiconductor layer 18, a first electrode of the transistor and a second electrode of the transistor are located in the semiconductor layer 18, the light-transmitting area 4 includes a sixth main light-transmitting area 60 and a sixth auxiliary light-transmitting area 61 surrounding the sixth main light-transmitting area 60, and the sixth auxiliary light-transmitting area 61 includes a dummy routing line 62 located in the semiconductor layer 18.

[0221] Since the pixel circuit 6 is not provided in the light-transmitting area 4, the distribution density of the semiconductor layer 18 at different positions of the display area 1 is uneven, which leads to poor etching uniformity of the semiconductor layer 18. Among them, at the junction of the main display area 11 and the optical component setting area 2, the distribution density of the semiconductor layer 18 on both sides of the junction is quite different, so the first and second poles of the transistor near the junction are more affected by etching. By providing some dummy wirings 62 in the sixth auxiliary light-transmitting area 61, the distribution density of the semiconductor layer 18 at the boundary position of the optical component setting area 2 can be increased by using the dummy wirings 62, thereby improving the etching uniformity of the semiconductor layer 18, and then effectively improving the working stability of the transistor at the boundary position.

[0222] Please refer again to Fig.65The pattern of the added dummy wiring 62 may be consistent with the pattern of the semiconductor layer 18 in the pixel circuit 6 , or the dummy wiring 62 may also be a wiring structure.

[0223] Furthermore, if Fig.67 As shown, Fig.67 Another structural schematic diagram of the dummy wiring 62 provided in an embodiment of the present invention, at least part of the dummy wiring 62 is multiplexed as the first scanning signal transmission line 9, so there is no need to set up additional metal wiring as the first scanning signal transmission line 9. Moreover, the dummy wiring 62 is formed of a semiconductor material with a higher light transmittance, thereby further improving the light transmittance of the optical component setting area 2.

[0224] In addition, please refer to Fig.67 , part of the dummy wiring 62 can also be multiplexed as one or more of the light emitting signal transmission line 52, the power signal transmission line 53, the second scanning signal transmission line 54, and the data signal transmission line 55. When the first electrode of the first reset transistor M1 and the first electrode of the second reset transistor M2 in the first pixel circuit 8 are electrically connected to the first reset signal line Vref1, the dummy wiring 62 can also be multiplexed as the first reset signal transmission line 15; when the first electrode of the first reset transistor M1 in the first pixel circuit 8 is electrically connected to the second reset signal line Vref2, and the second electrode of the second reset transistor M2 is electrically connected to the third reset signal, the dummy wiring 62 can also be multiplexed as the second reset signal transmission line 25 and the third reset signal transmission line 26.

[0225] Optionally, in order to improve the light transmittance of the optical component setting area, the signal transmission lines between two adjacent pixel areas along the first direction or along the second direction, such as the light emitting signal transmission line 52, the power signal transmission line 53, the second scanning signal transmission line 54, the data signal transmission line 55, the first reset signal transmission line 15, the first scanning signal transmission line 9, etc., can be arranged in the same layer with the semiconductor layer, that is, the signal transmission line is made of semiconductor material, please refer to Fig.71 , Fig.71 In the figure, the first scanning signal transmission line 9 and the semiconductor layer are taken as an example to illustrate.

[0226] When light passes through the transparent area of ​​the optical component setting area from the outside and enters the optical component (for example, a camera) for imaging, it can be understood that in the direction perpendicular to the plane where the display panel is located, due to the thickness of one or more transparent film layers in the area where the signal transmission line made of semiconductor material is located and the thickness and refractive index of the corresponding transparent film layers around are different, the optical path of the ambient light at different positions will be different. The optical path difference leads to the phase difference of the light, which will easily cause the diffraction phenomenon, and also affect the imaging effect of the optical device. Therefore, a transparent structure T can be set above or below the signal transmission line made of semiconductor material. In the direction perpendicular to the plane where the display panel is located, the transparent structure covers at least one signal transmission line made of semiconductor material, thereby adjusting the optical path difference on different light paths and reducing the diffraction phenomenon. The film thickness and material refractive index of the transparent structure T can be selected and designed according to actual needs. The transparent structure can be made of transparent conductive materials, such as ITO, IGZO, etc. Optionally, the light-transmitting structure can be reused as one or more of the light-emitting signal transmission line 52, the power signal transmission line 53, the second scanning signal transmission line 54, the data signal transmission line 55, the first reset signal transmission line 15, and the first scanning signal transmission line 9, which improves the light transmittance of the optical component setting area, reduces the diffraction effect of the light, and increases the area of ​​the high light transmittance region in the light-transmitting area 4. Please continue to refer to Fig.71 For example, the first reset signal transmission line 15 can be made of a transparent conductive material, and the first reset signal transmission line 15 and the first scanning signal transmission line 9 at least partially overlap, so as to reduce the space occupied by the wiring, and at the same time improve the transmittance of the optical component setting area 2, and improve the light diffraction problem caused by the optical path difference. Fig.71 The routing method in the figure is only for the convenience of understanding the technical solution and does not limit the specific routing signals. Fig.72 for Fig.71 In the cross-sectional view along the G1 - G2 direction, the first electrode 46 of the organic light emitting element may include a first transparent electrode 461 and a first reflective electrode 462 , so that the light-transmitting structure T and the first transparent electrode 461 may be formed in the same layer and process, thereby saving process and panel thickness.

[0227] Optionally, in order to increase the transmittance of the optical component setting area 2, the number of pixel circuits in the optical component setting area 2 may be reduced. In order to balance the brightness difference between the optical component setting area 2 and the main display area 11, the driving current in the first pixel circuit may be increased to increase the brightness of the optical component setting area 2. However, the greater the current density, the faster the life of the pixel decays. Therefore, a first pixel circuit may be set to electrically connect at least two organic light-emitting elements 7. The first electrodes of the two organic light-emitting elements 7 may be electrically connected, and only two pixel openings need to be set separately. Usually, in order to improve the pixel light extraction efficiency, the first electrode is set to a structure including a reflective electrode, which will lose a certain amount of transmittance of the display panel. Therefore, optionally, a transparent metal wiring (such as ITO, IGZO, etc.) may be used to electrically connect the first electrodes of the two organic light-emitting elements 7, thereby driving the first electrode to emit light. Optionally, when there are wirings made of semiconductor materials or other light-transmitting wirings in the light-transmitting area, the transparent metal wirings can at least partially cover the wirings made of semiconductor materials or other light-transmitting wirings in the direction perpendicular to the plane where the display panel is located, so as to improve the diffraction problem caused by the optical path difference and improve the imaging effect of the optical components.

[0228] In one embodiment, Fig.68 As shown, Fig.68 This is a schematic diagram of the structure of the second electrode 48 provided in an embodiment of the present invention. The organic light-emitting element 7 includes the second electrode 48, and the second electrode 48 is a cathode. In order to further improve the light transmittance of the optical component setting area 2, some hollow portions 63 can be set on the second electrode 48 in the optical component setting area 2. The hollow portions 63 expose the light-transmitting area 4 to avoid the second electrode 48 blocking the light-transmitting area 4.

[0229] In one embodiment, see again Fig.64 and Fig.65 , multiple pixels 5 include red pixels 63, green pixels 64 and blue pixels 65. In order to better achieve color mixing and optimize the display effect of the optical component setting area 2, the pixel area 3 includes at least one red pixel 63, at least one green pixel 64 and at least one blue pixel 65.

[0230] In one embodiment, Fig.69 As shown, Fig.69 This is a schematic diagram of an arrangement of pixel areas 3 provided in an embodiment of the present invention, wherein a light-transmitting area 4 is included between two adjacent pixel areas 3 in the first direction, and a light-transmitting area 4 is included between two adjacent pixel areas 3 in the second direction, and the first direction intersects the second direction. Based on this arrangement, the pixel areas 3 are evenly and dispersedly arranged in the optical component setting area 2, and the display effect of the optical component setting area 2 is better.

[0231] Or, in another embodiment, Fig.70 As shown, Fig.70 This is another arrangement schematic diagram of the pixel areas 3 provided in an embodiment of the present invention, wherein a light-transmitting area 4 is included between two adjacent pixel areas 3 in the first direction, and no light-transmitting area 4 is included between two adjacent pixel areas 3 in the second direction, and the first direction intersects with the second direction. Based on this arrangement, the light-transmitting areas 4 between two adjacent pixel areas 3 are arranged continuously in the second direction, the area of ​​the light-transmitting area in the optical component setting area 2 is larger and the light-transmitting area is more concentrated, and the light-transmitting performance of the optical component setting area 2 is better.

[0232] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.73 and Fig.74 As shown, Fig.73 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, Fig.74 for Fig.73 In the cross-sectional view along the F1-F2 direction, the display device includes the above-mentioned display panel 100 and an optical component 200 (such as a camera, an infrared light sensor, etc.). In the direction perpendicular to the plane where the display panel is located, the optical component setting area 2 in the display panel 100 at least partially overlaps with the optical component 200. The specific structure of the display panel 100 has been described in detail in the above embodiment and will not be repeated here. Of course, Fig.73 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0233] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0234] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, it includes: a display area, the display area includes an optical component setting area, the optical component setting area includes a plurality of pixel areas, and at least some of the adjacent two pixel areas include a light-transmitting area; a plurality of pixels located in the display area, the pixels include pixel circuits and organic light-emitting elements, the pixel circuits include a plurality of transistors, the plurality of transistors include a first reset transistor, a second reset transistor and a driving transistor, the first reset transistor responds to its corresponding scan signal to reset the gate of the driving transistor, and the second reset transistor responds to its corresponding scan signal to reset the first electrode of the organic light-emitting element; wherein, the pixel circuit includes a first pixel circuit located in the optical component setting area, and the gates of the first reset transistor and the second reset transistor in the first pixel circuit are electrically connected.

2. The display panel according to claim 1, characterized in that, the pixel area includes at least one of the first pixel circuits, and the gates of the first reset transistor and the second reset transistor in the pixel area are electrically connected to a first scan signal line; for two adjacent pixel areas in the first direction, the first scan signal lines electrically connected to the first pixel circuits in the pixel areas are electrically connected through a first scan signal transmission line.

3. The display panel according to claim 2, characterized in that, the first scan signal line includes a first scan line segment and a second scan line segment located in the pixel area; the first scan line segment is electrically connected to the gate of the first reset transistor, the second scan line segment is electrically connected to the gate of the second reset transistor, and the first scan line segment and the second scan line segment are electrically connected through a first connection trace.

4. The display panel according to claim 3, characterized in that, the first scan signal transmission line and the first scan line segment, the second scan line segment or the first connection trace directly connected thereto are arranged on the same layer.

5. The display panel according to claim 3, characterized in that, both ends of the second scan line segment are electrically connected to both ends of the first scan line segment through a first connection trace respectively.

6. The display panel according to claim 1, characterized in that, the display area further includes a main display area adjacent to the optical component setting area, the pixel circuit includes a second pixel circuit located in the main display area, and the gates of the first reset transistor and the second reset transistor in the second pixel circuit are electrically connected.

7. The display panel according to claim 6, characterized in that, the gates of the first reset transistor and the second reset transistor in the second pixel circuits arranged in the first direction are electrically connected to a second scan signal line; The second scanning signal line includes a third scanning segment and a fourth scanning segment located in the main display area. The third scanning segment is electrically connected to the gate of the first reset transistor, the fourth scanning segment is electrically connected to the gate of the second reset transistor, and the third scanning segment and the fourth scanning segment are electrically connected through a second connection trace. The pixel area includes at least one of the first pixel circuits. The gates of the first reset transistor and the second reset transistor in the pixel area are electrically connected to a first scanning signal line. Moreover, for the first pixel circuit and the second pixel circuit arranged along the first direction, the first scanning signal line and the second scanning signal line are electrically connected.

8. The display panel according to claim 3, wherein, The first pole of the first reset transistor in the pixel area is electrically connected to a first reset signal line, and the first pole of the second reset transistor is electrically connected to the first reset signal line. Moreover, for two adjacent pixel areas, the first reset signal line electrically connected to the first pixel circuit in the pixel area is electrically connected through a first reset signal transmission line.

9. The display panel according to claim 8, wherein, The pixel area includes a plurality of the first pixel circuits arranged along the first direction, and the first reset signal line extends along a second direction, and the second direction intersects with the first direction. The optical component setting area further includes a third connection trace and a fourth connection trace extending along the first direction. The first pole of the first reset transistor in the pixel area is electrically connected to the third connection trace, and the third connection trace is electrically connected to the first reset signal line. The first pole of the second reset transistor in the pixel area is electrically connected to the fourth connection trace, and the fourth connection trace is electrically connected to the first reset signal line.

10. The display panel according to claim 9, wherein, The display panel includes a semiconductor layer, and the first pole and the second pole of the transistor are located in the semiconductor layer. The third connection trace and the fourth connection trace are located in the semiconductor layer.

11. The display panel according to claim 8, wherein, The first reset signal line includes a first reset segment and a second reset segment located in the pixel area. The first reset segment is electrically connected to the first pole of the first reset transistor, the second reset segment is electrically connected to the first pole of the second reset transistor, and the second reset segment and the first reset segment are electrically connected through a fifth connection trace.

12. The display panel according to claim 11, wherein, The first reset signal transmission line and the first reset segment, the second reset segment, or the fifth connection trace directly connected thereto are disposed on the same layer.

13. The display panel according to claim 11, wherein, The light-transmitting region includes a first main light-transmitting region and a first auxiliary light-transmitting region. The first main light-transmitting region and the first auxiliary light-transmitting region are arranged along a second direction, and at least part of the first reset signal transmission line and the first scan signal transmission line extends within the first auxiliary light-transmitting region.

14. The display panel according to claim 13, wherein, the first reset signal transmission line and the first scan signal transmission line are arranged in different layers, and in a direction perpendicular to the plane of the display panel, the projection of the first reset signal transmission line and the projection of the first scan signal transmission line at least partially overlap.

15. The display panel according to claim 11, wherein, the first connection trace includes a first end and a second end. In a direction perpendicular to the plane of the display panel, the projection of the first end is located on a side of the projection of the first scan line segment away from the projection of the second scan line segment, and the projection of the second end is located on a side of the projection of the second scan line segment away from the projection of the first scan line segment; in a direction perpendicular to the plane of the display panel, the projection of the first end overlaps with the projection of the first reset line segment, and / or the projection of the second end overlaps with the projection of the second reset line segment.

16. The display panel according to claim 11, wherein, the display panel includes a semiconductor layer, and the first pole and the second pole of the transistor are located in the semiconductor layer; the first reset signal transmission line is located in the semiconductor layer.

17. The display panel according to claim 3, wherein, the first pole of the first reset transistor in the pixel region is electrically connected to a second reset signal line, and the second reset signal lines connected to the first pixel circuits in two adjacent pixel regions are electrically connected through a second reset signal transmission line. The second reset signal line is connected to a first voltage terminal; the first pole of the second reset transistor in the pixel region is electrically connected to a third reset signal line, and the third reset signal lines connected to the first pixel circuits in two adjacent pixel regions are electrically connected through a third reset signal transmission line. The third reset signal line is connected to a second voltage terminal.

18. The display panel according to claim 17, wherein, the pixel region includes a plurality of the first pixel circuits arranged along the first direction, the second reset signal line and the third reset signal line extend along a second direction, and the second direction intersects with the first direction; the optical component setting region further includes a sixth connection trace and a seventh connection trace extending along the first direction. The first pole of the first reset transistor in the pixel region is electrically connected to the sixth connection trace, and the sixth connection trace is also electrically connected to the second reset signal line; the first pole of the second reset transistor in the pixel region is electrically connected to the seventh connection trace, and the seventh connection trace is also electrically connected to the third reset signal line.

19. The display panel according to claim 18, wherein, The display panel includes a semiconductor layer, and a first pole and a second pole of the transistor are located in the semiconductor layer; The sixth connection trace and the seventh connection trace are located in the semiconductor layer.

20. The display panel according to claim 18, wherein, The pixel region includes x first pixel circuits arranged along the first direction, the second reset signal line is located on a side of the first pixel circuit away from the second first pixel circuit, and the third reset signal line is located on a side of the x-th first pixel circuit away from the (x-1)-th first pixel circuit; The light-transmitting region includes a second main light-transmitting region and two second auxiliary light-transmitting regions. One second auxiliary light-transmitting region, the second main light-transmitting region, and the other second auxiliary light-transmitting region are arranged along the first direction. At least a part of the second reset signal transmission line extends in the second auxiliary light-transmitting region, and at least a part of the third reset signal transmission line extends in the second auxiliary light-transmitting region.

21. The display panel according to claim 18, wherein, The pixel region includes x first pixel circuits arranged along the first direction; The light-transmitting region includes a third main light-transmitting region and a third auxiliary light-transmitting region. The third main light-transmitting region and the third auxiliary light-transmitting region are arranged along the first direction. At least a part of the second reset signal transmission line and the third reset signal transmission line extends in the third auxiliary light-transmitting region; The second reset signal line and the third reset signal line are located on a side of the first pixel circuit away from the second first pixel circuit, and the direction in which the third auxiliary light-transmitting region points to the third main light-transmitting region is the same as the direction in which the first pixel circuit points to the second first pixel circuit; or, the second reset signal line and the third reset signal line are located on a side of the x-th first pixel circuit away from the (x-1)-th first pixel circuit, and the direction in which the third auxiliary light-transmitting region points to the third main light-transmitting region is opposite to the direction in which the first pixel circuit points to the second first pixel circuit.

22. The display panel according to claim 17, wherein, The second reset signal line and the third reset signal line respectively extend along the first direction in the pixel region.

23. The display panel according to claim 22, wherein, The light-transmitting region includes a fourth main light-transmitting region and a fourth auxiliary light-transmitting region. The fourth auxiliary light-transmitting region and the fourth main light-transmitting region are arranged along the first direction. The fourth main light-transmitting region includes a first sub-region, a second sub-region, and a third sub-region arranged along a second direction, and the second direction intersects with the first direction; The second reset signal transmission line includes a first reset transmission segment located in the fourth auxiliary light-transmitting region and a second reset transmission segment located in the second sub-region, and the third reset signal transmission line includes a third reset transmission segment located in the fourth auxiliary light-transmitting region and a fourth reset transmission segment located in the second sub-region; In the direction pointing from the fourth auxiliary light-transmitting region to the fourth main light-transmitting region, the distance between the first reset transmission line segment and the third reset transmission line segment decreases.

24. The display panel according to claim 18, wherein, both the second reset signal transmission line and the third reset signal transmission line are arranged in a different layer from the first scan signal transmission line, and in the direction perpendicular to the plane where the display panel is located, the projection of the second reset signal transmission line and / or the projection of the third reset signal transmission line overlap with the projection of the first scan signal transmission line.

25. The display panel according to claim 18, wherein, the display panel includes a semiconductor layer, and the first pole and the second pole of the transistor are located in the semiconductor layer; the second reset signal transmission line and the third reset signal transmission line are located in the semiconductor layer.

26. The display panel according to claim 17, wherein, the first connection trace includes a first end portion and a second end portion. In the direction perpendicular to the plane where the display panel is located, the projection of the first end portion is located on the side of the projection of the first scan line segment away from the projection of the second scan line segment, and the projection of the second end portion is located on the side of the projection of the second scan line segment away from the projection of the first scan line segment; In the direction perpendicular to the plane where the display panel is located, the projection of the first end portion overlaps with the projection of the second reset signal line, and / or the projection of the second end portion overlaps with the projection of the third reset signal line.

27. The display panel according to claim 1, wherein, the display panel further includes a light-shielding portion located in the optical component setting area. In the direction perpendicular to the plane where the display panel is located, the light-shielding portion covers at least a part of the first pixel circuit.

28. The display panel according to claim 27, wherein, the light-shielding portion is electrically connected to the reset signal terminal, the light-shielding portion is electrically connected to the first pole of the first reset transistor, the light-shielding portion is electrically connected to the first pole of the second reset transistor, and adjacent two of the light-shielding portions are electrically connected through an eighth connection trace.

29. The display panel according to claim 27, wherein, the plurality of transistors further includes a power supply voltage writing transistor, the gate of the power supply voltage writing transistor is electrically connected to the light emission control signal line, and the second pole of the power supply voltage writing transistor is electrically connected to the first pole of the driving transistor; the light-shielding portion is electrically connected to the power supply signal terminal, the light-shielding portion is electrically connected to the first pole of the power supply voltage writing transistor, and adjacent two of the light-shielding portions are electrically connected through a ninth connection trace arranged in the same layer as the light-shielding portion.

30. The display panel according to claim 27, wherein, the display panel includes a semiconductor layer, the first pole and the second pole of the transistor are located in the semiconductor layer, and the light-shielding portion is located on the side of the semiconductor layer facing away from the light-emitting direction of the display panel.

31. The display panel according to claim 30, wherein, The plurality of the transistors further includes a threshold compensation transistor. A gate of the threshold compensation transistor is electrically connected to a third scan signal line. A first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor. A second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor; In a direction perpendicular to a plane where the display panel is located, a projection of the light-shielding portion covers a projection of at least one of the first reset transistor, the threshold compensation transistor, and the driving transistor.

32. The display panel according to claim 27, wherein, The organic light-emitting element includes a first electrode, a light-emitting layer, and a second electrode arranged along a light-emitting direction of the display panel. The first electrode of the organic light-emitting element is electrically connected to a first pole of the second reset transistor; The light-shielding portion is arranged in the same layer as the first electrode.

33. The display panel according to claim 27, wherein, The plurality of the transistors further includes: a power supply voltage writing transistor. A gate of the power supply voltage writing transistor is electrically connected to a light-emitting control signal line. A first pole of the power supply voltage writing transistor is electrically connected to a power supply signal line. A second pole of the power supply voltage writing transistor is electrically connected to a first pole of the driving transistor; a data voltage writing transistor. A gate of the data voltage writing transistor is electrically connected to a third scan signal line. A first pole of the data voltage writing transistor is electrically connected to a data line. A second pole of the data voltage writing transistor is electrically connected to a first pole of the driving transistor; a threshold compensation transistor. A gate of the threshold compensation transistor is electrically connected to a third scan signal line. A first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor. A second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor; a light-emitting control transistor. A gate of the light-emitting control transistor is electrically connected to the light-emitting control signal line. A first pole of the light-emitting control transistor is electrically connected to a second pole of the driving transistor. A second pole of the light-emitting control transistor is electrically connected to the first electrode of the organic light-emitting element; The pixel circuit further includes a storage capacitor. A first plate of the storage capacitor is electrically connected to the power supply signal line. A second plate of the storage capacitor is multiplexed with the gate of the driving transistor.

34. The display panel according to claim 33, wherein, The display area further includes a main display area adjacent to the optical component setting area. The pixel circuit includes a second pixel circuit located in the main display area; The display panel includes a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged along a light-emitting direction of the display panel. Among them, the first pole and the second pole of the transistor are located in the semiconductor layer. The gate of the transistor is located in the first metal layer. The first plate of the storage capacitor is located in the second metal layer; In the main display area, the first metal layer, the third metal layer, and the fourth metal layer respectively include at least one of the third scan signal line, the light emission control signal line, the power supply signal line, and the data line; In the optical component setting area, the light-shielding portion is located in the first metal layer, the third metal layer, or the fourth metal layer, and the light-shielding portion is disposed in a different layer from the third scan signal line, the light emission control signal line, the power supply signal line, and the data line in the optical component setting area.

35. The display panel according to claim 34, wherein, the light-shielding portion is located in the fourth metal layer.

36. The display panel according to claim 33, wherein, the light emission control signal lines electrically connected to the first pixel circuits in two adjacent pixel areas are electrically connected through light emission signal transmission lines; the power supply signal lines electrically connected to the first pixel circuits in two adjacent pixel areas are electrically connected through power supply signal transmission lines; the third scan signal lines electrically connected to the first pixel circuits in two adjacent pixel areas are electrically connected through second scan signal transmission lines; the data lines electrically connected to the first pixel circuits in two adjacent pixel areas are respectively electrically connected through data signal transmission lines; the light-transmitting area includes a fifth main light-transmitting area and a fifth auxiliary light-transmitting area surrounding the fifth main light-transmitting area, and the light emission signal transmission lines, the power supply signal transmission lines, the second scan signal transmission lines, and the data signal transmission lines extend in the fifth auxiliary light-transmitting area.

37. The display panel according to claim 1, wherein, the plurality of transistors further include a threshold compensation transistor, a gate of the threshold compensation transistor is electrically connected to the third scan signal line, a first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor; the pixel circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is electrically connected to the power supply signal line, and a second electrode plate of the storage capacitor is multiplexed with the gate of the driving transistor; the display panel further includes a shielding portion protruding from the first electrode plate, and in a direction perpendicular to the plane where the display panel is located, a projection of the shielding portion is adjacently disposed to a projection of the second pole of the threshold compensation transistor.

38. The display panel according to claim 2, wherein, the first scan signal transmission line includes at least two connected broken-line segments, or, the first scan signal transmission line includes at least two connected arc segments.

39. The display panel according to claim 1, wherein, the display panel includes a semiconductor layer, the first pole and the second pole of the transistor are located in the semiconductor layer; the light-transmitting area includes a sixth main light-transmitting area and a sixth auxiliary light-transmitting area surrounding the sixth main light-transmitting area, and the sixth auxiliary light-transmitting area includes dummy traces located in the semiconductor layer.

40. The display panel according to claim 39, wherein, The pixel region includes at least one of the first pixel circuits, and the gates of the first reset transistor and the second reset transistor in the pixel region are electrically connected to a first scan signal line; For two adjacent pixel regions in a first direction, the first scan signal lines electrically connected to the first pixel circuits in the pixel regions are electrically connected through a first scan signal transmission line; At least a part of the dummy trace is multiplexed as the first scan signal transmission line.

41. The display panel according to claim 1, wherein, The plurality of pixels include red pixels, green pixels, and blue pixels, and the pixel region includes at least one of the red pixels, at least one of the green pixels, and at least one of the blue pixels.

42. The display panel according to claim 1, wherein, A light-transmitting region is included between two adjacent pixel regions in a first direction, and a light-transmitting region is included between two adjacent pixel regions in a second direction, and the first direction intersects with the second direction.

43. A display device, wherein, It includes the display panel according to any one of claims 1 to 42.

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