Display substrate and display device

Abstract

The application provides a display substrate and a display device, relates to the technical field of display, and can ensure that transistors in a sub-pixel driving circuit have good characteristics. The display substrate comprises a substrate and a plurality of sub-pixel driving circuits arranged on the substrate, wherein the sub-pixel driving circuit comprises a plurality of transistors, the transistor comprises an active layer, and the active layer comprises a channel portion; the display substrate further comprises an adjusting layer, the orthographic projection of the adjusting layer on the substrate at least partially overlaps the orthographic projection of the channel portion included in at least three transistors in each sub-pixel driving circuit on the substrate, the adjusting layer can receive an input adjusting signal, and the adjusting layer can adjust the characteristics of the at least three transistors. The display device comprises the display substrate provided in the technical solution. The display substrate provided by the application is used for display.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202110832637.7, filed in China on July 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0004] With the continuous development of display technology, organic light-emitting diode (OLED) display panels and liquid crystal display panels are widely used in various fields.

[0005] Each subpixel in a display panel includes a subpixel driving circuit and a light-emitting element. The subpixel driving circuit provides driving signals to the light-emitting element to drive it to emit light. The subpixel driving circuit typically includes multiple transistors, and the characteristics of these transistors directly affect the display effect of the display panel. Therefore, ensuring that the transistors in the subpixel driving circuit have good characteristics is a problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this invention is to provide a display substrate and a display device that can ensure that the transistors in the sub-pixel driving circuit have good characteristics.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A first aspect of the present invention provides a display substrate, comprising: a substrate and a plurality of sub-pixel driving circuits disposed on the substrate, the sub-pixel driving circuits including a plurality of transistors, the transistors including an active layer, the active layer including a channel portion; the display substrate further comprising:

[0009] An adjustment layer, wherein the orthographic projection of the adjustment layer on the substrate at least partially overlaps with the orthographic projection of the channel portion of at least three transistors in each sub-pixel driving circuit on the substrate, the adjustment layer being capable of receiving an input adjustment signal, and the adjustment layer being capable of adjusting the characteristics of the at least three transistors.

[0010] Optionally, the adjustment layer includes a plurality of first adjustment patterns arranged in an array, each first adjustment pattern including at least a portion extending along a first direction;

[0011] The orthographic projection of the first adjustment pattern on the substrate at least partially overlaps with the orthographic projection of the channel portion of at least two transistors arranged along the first direction in the corresponding sub-pixel driving circuit on the substrate.

[0012] Optionally, the gates of the at least two transistors are coupled, and the first adjusting pattern is coupled to a gate signal.

[0013] Optionally, the display substrate further comprises a driving chip; the first adjusting patterns in the same row in the first direction are coupled in sequence to form a first adjusting line, at least one end of the first adjusting line is coupled to the driving chip, and the driving chip is configured to provide the adjusting signal.

[0014] Optionally, the display substrate comprises a plurality of scan lines, the scan lines comprise at least a portion extending in the first direction, and the gates of the at least two transistors are coupled to the same scan line; the first adjusting line has substantially the same shape as the scan line.

[0015] The first adjusting line has at least partial overlap with the scan line in the projection on the base.

[0016] Optionally, the adjusting layer comprises a plurality of second adjusting patterns, the second adjusting patterns have at least partial overlap with a channel portion of one transistor in the corresponding sub-pixel driving circuit in the projection on the base.

[0017] Optionally, the second adjusting pattern is coupled to the gate of the one transistor in the corresponding sub-pixel driving circuit.

[0018] Optionally, the display substrate further comprises a plurality of power lines; the one transistor comprises a driving transistor, and the second adjusting pattern is coupled to the power line.

[0019] Optionally, the second adjusting pattern comprises a main body portion and an extension portion; the main body portion has at least partial overlap with the channel portion of the driving transistor in the projection on the base; the extension portion has no overlap with the channel portion of the driving transistor in the projection on the base, and has at least partial overlap with the power line in the projection on the base, and the extension portion is coupled to the power line.

[0020] Optionally, the display substrate further comprises a plurality of light-emitting control lines, the light-emitting control lines comprise at least a portion extending in the first direction; the light-emitting control line has at least partial overlap with the extension portion in the projection on the base.

[0021] Optionally, the display substrate further comprises a driving chip; the second adjusting patterns in the same row in the first direction are coupled in sequence to form a second adjusting line, at least one end of the second adjusting line is coupled to the driving chip.

[0022] Optionally, the display substrate further comprises a plurality of first initialization signal lines and a plurality of second initialization signal lines; the at least two transistors comprise a first transistor and a seventh transistor; the sub-pixel driving circuit further comprises a driving transistor and a light emitting element; the plurality of first adjusting patterns comprises a plurality of first adjusting sub-patterns;

[0023] The first electrode of the first transistor is coupled with the first initialization signal line, and the second electrode of the first transistor is coupled with the gate electrode of the driving transistor; the first electrode of the seventh transistor is coupled with the second initialization signal line, and the second electrode of the seventh transistor is coupled with the light emitting element;

[0024] The orthogonal projection of the first adjusting sub-pattern on the base plate at least partially overlaps with the orthogonal projection of the channel part of the first transistor in the corresponding sub-pixel driving circuit on the base plate, and at least partially overlaps with the orthogonal projection of the channel part of the seventh transistor in the sub-pixel driving circuit adjacent in the second direction on the base plate.

[0025] Optionally, the display substrate further comprises a plurality of data lines; the at least two transistors comprise a second transistor and a fourth transistor; the plurality of first adjusting patterns comprises a plurality of second adjusting sub-patterns;

[0026] The first electrode of the second transistor is coupled with the second electrode of the driving transistor, and the second electrode of the second transistor is coupled with the gate electrode of the driving transistor; the first electrode of the fourth transistor is coupled with the corresponding data line, and the second electrode of the fourth transistor is coupled with the first electrode of the driving transistor;

[0027] The orthogonal projection of the second adjusting sub-pattern on the base plate at least partially overlaps with the orthogonal projection of the channel part of the second transistor in the corresponding sub-pixel driving circuit on the base plate, and at least partially overlaps with the orthogonal projection of the channel part of the fourth transistor in the corresponding sub-pixel driving circuit on the base plate.

[0028] Optionally, the display substrate further comprises a driving chip; a plurality of first adjusting sub-patterns located in the same row in the first direction are sequentially coupled to form a first sub-adjusting line; a plurality of the first sub-adjusting lines in the display substrate are coupled, and the first sub-adjusting line is coupled with the driving chip.

[0029] Optionally, the display substrate further comprises a driving chip; a plurality of second adjusting sub-patterns located in the same row in the first direction are sequentially coupled to form a second sub-adjusting line; a plurality of the second sub-adjusting lines in the display substrate are coupled, and the second sub-adjusting line is coupled with the driving chip.

[0030] Optionally, the first adjustment sub-pattern and the second adjustment sub-pattern are set in the same layer and with the same material; or, the first adjustment sub-pattern and the second adjustment sub-pattern are set in different layers.

[0031] Optionally, at least a portion of the conditioning layer is located between the active layer and the substrate.

[0032] Based on the above-described display substrate technical solution, a second aspect of the present invention provides a display device including the above-described display substrate.

[0033] In the technical solution provided by the present invention, by setting the orthographic projection of the adjustment layer on the substrate to at least partially overlap with the orthographic projection of the channel portion of at least three transistors in each sub-pixel driving circuit on the substrate, various characteristics of at least three transistors in each sub-pixel driving circuit can be controlled, thereby effectively improving defects caused by transistor characteristics and characteristic deviations caused by unstable factory processes. At the same time, by adjusting the transistor characteristics, the optical characteristics of the display substrate can be adjusted and improved, thereby enhancing the display effect of the display substrate under different optical characteristics such as brightness and chromaticity. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0035] Figure 1 This is a schematic diagram of the adjustment layer of a display substrate provided in an embodiment of the present invention;

[0036] Figure 2 A circuit diagram of a sub-pixel driving circuit provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the layout of two sub-pixel driving circuits provided in an embodiment of the present invention;

[0038] Figure 4 for Figure 3 A schematic diagram of the adjustment layer in the middle;

[0039] Figure 5 for Figure 3 A schematic diagram of the active layer and the first gate metal layer;

[0040] Figure 6 for Figure 3 A schematic diagram of the active layer;

[0041] Figure 7 for Figure 3 A schematic diagram of the second gate metal layer;

[0042] Figure 8 for Figure 3 A schematic diagram of the first source / drain metal layer. Detailed Implementation

[0043] To further illustrate the display substrate and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0044] Please see Figures 1 to 6 This invention provides a display substrate, including: a substrate and a plurality of sub-pixel driving circuits disposed on the substrate. Figure 3 The diagram illustrates two sub-pixel driving circuits, each including multiple transistors. Figure 5 Seven transistors are illustrated, each including an active layer ( Figure 6 The diagram illustrates the active layer corresponding to each transistor, wherein the active layer includes a channel portion ( Figure 6 (The diagram illustrates the channel portion corresponding to each transistor); the display substrate also includes:

[0045] An adjustment layer (e.g., including a first adjustment pattern 10 and a second adjustment pattern 20) whose orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of the channel portion of at least three transistors in each sub-pixel driving circuit, the adjustment layer being capable of receiving an input adjustment signal, and the adjustment layer being capable of adjusting the characteristics of the at least three transistors.

[0046] For example, the plurality of sub-pixel driving circuits are arrayed in the display area of ​​the display substrate. The plurality of sub-pixel driving circuits are divided into multiple rows arranged along a second direction, with each row including a plurality of sub-pixel driving circuits arranged along a first direction. Alternatively, the plurality of sub-pixel driving circuits can be divided into multiple columns arranged along the first direction, with each column including a plurality of sub-pixel driving circuits arranged along the second direction.

[0047] For example, the first direction intersects with the second direction. The first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0048] For example, the sub-pixel driving circuit includes a 3T1C circuit (i.e., including 3 transistors and 1 capacitor), a 6T1C circuit (i.e., including 6 transistors and 1 capacitor), a 7T1C circuit (i.e., including 7 transistors and 1 capacitor), an 8T1C circuit (i.e., including 8 transistors and 1 capacitor), a 9T1C circuit (i.e., including 9 transistors and 1 capacitor), etc., but is not limited to these.

[0049] The orthogonal projection of the adjusting layer on the substrate covers the orthogonal projection of the channel part of at least three transistors in each sub-pixel driving circuit on the substrate.

[0050] The transistor includes an active layer and a base gate, and the base gate is made of a gate metal layer. The orthogonal projection of the channel part of the active layer on the substrate is covered by the orthogonal projection of the base gate on the substrate. The channel part forms a channel region.

[0051] The adjusting layer can serve as an auxiliary gate of the at least three transistors, and the characteristics of the at least three transistors can be adjusted by controlling the voltage value of the adjusting signal loaded on the adjusting layer.

[0052] The at least three transistors are formed in a double-gate structure, and the gate thereof includes a base gate and an auxiliary gate. The transistor can work under the joint control of the base gate and the auxiliary gate.

[0053] The characteristics of the transistor, such as threshold voltage Vth, mobility Mob, on-current Ion and sub-threshold swing Drrange, directly affect the display effect of the display product. By controlling the voltage of the adjusting signal transmitted on the adjusting layer, the characteristics of the transistor can be well adjusted.

[0054] The adjusting layer can be coupled with a driving chip in the display substrate to directly receive the signal provided by the driving chip. Alternatively, the adjusting layer can be coupled with a conductive film layer in the display area of the display substrate, so that the adjusting layer and the conductive film layer coupled therewith have the same signal. The conductive film layer includes a power line 901 or a scan line (for example, a reset line 905, a gate line 902, a light-emitting control line 903, etc.), but is not limited thereto.

[0055] According to the specific structure of the display substrate, in the display substrate provided by the embodiment of the present application, the orthogonal projection of the adjusting layer on the substrate at least partially overlaps the orthogonal projection of the channel part of at least three transistors in each sub-pixel driving circuit on the substrate, so that the characteristics of the at least three transistors in each sub-pixel driving circuit are adjusted, thereby effectively improving the badness caused by the characteristics of the transistor and the characteristic deviation caused by unstable factory process, and the optical characteristics of the display substrate can also be adjusted and improved by adjusting the characteristics of the transistor, so as to improve the display effect of the display substrate under different brightness, chroma and other optical characteristics.

[0056] As Figure 4 and Figure 5In some embodiments, the adjusting layer includes a plurality of first adjusting patterns 10 arranged in an array, each of the first adjusting patterns 10 includes at least a portion extending along a first direction;

[0057] A projection of the first adjusting pattern 10 on the substrate at least partially overlaps with a projection of a channel portion of at least two transistors arranged along the first direction in a corresponding sub-pixel driving circuit on the substrate.

[0058] In some embodiments, each sub-pixel driving circuit corresponds to at least one first adjusting pattern 10.

[0059] In some embodiments, each sub-pixel driving circuit corresponds to at least two first adjusting patterns 10 arranged along the second direction.

[0060] In some embodiments, the channel portions of the at least two transistors arranged along the first direction are arranged along the second direction.

[0061] The above arrangement that the projection of the first adjusting pattern 10 on the substrate at least partially overlaps with the projection of the channel portion of the at least two transistors arranged along the first direction in the corresponding sub-pixel driving circuit on the substrate enables the first adjusting pattern 10 to simultaneously adjust the characteristics of the at least two transistors. This layout not only effectively adjusts the characteristics of the transistors, but also facilitates the layout of the adjusting layer.

[0062] In some embodiments, the gates of the at least two transistors are coupled, and the first adjusting pattern 10 is connected to a gate signal.

[0063] In some embodiments, the first adjusting pattern 10 is coupled to the gates of the at least two transistors through a via, and the first adjusting pattern 10 is connected to the same gate signal as the gates.

[0064] In some embodiments, the gates of the at least two transistors are coupled to the same scan line, the projection of the first adjusting pattern 10 on the substrate overlaps with the projection of the scan line on the substrate, the first adjusting pattern 10 is coupled to the scan line through a via, and the first adjusting pattern 10 is connected to the same scan signal as the scan line.

[0065] The above arrangement that the first adjusting pattern 10 is coupled to the gates of the at least two transistors enables the first adjusting pattern 10 and the gates of the at least two transistors to be loaded with the same gate signal, which not only enables better adjustment of the characteristics of the transistors, but also reduces the difficulty of loading the signal for the first adjusting pattern 10.

[0066] AsFigure 1 In some embodiments, the display substrate further comprises a driving chip IC; the first adjusting patterns in the same row in the first direction are coupled in sequence to form a first adjusting line 1, at least one end of the first adjusting line 1 is coupled with the driving chip, and the driving chip is configured to provide the adjusting signal.

[0067] For example, the display substrate comprises a display area and a peripheral area surrounding the display area, the driving chip is located in the peripheral area, and the driving chip can realize arbitrary setting of the adjusting layer voltage. The peripheral area can further comprise an ET (Electrical Test) PAD, a bonding pin, an FPC (Flexible Printed Circuit) connection pin, and the like.

[0068] For example, the first adjusting patterns in the same row in the first direction are coupled in sequence to form the first adjusting line 1 in an integrated structure.

[0069] For example, the display substrate comprises a plurality of first adjusting lines 1 arranged in the second direction, a first end of each of the plurality of first adjusting lines 1 covering a channel portion of the same transistor is coupled with a first transmission line 31, and the first transmission line 31 is coupled with the driving chip. For example, the display substrate comprises a plurality of first adjusting lines 1 arranged in the second direction, a second end of each of the plurality of first adjusting lines 1 covering a channel portion of the same transistor is coupled with a second transmission line 32, and the second transmission line 32 is coupled with the driving chip. For example, the first transmission line 31 and the second transmission line 32 are located in the peripheral area.

[0070] The above setting mode can not only realize better adjustment of the characteristics of the transistor, but also effectively reduce the layout difficulty of the first adjusting pattern and the difficulty of loading a signal for the first adjusting pattern.

[0071] As shown in Figure 4 and Figure 5 In some embodiments, the display substrate comprises a plurality of scan lines, the scan lines comprise at least a portion extending in the first direction, and the gate electrodes of the at least two transistors are coupled with the same scan line; and the shape of the first adjusting line 1 is substantially the same as the shape of the scan line.

[0072] For example, the orthogonal projection of the first adjusting line 1 on the substrate at least partially overlaps the orthogonal projection of the scan line on the substrate.

[0073] For example, the orthogonal projection of the first adjusting line 1 on the substrate coincides with the orthogonal projection of the scan line on the substrate.

[0074] Exemplarily, the normal projection of the scan line on the base substrate is inside the normal projection of the first adjusting line 1 on the base substrate.

[0075] Exemplarily, the gate of the at least two transistors is formed in an integral structure with the scan line coupled thereto.

[0076] The above arrangement can not only achieve better adjustment of the characteristics of the transistors, but also effectively reduce the layout difficulty of the first adjusting pattern 10 and the difficulty of loading signals for the first adjusting pattern 10. Moreover, the shape of the first adjusting line 1 is substantially the same as that of the scan line, so that the first adjusting line 1 can use the same manufacturing equipment as the scan line, such as the same mask plate, which is conducive to reducing the manufacturing cost of the display substrate.

[0077] As shown in Figure 4 and Figure 5 In some embodiments, the adjusting layer includes a plurality of second adjusting patterns 20, and the normal projection of the second adjusting pattern 20 on the base substrate at least partially overlaps with the normal projection of a channel portion included in one transistor in the corresponding sub-pixel drive circuit on the base substrate.

[0078] Exemplarily, the plurality of second adjusting patterns 20 correspond one-to-one to the plurality of sub-pixel drive circuits in the display substrate.

[0079] Exemplarily, the normal projection of the second adjusting pattern 20 on the base substrate covers the normal projection of the channel portion included in one transistor in the corresponding sub-pixel drive circuit on the base substrate.

[0080] The above arrangement can independently adjust the characteristics of one transistor through the second adjusting pattern 20, and can achieve better adjustment of the characteristics of the transistors.

[0081] As shown in Figures 3 to 5 In some embodiments, the second adjusting pattern 20 is coupled to the gate of the one transistor in the corresponding sub-pixel drive circuit.

[0082] It should be noted that Figure 3 The circles in the figure represent via hole positions.

[0083] Exemplarily, the normal projection of the second adjusting pattern 20 on the base substrate has an overlapping area with the normal projection of the gate of the one transistor in the corresponding sub-pixel drive circuit on the base substrate. The second adjusting pattern 20 is coupled to the gate through a via hole.

[0084] Exemplarily, the second adjusting pattern 20 is coupled with the gate of the one transistor through a conductive connection, and the conductive connection is coupled with the second adjusting pattern 20 and the gate of the one transistor through a via, respectively.

[0085] The second adjusting pattern 20 is coupled with the gate of the one transistor in the corresponding sub-pixel driving circuit, so that the second adjusting pattern 20 and the gate of the one transistor can load the same signal, which not only can realize better adjustment of the characteristics of the transistor, but also can reduce the difficulty of loading the signal for the second adjusting pattern 20.

[0086] As shown in Figures 3 to 8 In some embodiments, the display substrate further includes a plurality of power lines 901, and the one transistor includes a driving transistor T3, and the second adjusting pattern 20 is coupled with the power line 901.

[0087] Exemplarily, the plurality of power lines 901 are arranged along the first direction, and the power line 901 includes at least a part extending along the second direction. The second adjusting pattern 20 is coupled with the power line 901, so that the second adjusting pattern 20 has the same power signal as the power line 901.

[0088] Exemplarily, the orthographic projection of the second adjusting pattern 20 on the substrate at least partially overlaps with the orthographic projection of the power line 901 on the substrate, and the second adjusting pattern 20 is coupled with the power line 901 at the overlapping position through a via.

[0089] The second adjusting pattern 20 is coupled with the power line 901, and the characteristics of the driving transistor T3 are adjusted through the second adjusting pattern 20, which is conducive to the stability of the characteristics of the driving transistor T3.

[0090] As shown in Figures 3 to 8 In some embodiments, the second adjusting pattern 20 includes a main body part 201 and an extension part 202, the orthographic projection of the main body part 201 on the substrate at least partially overlaps with the orthographic projection of the channel part 43 of the driving transistor T3 on the substrate, the orthographic projection of the extension part 202 on the substrate does not overlap with the channel part of the driving transistor, and at least partially overlaps with the orthographic projection of the power line 901 on the substrate, and the extension part 202 is coupled with the power line 901.

[0091] Exemplarily, the main body part 201 and the extension part 202 are formed as an integral structure.

[0092] For example, the orthographic projection of the main body portion 201 on the substrate covers the orthographic projection of the channel portion 43 of the driving transistor T3 on the substrate.

[0093] For example, the orthographic projection of the main body 201 on the substrate at least partially overlaps with the orthographic projection of the power line 901 on the substrate.

[0094] For example, the shape of the main body 201 is approximately the same as the shape of the gate of the driving transistor T3.

[0095] For example, the orthographic projection of the main body portion 201 on the substrate covers the orthographic projection of the gate of the driving transistor T3 on the substrate.

[0096] For example, the extension 202 includes at least a portion extending along the second direction.

[0097] For example, the orthographic projection of the extension 202 on the substrate does not overlap with the orthographic projection of the channel portion 45 of the fifth transistor T5 in the sub-pixel driving circuit on the substrate, and does not overlap with the orthographic projection of the channel portion 46 of the sixth transistor T6 in the sub-pixel driving circuit on the substrate.

[0098] For example, at least a portion of the orthographic projection of the extension 202 onto the substrate is located between the orthographic projection of the channel portion 45 of the fifth transistor T5 onto the substrate and the orthographic projection of the channel portion 46 of the sixth transistor T6 onto the substrate.

[0099] For example, the extension 202 is coupled to the power line 901 via a via. At least a portion of the orthographic projection of the light-emitting control line 903 onto the substrate is located between the orthographic projection of the via onto the substrate and the orthographic projection of the main body 201 onto the substrate.

[0100] The above configuration not only enables better adjustment of the characteristics of the driving transistor T3, but also effectively reduces the layout difficulty of the second adjustment pattern 20 and the difficulty of loading signals for the second adjustment pattern 20.

[0101] like Figures 3 to 8 As shown, in some embodiments, the display substrate further includes a plurality of light-emitting control lines 903, the light-emitting control lines 903 including at least a portion extending along a first direction; the orthographic projection of the light-emitting control lines 903 on the substrate at least partially overlaps with the orthographic projection of the extension 202 on the substrate.

[0102] The above configuration not only enables better adjustment of the characteristics of the driving transistor T3, but also effectively reduces the layout difficulty of the second adjustment pattern 20 and the difficulty of loading signals for the second adjustment pattern 20.

[0103] In some embodiments, the display substrate further includes a driver chip; second adjustment patterns 20 located in the same row along the first direction are sequentially coupled to form a second adjustment line, and at least one end of the second adjustment line is coupled to the driver chip.

[0104] For example, second adjustment patterns 20 located in the same row along the first direction are sequentially coupled through a first conductive connection portion. For example, the second adjustment pattern 20 and the first conductive connection portion are formed as an integral structure.

[0105] For example, the display substrate includes a plurality of second adjustment lines arranged along the second direction. For example, the first ends of the plurality of second adjustment lines are coupled together, and / or the second ends of the plurality of second adjustment lines are coupled together. For example, the first end and / or the second end of the second adjustment lines are coupled to the driver chip.

[0106] The above configuration not only enables better adjustment of the characteristics of the driving transistor T3, but also effectively reduces the layout difficulty of the second adjustment pattern 20 and the difficulty of loading signals for the second adjustment pattern 20.

[0107] Taking the sub-pixel driving circuit including 7T1C as an example, the specific layout of the display substrate is as follows:

[0108] like Figures 3 to 8 As shown, in some embodiments, the display substrate further includes multiple first initialization signal lines 906 and multiple second initialization signal lines 904; the at least two transistors include a first transistor T1 and a seventh transistor T7; the sub-pixel driving circuit further includes a driving transistor T3 and a light-emitting element; the multiple first adjustment patterns 10 include multiple first adjustment sub-patterns 101;

[0109] The first terminal of the first transistor T1 is coupled to the first initialization signal line 906, and the second terminal of the first transistor T1 is coupled to the gate of the driving transistor T3; the first terminal of the seventh transistor T7 is coupled to the second initialization signal line 904, and the second terminal of the seventh transistor T7 is coupled to the light-emitting element.

[0110] The first adjusting sub-pattern 101 has a projection on the substrate which at least partially overlaps with a projection on the substrate of a channel portion 41 of a first transistor T1 in a corresponding sub-pixel driving circuit, and also at least partially overlaps with a projection on the substrate of a channel portion 47 of the seventh transistor T7 in a sub-pixel driving circuit adjacent in a second direction.

[0111] Illustratively, the plurality of first adjusting sub-patterns 101 correspond one-to-one to a plurality of sub-pixel driving circuits in the display substrate.

[0112] Illustratively, the display substrate includes a plurality of reset lines 905 which include at least a portion extending in the first direction. The plurality of reset lines 905 correspond one-to-one to a plurality of rows of sub-pixel driving circuits in the display substrate. The reset line 905 is coupled to a gate of the first transistor T1 in a corresponding sub-pixel driving circuit, and also coupled to a gate of the seventh transistor T7 in a sub-pixel driving circuit adjacent in the second direction.

[0113] Illustratively, the at least two transistors include the first transistor T1 in a current sub-pixel driving circuit, and the seventh transistor T7 in a sub-pixel driving circuit adjacent in the second direction.

[0114] Since the gate of the first transistor T1 in the current sub-pixel driving circuit and the gate of the seventh transistor T7 in the sub-pixel driving circuit adjacent in the second direction are coupled to the same reset line 905, the gates of the first transistor T1 and the seventh transistor T7 receive the same scan signal.

[0115] Illustratively, in the second direction, the first initialization signal lines 906 and the second initialization signal lines 904 are arranged alternately.

[0116] Illustratively, the plurality of first initialization signal lines 906 correspond one-to-one to a plurality of rows of sub-pixel driving circuits in the display substrate. The plurality of second initialization signal lines 904 correspond one-to-one to a plurality of rows of sub-pixel driving circuits in the display substrate.

[0117] Illustratively, a first electrode of the first transistor T1 is coupled to a first initialization signal line 906 corresponding to a sub-pixel driving circuit to which the first transistor T1 belongs, and a second electrode of the first transistor T1 is coupled to a gate of a driving transistor T3 in the sub-pixel driving circuit to which the first transistor T1 belongs. A first electrode of the seventh transistor T7 is coupled to a second initialization signal line 904 corresponding to a sub-pixel driving circuit to which the seventh transistor T7 belongs, and a second electrode of the seventh transistor T7 is coupled to an anode of a light emitting element in the sub-pixel driving circuit to which the seventh transistor T7 belongs.

[0118] For example, the first transistor T1 is configured to reset the gate of the driving transistor T3, and the seventh transistor T7 is configured to reset the anode of the light emitting element.

[0119] For example, the channel portion 41 of the first transistor T1 in the current sub-pixel driving circuit and the channel portion 47 of the seventh transistor T7 in the sub-pixel driving circuit adjacent along the second direction are arranged along the first direction.

[0120] For example, the orthogonal projection of the first adjusting sub-pattern 101 on the substrate covers the orthogonal projection of the channel portion 41 of the first transistor T1 in the corresponding sub-pixel driving circuit on the substrate, and covers the orthogonal projection of the channel portion 47 of the seventh transistor T7 in the sub-pixel driving circuit adjacent along the second direction on the substrate.

[0121] For example, the orthogonal projection of the first adjusting sub-pattern 101 on the substrate covers the orthogonal projection of the gate of the first transistor T1 in the corresponding sub-pixel driving circuit on the substrate, and covers the orthogonal projection of the gate of the seventh transistor T7 in the sub-pixel driving circuit adjacent along the second direction on the substrate.

[0122] The above-mentioned orthogonal projection of the first adjusting sub-pattern 101 on the substrate at least partially overlaps the orthogonal projection of the channel portion 41 of the first transistor T1 in the corresponding sub-pixel driving circuit on the substrate, and at least partially overlaps the orthogonal projection of the channel portion 47 of the seventh transistor T7 in the sub-pixel driving circuit adjacent along the second direction on the substrate; so that the first adjusting sub-pattern 101 can simultaneously adjust the characteristics of the first transistor T1 and the seventh transistor T7. Therefore, it is beneficial to simplify the layout structure of the adjusting layer, reduce the layout difficulty of the adjusting layer, and reduce the difficulty of providing the adjusting signal for the adjusting layer.

[0123] Moreover, since the gates of the first transistor T1 and the seventh transistor T7 receive the same signal, the same first adjusting sub-pattern 101 can accurately adjust the characteristics of the first transistor T1 and the seventh transistor T7.

[0124] As Figures 3 to 8 shown in some embodiments, the display substrate further comprises a plurality of data lines; the at least two transistors comprise a second transistor T2 and a fourth transistor T4; the plurality of first adjusting patterns 10 comprises a plurality of second adjusting sub-patterns 102;

[0125] The first electrode of the second transistor T2 is coupled with the second electrode of the driving transistor T3, and the second electrode of the second transistor T2 is coupled with the gate electrode of the driving transistor T3; the first electrode of the fourth transistor T4 is coupled with a corresponding data line, and the second electrode of the fourth transistor T4 is coupled with the first electrode of the driving transistor T3 in the corresponding sub-pixel driving circuit.

[0126] The normal projection of the second adjusting sub-pattern 102 on the substrate at least partially overlaps with the normal projection of the channel portion 42 of the second transistor T2 in the corresponding sub-pixel driving circuit on the substrate, and at least partially overlaps with the normal projection of the channel portion 44 of the fourth transistor T4 in the corresponding sub-pixel driving circuit on the substrate.

[0127] Illustratively, the plurality of first adjusting sub-patterns 101 correspond to the plurality of sub-pixel driving circuits in the display substrate one by one.

[0128] Illustratively, the data line includes at least a portion extending along the second direction. The data line is used to transmit a data signal. The plurality of data lines correspond to the plurality of columns of sub-pixel driving circuits in the display substrate one by one.

[0129] Illustratively, the display substrate includes a plurality of gate lines 902, and the gate lines 902 include at least a portion extending along the first direction in the opposite direction. The plurality of gate lines 902 correspond to the plurality of rows of sub-pixel driving circuits in the display substrate one by one.

[0130] Illustratively, the sub-pixel driving circuit includes a second transistor T2 and a fourth transistor T4. The gate electrode of the second transistor T2 is coupled with a corresponding gate line 902, the first electrode of the second transistor T2 is coupled with the second electrode of the driving transistor T3 in the sub-pixel driving circuit to which the second transistor T2 belongs, and the second electrode of the second transistor T2 is coupled with the gate electrode of the driving transistor T3. The gate electrode of the fourth transistor T4 is coupled with a corresponding gate line 902, the first electrode of the fourth transistor T4 is coupled with a corresponding data line, and the second electrode of the fourth transistor T4 is coupled with the first electrode of the driving transistor T3 in the sub-pixel driving circuit to which the fourth transistor T4 belongs.

[0131] Since the second transistor T2 and the fourth transistor T4 are coupled with the same gate line 902, the second transistor T2 and the fourth transistor T4 receive the same scan signal.

[0132] Illustratively, the second transistor T2 is used to compensate the driving transistor T3, and the fourth transistor T4 is used to write a data signal.

[0133] For example, at least a portion of the channel portion 42 of the second transistor T2 is aligned with the channel portion 44 of the fourth transistor T4 along the first direction. For example, the second transistor T2 includes a dual-gate structure, the active layer corresponding to the second transistor T2 is L-shaped, the two channel portions of the second transistor T2 are respectively located on two sides of the L-shape, and one channel portion of the second transistor T2 and the channel portion 44 of the fourth transistor T4 are located in the same row along the first direction.

[0134] For example, the orthographic projection of the second adjustment sub-pattern 102 on the substrate covers the orthographic projection of the channel portion 42 of the second transistor T2 in the corresponding sub-pixel driving circuit on the substrate, and also covers the orthographic projection of the channel portion 44 of the fourth transistor T4 in the corresponding sub-pixel driving circuit on the substrate.

[0135] For example, the orthographic projection of the second adjustment sub-pattern 102 on the substrate covers the orthographic projection of the gate of the second transistor T2 in the corresponding sub-pixel driving circuit on the substrate, and also covers the orthographic projection of the gate of the fourth transistor T4 in the corresponding sub-pixel driving circuit on the substrate.

[0136] The above-described configuration allows the orthographic projection of the second adjustment sub-pattern 102 onto the substrate to at least partially overlap with the orthographic projection of the channel portion 42 of the second transistor T2 in the corresponding sub-pixel driving circuit onto the substrate, and also to at least partially overlap with the orthographic projection of the channel portion 44 of the fourth transistor T4 in the corresponding sub-pixel driving circuit onto the substrate. This enables the second adjustment sub-pattern 102 to simultaneously adjust the characteristics of both the second transistor T2 and the fourth transistor T4. Therefore, this simplifies the layout structure of the adjustment layer, reduces the difficulty of layout, and lowers the difficulty of providing adjustment signals to the adjustment layer.

[0137] Furthermore, since the gates of the second transistor T2 and the fourth transistor T4 receive the same signal, the characteristics of the second transistor T2 and the fourth transistor T4 can be accurately adjusted using the same second adjustment sub-pattern 102.

[0138] like Figures 3 to 8 As shown, in some embodiments, the display substrate further includes multiple power lines 901; the at least two transistors include a fifth transistor T5 and a sixth transistor T6;

[0139] The first electrode of the fifth transistor T5 is coupled with the power supply line 901, and the second electrode of the fifth transistor T5 is coupled with the first electrode of the driving transistor T3; the first electrode of the sixth transistor T6 is coupled with the second electrode of the driving transistor T3, and the second electrode of the sixth transistor T6 is coupled with the light emitting element.

[0140] Exemplarily, the plurality of power supply lines 901 correspond to the plurality of columns of sub-pixel driving circuits in the display substrate one by one, and the power supply line 901 comprises at least a portion extending along the second direction. The power supply line 901 is used for transmitting a power supply signal.

[0141] Exemplarily, the display substrate further comprises a plurality of light emitting control lines 903, and the plurality of light emitting control lines 903 correspond to the plurality of rows of sub-pixel driving circuits in the display substrate one by one. The light emitting control line 903 comprises at least a portion extending along the first direction. The light emitting control line 903 is used for transmitting a light emitting control signal.

[0142] Exemplarily, the sub-pixel driving circuit comprises a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is coupled with the corresponding light emitting control line 903, the first electrode of the fifth transistor T5 is coupled with the corresponding power supply line 901, and the second electrode of the fifth transistor T5 is coupled with the first electrode of the driving transistor T3 in the sub-pixel driving circuit to which the fifth transistor T5 belongs. The gate of the sixth transistor T6 is coupled with the corresponding light emitting control line 903, the first electrode of the sixth transistor T6 is coupled with the second electrode of the driving transistor T3 in the sub-pixel driving circuit to which the sixth transistor T6 belongs, and the second electrode of the sixth transistor T6 is coupled with the anode of the light emitting element. The cathode of the light emitting element receives a negative power supply signal.

[0143] Since the fifth transistor T5 and the sixth transistor T6 are coupled with the same light emitting control line 903, the fifth transistor T5 and the sixth transistor T6 receive the same scanning signal.

[0144] Exemplarily, the fifth transistor T5 and the sixth transistor T6 are used for controlling the light emitting element to realize light emission.

[0145] Exemplarily, the channel portion 45 of the fifth transistor T5 and the channel portion 46 of the sixth transistor T6 are arranged along the first direction.

[0146] As Figure 4 and Figure 5In some embodiments, the display substrate is provided as shown. In some embodiments, the display substrate further comprises a driving chip; a plurality of first adjusting sub-patterns 101 in the same row in the first direction are sequentially coupled to form a first adjusting sub-line 11; and a plurality of first adjusting sub-lines 11 in the display substrate are coupled to each other, and the first adjusting sub-line 11 is coupled to the driving chip.

[0147] In some embodiments, a plurality of first adjusting sub-patterns 101 in the same row in the first direction are sequentially coupled to form a first adjusting sub-line 11 in an integrated structure.

[0148] In some embodiments, the reset line 905 is multiplexed as the gate of a first transistor T1 and the gate of a seventh transistor T7 in the same row, and the shape of the first adjusting sub-line 11 is substantially the same as the shape of the reset line 905 coupled to the first transistor T1. It should be noted that "overlap" here refers to the orthographic projection of the first adjusting sub-line on the substrate and the orthographic projection of the channel portion 41 of the first transistor T1 on the substrate.

[0149] In some embodiments, the orthographic projection of the first adjusting sub-line 11 on the substrate at least partially overlaps with the orthographic projection of the reset line 905 coupled to the first transistor T1 on the substrate. In some embodiments, the orthographic projection of the first adjusting sub-line 11 on the substrate coincides with the orthographic projection of the reset line 905 coupled to the first transistor T1 on the substrate. In some embodiments, the orthographic projection of the first adjusting sub-line 11 on the substrate surrounds the orthographic projection of the reset line 905 coupled to the first transistor T1 on the substrate.

[0150] In some embodiments, the display substrate comprises a plurality of first adjusting sub-lines 11, and the plurality of first adjusting sub-lines 11 correspond to a plurality of rows of sub-pixel driving circuits in the display substrate.

[0151] In some embodiments, the first ends of the plurality of first adjusting sub-lines 11 are coupled to each other through a first sub-transmission line, and the first sub-transmission line is coupled to the driving chip. In some embodiments, the first sub-transmission line is located in the peripheral region of the display substrate.

[0152] In some embodiments, the second ends of the plurality of first adjusting sub-lines 11 are coupled to each other through a second sub-transmission line, and the second sub-transmission line is coupled to the driving chip. In some embodiments, the second sub-transmission line is located in the peripheral region of the display substrate.

[0153] The above arrangement can ensure that the first adjusting sub-line 11 can adjust the characteristics of the first transistor T1 and the seventh transistor T7, while reducing the layout difficulty of the first adjusting sub-line 11 and the difficulty of providing an adjusting signal for the first adjusting sub-line 11.

[0154] As shown in Figure 4 and Figure 5 In some embodiments, the display substrate further comprises a driving chip; a plurality of second adjusting sub-patterns 102 in the same row in the first direction are sequentially coupled to form a second sub-adjusting line 12; a plurality of second sub-adjusting lines 12 in the display substrate are coupled, and the second sub-adjusting line 12 is coupled to the driving chip.

[0155] For example, a plurality of second adjusting sub-patterns 102 in the same row in the first direction are sequentially coupled to form a second sub-adjusting line 12 in an integrated structure.

[0156] For example, the gate line 902 is multiplexed as the gate of a second transistor T2 and the gate of a fourth transistor T4 in a row coupled thereto, and the shape of the second sub-adjusting line 12 is substantially the same as the shape of the gate line 902 coupled to the second transistor T2 covered thereby.

[0157] For example, the orthographic projection of the second sub-adjusting line 12 on the substrate at least partially overlaps the orthographic projection of the gate line 902 coupled to the second transistor T2 covered thereby on the substrate. For example, the orthographic projection of the second sub-adjusting line 12 on the substrate coincides with the orthographic projection of the gate line 902 coupled to the second transistor T2 covered thereby on the substrate. For example, the orthographic projection of the second sub-adjusting line 12 on the substrate surrounds the orthographic projection of the gate line 902 coupled to the second transistor T2 covered thereby on the substrate.

[0158] For example, the display substrate comprises a plurality of second sub-adjusting lines 12, and the plurality of second sub-adjusting lines 12 correspond one-to-one to a plurality of rows of sub-pixel driving circuits in the display substrate.

[0159] For example, the first ends of the plurality of second sub-adjusting lines 12 are coupled through a third sub-transmission line, and the third sub-transmission line is coupled to the driving chip. For example, the third sub-transmission line is located in the peripheral region of the display substrate.

[0160] For example, the second ends of the plurality of second sub-adjusting lines 12 are coupled through a fourth sub-transmission line, and the fourth sub-transmission line is coupled to the driving chip. For example, the fourth sub-transmission line is located in the peripheral region of the display substrate.

[0161] The above arrangement can ensure that the second sub-adjusting line 12 can adjust the characteristics of the second transistor T2 and the fourth transistor T4, while reducing the layout difficulty of the second sub-adjusting line 12 and the difficulty of providing an adjusting signal for the second sub-adjusting line 12.

[0162] In some embodiments, as shown in FIG. 1, the display substrate 100 includes a base 1000, a first adjusting sub-pattern 101, a second adjusting sub-pattern 102, and a display layer 103. The display layer 103 is disposed on the base 1000. The first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 are disposed on the display layer 103. Figure 4 In some embodiments, as shown in FIG. 1, the display substrate 100 includes a base 1000, a first adjusting sub-pattern 101, a second adjusting sub-pattern 102, and a display layer 103. The display layer 103 is disposed on the base 1000. The first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 are disposed on the display layer 103.

[0163] In some embodiments, the first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 are disposed in the same layer and are made of the same material. In this way, the first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 can be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0164] In some embodiments, the first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 are disposed in different layers. In this way, the insulating layer is added between the two layers in which the first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 are disposed. In this way, the layout of the first adjusting sub-pattern 101 and the second adjusting sub-pattern 102 is conducive to reducing the probability of short circuit between the first adjusting sub-pattern 101 and the second adjusting sub-pattern 102, and reducing the layout difficulty of the adjusting layer.

[0165] In some embodiments, at least part of the adjusting layer is located between the active layer and the base.

[0166] In some embodiments, the display substrate includes, in sequence from the base, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first passivation layer, a first planarization layer, a second source / drain metal layer, a second passivation layer, a second planarization layer, an anode layer, a pixel definition layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer. In some embodiments, the display substrate can also not include the first passivation layer and the second passivation layer. In some embodiments, the display substrate can also not include the second source / drain metal layer, the second passivation layer, and the second planarization layer.

[0167] In some embodiments, the active layer is used to form the channel part of each transistor in the sub-pixel driving circuit, and can also be used to form the first electrode and the second electrode of each transistor.

[0168] In some embodiments, the first gate metal layer is used to form the reset line 905, the gate line 902, the light-emitting control line 903, and the gate electrode of each transistor in the display substrate. It is worth noting that the gate electrode of the driving transistor T3 can be multiplexed as the first electrode plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.

[0169] In some embodiments, the second gate metal layer is used to form the first initialization signal line 906, the second initialization signal line 904, the second electrode plate Cst2 of the storage capacitor Cst, and the shielding pattern in the display substrate.

[0170] For example, the first source-drain metal layer is used to form a data line in the display substrate, a power supply line 901, and some conductive connection parts.

[0171] For example, the adjusting layer is made of a metal material. At least part of the adjusting layer is located between the active layer and the substrate, and the adjusting layer and the active layer have a base insulating layer therebetween. For example, the second adjusting pattern 20 can be coupled with the power supply line 901 through a via hole penetrating through the base insulating layer, the first gate insulating layer, the second insulating layer, and the interlayer insulating layer.

[0172] The above arrangement that at least part of the adjusting layer is located between the active layer and the substrate makes the adjusting layer be located in an independent layer, which can reduce the probability of short circuit between the adjusting layer and other film layers in the display substrate, and can also reduce the layout difficulty of the adjusting layer.

[0173] In some embodiments, the driving chip can independently provide an adjusting signal for the first sub-adjusting line 11 and the second sub-adjusting line 12. For example, the adjusting signal provided for the first sub-adjusting line 11 is the same as the signal transmitted by the reset line 905, and the adjusting signal provided for the second sub-adjusting line 12 is the same as the signal transmitted by the gate line 902.

[0174] The embodiment of the present application also provides a display device including the display substrate provided by the above embodiment.

[0175] It should be noted that the display device can be any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board, a back plate, etc.

[0176] Since the display substrate provided by the above embodiment has the adjusting layer whose orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of the channel part included in at least three transistors in each sub-pixel driving circuit, the various characteristics of the at least three transistors in each sub-pixel driving circuit are adjusted and controlled, thereby effectively improving the adverse effects caused by the characteristics of the transistors and the characteristic deviation caused by unstable factory process, and also adjusting and improving the optical characteristics of the display substrate by adjusting the characteristics of the transistors, and improving the display effect of the display substrate under different brightness, chroma, and other optical characteristics.

[0177] Therefore, the display device provided by the embodiment of the present application also has the above beneficial effects when including the above display substrate, which will not be described herein again.

[0178] It should be noted that the "same layer" in the embodiments of the present application can refer to a film layer on the same structure layer. Or for example, the film layers on the same layer can be layer structures formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to pattern the film layer by a one-time patterning process. According to the difference of the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0179] In the method embodiments of the present application, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes in the sequence of the steps without creative labor are also within the protection scope of the present application.

[0180] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, they are described more simply, and the relevant parts can be referred to the part of the description of the product embodiments.

[0181] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the common meaning understood by a person skilled in the art. The "first", "second" and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. "Include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0182] It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0183] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0184] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized in that, include: The display substrate includes a substrate and a plurality of sub-pixel driving circuits disposed on the substrate, the sub-pixel driving circuits including a plurality of transistors, the transistors including an active layer, the active layer including a channel portion; the display substrate further includes: An adjustment layer, wherein the orthographic projection of the adjustment layer on the substrate at least partially overlaps with the orthographic projection of the channel portion of at least three transistors in each sub-pixel driving circuit on the substrate, the adjustment layer is capable of receiving an input adjustment signal, and the adjustment layer is capable of adjusting the characteristics of the at least three transistors; The adjustment layer includes a plurality of first adjustment patterns arranged in an array, each first adjustment pattern including at least a portion extending along a first direction; the orthographic projection of the first adjustment pattern on the substrate at least partially overlaps with the orthographic projection of the channel portion of at least two transistors arranged along the first direction in the corresponding sub-pixel driving circuit on the substrate. The display substrate further includes a driving chip; first adjustment patterns located in the same row along the first direction are sequentially coupled to form a first adjustment line, at least one end of the first adjustment line is coupled to the driving chip, and the driving chip is used to provide the adjustment signal; The display substrate includes multiple scan lines, each scan line including at least a portion extending along the first direction, and the gates of the at least two transistors are coupled to the same scan line; the shape of the first adjustment line is substantially the same as the shape of the scan line; the orthographic projection of the first adjustment line on the substrate at least partially overlaps with the orthographic projection of the scan line on the substrate. The display substrate includes multiple first adjustment lines arranged along a second direction. The first ends of the multiple first adjustment lines covering the channel portion of the same transistor are respectively coupled to a first transmission line, and the first transmission line is coupled to the driver chip.

2. The display substrate according to claim 1, characterized in that, The gates of the at least two transistors are coupled together, and the first adjustment pattern is connected to the gate signal.

3. The display substrate according to claim 1, characterized in that, The adjustment layer includes a plurality of second adjustment patterns, the orthographic projection of the second adjustment pattern on the substrate at least partially overlapping the orthographic projection of the channel portion of a transistor in a corresponding sub-pixel driving circuit on the substrate.

4. The display substrate according to claim 3, characterized in that, The second adjustment pattern is coupled to the gate of a transistor in the corresponding sub-pixel driving circuit.

5. The display substrate according to claim 3, characterized in that, The display substrate also includes multiple power lines; the transistor includes a driving transistor, and the second adjustment pattern is coupled to the power lines.

6. The display substrate according to claim 5, characterized in that, The second adjustment pattern includes a main body and an extension; the orthographic projection of the main body on the substrate at least partially overlaps with the orthographic projection of the channel portion of the driving transistor on the substrate. The orthographic projection of the extension on the substrate does not overlap with the channel portion of the driving transistor, but at least partially overlaps with the orthographic projection of the power line on the substrate, and the extension is coupled to the power line.

7. The display substrate according to claim 6, characterized in that, The display substrate further includes multiple light-emitting control lines, each light-emitting control line including at least a portion extending along a first direction; the orthographic projection of the light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the extension portion on the substrate.

8. The display substrate according to claim 3, characterized in that, The display substrate further includes a driver chip; second adjustment patterns located in the same row along a first direction are sequentially coupled to form a second adjustment line, and at least one end of the second adjustment line is coupled to the driver chip.

9. The display substrate according to claim 1 or 2, characterized in that, The display substrate further includes multiple first initialization signal lines and multiple second initialization signal lines; the at least two transistors include a first transistor and a seventh transistor; the sub-pixel driving circuit further includes a driving transistor and a light-emitting element; the multiple first adjustment patterns include multiple first adjustment sub-patterns; The first terminal of the first transistor is coupled to the first initialization signal line, and the second terminal of the first transistor is coupled to the gate of the driving transistor; the first terminal of the seventh transistor is coupled to the second initialization signal line, and the second terminal of the seventh transistor is coupled to the light-emitting element; The orthographic projection of the first adjustment sub-pattern onto the substrate at least partially overlaps with the orthographic projection of the channel portion of the first transistor in the corresponding sub-pixel driving circuit onto the substrate, and also at least partially overlaps with the orthographic projection of the channel portion of the seventh transistor in the adjacent sub-pixel driving circuit along the second direction onto the substrate.

10. The display substrate according to claim 9, characterized in that, The display substrate further includes multiple data lines; the at least two transistors include a second transistor and a fourth transistor; the plurality of first adjustment patterns include a plurality of second adjustment sub-patterns; The first terminal of the second transistor is coupled to the second terminal of the driving transistor, and the second terminal of the second transistor is coupled to the gate of the driving transistor; the first terminal of the fourth transistor is coupled to the corresponding data line, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor. The orthographic projection of the second adjustment sub-pattern onto the substrate at least partially overlaps with the orthographic projection of the channel portion of the second transistor in the corresponding sub-pixel driving circuit onto the substrate, and also at least partially overlaps with the orthographic projection of the channel portion of the fourth transistor in the corresponding sub-pixel driving circuit onto the substrate.

11. The display substrate according to claim 9, characterized in that, The display substrate further includes a driving chip; a plurality of first adjustment sub-patterns located in the same row along the first direction are sequentially coupled to form a first sub-adjustment line; a plurality of first sub-adjustment lines in the display substrate are coupled to each other, and the first sub-adjustment lines are coupled to the driving chip.

12. The display substrate according to claim 10, characterized in that, The display substrate further includes a driving chip; a plurality of second adjustment sub-patterns located in the same row along the first direction are sequentially coupled to form a second sub-adjustment line; a plurality of second sub-adjustment lines in the display substrate are coupled to each other, and the second sub-adjustment lines are coupled to the driving chip.

13. The display substrate according to claim 12, characterized in that, The first adjustment sub-pattern and the second adjustment sub-pattern are set in the same layer and made of the same material; or... The first adjustment sub-graphic and the second adjustment sub-graphic are set in different layers.

14. The display substrate according to claim 1, characterized in that, At least a portion of the conditioning layer is located between the active layer and the substrate.

15. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 14.

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