Micro-LED full-color display device and manufacturing method thereof

Abstract

The invention relates to a Micro-LED full-color display device and a manufacturing method thereof. The display device comprises a driving substrate and first, second and third light-emitting component layers which are bonded in sequence to form a vertical stacked structure. The light-emitting component layers are electrically interconnected among layers through the through electrode group, the first active layer of the first light-emitting component layer is kept continuous, and the active region is prevented from being damaged by controlling the etching depth. The first, second and third light-emitting regions are respectively configured as red, green and blue light-emitting regions, the projection positions on the horizontal plane are staggered, and the area ratio is 2: 1: 1, so that the red light efficiency loss is compensated. The manufacturing method comprises the steps of forming the light-emitting component layers on the temporary substrate and sequentially bonding the light-emitting component layers, wherein when the first light-emitting structure is formed, etching is controlled to be stopped before reaching the first active layer. The method further comprises the processes of filling and planarization of an insulating layer, removal of a temporary substrate, formation of an optical isolation layer and electrode segmentation, and the performance and the manufacturing yield of the device are improved through structural innovation and process optimization.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a Micro-LED full-color display device and its manufacturing method. Background Technology

[0002] Micro-LED display technology, with its high brightness, high contrast, fast response, low power consumption, and long lifespan, is considered a core direction for next-generation display technology, showing particular application potential in augmented reality (AR), virtual reality (VR), and large-size high-definition displays. However, as LED chip sizes shrink to the micrometer scale, the "size effect" becomes increasingly prominent, causing the external quantum efficiency (EQE) to drop sharply with size reduction. This becomes an obstacle restricting the realization of low-power, high-brightness, full-color displays in Micro-LEDs. This problem is particularly prominent in red Micro-LEDs, forming the so-called "red light problem." In the Micro-LED manufacturing process, pixel mesa is typically defined using inductively coupled plasma (ICP) dry etching, which is highly complex. Individual red pixels require multiple photolithography / etching processes. This process easily introduces dangling bonds, lattice damage, and impurities into the sidewalls, forming deep-level defect states that become channels for non-radiative recombination. Studies have shown that sidewall defect density is inversely proportional to device size, with a particularly significant impact on small-sized red Micro-LEDs. Although passivation layer deposition (such as SiO2) and wet repair can reduce the impact of defects, how to intrinsically suppress defect generation within the chip microstructure remains a key challenge at the process level. Furthermore, in traditional single-grid layouts, the red light area accounts for less than 50%, failing to effectively compensate for efficiency losses.

[0003] Red light efficiency degradation, controllability of sidewall damage, and process complexity remain core challenges. Therefore, device structures and manufacturing methods that optimize structure and reduce the impact of sidewall defects are needed to balance efficiency, cost, and reliability. Summary of the Invention

[0004] The purpose of this application is to provide an improved Micro-LED display device and its manufacturing method, which aims to solve the problem of low luminous efficiency of red sub-pixels in the prior art, thereby improving the overall power efficiency, brightness and color performance of the display device without increasing the complexity of the process.

[0005] The purpose of this application is achieved through the following technical solution: the Micro-LED full-color display device of this application includes a driving substrate, a first light-emitting component layer, a second light-emitting component layer, and a third light-emitting component layer. The driving substrate, the first light-emitting component layer, the second light-emitting component layer, and the third light-emitting component layer are bonded together from bottom to top to form a first bonding interface, a second bonding interface, and a third bonding interface, respectively. The first light-emitting component layer includes a first through electrode group, a second through electrode group and a first light-emitting structure; the second light-emitting component layer includes a third through electrode group and a plurality of second light-emitting structures; and the third light-emitting component layer includes a plurality of third light-emitting structures. The first through electrode group and the second through electrode group extend from the second bonding interface to the first bonding interface and are electrically connected to the corresponding pixel electrode on the driving substrate. The third through electrode group extends from the third bonding interface to the second bonding interface and is electrically connected to the second through electrode group. The first light-emitting structure includes a first connecting electrode group connected to a pixel electrode on a driving substrate; the second light-emitting structure includes a second connecting electrode group connected to a first through electrode group; and the third light-emitting structure includes a third connecting electrode group connected to a third through electrode group. The first light-emitting structure includes multiple first p-type electrode layers, a first p-type layer, a first active layer, a first n-type layer, and multiple first n-type electrode layers. The region corresponding to one first p-type electrode layer and one first n-type electrode layer is used as the first light-emitting region, and the first active layer is a continuous layer.

[0006] In one embodiment, the second light-emitting component includes a second light-emitting area, the third light-emitting component includes a third light-emitting area, the first light-emitting area is a red light-emitting area, the second light-emitting area is a green light-emitting area, and the third light-emitting area is a blue light-emitting area, and the projection positions of the first light-emitting area, the second light-emitting area and the third light-emitting area on the horizontal plane are staggered.

[0007] In one embodiment, the area ratio of the first light-emitting region, the second light-emitting region, and the third light-emitting region is 2:1:1.

[0008] This application further provides a method for manufacturing a Micro-LED full-color display device, comprising: A first light-emitting component layer is formed on a temporary substrate. The first light-emitting component layer includes a first through electrode group, a second through electrode group, and a first light-emitting structure. The first through electrode group and the second through electrode group extend through the first light-emitting component layer. The first light-emitting structure includes a first connecting electrode group. The first light-emitting component layer is bonded to the driving substrate, so that the first through electrode group, the second through electrode group and the first connection electrode group are electrically connected to the corresponding pixel electrode on the driving substrate. A second light-emitting component layer is formed on a temporary substrate. The second light-emitting component layer includes a third through electrode group and a plurality of second light-emitting structures. The third through electrode group extends through the second light-emitting component layer. The second light-emitting structure includes a second connecting electrode group. The second light-emitting component layer is bonded to the first light-emitting component layer, so that the third through electrode group is electrically connected to the second through electrode group, and the second connecting electrode group is electrically connected to the first through electrode group. A third light-emitting component layer is formed on a temporary substrate, the third light-emitting component layer including a plurality of third light-emitting structures, the third light-emitting structures including a third connecting electrode group; The third light-emitting component layer is bonded to the second light-emitting component layer, so that the third connecting electrode group is correspondingly electrically connected to the third through electrode group; The specific steps for forming the first light-emitting structure include sequentially forming a first n-type electrode layer, a first n-type layer, a first active layer, a first p-type layer, and a first p-type electrode layer; etching starting from the first n-type electrode layer; etching through the first n-type electrode layer and the first n-type layer; dividing the first n-type electrode layer; and stopping before reaching the first active layer.

[0009] In one embodiment, the bonding process further includes a step of removing the temporary substrate.

[0010] In one embodiment, the bonding process includes a step of filling an insulating layer before bonding, and planarizing the filled insulating layer to form a flat surface for bonding.

[0011] In one embodiment, forming the first light-emitting component layer further includes dividing the first p-type electrode layer, with a region corresponding to one first p-type electrode layer and one first n-type electrode layer serving as a first light-emitting region.

[0012] In one embodiment, the specific steps for forming the second light-emitting structure include sequentially forming a second n-type electrode layer, a second n-type layer, a second active layer, a second p-type layer, and a second p-type electrode layer, and etching the stacked structure to form an independent portion as the second light-emitting region. The specific steps for forming the third light-emitting structure include sequentially forming a third n-type electrode layer, a third n-type layer, a third active layer, a third p-type layer, and a third p-type electrode layer, and etching the stacked structure to form an independent portion as the third light-emitting region.

[0013] In one embodiment, the step of forming an optical isolation layer at the bonding interface is further included.

[0014] In one embodiment, the steps of forming the first through electrode group, the second through electrode group and the third through electrode group include forming through holes, forming an insulating layer on the inner wall of the through holes and then filling them with conductive material.

[0015] Compared with the prior art, this application has the following beneficial effects: This application adopts a vertical stacking structure in which a driving substrate and three light-emitting component layers are bonded in sequence, and a through-electrode group is provided to achieve interlayer electrical connection. When forming the first light-emitting structure, the etching stops before reaching the first active layer, so that the first active layer is a continuous layer, avoiding plasma etching damage to the active layer region, fundamentally reducing the formation of sidewall non-radiative recombination centers, helping to reduce the reverse leakage current of the device, and improving the internal quantum efficiency. For red Micro-LEDs that are particularly sensitive to sidewall damage, the effect is more prominent.

[0016] Adopt a vertical stacking structure in which a driving substrate, first, second, and third light-emitting component layers are bonded in sequence, and interlayer interconnection is achieved through a through-electrode group, so that RGB sub-pixels can be independently controlled. This structure avoids the problems of blue light leakage and material stability existing in the quantum dot color conversion scheme. At the same time, compared with arranging RGB pixels in a plane, this vertical integration method helps to achieve a higher pixel density and meet the high-resolution requirements of near-eye display devices such as AR / VR.

[0017] In addition, this application defines a new minimum repeating pixel unit, which consists of two adjacent "field" - shaped grids, forming a 2×4 or 4×2 array. In this unit, there are four red (R) sub-pixel units, two green (G) sub-pixel units, and two blue (B) sub-pixel units. Combine the four red sub-pixel units into a single, physically continuous and electrically unified 2x2 block structure, and directly compensate for the relatively low internal quantum efficiency and external quantum efficiency of the red light material itself by doubling the effective light-emitting area of the red sub-pixels. Brief Description of the Drawings

[0018] Figure 1 is a schematic structural diagram of a Micro-LED full-color display device in an embodiment of this application; Figure 2 is a schematic diagram of the pixel layout of a Micro-LED full-color display device in an embodiment of this application; Figures 3-5 is a schematic diagram of the step-by-step structure in the manufacturing method of a Micro-LED full-color display device in an embodiment of this application.

[0019] Explanation of reference numerals in the attached drawings: 100, driving substrate; 200, first light-emitting component layer; 210, first bonding interface; 220, first light-emitting structure; 230, first connecting electrode group; 300, second light-emitting component layer; 310, second bonding interface; 320, second light-emitting structure; 330, second connecting electrode group; 400, third light-emitting component layer; 410, third bonding interface; 420, third light-emitting structure; 430, third connecting electrode group; 510, first through electrode group; 520, second through electrode group; 530, third through electrode group; 610, first light-emitting area; 620, second light-emitting area; 630, third light-emitting area. Detailed Implementation

[0020] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0021] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Next, addressing the issues mentioned in the background section regarding the low red light luminous efficiency, non-radiative recombination due to sidewall damage, and complex full-color manufacturing processes in Micro-LED full-color displays, exemplary implementation schemes will be provided. These schemes will specifically illustrate Micro-LED full-color display devices employing a vertically stacked architecture and their manufacturing methods. Each light-emitting component layer is electrically interconnected through a through-electrode group, and further optimizations are made in the structural design and process steps to synergistically improve device performance. Please refer to [link to relevant documentation]. Figure 1In a preferred embodiment of this application, the Micro-LED full-color display device includes a driving substrate 100, a first light-emitting component layer 200, a second light-emitting component layer 300, and a third light-emitting component layer 400. The driving substrate 100, the first light-emitting component layer 200, the second light-emitting component layer 300, and the third light-emitting component layer 400 are bonded together sequentially from bottom to top to form a first bonding interface 210, a second bonding interface 310, and a third bonding interface 410, respectively. The first light-emitting component layer 200 includes a first through-electrode group 510, a second through-electrode group 520, and a first light-emitting structure 220. The second light-emitting component layer 300 includes a third through-electrode group 530 and a plurality of second light-emitting structures 320. The third light-emitting component layer 400 includes a plurality of third light-emitting structures 420. A through electrode group 510 and a second through electrode group 520 extend from the second bonding interface 310 to the first bonding interface 210, respectively, and are electrically connected to the corresponding pixel electrodes on the driving substrate 100. Here, the connecting electrode group includes at least a positive electrode line and a negative electrode line. "Corresponding" means that the positive electrode is connected to the positive electrode in the pixel electrode, and the negative electrode is connected to the negative electrode in the pixel. The third through electrode group 530 extends from the third bonding interface 410 to the second bonding interface 310. The third through electrode group 530 is electrically connected to the second through electrode group 520. Here, each through electrode group includes at least a positive electrode line and a negative electrode line. "Corresponding" also means that the positive electrode is connected to the positive electrode in the pixel electrode, and the negative electrode is connected to the negative electrode in the pixel.

[0024] The first light-emitting structure 220 includes a first connecting electrode group 230 connecting to the pixel electrode on the driving substrate 100; the second light-emitting structure 320 includes a second connecting electrode group 330 connecting to the first through electrode group 510; and the third light-emitting structure 420 includes a third connecting electrode group 430 connecting to the third through electrode group 530. The first light-emitting structure 220 includes multiple first p-type electrode layers, a first p-type layer, a first active layer, a first n-type layer, and multiple first n-type electrode layers. A region corresponding to one first p-type electrode layer and one first n-type electrode layer is designated as a first light-emitting region 610. The first active layer is a continuous layer. Here, a continuous layer refers to an active layer that, after being formed as a whole, is not further divided, and all regions are connected together, but there are vias penetrating the active layer. The presence of vias does not affect the definition of a continuous layer.

[0025] The driving substrate 100, the first light-emitting component layer 200, the second light-emitting component layer 300, and the third light-emitting component layer 400 are bonded sequentially from bottom to top, forming first, second, and third bonding interfaces 410. This structure constitutes a vertically stacked full-color pixel unit. This architecture differs from the planar arrangement of traditional RGB pixels, increasing pixel density through vertical integration and contributing to higher resolution display effects. Interlayer bonding technology enables reliable interconnection between different light-emitting component layers and the driving substrate 100. The driving substrate 100 not only provides pixel electrodes but also carries driving circuits such as thin-film transistors (TFTs) to ensure that each light-emitting unit can be independently addressed and controlled. This vertically stacked design allows RGB sub-pixels to be physically separated, providing a structural basis for the staggered projection positions and differentiated area configurations described later.

[0026] The first through-electrode group 510 and the second through-electrode group 520 penetrate the first light-emitting component layer 200 and are electrically connected to the corresponding pixel electrodes on the driving substrate 100; the third through-electrode group 530 penetrates the second light-emitting component layer 300 and is correspondingly electrically connected to the second through-electrode group 520. These through-electrode groups form an interlayer interconnect current path in the vertical direction, allowing the driving signal to be sequentially transmitted from the driving substrate 100 to the upper light-emitting component, thereby realizing the vertical lead-out of the electrodes and the common electrode design. Specifically, the fabrication of the conductive via may include forming a through-hole, forming an insulating layer on the inner wall of the via to prevent interlayer short circuits, and then filling it with a conductive material (such as metal) to form a conductive channel. This interconnection mechanism avoids the wiring congestion problem that may be caused by arranging a large number of wires in a single plane, and helps to simplify wiring design.

[0027] In the first light-emitting structure 220, its first active layer is constructed as a continuous layer. During the manufacturing process, the etching step is controlled to stop before reaching the first active layer, thereby maintaining the structural integrity of the first active layer. This method reduces the possibility of damage introduced into the sidewalls of the first active layer by the etching process. Sidewall damage is one of the important factors in the efficiency decay of Micro-LEDs, especially for devices with increased perimeter-to-area ratios after miniaturization. Sidewall defects act as non-radiative recombination centers, reducing internal quantum efficiency. Maintaining the continuity of the first active layer means reducing the number of sidewall non-radiative recombination centers generated by etching within that layer, which helps maintain a high carrier radiative recombination efficiency. In addition, the first light-emitting structure 220, by separately setting multiple first p-type electrode layers and first n-type electrode layers, and cooperating with the continuous p-type layer, active layer, and n-type layer, allows the regions corresponding to one first p-type electrode layer and one first n-type electrode layer to form an independently controllable first light-emitting region 610. This design can achieve electrical isolation and driving of multiple independent light-emitting regions while ensuring the continuity of the active layer.

[0028] In the specific structure, the first light-emitting structure 220 includes a first p-type connection electrode, a first p-type electrode layer, a first p-type layer, a first active layer, a first n-type layer, a first n-type electrode layer, and a first n-type connection electrode. The regions corresponding to the first p-type electrode layer and the first n-type electrode layer are the first light-emitting regions 610. The first p-type connection electrode is electrically connected to the first p-type electrode layer, and the first n-type connection electrode is electrically connected to the first n-type electrode layer. The first p-type connection electrode and the first n-type connection electrode extend to the bonding interface with the driving substrate 100 and are electrically connected to the pixel electrode on the driving substrate 100.

[0029] The second light-emitting structure 320 includes a second p-type connecting electrode, a second p-type electrode layer, a second p-type layer, a second active layer, a second n-type layer, a second n-type electrode layer, and a second n-type connecting electrode. The regions corresponding to the second p-type electrode layer and the second n-type electrode layer are the second light-emitting regions 620. The second p-type connecting electrode is electrically connected to the second p-type electrode layer, and the second n-type connecting electrode is electrically connected to the second n-type electrode layer. The second p-type connecting electrode and the second n-type connecting electrode extend to the bonding interface with the first light-emitting component layer 200 and are electrically connected to the electrodes in the first through electrode group 510. The third through electrode group 530 is correspondingly electrically connected to the second through electrode group 520.

[0030] The third light-emitting structure 420 includes a third p-type connecting electrode, a third p-type electrode layer, a third p-type layer, a third active layer, a third n-type layer, a third n-type electrode layer, and a third n-type connecting electrode. The regions corresponding to the third p-type electrode layer and the third n-type electrode layer are the third light-emitting regions 630. The third p-type connecting electrode is electrically connected to the third p-type electrode layer, and the third n-type connecting electrode is electrically connected to the third n-type electrode layer. The third p-type connecting electrode and the third n-type connecting electrode extend to the bonding interface with the second light-emitting component layer 300 and are electrically connected to the electrodes in the third through electrode group 530.

[0031] In the Micro-LED full-color display device, the first light-emitting area 610, the second light-emitting area 620, and the third light-emitting area 630 are respectively configured as red light-emitting areas, green light-emitting areas, and blue light-emitting areas, and the three are staggered in their horizontal projection onto the display device. Specifically, this staggered arrangement ensures that sub-pixels of different light-emitting colors do not overlap in either the horizontal or vertical directions. This arrangement allows light-emitting chips of different colors to effectively emit light, helping to improve the problem of non-white light color deviation bright lines that may appear at the edges of the LED display module. By spatially dispersing sub-pixels of different colors through staggered arrangement, mutual interference between light emitted from adjacent sub-pixels of the same or different colors due to viewing angle or spacing can be reduced, thereby mitigating optical crosstalk.

[0032] Furthermore, the staggered projection positions provide a layout basis for optimizing the area allocation of each light-emitting area. For example, based on the different external quantum efficiency characteristics of red, green, and blue light-emitting materials under miniaturization conditions, a larger light-emitting area can be allocated to the relatively less efficient red light-emitting area to compensate for its efficiency loss, thereby balancing the luminous efficiency of the three RGB colors and improving the white field uniformity of full-color displays. This combination of area differentiation and staggered arrangement can synergistically improve the overall color performance of display devices without increasing process complexity.

[0033] In the Micro-LED full-color display device, the area ratio of the first light-emitting area 610 (red light-emitting area), the second light-emitting area 620 (green light-emitting area), and the third light-emitting area 630 (blue light-emitting area) is configured as 2:1:1. This area ratio primarily addresses the technical problem of the sharp decline in external quantum efficiency (EQE) of red Micro-LEDs at the micrometer scale. Research shows that compared to blue and green LEDs based on indium gallium nitride (IGaN) materials, the efficiency of red LEDs is more sensitive to size reduction. Allocating a larger light-emitting area to the red light-emitting area, where efficiency decline is most pronounced, can directly compensate for the efficiency loss caused by size effects, thereby improving the absolute light output intensity of red pixels and contributing to improved white field uniformity and color reproduction capabilities in full-color displays.

[0034] In practical implementation, the area ratio can be coordinated with electrode design. For example, by adjusting the area ratio of the P electrode in each light-emitting region, the current spread and light extraction efficiency of the device can be affected, effectively improving the photoelectric performance of Micro-LEDs. Because the red light-emitting region has a larger area, the electrode design can be optimized to match its expanded light-emitting area. Furthermore, the 2:1:1 area ratio configuration complements the staggered projection positions of the first light-emitting region 610, the second light-emitting region 620, and the third light-emitting region 630 on the horizontal plane. This staggered projection provides layout space for the differentiated area allocation of different light-emitting regions, avoiding intra-pixel layout conflicts caused by the increased red light area.

[0035] Furthermore, in the manufacturing process of the Micro-LED full-color display device, for the second light-emitting component layer 300 (typically green light) and the third light-emitting component layer 400 (typically blue light), a specific etching strategy is implemented to ensure that the area of ​​the lower conductive layer (e.g., n-type electrode layer) removed by etching is larger than the area of ​​their respective active layers. This allows a certain physical distance to be maintained between the blue and green light-emitting areas and the etched mesa boundary. In the manufacturing of Micro-LEDs, the pixel mesa is typically defined using inductively coupled plasma (ICP) dry etching technology. This high-energy physical process inevitably generates defects such as lattice damage and dangling bonds on the etched sidewalls. These sidewall defects form deep-level trap states in the semiconductor bandgap, becoming non-radiative recombination centers. When injected electrons and holes diffuse to the vicinity of the sidewalls, they are easily captured by these trap states and recombine by releasing heat rather than photons, resulting in a decrease in the device's internal quantum efficiency. By making the etching range of the lower conductive layer larger than the active region, the key light-emitting region of the active layer is horizontally moved away from the etching-induced damage area, effectively reducing the diffusion and recombination of charge carriers to sidewall defects. Untreated sidewall defects increase the reverse leakage current of the device and restrict its high-frequency performance, such as modulation bandwidth. By designing the structure to keep the light-emitting region away from the etching boundary, the influence of sidewall defects on the carrier behavior of the light-emitting region can be reduced. This differs from the technical approach of repairing damage by chemical treatment of the sidewalls through TMAH or other alternative processes such as ion implantation to avoid plasma damage. No additional treatment is required after etching, which simplifies the process. This design does not require subsequent sidewall passivation processes (such as depositing an Al2O3 / SiO2 bilayer passivation film). Through the physical spacing built into the device, the impact of etching-induced sidewall defects on the light-emitting core region is reduced, thereby helping to maintain high internal quantum efficiency and improve the electrical and optical characteristics of the device.

[0036] This application further provides a method for manufacturing a Micro-LED full-color display device, comprising: A first light-emitting component layer 200 is formed on a temporary substrate. The first light-emitting component layer 200 includes a first through electrode group 510, a second through electrode group 520 and a first light-emitting structure 220. The first through electrode group 510 and the second through electrode group 520 extend through the first light-emitting component layer 200. The first light-emitting structure 220 includes a first connecting electrode group 230. The first light-emitting component layer 200 is bonded to the driving substrate 100, so that the first through electrode group 510, the second through electrode group 520 and the first connecting electrode group 230 are electrically connected to the corresponding pixel electrode on the driving substrate 100. "Corresponding" also means that the positive electrode is connected to the positive electrode in the pixel electrode and the negative electrode is connected to the negative electrode in the pixel. A second light-emitting component layer 300 is formed on a temporary substrate. The second light-emitting component layer 300 includes a third through electrode group 530 and a plurality of second light-emitting structures 320. The third through electrode group 530 extends through the second light-emitting component layer 300. The second light-emitting structure 320 includes a second connecting electrode group 330. The second light-emitting component layer 300 is bonded to the first light-emitting component layer 200, so that the third through electrode group 530 is correspondingly electrically connected to the second through electrode group 520, and the second connecting electrode group 330 is correspondingly electrically connected to the first through electrode group 510. A third light-emitting component layer 400 is formed on a temporary substrate. The third light-emitting component layer 400 includes a plurality of third light-emitting structures 420, and the third light-emitting structure 420 includes a third connecting electrode group 430. The third light-emitting component layer 400 is bonded to the second light-emitting component layer 300, so that the third connecting electrode group 430 is correspondingly electrically connected to the third through electrode group 530; The specific steps for forming the first light-emitting structure 220 include sequentially forming a first n-type electrode layer, a first n-type layer, a first active layer, a first p-type layer, and a first p-type electrode layer; starting from the first n-type electrode layer, etching is performed, passing through the first n-type electrode layer and the first n-type layer, dividing the first n-type electrode layer, and stopping before reaching the first active layer.

[0037] The manufacturing method first forms a first light-emitting component layer 200 on a temporary substrate. This layer includes a first through-electrode group 510 and a second through-electrode group 520 extending through the substrate. It is then bonded to a driving substrate 100, so that the through-electrode groups and the first connecting electrode group 230 are electrically connected to corresponding pixel electrodes on the driving substrate 100. Here, "corresponding electrical connection" means accurate interconnection between positive electrodes and between negative electrodes. When forming the first light-emitting structure 220, the method includes sequentially forming a first n-type electrode layer, a first n-type layer, a first active layer, a first p-type layer, and a first p-type electrode layer. Etching begins from the first n-type electrode layer, proceeds through the n-type electrode layers and the n-type layers, and stops before reaching the first active layer. Controlling the etching depth ensures that the first active layer remains a continuous layer, preventing plasma etching damage to the active region. Dry etching (such as ICP) is a common method for forming Micro-LED mesa structures, but this process introduces etching damage, forming non-radiative recombination sidewall defects. The method, by controlling the etching depth, physically isolates the active layer from the sidewall damage region formed by etching, which helps to reduce the adverse effects of sidewall defects as non-radiative recombination centers on the carrier recombination process.

[0038] After bonding the first light-emitting component layer 200, the method continues to sequentially form the second and third light-emitting component layers 400 on a temporary substrate, and achieves interlayer electrical interconnection through their respective through-electrode groups (such as the third through-electrode group 530) and the corresponding through-electrode groups (such as the second through-electrode group 520) of the lower layer. This layer-by-layer construction and bonding scheme allows each layer structure to be independently processed and optimized before bonding. The formation of the through-electrode groups in the method may include preparing through holes, forming an insulating layer on the inner wall of the holes, and then filling them with conductive material, which is similar to the process of etching to form mesa and depositing electrode interconnect structures in some schemes.

[0039] In the manufacturing method of the Micro-LED full-color display device, the step of forming the connecting electrode group or the through electrode group can be arranged after the first light-emitting component layer 200 is bonded to the driving substrate 100, and coordinated with the subsequent step of filling the insulating layer. That is, the connecting electrode group or the through electrode group is formed after the insulating layer is filled. Specifically, the manufacturing method first bonds the first light-emitting component layer 200 to the driving substrate 100. This step establishes preliminary mechanical and electrical connection pathways. Subsequently, the insulating layer is filled, which can cover the bonding interface and the formed structural steps, and a planarization process is performed to form a flat surface. This flat surface provides a better process substrate for the subsequent formation of the connecting electrode group or the through electrode group. The insulating layer material can be selected as oxide or nitride, and it is formed by chemical vapor deposition or other methods.

[0040] After the insulating layer is filled and planarized, contact holes or through holes are formed through processes such as photolithography and etching. Then, conductive material is deposited to form a connecting electrode group or a through electrode group. The formation of the through electrode group may include preparing through holes, forming an insulating layer on the inner wall of the hole, and then filling it with conductive material. This allows the insulating layer to establish effective interlayer electrical isolation before the electrodes, reducing the risk of short circuits between the electrodes and adjacent semiconductor or metal layers.

[0041] The temporary substrate removal process following the bonding step can be performed using methods such as laser lift-off (LLO), mechanical polishing, or chemical etching. This step aims to release the light-emitting component layer pre-formed on the temporary substrate and transfer it to the target driving substrate 100 or a higher functional structure. Different removal methods are selected based on the temporary substrate material, device structure characteristics, and subsequent process requirements. Laser lift-off (LLO) technology uses a laser beam of a specific wavelength to irradiate the interface between the temporary substrate and the functional layer, causing the interface material to ablate or decompose, thereby achieving substrate separation. Mechanical polishing and chemical etching can also be used as alternatives or auxiliary methods for substrate removal or thinning.

[0042] In the manufacturing process of the Micro-LED full-color display device, the insulating layer filling and subsequent planarization treatment performed before the bonding step are crucial steps to ensure the yield and performance of the multilayer stacked structure. The insulating layer filling and planarization treatment directly affect the quality of interlayer bonding. In the manufacturing of multilayer stacked Micro-LED devices, before one light-emitting component layer is bonded to the driving substrate 100 or another light-emitting component layer, its surface may have step heights or undulations due to previous process steps (such as electrode formation or semiconductor layer etching). Filling with insulating material (such as oxides, nitrides, or combinations thereof) and performing planarization can eliminate surface topological undulations, forming a smooth and uniform bonding interface. Furthermore, this step, while achieving mechanical structural flatness, also serves an electrical isolation function. The filled insulating layer can electrically isolate the through-electrode group or connecting electrode from the surrounding semiconductor material or other conductive structures in the same layer, preventing short circuits within or between layers. From the perspective of subsequent process integration, a flat surface also provides a better substrate for micro-nano fabrication steps such as photolithography, etching, and re-deposition. This helps to improve the processing accuracy and shape integrity of the patterns formed on the plane (such as the through electrodes or connecting electrodes of the subsequent light-emitting component layer), thereby ensuring the uniformity of current spread and the consistency of device performance.

[0043] In the manufacturing process of the Micro-LED full-color display device, the first p-type electrode layer in the first light-emitting component layer 200 is divided, so that the area corresponding to one divided first p-type electrode layer and one first n-type electrode layer jointly defines an independent first light-emitting area 610. Specifically, the first p-type electrode layer is divided into multiple electrically isolated electrode units by micro-nano processing techniques such as photolithography and etching, which may otherwise be continuous or have a large area. This division process can be coordinated with the patterning of the first n-type electrode layer, so that each divided first p-type electrode unit and a corresponding first n-type electrode unit jointly define an area with independent light-emitting function, namely the first light-emitting area 610, in the vertical projection. After division, each first light-emitting area 610 can be connected to the corresponding pixel driving circuit on the driving backplane, thereby realizing independent addressing and control of each light-emitting unit.

[0044] By precisely controlling the segmentation size and shape of the first p-type electrode layer, the expansion and distribution of current within the light-emitting region can be regulated. For example, a well-designed electrode pattern helps to make the current flow more uniformly through the first p-type layer, the first active layer, and the first n-type layer in the first light-emitting structure 220, which has a positive effect on improving the internal quantum efficiency and light emission uniformity of the device.

[0045] Specifically, the steps for forming the second light-emitting structure 320 include sequentially forming a second n-type electrode layer, a second n-type layer, a second active layer, a second p-type layer, and a second p-type electrode layer, etching the stacked structure to form an independent portion as the second light-emitting region 620, and the steps for forming the third light-emitting structure 420 include sequentially forming a third n-type electrode layer, a third n-type layer, a third active layer, a third p-type layer, and a third p-type electrode layer, etching the stacked structure to form an independent portion as the third light-emitting region 630.

[0046] In a preferred embodiment, the method further includes a step of forming an optical isolation layer at the bonding interface. In the manufacturing method of the Micro-LED full-color display device, the step of forming an optical isolation layer at the bonding interface specifically includes preparing a whole layer of optical isolation material for the first light-emitting component at its bonding interface, and opening an opening in the region corresponding to the first light-emitting area 610 to allow light to be emitted; simultaneously, preparing optical isolation walls that vertically surround the second light-emitting area 620 and the third light-emitting area 630 for the second light-emitting component. By constructing a specific lateral optical barrier structure, the light propagation path generated by each layer of light-emitting units in the stacked structure is physically limited to suppress intra-layer and inter-layer light crosstalk and optimize light extraction efficiency.

[0047] Specifically, a whole layer of light-isolating material is prepared at the bonding interface of the first light-emitting component, and a light-emitting opening is formed, so that the light emitted by the first light-emitting region 610 (usually a red light-emitting region) is confined within the opening area. This structure can absorb or block the lateral propagation of light to adjacent pixel regions, and pixel light isolation is achieved by filling the LED chip spacers with light-shielding filler. For the second light-emitting component, a light-isolating wall is constructed vertically surrounding the second light-emitting region 620 (green light) and the third light-emitting region 630 (blue light), which can form an optical barrier on the sidewall of the light-emitting structure. This sidewall isolation structure helps to absorb or reflect light incident on neighboring pixels, thereby reducing optical crosstalk caused by light diffusion between adjacent heterochromatic sub-pixels.

[0048] The optical isolation layer and optical isolation wall are arranged in conjunction with the staggered projection positions of the first light-emitting area 610, the second light-emitting area 620, and the third light-emitting area 630 on the horizontal plane. This staggered projection sets different light-emitting positions for each light-emitting area, while the optical isolation structure further ensures that each color of light is confined to its preset fixed light-emitting area, jointly contributing to improving the display's contrast and color purity. In terms of material selection and process implementation, the optical isolation material can be a substance with high light absorption characteristics, such as black adhesive, or a material with high reflectivity, such as a metal reflective layer.

[0049] In the manufacturing process of the Micro-LED full-color display device, the steps of forming the first, second, and third through-electrode groups 530 specifically include: firstly, forming through holes on the corresponding light-emitting component layers; then, forming an insulating layer on the inner wall of the through holes; and finally, filling the holes with conductive material. The fabrication of the through-electrode groups begins with forming through holes at predetermined positions on each light-emitting component layer (e.g., the first, second, and third light-emitting component layers 400). These through holes are typically formed using microfabrication techniques such as dry etching (e.g., inductively coupled plasma etching) or wet etching, extending through the functional structure of the layer. Subsequently, an insulating material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), is deposited or grown on the inner wall of the through holes to form a continuous insulating layer. The main function of this insulating layer is to electrically isolate the subsequently filled conductive material from the semiconductor bulk material (e.g., n-type layer, p-type layer) or other conductive pathways of the light-emitting component layers, preventing current leakage or intra-layer short circuits, thereby ensuring that current can be transmitted through the designed vertical path.

[0050] After the insulating layer is applied, conductive material, such as copper (Cu), aluminum (Al), or tungsten (W) or their alloys, is filled into the through-holes to form conductive channels. This filling process can be combined with thin film deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating. The conductive channels, together with the first connecting electrode group 230, the second connecting electrode group 330, and the third connecting electrode group 430, constitute a vertical electrical interconnection path for the drive signal to be transmitted from the drive substrate 100 through the first light-emitting component layer 200, the second light-emitting component layer 300, and the third light-emitting component layer 400, allowing independent addressing and control of different light-emitting component layers (such as red, green, and blue light-emitting layers).

[0051] Furthermore, the structural design and fabrication process of the through-electrode assembly are adapted to the manufacturing process of forming the light-emitting component layer on a temporary substrate and subsequently bonding it to the driving substrate 100 or the next light-emitting component layer. Performing insulating layer filling and planarization treatment before bonding provides a flatter substrate for the fabrication of the through-electrode, which helps improve the morphological quality of the through-hole etching, the uniformity of the insulating layer coverage, and the density of the conductive material filling, thereby improving the electrical connection reliability and yield of the through-electrode.

[0052] As described above, this application provides a Micro-LED full-color display device and its manufacturing method. The display device adopts a vertically stacked architecture, including a driving substrate and first, second, and third light-emitting component layers bonded sequentially from bottom to top, with bonding interfaces formed between each layer. The first light-emitting component layer is provided with a first through-electrode group and a second through-electrode group, and the second light-emitting component layer is provided with a third through-electrode group. These through-electrode groups extend through the corresponding layers, forming channels for interlayer electrical interconnection, enabling driving signals to be transmitted from the driving substrate to each light-emitting component layer.

[0053] The first light-emitting structure has a continuous first active layer, which is achieved by controlling the etching depth to avoid plasma etching damage to the active region. The first, second, and third light-emitting regions are configured as red, green, and blue light-emitting regions, respectively, and their projected positions on the horizontal plane are staggered, with a preferred area ratio of 2:1:1. This design aims to compensate for the efficiency loss of red Micro-LEDs during the miniaturization process. For green and blue light-emitting components, by making the etching area of ​​the lower conductive layer larger than the area of ​​the active layer, the light-emitting region is kept at a distance from the etching boundary to reduce the impact of sidewall defects on luminous efficiency.

[0054] The manufacturing method includes sequentially forming each light-emitting component layer on a temporary substrate and achieving vertical integration through a bonding process. The method also includes a step of forming an optical isolation layer or optical isolation wall at the bonding interface to suppress interlayer optical crosstalk. The formation of the through-hole electrode assembly includes fabricating through-holes, forming an insulating layer on the inner wall of the holes, and then filling them with conductive material. Furthermore, the manufacturing process involves insulating layer filling and planarization, temporary substrate removal, and the segmentation of the first p-type electrode layer, which together ensure the integrity of the device structure and the reliability of the electrical connections.

[0055] The above is only one specific implementation of this application, and any other improvements made based on the concept of this application shall be considered within the scope of protection of this application.

Claims

1. A Micro-LED full-color display device, characterized in that, It includes a driving substrate, a first light-emitting component layer, a second light-emitting component layer, and a third light-emitting component layer. The driving substrate, the first light-emitting component layer, the second light-emitting component layer, and the third light-emitting component layer are bonded together from bottom to top to form a first bonding interface, a second bonding interface, and a third bonding interface, respectively. The first light-emitting component layer includes a first through electrode group, a second through electrode group and a first light-emitting structure; the second light-emitting component layer includes a third through electrode group and a plurality of second light-emitting structures; and the third light-emitting component layer includes a plurality of third light-emitting structures. The first through electrode group and the second through electrode group extend from the second bonding interface to the first bonding interface and are electrically connected to the corresponding pixel electrode on the driving substrate. The third through electrode group extends from the third bonding interface to the second bonding interface and is electrically connected to the second through electrode group. The first light-emitting structure includes a first connecting electrode group connected to a pixel electrode on a driving substrate; the second light-emitting structure includes a second connecting electrode group connected to a first through electrode group; and the third light-emitting structure includes a third connecting electrode group connected to a third through electrode group. The first light-emitting structure includes multiple first p-type electrode layers, a first p-type layer, a first active layer, a first n-type layer, and multiple first n-type electrode layers. The region corresponding to one first p-type electrode layer and one first n-type electrode layer is used as the first light-emitting region, and the first active layer is a continuous layer.

2. The Micro-LED full-color display device according to claim 1, characterized in that, The second light-emitting component includes a second light-emitting area, and the third light-emitting component includes a third light-emitting area. The first light-emitting area is a red light-emitting area, the second light-emitting area is a green light-emitting area, and the third light-emitting area is a blue light-emitting area. The projection positions of the first light-emitting area, the second light-emitting area, and the third light-emitting area on the horizontal plane are staggered.

3. The Micro-LED full-color display device according to claim 2, characterized in that, The area ratio of the first light-emitting area, the second light-emitting area, and the third light-emitting area is 2:1:

1.

4. A method for manufacturing a Micro-LED full-color display device, characterized in that, include: A first light-emitting component layer is formed on a temporary substrate. The first light-emitting component layer includes a first through electrode group, a second through electrode group, and a first light-emitting structure. The first through electrode group and the second through electrode group extend through the first light-emitting component layer. The first light-emitting structure includes a first connecting electrode group. The first light-emitting component layer is bonded to the driving substrate, so that the first through electrode group, the second through electrode group and the first connection electrode group are electrically connected to the corresponding pixel electrode on the driving substrate. A second light-emitting component layer is formed on a temporary substrate. The second light-emitting component layer includes a third through electrode group and a plurality of second light-emitting structures. The third through electrode group extends through the second light-emitting component layer. The second light-emitting structure includes a second connecting electrode group. The second light-emitting component layer is bonded to the first light-emitting component layer, so that the third through electrode group is electrically connected to the second through electrode group, and the second connecting electrode group is electrically connected to the first through electrode group. A third light-emitting component layer is formed on a temporary substrate. The third light-emitting component layer includes a plurality of third light-emitting structures, and the third light-emitting structure includes a third connecting electrode group. The third light-emitting component layer is bonded to the second light-emitting component layer, so that the third connecting electrode group is correspondingly electrically connected to the third through electrode group; The specific steps for forming the first light-emitting structure include sequentially forming a first n-type electrode layer, a first n-type layer, a first active layer, a first p-type layer, and a first p-type electrode layer; etching starting from the first n-type electrode layer; etching through the first n-type electrode layer and the first n-type layer; dividing the first n-type electrode layer; and stopping before reaching the first active layer.

5. The method for manufacturing a Micro-LED full-color display device according to claim 4, characterized in that, The bonding process also includes a step of removing the temporary substrate.

6. The method for manufacturing a Micro-LED full-color display device according to claim 5, characterized in that, The bonding process includes a step of filling an insulating layer, and the filled insulating layer is planarized to form a flat surface for bonding.

7. The method for manufacturing a Micro-LED full-color display device according to claim 4, characterized in that, Forming the first light-emitting component layer also includes dividing the first p-type electrode layer, with a region corresponding to one first p-type electrode layer and one first n-type electrode layer serving as the first light-emitting region.

8. The method for manufacturing a Micro-LED full-color display device according to claim 4, characterized in that, The specific steps for forming the second light-emitting structure include sequentially forming a second n-type electrode layer, a second n-type layer, a second active layer, a second p-type layer, and a second p-type electrode layer, etching the stacked structure to form an independent portion as the second light-emitting region. The specific steps for forming the third light-emitting structure include sequentially forming a third n-type electrode layer, a third n-type layer, a third active layer, a third p-type layer, and a third p-type electrode layer, etching the stacked structure to form an independent portion as the third light-emitting region.

9. The method for manufacturing a Micro-LED full-color display device according to claim 4, characterized in that, It also includes the step of forming an optical isolation layer at the bonding interface.

10. The method for manufacturing a Micro-LED full-color display device according to claim 9, characterized in that, The steps of forming the first through electrode group, the second through electrode group and the third through electrode group include forming through holes, forming an insulating layer on the inner wall of the through holes and then filling them with conductive material.

Images