Data decoding circuit and method

Abstract

The present application discloses a data decoding circuit and a data decoding method. The data decoding circuit includes a data reorganization circuit that receives encoded data encoded by tail-biting convolutional coding technology to sequentially identify a first unknown bit segment, a known bit segment, and a second unknown bit segment of the encoded data, and further sequentially connect the second unknown bit segment and the first unknown bit segment as data to be decoded. The decoding circuit decodes the data to be decoded according to the Viterbi algorithm and at least one known bit information to generate a decoding result, wherein the decoding result includes a second decoded bit segment and a first decoded bit segment that sequentially correspond to the second unknown bit segment and the first unknown bit segment. The data restoration circuit sequentially connects the first decoded bit segment, the known decoded bit segment corresponding to the known bit segment, and the second decoded bit segment to generate decoded data.

Description

Technical Field

[0001] The present invention relates to data decoding technology, and more particularly to a data decoding circuit and method. Background Art

[0002] In low-power wide area networks, users have an increasing demand for low power consumption. Especially in the application of the Internet of Things, a large number of devices need to be connected to the network. Some of these devices require low data transmission with long waiting times. When the packet error rate of data reception is too high, these devices must wait for the signal transmitter to repeat the signal to improve the accuracy of demodulation.

[0003] Therefore, how to improve the performance of the receiving end in terms of packet error rate to reduce the number of retransmissions and thereby save power consumption and extend battery life is a very important issue. Summary of the invention

[0004] In view of the problems in the prior art, one object of the present invention is to provide a data decoding circuit and method to improve the prior art.

[0005] The present invention includes a data decoding circuit, including: a data reorganization circuit, a decoding circuit and a data restoration circuit. The data reorganization circuit is configured to receive encoded data encoded by tail-biting convolutional coding technology to sequentially identify a first unknown bit segment, a known bit segment and a second unknown bit segment included in the encoded data, and further sequentially connect the second unknown bit segment and the first unknown bit segment as data to be decoded. The decoding circuit is configured to decode the data to be decoded according to the Viterbi algorithm and at least one known bit information to generate a decoding result, wherein the decoding result includes a second decoded bit segment and a first decoded bit segment that sequentially correspond to the second unknown bit segment and the first unknown bit segment. The data restoration circuit is configured to sequentially connect the first decoded bit segment, the known decoded bit segment corresponding to the known bit segment and the second decoded bit segment to generate decoded data.

[0006] The present invention further includes a data decoding method, which is applied in a data decoding circuit, comprising: enabling a data reorganization circuit to receive encoded data encoded by a tail-biting convolutional code technique to sequentially identify a first unknown bit segment, a known bit segment, and a second unknown bit segment included in the encoded data, and further sequentially connecting the second unknown bit segment and the first unknown bit segment as data to be decoded; enabling a decoding circuit to decode the data to be decoded according to a Viterbi algorithm and at least one known bit information to generate a decoding result, wherein the decoding result includes a second decoded bit segment and a first decoded bit segment that sequentially correspond to the second unknown bit segment and the first unknown bit segment; and enabling a data restoration circuit to sequentially connect the first decoded bit segment, a known decoded bit segment corresponding to the known bit segment, and the second decoded bit segment to generate decoded data.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing a data receiving device according to an embodiment of the present invention;

[0009] Figure 2 A schematic diagram showing how original data is converted into encoded data through an encoding process in one embodiment of the present invention;

[0010] Figure 3 A schematic diagram showing an encoding circuit in one embodiment of the present invention;

[0011] Figure 4 In one embodiment of the present invention, Figure 1 A block diagram of a data decoding circuit;

[0012] Figure 5 A schematic diagram showing a process of generating decoded data by processing coded data through a data decoding circuit in one embodiment of the present invention;

[0013] Figure 6 A schematic diagram showing the performance of a data decoding circuit after decoding according to different decoding methods in one embodiment of the present invention;

[0014] Figure 7 is a flow chart of a data decoding method in one embodiment of the present invention; and

[0015] Figure 8 In one embodiment of the present invention, Figure 7 In the step of, a flowchart of a decoding process for decoding the data to be decoded is provided.

[0016]

Explanation of symbols

[0017] 100: Data receiving device

[0018] 110: Channel estimation circuit

[0019] 120:Signal detection circuit

[0020] 130: Descrambling circuit

[0021] 140: Solution rate matching circuit

[0022] 150: Data decoding circuit

[0023] 160: Cyclic redundancy check circuit

[0024] S210~S230: Steps

[0025] 300: encoding circuit

[0026] 310: Cache

[0027] 320: Adder

[0028] 400: Data reorganization circuit

[0029] 410: decoding circuit

[0030] 420: Data recovery circuit

[0031] 700: Data decoding method

[0032] S710~S730: Steps

[0033] 800: Decoding process

[0034] S810~S895: Steps

[0035] A: Raw data

[0036] B: Debug data

[0037] C: Data

[0038] DD: Decoded data

[0039] DS1: First decoded bit segment

[0040] DS2: Second decoded bit segment

[0041] DR: Decoding result

[0042] ED: Encoded Data

[0043] KD: known decoding bit segment

[0044] KI: Known bit information

[0045] KS: Known bits segment

[0046] RD: Receive Data

[0047] SE1: first bit segment to be encoded

[0048] SE2: The second bit segment to be encoded

[0049] SE3: The third bit segment to be encoded

[0050] UDD: Data to be decoded

[0051] US1: The first unknown bit segment

[0052] US2: The second unknown bit segment

[0053] Y: Data to be transmitted

[0054] Z: Data DETAILED DESCRIPTION

[0055] One object of the present invention is to provide a data decoding device and method, which utilizes the characteristics of tail-biting convolutional codes to reduce the search order and maintain the decoding performance. The present invention is applicable to general communication systems using tail-biting convolutional code encoders / decoders, such as the fourth generation mobile communication system (Long Term Evolution; LTE), the Internet of Things (IoT), etc.

[0056] Please refer to Figure 1 . Figure 1 The block diagram of a data receiving device 100 according to an embodiment of the present invention is shown. The data receiving device 100 comprises a channel estimation circuit 110 , a signal detection circuit 120 , a descrambling circuit 130 , a rate matching circuit 140 , a data decoding circuit 150 and a cyclic redundancy check circuit 160 .

[0057] In one embodiment, the channel estimation circuit 110 receives the received data RD transmitted by the data transmission device (not shown) through the transmission channel. The channel estimation circuit 110, the signal detection circuit 120, the descrambling circuit 130 and the rate matching circuit 140 sequentially perform corresponding pre-processing on the received data RD to generate the encoded data ED. Among them, those skilled in the art can perform the above-mentioned pre-processing in different ways, which will not be described in detail here.

[0058] The data decoding circuit 150 decodes the encoded data ED to generate decoded data DD, and the cyclic redundancy check circuit 160 checks the portion of the decoded data DD corresponding to the cyclic redundancy check (CRC) code, and completes data reception after the check is correct.

[0059] In one embodiment, the decoding method is related to the encoding characteristics of the coded data ED at one end of the data transmission device. In one embodiment, the coded data ED is generated by encoding the original data by the encoding circuit in the data transmission device through the tail-biting convolutional coding technology.

[0060] The following is a detailed description of the characteristics of the encoding technology of the tail-biting convolutional code.

[0061] Please also refer to Figure 2 as well as Figure 3 . Figure 2 A schematic diagram showing how original data A generates encoded data Z through an encoding process in one embodiment of the present invention. Figure 3A schematic diagram showing an encoding circuit 300 according to an embodiment of the present invention.

[0062] like Figure 2 As shown, the original data A is of length N A ×1 vector, that is, it is a vector with N A The single-digit data includes the first and second to-be-encoded bit segments SE1 and SE2, which are respectively unknown and known bit segments relative to the predictable decoding end. The first to-be-encoded bit segment SE1 includes, for example, but not limited to, a system frame number (SFN) and a hyper SFN.

[0063] In step S210, the original data A is added with a third bit segment SE3 to be encoded, for example, with a length of N B The debugging data B becomes N in length C ×1 data C. The debugging data B can be implemented by, for example but not limited to, a cyclic redundancy check, and is used to verify the correctness of the original data A. The debugging data B segment is generated by the first and second to-be-encoded bit segments SE1 and SE2, and is also an unknown bit segment. At this time, N C =N A +N B .

[0064] In step S220 , the data C is channel-coded by the coding circuit 300 to combat the channel effect.

[0065] like Figure 3 As shown, in one embodiment, the encoding circuit 300 includes L (eg, 6) multi-bit registers 310 (indicated by the letter 'D') and a multi-bit adder 320 (indicated by the symbol '+'). Figure 3 The encoding circuit 300 implements the tail-biting convolution technique encoding with a coding rate of, for example, 1 / 3, and generates a length of 3N C ×1 data Z. However, the coding rate used for encoding in the present invention is not limited thereto.

[0066] The debugging data B based on the cyclic redundancy check is related to any bit of the original data A. When the original data A has an unknown bit (the first bit segment to be encoded SE1), the debugging data B are all unknown bits. Therefore, in the data C, the first and third bit segments to be encoded SE1 and SE3 are both unknown bit segments, and the second bit segment to be encoded SE2 is a known bit segment.

[0067] The characteristics of the convolutional code increase the number of unknown bits in the data Z, and the number of unknown bits is related to the coding rate and constraint length of the convolutional code. The constraint length is the number L of the buffers 210 included in the encoding circuit 300. In one embodiment, the data Z includes a first unknown bit segment US1, a known bit segment KS, and a second unknown bit segment US2.

[0068] In an actual numerical example, the lengths of the first, second and third to-be-encoded bit segments SE1, SE2 and SE3 are 6, 28 and 16 bits respectively.

[0069] With a coding rate of 1 / 3, the first unknown bit segment US1 is generated based on the first bit segment to be encoded SE1 (6 bits) and the first part (6 bits) of the second bit segment to be encoded SE2, which is adjacent to the first bit segment to be encoded SE1 and has a length equivalent to the buffer length L, and has a length of (6+6)×3=36 bits. The known bit segment KS is based on the second part (22 bits) of the second bit segment to be encoded SE2 other than the first part, and has a length of (28-6)×3=66 bits. The second unknown bit segment US2 is based on the third bit segment to be encoded SE3, and has a length of 16×3=48 bits.

[0070] In step S230, the data Z is evenly distributed to all available resource units through rate matching and / or scrambling, forming a modulated / encoded length of N. RM × 1. This step does not affect the ratio of the number of unknown bits to the number of known bits, but only affects the position of the unknown bits in the data Y to be transmitted.

[0071] The data to be transmitted Y is transmitted through the transmission channel and is received as received data RD by the channel estimation circuit 110. The coded data ED generated after pre-processing will have content equivalent to the data Z.

[0072] The data decoding circuit 150 decodes the encoded data ED according to the known bit information KI in response to the characteristics of the tail-biting convolutional code. The structure and operation of the data decoding circuit 150 will be described in detail below.

[0073] Please also refer to Figure 4 as well as Figure 5 . Figure 4 In one embodiment of the present invention, Figure 1 FIG. 1 is a block diagram of a data decoding circuit 150 . Figure 5 The schematic diagram shows a process of generating decoded data DD from encoded data ED by the data decoding circuit 150 according to an embodiment of the present invention.

[0074] In one embodiment, the data decoding circuit 150 includes a data reassembly circuit 400 , a decoding circuit 410 and a data restoration circuit 420 .

[0075] The data reorganization circuit 400 receives the encoded data ED to identify segments of different properties in the encoded data ED and reorganizes the segments to generate to-be-decoded data UDD.

[0076] As mentioned above, the content of the encoded data ED is actually the same as Figure 2 The data reorganization circuit 300 sequentially identifies the first unknown bit segment US1, the known bit segment KS and the second unknown bit segment US2 included in the encoded data ED, and sequentially connects the second unknown bit segment US2 and the first unknown bit segment US1 as the to-be-decoded data UDD.

[0077] For the tail-biting convolutional code, the start and end states of the buffer are the same, so decoding can be performed by connecting the front-end data to the back-end data. According to the previous numerical example, since the first unknown bit segment US1 has a length of 36 bits and the second unknown bit segment US2 has a length of 48 bits, the decoded data UDD will have a length of 48+36=84 bits.

[0078] The decoding circuit 410 decodes the to-be-decoded data UDD according to a Viterbi algorithm and the known bit information KI to generate a decoding result DR.

[0079] In one embodiment, the known bit information KI is a part of the circuit (not shown) in the data receiving device 100 that uses long-term statistics and analysis of previously transmitted data to predict the values ​​of certain bits of the current signal. The method for generating the known bit information KI can refer to, for example, but not limited to, Taiwan Patent Publication No. I672930. However, the present invention is not limited thereto. In one embodiment, the content of the known bit information KI corresponds to the second bit segment SE2 to be encoded in the data C.

[0080] The decoding circuit 410 needs to set an initial search state before performing a search procedure for various possible states on the data to be decoded UDD. Since the length of the buffer used for encoding in the data encoding device 300 is L, and the data to be decoded UDD has placed the second unknown bit segment US2 corresponding to the cyclic redundancy check code at the front, the decoding circuit 410 determines the initial search state based on the portion of the second bit segment SE2 to be encoded in the data C that is adjacent to the third bit segment SE3 to be encoded and has a length equivalent to the buffer length L (e.g., 6 bits).

[0081] After the initial search state is set, the decoding circuit 410 sets each bit of the to-be-decoded data UDD as the lower bit in sequence to perform the search procedure.

[0082] First, the decoding circuit 410 determines whether the lower bit is known according to the known bit information KI. When the lower bit is known, the decoding circuit 410 sets the second half of the multi-bit state corresponding to the lower bit to be invalid and sets the corresponding cumulative metric value to the minimum when the lower bit is 0, and sets the first half of the state corresponding to the lower bit to be invalid and sets the corresponding cumulative metric value to the minimum when the lower bit is 1.

[0083] For example, if the buffer length L is 6, the lower bit has 2 6 = 64 possible states. When the lower bit is 0, the decoding circuit 410 sets the corresponding lower bit from 32 to 63 to invalid, and when the lower bit is 1, sets the corresponding lower bit from 0 to 31 to invalid, and sets the corresponding cumulative metric value to the minimum.

[0084] Next, when the lower bit is known or unknown, the decoding circuit 410 determines whether at least one of the two preceding states corresponding to any current possible state is valid in the state where the lower bit is not set to invalid.

[0085] When both leading states are invalid, the decoding circuit 410 sets the current possible state to invalid and sets the corresponding cumulative metric value to the minimum. When at least one of the two leading states is valid, the decoding circuit 410 sets the current possible state to valid and calculates the cumulative metric values ​​of the current possible state corresponding to the two leading states.

[0086] Specifically, when only one of the two preceding states is valid, the cumulative metric value Mac of the current possible state is the sum of the cumulative metric value Mpre of the valid preceding state and the current metric value Mcur of the current possible state (Mac=Mpre+Mcur). The calculation method of the current metric value Mcur is well known to those with ordinary knowledge in the technical field and will not be described in detail.

[0087] When both leading states are valid, the current possible state will generate two cumulative metric values ​​Mac0 and Mac1 corresponding to the two leading states. The cumulative metric value Mac0 is the sum of the corresponding leading state cumulative metric value Mpre0 and the current metric value Mcur0 of the current possible state (Mac0=Mpre0+Mcur0). The cumulative metric value Mac1 is the sum of the corresponding leading state cumulative metric value Mpre1 and the current metric value Mcur1 of the current possible state (Mac1=Mpre1+Mcur1).

[0088] The decoding circuit 410 selects the larger cumulative metric value from the cumulative metric values ​​of the two predecessor states as the cumulative metric value of the current possible state, and selects the predecessor state corresponding to the larger cumulative metric value as the survivor path. When only one of the predecessor states is valid, since only one corresponding cumulative metric value exists, the cumulative metric value is directly selected as the cumulative metric value of the current possible state, and the valid predecessor state is used as the survivor path.

[0089] When all states have been determined and the corresponding cumulative metric values ​​have been generated, the decoding circuit 410 uses the next bit of the next bit as the next bit to perform the search process, and after all bits have completed the search process, generates a decoding result DR based on the survivor path backtracking. In one embodiment, the decoding result DR includes a second decoded bit segment DS2 and a first decoded bit segment DS1 that correspond to the second unknown bit segment US2 and the first unknown bit segment US1 in sequence.

[0090] The data recovery circuit 420 sequentially connects the first decoded bit segment DS1, the known decoded bit segment KD corresponding to the known bit segment KS, and the second decoded bit segment DS2 to generate decoded data DD. Since the original content of the known bit segment KS can be known from the known bit information KI, the known decoded bit segment KD can be generated without decoding.

[0091] Comparison Figure 2 In the content shown and the aforementioned numerical examples, the first decoded bit segment DS1 includes data content corresponding to the first bit segment to be encoded SE1 (6 bits) and the first part (6 bits) of the second bit segment to be encoded SE2, which is adjacent to the first bit segment to be encoded SE1 and has a length equivalent to the buffer length L. The known decoded bit segment KD includes the second part (22 bits) of the second bit segment to be encoded SE2 other than the first part. The second decoded bit segment DS2 includes data content of the third bit segment to be encoded SE3 (16 bits).

[0092] Please refer to Figure 6 . Figure 6 A schematic diagram showing the performance of a data decoding circuit according to different decoding methods in one embodiment of the present invention. Figure 6 The horizontal axis represents the signal-to-noise ratio (SNR) in decibels (dB), and the vertical axis represents the packet error rate (packet error rate).

[0093] like Figure 6As shown, the line segments connected by square grids represent the first type of decoding method, which copies the coded data twice and then performs Viterbi decoding to search for all possible paths. The line segments connected by crosses represent the second type of decoding method, which copies the coded data once and then performs Viterbi decoding, and excludes some paths according to known bit information to search for the remaining possible paths. The line segments connected by dots represent the method of the present invention, which does not require copying the coded data, but reorganizes the coded data and excludes some paths according to known bit information to search for the remaining possible paths.

[0094] By comparison Figure 2 In the content shown and the numerical examples mentioned above, there are three segments of data C with a total of 50 bits (6+28+16). The first type of decoding method needs to perform 150-order searches after being copied twice, the second type of decoding method needs to perform 100-order searches after being copied once, and the present invention only needs to perform 28-order searches (6+6+16) after reorganization. In terms of packet error rate, the present invention has a significant decrease compared to the first type of decoding method. Compared with the second type of decoding method, it still has the same performance with a significant decrease in the number of search orders.

[0095] Therefore, the data decoding circuit of the present invention can utilize the characteristics of tail-biting convolutional codes to reduce the search order while maintaining the decoding performance. The power consumption of the data decoding circuit can be greatly reduced, thereby making the data receiving device more power-saving.

[0096] Please refer to Figure 7 . Figure 7 FIG. 7 is a flow chart of a data decoding method 700 according to an embodiment of the present invention.

[0097] In addition to the aforementioned apparatus, the present invention further discloses a data decoding method 700, which is applied to, for example, but not limited to Figure 3 In the data decoding circuit 150. An embodiment of the data decoding method 700 is as follows Figure 7 As shown, it includes the following steps:

[0098] In step S710: the data reassembly circuit 400 receives the encoded data ED encoded by the tail-biting convolutional coding technique to sequentially identify the first unknown bit segment US1, the known bit segment KS and the second unknown bit segment US2 included in the encoded data, and further sequentially connect the second unknown bit segment US2 and the first unknown bit segment US1 as the to-be-decoded data UDD.

[0099] In step S720 , the decoding circuit 410 decodes the to-be-decoded data UDD according to the Viterbi algorithm and at least one known bit information KI to generate a decoding result DR, wherein the decoding result DR includes a second decoded bit segment DS2 and a first decoded bit segment DS1 corresponding to the second unknown bit segment US2 and the first unknown bit segment US1 in sequence.

[0100] In step S730 : the data recovery circuit 420 is enabled to sequentially connect the first decoded bit segment DS1 , the known decoded bit segment KD corresponding to the known bit segment KS, and the second decoded bit segment DS2 to generate decoded data DD.

[0101] Please refer to Figure 8 . Figure 8 In one embodiment of the present invention, Figure 7 In step S720, a flowchart of a decoding process 800 for decoding the to-be-decoded data UDD is shown. An embodiment of the decoding process 800 is as follows: Figure 8 As shown, it includes the following steps:

[0102] In step S810 : the decoding circuit 410 determines whether the search for all states corresponding to the last bit is completed.

[0103] In step S820 : when the search for all states corresponding to the last bit has not been completed, the decoding circuit 410 further determines whether the next bit is known according to the known bit information KI.

[0104] In step S830 : when the lower bit is known, the decoding circuit 410 sets half of the corresponding states to be invalid according to the value of the lower bit.

[0105] Step S840: When the lower bit is determined to be unknown in step S820 or after step S830, the decoding circuit 410 determines whether at least one of the two preceding states corresponding to any current possible state is valid in the state where the lower bit is not set to invalid.

[0106] In step S850 : when both the two preceding states are invalid, the decoding circuit 410 sets the current possible state to invalid, and sets the corresponding cumulative metric value to the minimum.

[0107] In step S860 : when at least one of the two preceding states is valid, the decoding circuit 410 sets the current possible state to be valid, so as to respectively calculate the cumulative metric values ​​of the current possible state corresponding to the two preceding states.

[0108] In step S870 : the decoding circuit 410 selects a larger cumulative metric value from the cumulative metric values ​​of the two predecessor states as the cumulative metric value of the current possible state, and selects the predecessor state corresponding to the larger cumulative metric value as the survivor path.

[0109] In step S880: after steps S850 and S870, the decoding circuit 410 determines whether the search of all states is completed. If the search of all states is not completed, the process will return to step S840 to continue searching the unfinished searched states. If the search of all states is completed, the process will enter step S890.

[0110] In step S890 : the decoding circuit 410 determines whether the next bit is the last bit.

[0111] In step S895 : when the lower bit is not the last bit, the decoding circuit 410 uses the next bit as the lower bit to perform the search procedure.

[0112] When step S890 determines that the next digit is the last digit, or when step S895 is completed, the process returns to step S810 for determination.

[0113] When it is determined in step S810 that the search for all states corresponding to the last bit has been completed, the process proceeds to step S815 , where the decoding circuit 410 generates a decoding result DR according to the surviving path backtracking.

[0114] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without violating the spirit of the present invention.

[0115] In summary, the data decoding device and method of the present invention utilizes the characteristics of tail-biting convolutional codes to reduce the search order while maintaining the decoding performance. The power consumption of the data decoding circuit can be greatly reduced, thereby making the data receiving device more power-saving.

[0116] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person having ordinary knowledge in the technical field may make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined in the claims of this specification.

Claims

1. A data decoding circuit, characterized in that: Include: a data reorganization circuit configured to receive a coded data coded by tail-biting convolutional coding technology, to sequentially identify a first unknown bit segment, a known bit segment and a second unknown bit segment included in the coded data, and to further sequentially connect the second unknown bit segment and the first unknown bit segment into a data to be decoded; a decoding circuit configured to decode the to-be-decoded data according to a Viterbi algorithm and at least one known bit information to generate a decoding result, wherein the decoding result comprises a second decoded bit segment and a first decoded bit segment which sequentially correspond to the second unknown bit segment and the first unknown bit segment; as well as A data recovery circuit is configured to sequentially connect the first decoded bit segment, a known decoded bit segment corresponding to the known bit segment, and the second decoded bit segment to generate a decoded data.

2. The data decoding circuit according to claim 1, characterized in that: The encoded data is generated by a data encoding device having a buffer length according to a to-be-encoded data, and the to-be-encoded data comprises a first to-be-encoded bit segment, a second to-be-encoded bit segment and a third to-be-encoded bit segment, wherein the first to-be-encoded bit segment and the third to-be-encoded bit segment are respectively unknown bit segments, and the second to-be-encoded bit segment is a known bit segment and corresponds to the known bit information; The data encoding device generates the first unknown bit segment according to the first bit segment to be encoded and a first part of the second bit segment to be encoded that is adjacent to the first bit segment to be encoded and has a length equivalent to the buffer length, generates the known bit segment according to a second part of the second bit segment to be encoded outside the first part, and generates the second unknown bit segment according to the third bit segment to be encoded.

3. The data decoding circuit according to claim 2, characterized in that: The first bit segment to be encoded includes a system frame number and a super system frame number, and the third bit segment to be encoded includes a cyclic redundancy check code.

4. The data decoding circuit according to claim 2, characterized in that: The decoding circuit is configured to set an initial search state according to a portion of the second bit segment to be encoded that is adjacent to the third bit segment to be encoded and has a length equal to the buffer length, and sequentially set each multi-bit byte of the data to be decoded to a lower bit to perform a search procedure, the search procedure comprising: According to the known bit information, determining whether the current bit is known; When the lower bit is known, when the lower bit is 0, the second half of the multi-bit state corresponding to the lower bit is set to be invalid and the corresponding cumulative metric value is set to be minimum, and when the lower bit is 1, the first half of the multi-bit state corresponding to the lower bit is set to be invalid and the corresponding cumulative metric value is set to be minimum; When the lower bit is known or unknown, determining whether at least one of the two preceding states corresponding to any current possible state in the multiple bit states that are not set to invalid is valid; When both of the two leading states are invalid, the current possible state is set to invalid, and the corresponding cumulative metric value is set to the minimum; When at least one of the two predecessor states is valid, the current possible state is set to be valid, the cumulative metric values ​​of the two valid predecessor states corresponding to the current possible state are calculated respectively, and a larger cumulative metric value is selected from the cumulative metric values ​​of the two predecessor states as the cumulative metric value of the current possible state, and the predecessor state corresponding to the larger cumulative metric value is selected as a survivor path; as well as When all the multi-bit states have been determined and the corresponding cumulative metric values ​​have been generated, the next bit of the lower bit is used as the lower bit to perform the search procedure.

5. The data decoding circuit according to claim 4, characterized in that: The decoding circuit is further configured to generate the decoding result by backtracking according to the surviving path after all the bits of the data to be decoded have completed the search procedure.

6. A data decoding method, applied to a data decoding circuit, characterized in that: Include: A data reorganization circuit is configured to receive a coded data coded by tail-biting convolutional coding technology, to sequentially identify a first unknown bit segment, a known bit segment and a second unknown bit segment included in the coded data, and to further sequentially connect the second unknown bit segment and the first unknown bit segment into a data to be decoded; Enable a decoding circuit to decode the to-be-decoded data according to a Viterbi algorithm and at least one known bit information to generate a decoding result, wherein the decoding result includes a second decoded bit segment and a first decoded bit segment which sequentially correspond to the second unknown bit segment and the first unknown bit segment; as well as A data recovery circuit is configured to sequentially connect the first decoded bit segment, a known decoded bit segment corresponding to the known bit segment, and the second decoded bit segment to generate a decoded data.

7. The data decoding method according to claim 6, characterized in that: The encoded data is generated by a data encoding device having a buffer length according to a to-be-encoded data, and the to-be-encoded data comprises a first to-be-encoded bit segment, a second to-be-encoded bit segment and a third to-be-encoded bit segment, wherein the first to-be-encoded bit segment and the third to-be-encoded bit segment are respectively unknown bit segments, and the second to-be-encoded bit segment is a known bit segment and corresponds to the known bit information; The data encoding device generates the first unknown bit segment according to the first bit segment to be encoded and a first part of the second bit segment to be encoded that is adjacent to the first bit segment to be encoded and has a length equivalent to the buffer length, generates the known bit segment according to a second part of the second bit segment to be encoded outside the first part, and generates the second unknown bit segment according to the third bit segment to be encoded.

8. The data decoding method according to claim 7, characterized in that: The first bit segment to be encoded includes a system frame number and a super system frame number, and the third bit segment to be encoded includes a cyclic redundancy check code.

9. The data decoding method according to claim 7, characterized in that: Also includes: The decoding circuit is set to an initial search state according to a portion of the second bit segment to be encoded that is adjacent to the third bit segment to be encoded and has a length equal to the buffer length, and each multi-bit byte of the data to be decoded is sequentially set to a lower bit to perform a search procedure, the search procedure comprising: According to the known bit information, determining whether the current bit is known; When the lower bit is known, when the lower bit is 0, the second half of the multi-bit state corresponding to the lower bit is set to be invalid and the corresponding cumulative metric value is set to be minimum, and when the lower bit is 1, the first half of the multi-bit state corresponding to the lower bit is set to be invalid and the corresponding cumulative metric value is set to be minimum; When the lower bit is known or unknown, determining whether at least one of the two preceding states corresponding to any current possible state in the multiple bit states that are not set to invalid is valid; When both of the two leading states are invalid, the current possible state is set to invalid, and the corresponding cumulative metric value is set to the minimum; When at least one of the two predecessor states is valid, the current possible state is set to be valid, the cumulative metric values ​​of the two valid predecessor states corresponding to the current possible state are calculated respectively, and a larger cumulative metric value is selected from the cumulative metric values ​​of the two predecessor states as the cumulative metric value of the current possible state, and the predecessor state corresponding to the larger cumulative metric value is selected as a survivor path; as well as When all the multi-bit states have been determined and the corresponding cumulative metric values ​​have been generated, the next bit of the lower bit is used as the lower bit to perform the search procedure.

10. The data decoding method according to claim 9, characterized in that: Also includes: After all the bits of the data to be decoded have completed the search procedure, the decoding circuit generates the decoding result by backtracking according to the surviving path.

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