A method for onboard system self-monitoring based on multi-core processor

Abstract

This application provides a self-monitoring method for airborne systems based on multi-core processors. The method includes: constructing a dual-redundant flight control computer self-monitoring model based on a multi-core processor; pre-setting a multi-core processor self-monitoring algorithm; and using the dual-redundant flight control computer self-monitoring model and the multi-core processor self-monitoring algorithm to monitor the reliability of the airborne system operation.

Description

Technical Field

[0001] This application relates to aviation technology, specifically to a self-monitoring method for airborne systems based on multi-core processors. Background Technology

[0002] The flight control computer is a key piece of equipment in the airborne system, and the processor is the core component of the flight control computer. Currently, foreign components are mainly used, which severely restricts the technology. However, domestically developed and controllable processors, such as Phytium and Loongson, are gradually emerging, making it possible to realize flight control computers based on domestic processors. Summary of the Invention

[0003] This application proposes a self-monitoring method for airborne systems based on multi-core processors, which solves the problem of comprehensive isolation of the functions and physical components of an aircraft platform. On the one hand, it enhances the integration capability of airborne systems, and on the other hand, it improves system reliability.

[0004] Technical solution: A self-monitoring method for airborne systems based on multi-core processors, the method comprising:

[0005] Construct a self-monitoring model for a dual-redundant flight control computer based on a multi-core processor;

[0006] Pre-configure the self-monitoring algorithm for multi-core processors;

[0007] The reliability of the airborne system operation is monitored using the dual-redundant flight control computer self-monitoring model and the multi-core processor self-monitoring algorithm.

[0008] Specifically, the dual-redundant flight controller computer self-monitoring model includes a redundant flight controller computer CHA and a redundant flight controller computer CHB; each redundant flight controller computer contains two CPUs of the same model, namely CPU1 and CPU2.

[0009] Specifically, each CPU contains two cores, namely core 0 and core 1. Core 0 runs safety-critical functions, while core 1 runs non-safety-critical functions. Core 0 has a higher priority than core 1. Core 0 and core 1 communicate through an inter-core data pool. Core 0, as the master core, is responsible for managing the external interface input and output of core 1. Core 0 and core 1 operate independently of each other.

[0010] Specifically, each redundant flight control computer's CPU1 and CPU2 operate in a self-monitoring pair mode. Each CPU's core 0 and core 1 form an independently operating functional unit. Core 0 obtains data from core 1 for calculation, and finally, the core 0 of CPU1 and CPU2 monitors and compares the calculation results through internal communication.

[0011] Specifically, the redundancy flight controller (CHA) and the redundancy flight controller (CHB) communicate via a cross-channel data link.

[0012] Specifically, the multi-core processor self-monitoring algorithm includes:

[0013] Core 0 is a safety-critical function with the highest priority, while Core 1 has a lower priority than Core 0.

[0014] Specifically, the multi-core processor self-monitoring algorithm includes:

[0015] If either CPU1 or CPU2's core 0 fails, this channel will be directly disconnected.

[0016] Specifically, the multi-core processor self-monitoring algorithm includes:

[0017] When both core 0 and core 1 of CPU1 and CPU2 are normal, the self-monitoring algorithm is run to determine whether the channel is valid based on the self-monitoring results.

[0018] Specifically, the multi-core processor self-monitoring algorithm includes:

[0019] When both CPU1 and CPU2 cores 0 are normal, if either CPU1 or CPU2 core 1 fails, then core 1 of this channel will not be used. The status and data of other cores 1 will be obtained through CCDL to determine whether other cores 1 are valid. If they are valid, the data of other cores 1 will be used; otherwise, the data of other cores 1 will not be used. After confirming the data source of core 1, the self-monitoring algorithm will be run to determine whether this channel is valid based on the self-monitoring results.

[0020] In summary, this application proposes an airborne system self-monitoring method based on a multi-core processor, which has the following advantages: the system structure is simplified, the self-monitoring improves the fault coverage of the flight control computer, and compared with the traditional triple-redundant flight control computer structure, the self-monitoring system only requires two redundancies for the flight control computer; the multi-core processor-based flight control computer realizes the integration of aircraft platform functions and physics, saves platform resources, and the airborne system has a simple structure and is easy to maintain.

[0021] Explanation of the attached diagram

[0022] Figure 1 A schematic diagram of the airborne system self-monitoring method based on a multi-core processor provided in this application. Detailed Implementation

[0023] The specific embodiments of the present invention will be described in further detail below.

[0024] This application proposes an airborne system self-monitoring method based on a multi-core processor, constructs a dual-redundant flight control computer self-monitoring model based on a multi-core processor, and designs a multi-core processor self-monitoring algorithm.

[0025] like Figure 1 As shown, the method includes:

[0026] Step 1: Construct a self-monitoring model for a dual-redundant air-to-air computer based on a multi-core processor;

[0027] Specifically, the dual-redundant flight controller computer self-monitoring model includes a redundant flight controller computer CHA and a redundant flight controller computer CHB; each redundant flight controller computer contains two CPUs of the same model, namely CPU1 and CPU2.

[0028] Specifically, each CPU contains two cores, namely core 0 and core 1. Core 0 runs safety-critical functions, while core 1 runs non-safety-critical functions. Core 0 has a higher priority than core 1. Core 0 and core 1 communicate through an inter-core data pool. Core 0, as the master core, is responsible for managing the external interface input and output of core 1. Core 0 and core 1 operate independently of each other.

[0029] Specifically, each redundant flight control computer's CPU1 and CPU2 operate in a self-monitoring pair mode. Each CPU's core 0 and core 1 form an independently operating functional unit. Core 0 obtains data from core 1 for calculation, and finally, the core 0 of CPU1 and CPU2 monitors and compares the calculation results through internal communication.

[0030] Specifically, the redundancy flight controller (CHA) and the redundancy flight controller (CHB) communicate via a cross-channel data link (CCDL).

[0031] Step 2: Pre-configure the multi-core processor self-monitoring algorithm;

[0032] As shown in Table 1, the self-monitoring algorithm based on multi-core processors specifically includes:

[0033] Core 0 is a safety-critical function and has the highest priority; Core 1 has a lower priority than Core 0.

[0034] If either CPU1 or CPU2 core 0 fails, this channel will be directly disconnected.

[0035] When both core 0 and core 1 of CPU1 and CPU2 are normal, the self-monitoring algorithm is run to determine whether the channel is valid based on the self-monitoring results.

[0036] When both CPU1 and CPU2 cores 0 are normal, if either CPU1 or CPU2 core 1 fails, then core 1 of this channel will not be used. The status and data of other cores 1 will be obtained through CCDL to determine whether other cores 1 are valid. If they are valid, the data of other cores 1 will be used; otherwise, the data of other cores 1 will not be used. After confirming the data source of core 1, the self-monitoring algorithm will be run to determine whether this channel is valid based on the self-monitoring results.

[0037] Table 1

[0038]

[0039] Step 3: Using the dual-redundant flight control computer self-monitoring model and the multi-core processor self-monitoring algorithm, monitor the reliability of the airborne system operation.

[0040] In summary, the multi-core processor-based flight control computer of this application has high processing performance and comprehensive capabilities in terms of aircraft platform functions and physics. Under the dual-redundant multi-core multi-processor flight control computer architecture, this invention designs a self-monitoring method for airborne systems based on multi-core processors, which improves the comprehensive capabilities of airborne systems on the one hand and enhances system reliability on the other.

[0041] The above description is merely a specific embodiment of the present invention, providing a detailed description of the invention. Parts not covered herein are conventional techniques. However, the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A self-monitoring method for an airborne system based on a multi-core processor, characterized in that, The method includes: A dual-redundant air-to-air computer self-monitoring model based on a multi-core processor is constructed. The dual-redundant air-to-air computer self-monitoring model includes a redundant air-to-air computer CHA and a redundant air-to-air computer CHB. Each redundant air-to-air computer contains two CPUs of the same model, namely CPU1 and CPU2. Pre-configure the self-monitoring algorithm for multi-core processors; Using the aforementioned dual-redundant flight control computer self-monitoring model and the aforementioned multi-core processor self-monitoring algorithm, the reliability of the airborne system operation is monitored. Multi-core processor self-monitoring algorithms, specifically including: If either CPU1 or CPU2's core 0 fails, this channel will be directly disconnected. When both core 0 and core 1 of CPU1 and CPU2 are normal, the self-monitoring algorithm is run to determine whether the channel is valid based on the self-monitoring results. When both CPU1 and CPU2 cores 0 are normal, if either CPU1 or CPU2 core 1 fails, then core 1 of this channel will not be used. The status and data of other channel cores 1 will be obtained through CCDL to determine whether other channel cores 1 are valid. If they are valid, the data of other channel cores 1 will be used; otherwise, the data of other channel cores 1 will not be used. After confirming the data source of core 1, the self-monitoring algorithm will be run to determine whether this channel is valid based on the self-monitoring results. Each CPU contains two cores, namely core 0 and core 1. Core 0 runs safety-critical functions, while core 1 runs non-safety-critical functions. Core 0 has a higher priority than core 1. Core 0 and core 1 communicate through an inter-core data pool. Core 0, as the master core, is responsible for managing the external interface input and output of core 1. Core 0 and core 1 operate independently of each other.

2. The airborne system self-monitoring method according to claim 1, characterized in that, Each redundant flight control computer's CPU1 and CPU2 operate in a self-monitoring mode. Each CPU's core 0 and core 1 form an independently operating functional unit. Core 0 obtains data from core 1 for calculation, and finally, the core 0 of CPU1 and CPU2 monitors and compares the calculation results through internal communication.

3. The airborne system self-monitoring method according to claim 2, characterized in that, The redundancy flight controller (CHA) and the redundancy flight controller (CHB) communicate via a cross-channel data link.

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