High bandwidth impedance matching integrated ceramic substrate circuit and manufacturing method thereof

Abstract

The present invention relates to a high-bandwidth impedance matching integrated ceramic substrate circuit, comprising a ceramic substrate, wherein the front of the ceramic substrate is provided with a signal output microstrip line formed by metal plating, a grounding metal plating, a microstrip line transition section, a P-electrode connection part, two N-electrode transmission lines and a sampling resistor of a matching network; the P-electrode connection part and the two N-electrode transmission lines are respectively provided with flip-chip gold pillars; a grounding through hole is provided in the middle of the grounding metal plating, and the back of the ceramic substrate and the hole wall of the grounding through hole are covered with a gold layer. In the present invention, a circuit structure is formed on the ceramic substrate by plating, and by designing the size of each device of the ceramic substrate circuit, the microstrip line transmission has a high matching degree with the high-speed photodiode chip, and the transmission loss is small, so that the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz, and the radio frequency reflection loss within 30GHz can reach 8.366dB.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a high-bandwidth impedance matching integrated ceramic substrate circuit and a manufacturing method thereof. Background Art

[0002] With the continuous development of 5G communications, high-speed fiber-optic communication systems have been rapidly developed and widely used. The demand for high-speed photodetector modules as core components of high-speed fiber-optic communication systems has also been increasing.

[0003] The existing high-speed photodetector module impedance matching circuit assembly mainly adopts discrete component mounting and gold wire bonding connection. The assembly steps are complicated, the reliability is low, and the RF reflection loss is large, which affects the performance of subsequent power devices. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a high-bandwidth impedance matching integrated ceramic substrate circuit and a manufacturing method thereof.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A high-bandwidth impedance matching integrated ceramic substrate circuit comprises a ceramic substrate, wherein the ceramic substrate is provided with a front side and a back side opposite to the front side; the front side is provided with a signal output microstrip line, a grounding metal plating layer, a microstrip line transition section, a P-electrode connection part and two N-electrode transmission lines formed by a first metal plating layer, and a sampling resistor of a matching network formed by a second metal plating layer; one end of the signal output microstrip line is connected to the P-electrode connection part through a trapezoidal microstrip line transition section, the two N-electrode transmission lines are symmetrically arranged on both sides of the P-electrode connection part, the P-electrode connection part is provided with a first flip-chip gold column, and the two N-electrode transmission lines are respectively provided with a second flip-chip gold column; one side of the signal output microstrip line is connected to the sampling resistor, the sampling resistor is connected to the grounding metal plating layer, a grounding through hole is opened in the middle of the grounding metal plating layer and penetrates to the back side, the back side of the ceramic substrate is covered with a second gold layer, the second gold layer is used for grounding, and the hole wall of the grounding through hole is covered with a third gold layer connecting the grounding metal plating layer and the second gold layer.

[0007] Furthermore, the size of the signal output microstrip line is 1.15 mm×0.4 mm; the size of the grounding metal plating layer is 1 mm×0.3 mm; the size of the two N-electrode transmission lines is 0.3 mm×

[0008] 0.06mm.

[0009] Furthermore, the first metal coating includes a tungsten-titanium alloy layer disposed on the ceramic substrate, a platinum layer disposed on the tungsten-titanium alloy layer, and a first gold layer disposed on the platinum layer.

[0010] Furthermore, the thickness of the tungsten-titanium alloy layer is 0.1 μm; the thickness of the platinum layer is 0.2 μm; and the thickness of the first gold layer is 3.0-3.5 μm.

[0011] Furthermore, the second metal coating is a tantalum nitride layer; the size of the tantalum nitride layer is 0.15 mm×0.3 mm, and the resistance is 50Ω.

[0012] Furthermore, a third flip-chip gold column is provided on the front side, and the third flip-chip gold column is used for fixing the chip.

[0013] Furthermore, the number of the grounding through holes is two, and the radius is 0.1 mm.

[0014] A method for manufacturing a high-bandwidth impedance matching integrated ceramic substrate circuit comprises the following steps:

[0015] S1. Grinding, cleaning and drying the ceramic substrate;

[0016] S2, forming a tantalum nitride layer in the resistance region on the front side of the ceramic substrate, forming a tungsten-titanium alloy layer in the metal region, and forming a platinum layer on the tungsten-titanium alloy layer;

[0017] S3, forming a first gold layer on the platinum layer by an electroplating process;

[0018] S4, opening a grounding through hole penetrating the front and back sides of the ceramic substrate in the grounding metal plating layer, and forming a second gold layer on the back side of the ceramic substrate by an electroplating process, and forming a third gold layer on the hole wall of the grounding through hole;

[0019] S5, using photolithography and etching processes to complete the pattern preparation of the signal output microstrip line, the ground metal plating layer, the microstrip line transition section, the P electrode connection part, the two N electrode transmission lines and the sampling resistor of the matching network;

[0020] S6, heat-treating the ceramic substrate, cutting the sampling resistor into an L shape, adjusting its resistance to 50Ω, and then heat-treating it again;

[0021] S7, forming flip-chip gold pillars at the P-electrode connection portion and the two N-electrode transmission lines respectively by electroplating process;

[0022] S8. Divide the ceramic substrate into independent units by dicing.

[0023] Furthermore, the thickness of the tungsten-titanium alloy layer is 0.1 μm; the thickness of the platinum layer is 0.2 μm; the thickness of the first gold layer is 3.0-3.5 μm; the thickness of the second gold layer and the third gold layer is 1.5-2.0 μm.

[0024] Furthermore, the step S6 specifically includes the following sub-steps:

[0025] S61, heat treating the ceramic substrate with the pattern formed thereon at 250-350° C. for 1.5-2.5 hours;

[0026] S62, heat treating the ceramic substrate at 130-170° C. for 20-28 hours;

[0027] S63, using a laser to perform L-shaped cutting on the sampling resistor, and adjusting its resistance value according to the required target resistance value and accuracy;

[0028] S64, heat-treating the ceramic substrate after resistance adjustment at 130-170° C. for 20-28 hours.

[0029] In the present invention, a circuit structure is formed on a ceramic substrate by plating. By designing the dimensions of various components of the ceramic substrate circuit, the microstrip line transmission and the high-speed photodiode chip are highly matched and the transmission loss is small, so that the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz and the RF reflection loss within 30GHz can reach -8.366dB. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 The figure is a schematic structural diagram of a preferred embodiment of the high-bandwidth impedance matching integrated ceramic substrate circuit of the present invention.

[0032] Figure 2 for Figure 1 Enlarged view of point A in the middle.

[0033] Figure 3 for Figure 1 Top view of the .

[0034] Figure 4 for Figure 1 Bottom view of .

[0035] Figure 5 The present invention is a flowchart of a preferred embodiment of the method for manufacturing a high-bandwidth impedance matching integrated ceramic substrate circuit.

[0036] Figure 6 Simulation equivalent circuit schematic for high bandwidth impedance matching integrated ceramic substrate circuit.

[0037] Figure 7 This is the simulation S-parameter output result diagram of the high-bandwidth impedance matching integrated ceramic substrate circuit.

[0038] In the figure: 1. ceramic substrate, 2. ground through hole, 100. front side, 110. signal output microstrip line, 111. microstrip line transition section, 112. P electrode connection part, 120. N electrode transmission line, 130. sampling resistor, 140. ground metal plating, 151. first flip-chip gold column, 152. second flip-chip gold column, 153. third flip-chip gold column, 200. back side. DETAILED DESCRIPTION

[0039] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0040] like Figure 1 , Figure 2 and Figure 3 As shown, a preferred embodiment of the high-bandwidth impedance matching integrated ceramic substrate circuit of the present invention includes a ceramic substrate 1, which is preferably an alumina ceramic substrate, and the size is preferably 2mm×2mm×0.381mm; the ceramic substrate 1 is provided with a front side 100 and a back side 200 opposite to the front side 100; the front side 100 is provided with a signal output microstrip line 110, a grounding metal plating layer 140, a microstrip line transition section 111, a P electrode connection part 112 and two N electrode transmission lines 120 formed by a first metal plating layer. The first metal plating layer includes a tungsten-titanium alloy layer arranged on the ceramic substrate 1, a platinum layer arranged on the tungsten-titanium alloy layer, and a first gold layer arranged on the platinum layer. The material of the tungsten-titanium alloy layer is WTi, and the thickness is preferably 0.1μm; the material of the platinum layer is Pt, and the thickness is preferably 0.2μm; the material of the first gold layer is Au, and the thickness is preferably 3.0-3.5μm. The front side 100 is also provided with a sampling resistor 130 of a matching network formed by a second metal plating layer, and the second plating layer is a tantalum nitride layer.

[0041] The size of the signal output microstrip line 110 is preferably 1.15mm×0.4mm; one end of the signal output microstrip line 110 is connected to the P electrode connection part 112 through a trapezoidal microstrip line transition section 111, and the two N electrode transmission lines 120 are symmetrically arranged on both sides of the P electrode connection part 112, and the size of the two N electrode transmission lines 120 is preferably 0.3mm×0.06mm. The P electrode connection part 112 is provided with a first flip-chip gold column 151, and the first flip-chip gold column 151 is used to connect the P electrode of the high-speed photodiode chip; the two N electrode transmission lines 120 are respectively provided with a second flip-chip gold column 152, and the second flip-chip gold column 152 is used to connect the N electrode of the high-speed photodiode chip; the materials of the first flip-chip gold column 151 and the second flip-chip gold column 152 are both Au. To facilitate fixation, in some embodiments, to facilitate fixation of the high-speed photodiode chip, the front side 100 may also be provided with a third flip-chip gold column 153 , preferably two third flip-chip gold columns 153 , the size and material of the third flip-chip gold column 153 being the same as those of the first flip-chip gold column 151 .

[0042] One side of the signal output microstrip line 110 is connected to the sampling resistor 130 of the matching network. The size of the sampling resistor 130 is preferably 0.15mm×0.3mm, and the resistance is 50Ω. The sampling resistor 130 is connected to the grounding metal plating layer 140. The size of the grounding metal plating layer 140 is preferably 1mm×0.3mm. Figure 4 As shown, a grounding through hole 2 is provided in the middle of the grounding metal plating layer 140 and extends to the reverse side 200. The number of the grounding through holes 2 is preferably two, and the radius is preferably 0.1 mm. The reverse side 200 of the ceramic substrate 1 is covered with a second gold layer, and the second gold layer is used for grounding. The hole wall of the grounding through hole 2 is covered with a third gold layer connecting the grounding metal plating layer 140 and the second gold layer. The materials of the second gold layer and the third gold layer are both Au, and the thickness is 1.5 to 2.0 μm.

[0043] In this embodiment, a circuit structure is formed on a ceramic substrate by plating. The ceramic substrate circuit realizes CPW (coplanar waveguide) connection with a high-speed photodiode chip through a flip-chip gold column; the conversion of current to voltage signal is realized through a sampling resistor; and the signal is output through a signal transmission microstrip line. By designing the dimensions of each component of the ceramic substrate circuit, the microstrip line transmission and the high-speed photodiode chip have a high matching degree and a small transmission loss, so that the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz, and the RF reflection loss within 30GHz can reach -8.366dB.

[0044] like Figure 5 As shown, a preferred embodiment of the method for manufacturing a high-bandwidth impedance matching integrated ceramic substrate circuit of the present invention comprises the following steps:

[0045] S1. Grind the ceramic substrate 1, and wash the polished ceramic substrate 1 with deionized water and dry it.

[0046] S2. A tantalum nitride layer made of TaN is formed by evaporation or sputtering in the resistance area (area for forming the sampling resistor 130) on the front side 100 of the ceramic substrate 1 by a stripping process; the tantalum nitride layer is the second metal coating. A tungsten-titanium alloy layer made of WTi is formed by evaporation or sputtering in the metal area (area for forming the signal output microstrip line 110, the grounding metal coating 140, the microstrip line transition section 111, the P electrode connection part 112 and the two N electrode transmission lines 120) on the front side 100 of the ceramic substrate 1 by a stripping process, and the thickness of the tungsten-titanium alloy layer is preferably 0.1 μm. A platinum layer made of Pt is formed on the tungsten-titanium alloy layer, and the thickness of the platinum layer is preferably 0.2 μm.

[0047] S3, forming a first gold layer on the platinum layer by electroplating; the material of the first gold layer is Au, and the thickness is preferably 3.0-3.5 μm. The tungsten-titanium alloy layer on the front surface 100 of the ceramic substrate 1, the platinum layer on the tungsten-titanium alloy layer, and the first gold layer on the platinum layer form a first metal plating layer.

[0048] S4. A grounding through hole 2 is provided on the grounding metal plating layer 140, which passes through the front surface 100 and the back surface 200 of the ceramic substrate 1. Preferably, two grounding through holes 2 are provided. A second gold layer is formed on the back surface 200 of the ceramic substrate 1 by electroplating, and a third gold layer is formed on the hole wall of the grounding through hole 2. The second gold layer and the third gold layer can be formed at the same time. The materials of the second gold layer and the third gold layer are both Au, and the thickness is 1.5-2.0 μm.

[0049] S5. Use photolithography and etching processes to complete the pattern preparation of the signal output microstrip line 110, the grounding metal plating layer 140, the microstrip line transition section 111, the P-electrode connection portion 112, the two N-electrode transmission lines 120 and the sampling resistor 130 of the matching network. Specifically, the signal output microstrip line 110, the grounding metal plating layer 140, the microstrip line transition section 111, the P-electrode connection portion 112 and the two N-electrode transmission lines 120 regions are first defined on the first metal plating layer by photolithography, and the pattern preparation of the above-mentioned devices in the metal region is completed by combining ICP dry etching and wet etching; wherein, the size of the signal output microstrip line 110 is 1.15mm×0.4mm; the size of the grounding metal plating layer 140 is 1mm×0.3mm; the size of the two N-electrode transmission lines 120 is 0.3mm×0.06mm. Then, a photolithography process is used to define a resistor region on the second metal plating layer, and a pattern preparation of a sampling resistor 130 in the resistor region is completed by combining ICP dry etching and wet etching. The size of the sampling resistor 130 is 0.15 mm×0.3 mm.

[0050] S6, heat-treating the ceramic substrate 1 with the pattern formed thereon, and performing an L-shaped cut on the sampling resistor 130, adjusting its resistance to 50Ω, and then heat-treating it again. This step may specifically include the following sub-steps:

[0051] S61, heat-treating the ceramic substrate 1 with the pattern formed thereon at 250-350°C for 1.5-2.5 hours; preferably, heat-treating the ceramic substrate 1 at 300°C for 2 hours.

[0052] S62, heat-treating the ceramic substrate 1 at 130-170°C for 20-28 hours, preferably at 150°C for 24 hours. The film layer (ie, metal coating) of the ceramic substrate 1 is solidified by two heat treatments to keep the film layer stable.

[0053] S63 , using a laser to perform L-shaped cutting on the sampling resistor 130 of the heat-treated ceramic substrate 1 , so as to adjust its resistance value according to the required target resistance value (ie 50Ω) and accuracy.

[0054] S64, heat-treating the ceramic substrate 1 after resistance adjustment at 130-170° C. for 20-28 hours; preferably, heat-treating at 150° C. for 24 hours.

[0055] S7. Form flip-chip gold pillars at the P-electrode connection portion 112 and the two N-electrode transmission lines 120 respectively by electroplating. Preferably, a first flip-chip gold pillar 151 is formed at the P-electrode connection portion 112, and a second flip-chip gold pillar 152 is formed at the two N-electrode transmission lines 120 respectively. To facilitate the fixing of the high-speed photodiode chip, the front side 100 may also form a third flip-chip gold pillar 153 by electroplating, preferably forming two third flip-chip gold pillars 153, and the size and material of the third flip-chip gold pillar 153 are the same as those of the first flip-chip gold pillar 151. The sizes of the first flip-chip gold pillar 151, the second flip-chip gold pillar 152 and the third flip-chip gold pillar 153 are all the same, and the size of the flip-chip gold pillar is calculated by the CPW (coplanar waveguide) model according to the pad size of the high-speed photodiode chip and the chip output bandwidth; for example, in this embodiment, the diameter of the flip-chip gold pillar is calculated to be 50 μm and the height is 10 to 15 μm.

[0056] S8, the ceramic substrate 1 is divided into independent units by grinding wheel scribing. After that, the high-speed photodiode chip can be soldered on the ceramic substrate 1 of the independent unit by flip-chip soldering, so that the first flip-chip gold pillar 151 is connected to the P electrode of the high-speed photodiode chip, and the two second flip-chip gold pillars 152 are connected to the N electrode of the high-speed photodiode chip.

[0057] like Figure 6 and Figure 7 As shown, before manufacturing, the size of each component of the ceramic substrate circuit can also be determined by simulation, specifically: first simulate the detector assembly equivalent circuit through ADS to establish a circuit model of the ceramic substrate 1; the simulation equivalent circuit schematic diagram of the high-bandwidth impedance matching integrated ceramic substrate circuit is shown in Figure 6 Then, the S parameter model of the high-speed photodiode chip is established through MATLB, and it is combined with the circuit model for simulation; the simulation S parameter output result of the high-bandwidth impedance matching integrated ceramic substrate circuit is shown in the figure below. Figure 7 Then, the microstrip structure of the circuit model is designed through XLINE, and the circuit structure simulation design is performed through ADS; when the simulation results show that the 3dB bandwidth reaches 36.95GHz and the RF reflection loss within 30GHz reaches -8.366dB, the design circuit corresponding to the simulation results is used as the ceramic substrate circuit determined by the layout design.

[0058] In this embodiment, the size of the flip-chip gold pillar is calculated by the CPW model according to the size of the high-speed photodiode chip and the chip output bandwidth; the resistance value of the sampling resistor is determined according to the impedance matching principle (i.e., 50Ω); the width and length of the microstrip line are calculated by the microstrip line model according to the dielectric constant of the alumina substrate and the surface coating and the thickness of the substrate; the microstrip line transmission is highly matched with the high-speed photodiode chip and the transmission loss is small, so that the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz, and the RF reflection loss within 30GHz can reach -8.366dB.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A high bandwidth impedance matching integrated ceramic substrate circuit, characterized in that: The invention comprises a ceramic substrate, wherein the ceramic substrate is provided with a front side and a back side opposite to the front side; the front side is provided with a signal output microstrip line, a ground metal plating layer, a microstrip line transition section, a P electrode connection part and two N electrode transmission lines formed by a first metal plating layer, and a sampling resistor of a matching network formed by a second metal plating layer; the first metal plating layer comprises a tungsten-titanium alloy layer arranged on the ceramic substrate, a platinum layer arranged on the tungsten-titanium alloy layer, and a first gold layer arranged on the platinum layer, wherein the thickness of the tungsten-titanium alloy layer is 0.1 μm; the thickness of the platinum layer is 0.2 μm; the thickness of the first gold layer is 3.0 to 3.5 μm; the second metal plating layer is a tantalum nitride layer; the size of the tantalum nitride layer is 0. 15mm×0.3mm, with a resistance of 50Ω; one end of the signal output microstrip line is connected to the P electrode connecting part through a trapezoidal microstrip line transition section, the two N electrode transmission lines are symmetrically arranged on both sides of the P electrode connecting part, the P electrode connecting part is provided with a first flip-chip gold column, and the two N electrode transmission lines are respectively provided with a second flip-chip gold column; one side of the signal output microstrip line is connected to the sampling resistor, the sampling resistor is connected to the grounding metal plating, the middle part of the grounding metal plating is provided with a grounding through hole that penetrates to the back side, the back side of the ceramic substrate is covered with a second gold layer, the second gold layer is used for grounding, and the hole wall of the grounding through hole is covered with a third gold layer connecting the grounding metal plating layer and the second gold layer.

2. The high bandwidth impedance matching integrated ceramic substrate circuit according to claim 1, characterized in that: The size of the signal output microstrip line is 1.15 mm×0.4 mm; the size of the grounding metal plating layer is 1 mm×0.3 mm; the size of the two N-electrode transmission lines is 0.3 mm×0.06 mm.

3. The high bandwidth impedance matching integrated ceramic substrate circuit according to claim 1, characterized in that: The front side is provided with a third flip-chip gold column, and the third flip-chip gold column is used for chip fixing.

4. The high bandwidth impedance matching integrated ceramic substrate circuit according to claim 3, characterized in that: The number of the grounding through holes is two, and the radius is 0.1 mm.

5. A method for manufacturing a high-bandwidth impedance matching integrated ceramic substrate circuit, used to manufacture the high-bandwidth impedance matching integrated ceramic substrate circuit as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: S1. Grinding, cleaning and drying the ceramic substrate; S2, forming a tantalum nitride layer in the resistance region on the front side of the ceramic substrate, forming a tungsten-titanium alloy layer in the metal region, and forming a platinum layer on the tungsten-titanium alloy layer; S3, forming a first gold layer on the platinum layer by an electroplating process; S4, opening a grounding through hole penetrating the front and back sides of the ceramic substrate in the grounding metal plating layer, and forming a second gold layer on the back side of the ceramic substrate by an electroplating process, and forming a third gold layer on the hole wall of the grounding through hole; S5, using photolithography and etching processes to complete the pattern preparation of the signal output microstrip line, the ground metal plating layer, the microstrip line transition section, the P electrode connection part, the two N electrode transmission lines and the sampling resistor of the matching network; S6, heat-treating the ceramic substrate, cutting the sampling resistor into an L shape, adjusting its resistance to 50Ω, and then heat-treating it again; S7, forming flip-chip gold pillars at the P-electrode connection portion and the two N-electrode transmission lines respectively by electroplating process; S8. Divide the ceramic substrate into independent units by dicing.

6. The method for manufacturing a high-bandwidth impedance matching integrated ceramic substrate circuit according to claim 5, characterized in that: The thickness of the second gold layer and the third gold layer is 1.5-2.0 μm.

7. The method for manufacturing a high-bandwidth impedance matching integrated ceramic substrate circuit according to claim 5, characterized in that: The step S6 specifically includes the following sub-steps: S61, heat treating the ceramic substrate with the pattern formed thereon at 250-350° C. for 1.5-2.5 hours; S62, heat treating the ceramic substrate at 130-170° C. for 20-28 hours; S63, using a laser to perform L-shaped cutting on the sampling resistor, and adjusting its resistance value according to the required target resistance value and accuracy; S64, heat-treating the ceramic substrate after resistance adjustment at 130-170° C. for 20-28 hours.

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