Semiconductor device

Abstract

A semiconductor device includes a memory element disposed on a substrate, wherein the memory element includes a tapered upper end structure, wherein the tapered upper end structure includes a top electrode layer and a spacer surrounding the top electrode layer, a gap fill dielectric layer disposed around the spacer, a conductive cap layer covering the top electrode layer and the spacer, an intermetal dielectric layer on the conductive cap layer, and a metal interconnect disposed in the intermetal dielectric layer and electrically connected to the top electrode layer through the conductive cap layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device, and more particularly to a magnetic random access memory (MRAM) element and a method of fabricating the same. BACKGROUND

[0002] A magnetic random access memory (MRAM) element is considered as a next generation memory technology due to its fast read / write speed, non-volatility, and easy integration with semiconductor fabrication processes.

[0003] Figure 1 A cross-sectional view of a magnetic memory element fabricated according to the prior art. As shown in FIG. 1, a substrate 100P is provided with a storage element MC in a storage cell region CR and a logic element LE in a logic region LR. The storage element MC is formed by a tunneling dielectric layer 110P, a ferromagnetic layer 120P, a barrier layer 122P, a ferromagnetic layer 124P, and a top electrode layer TE. The logic element LE is formed by a tunneling dielectric layer 116P, a ferromagnetic layer 126P, a barrier layer 128P, a ferromagnetic layer 130P, and a top electrode layer TE. Figure 1 After the fabrication of the storage element MC in the storage cell region CR is completed, a super low-k dielectric layer 130P is formed over the substrate 100P, and then planarized. A doped nitrogen carbon silicon layer 134P and a super low-k dielectric layer 140P are sequentially deposited. A metallization process is then performed in the super low-k dielectric layer 140P and the doped nitrogen carbon silicon layer 134P to form interconnects IM and vias VM in the storage cell region CR, and interconnects IL and vias VL in the logic region LR.

[0004] However, in the formation of the via VM in the storage cell region CR, the super low-k dielectric layer 130P over the doped nitrogen carbon silicon layer 134P and the storage element MC has to be etched through before the via VM can be electrically connected to the top electrode layer TE of the storage element MC. After the doped nitrogen carbon silicon layer 134P is etched through, the etching rate will suddenly increase, resulting in a negative slope profile NSP on the sidewall of the via VM. This will cause poor coverage and even defects such as Cu voids when a Ta / TaN barrier layer is subsequently deposited. In addition, in the planarization of the super low-k dielectric layer 130P, a predetermined thickness (e.g. about 300 angstroms) of the super low-k dielectric layer 130P has to be left over the storage element MC, which makes the chemical mechanical polishing process difficult to control.

[0005] Therefore, there is a need for an improved magnetic random access memory element and a method of fabricating the same to overcome the above problems and drawbacks of the prior art. SUMMARY

[0006] The main object of the present invention is to provide an improved semiconductor device and a method of fabricating the same to overcome the above problems and drawbacks of the prior art.

[0007] One aspect of the present application provides a semiconductor device comprising a memory element disposed on a substrate, wherein the memory element comprises a tapered upper end structure, wherein the tapered upper end structure comprises a top electrode layer and a spacer surrounding the top electrode layer; a gap fill dielectric layer disposed around the spacer; a conductive cap layer covering the top electrode layer and the spacer; an intermetallic dielectric layer on the conductive cap layer; and a metal interconnect disposed in the intermetallic dielectric layer and electrically connected to the top electrode layer through the conductive cap layer.

[0008] According to an embodiment of the present application, the memory element comprises a magnetic tunnel junction structure under the top electrode layer.

[0009] According to an embodiment of the present application, the magnetic tunnel junction structure comprises a magnetic reference layer on a bottom electrode layer, a tunneling layer on the magnetic reference layer, a magnetic free layer on the tunneling layer, and an upper cap layer on the magnetic free layer.

[0010] According to an embodiment of the present application, the top electrode layer comprises tantalum.

[0011] According to an embodiment of the present application, the spacer directly contacts a sidewall of the top electrode layer.

[0012] According to an embodiment of the present application, the spacer comprises silicon nitride.

[0013] According to an embodiment of the present application, the gap fill dielectric layer comprises a silicon oxide layer.

[0014] According to an embodiment of the present application, the gap fill dielectric layer comprises a recessed top surface, a lowest point of the recessed top surface being lower than a bottom surface of the top electrode layer.

[0015] According to an embodiment of the present application, the conductive cap layer comprises titanium, titanium nitride, tantalum, or tantalum nitride.

[0016] According to an embodiment of the present application, the conductive cap layer directly contacts the top electrode layer and the spacer.

[0017] According to an embodiment of the present application, the metal interconnect comprises a copper damascene structure.

[0018] According to an embodiment of the present application, the metal interconnect comprises a downwardly directed toothed structure surrounding the top electrode layer and the spacer.

[0019] Another aspect of the present application provides a semiconductor device, comprising a substrate comprising a memory cell region and a logic region thereon; a first intermetallic dielectric layer disposed on the substrate and covering the memory cell region and the logic region; a memory element disposed on the first intermetallic dielectric layer within the memory cell region, wherein the memory element comprises a tapered upper end structure, wherein the tapered upper end structure comprises a top electrode layer and a spacer around the top electrode; a gap fill dielectric layer disposed around the spacer; a conductive cap layer covering the top electrode layer and the spacer, wherein the conductive cap layer extends to a sidewall surface of the gap fill dielectric layer at an interface between the memory cell region and the logic region; a second intermetallic dielectric layer disposed on the conductive cap layer and the first intermetallic dielectric layer; and a metal interconnect disposed in the second intermetallic dielectric layer and electrically connected to the top electrode layer through the conductive cap layer.

[0020] According to an embodiment of the present application, the conductive cap layer does not cover an upper surface of the first intermetallic dielectric layer within the logic region.

[0021] According to an embodiment of the present application, the conductive cap layer comprises titanium, titanium nitride, tantalum or tantalum nitride.

[0022] According to an embodiment of the present application, the conductive cap layer directly contacts the top electrode layer and the spacer.

[0023] According to an embodiment of the present application, the metal interconnect comprises a copper damascene structure.

[0024] According to an embodiment of the present application, the metal interconnect comprises a downwardly extending tooth-like structure around the top electrode layer and the spacer.

[0025] According to an embodiment of the present application, the memory element comprises a magnetic tunnel junction structure below the top electrode layer.

[0026] According to an embodiment of the present application, the magnetic tunnel junction structure comprises a magnetic reference layer on a bottom electrode layer, a tunneling layer on the magnetic reference layer, a magnetic free layer on the tunneling layer, and an upper cap layer on the magnetic free layer. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A cross-sectional schematic view of a magnetic memory structure made by the prior art;

[0028] Figures 2 to 1 IB A schematic view of a method of making a semiconductor device according to an embodiment of the present application, wherein, Figure 2 An upper perspective view of a semiconductor device after forming a magnetic tunnel junction structure and a full silicon nitride cap layer is shown,Figures 3 to 6 Fig. 1 is a schematic cross-sectional view along the tangent I-I' of a semiconductor device in accordance with the present application, Figure 2 Fig. 2 is a schematic cross-sectional view along the tangent I-I' of a semiconductor device in accordance with the present application, Figure 7 Fig. 3 is a top view of a semiconductor device after forming a patterned photoresist on a conductive cap layer, Figure 7A Fig. 4 is a schematic cross-sectional view along the tangent I-I' of a semiconductor device in accordance with the present application, 8A Fig. 5 is a schematic cross-sectional view along the tangent II-II' of a semiconductor device in accordance with the present application, Figure 7 Fig. 6 is a schematic cross-sectional view along the tangent I-I' of a semiconductor device in accordance with the present application, Figure 7B Fig. 7 is a schematic cross-sectional view along the tangent II-II' of a semiconductor device in accordance with the present application, 8B Fig. 8 is a schematic cross-sectional view along the tangent I-I' of a semiconductor device in accordance with the present application, Figure 7 Fig. 9 is a schematic cross-sectional view along the tangent II-II' of a semiconductor device in accordance with the present application.

[0029] Explanation of main element symbols

[0030] 100, 100P substrate

[0031] 102 dielectric layer

[0032] 102MC, 102ML lower metal interconnect

[0033] 104, 134, 134P, 144 doped nitrogen silicon carbide layer

[0034] 106, 130, 140 intermetal dielectric layer

[0035] 106a upper surface

[0036] 108 silicon nitride cap layer

[0037] 108S spacer

[0038] 110 gap fill dielectric layer

[0039] 110a top surface

[0040] 110b sidewall surface

[0041] 120 conductive cap layer

[0042] 120P patterned conductive cap layer

[0043] 130P, 140P ultra low dielectric constant dielectric layer

[0044] 130MC, 130MC1, 130MC2, 130ML, 140MC, 140MC1, 140MC2, 140ML metal interconnect

[0045] 130MI, 130MT tooth-like structure

[0046] 130VL, 140VC1, 140VC2, 140VL conductive via

[0047] BE bottom electrode layer

[0048] CA cap layer

[0049] CR cell region

[0050] GP gap

[0051] LR logic region

[0052] M2 second metal interconnect layer

[0053] M3 third metal interconnect layer

[0054] M4 fourth metal interconnect layer

[0055] MC memory element

[0056] MF magnetic free layer

[0057] MR magnetic reference layer

[0058] MTJ magnetic tunnel junction structure

[0059] NSP negative slope profile

[0060] IM lead

[0061] IL lead

[0062] OP opening

[0063] PR patterned photoresist

[0064] R recessed trench

[0065] S1 upper surface

[0066] S2 sloped surface

[0067] S3 top surface

[0068] S4 sidewall

[0069] S5 bottom surface

[0070] t thickness

[0071] TB tunneling layer

[0072] TE top electrode layer

[0073] V2 second via

[0074] V3 third via

[0075] VM via

[0076] VL via

[0077] WV tungsten plug Detailed Implementation

[0078] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0079] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0080] Please see Figures 2 to 1 1, is a schematic diagram illustrating a method for manufacturing a semiconductor device 1 according to an embodiment of the present invention, wherein, Figure 2 This is an example of a top perspective view of a semiconductor device 1 after a magnetic tunneling junction (MTJ) structure has been formed and fully covered by a silicon nitride capping layer. Figures 3 to 6 for Figure 2 A schematic cross-sectional view taken along the tangent line I-I'. Figure 7 This is an example of a top view of a semiconductor device 1 after a patterned photoresist has been formed on a conductive capping layer. Figure 7A , 8A 9A, 10A, and 11A are along Figure 7 A schematic diagram of the cross section viewed from the mid-tangent line I-I'. Figure 7B , 8B 9B, 10B, and 11B are along Figure 7 A schematic diagram of the cross section viewed from the mid-tangent II-II'.

[0081] like Figures 2 to 1 and Figure 3 As shown, a memory cell region CR and a logic region LR are included on the substrate 100. Multiple memory elements MC are formed in the memory cell region CR and arranged in an array. For simplicity, in... Figure 2Only a 2x2 array is shown. According to an embodiment of the application, the substrate 100 can comprise a silicon substrate, but is not limited thereto. At least one dielectric layer 102, such as an ultra-low k (ULK) dielectric layer, for example, having a k value less than 2.8, is formed on the substrate 100. A nitrogen-doped carbide (NDC) layer 104 and an intermetallic dielectric layer 106, such as a silicon oxide layer, are provided on the dielectric layer 102, covering the memory cell region CR and the logic region LR. In the dielectric layer 102 within the memory cell region CR and the logic region LR, lower metal interconnects 102MC and 102ML are provided, respectively. According to an embodiment of the application, the lower metal interconnects 102MC and 102ML can be in the second layer metal interconnect layer M2, but are not limited thereto.

[0082] According to an embodiment of the application, each memory element MC in the memory cell region CR is disposed on the intermetallic dielectric layer 106 and is electrically connected to the lower metal interconnect 102MC through a tungsten via Wv formed in the intermetallic dielectric layer 106 and the nitrogen-doped carbide layer 104.

[0083] According to an embodiment of the application, each memory element MC can comprise a bottom electrode layer BE disposed on the tungsten via Wv, a magnetic tunnel junction structure MTJ disposed on the bottom electrode BE, and a top electrode layer TE disposed on the magnetic tunnel junction structure MTJ, for example. According to an embodiment of the application, the magnetic tunnel junction structure MTJ can comprise a magnetic reference layer MR disposed on the bottom electrode layer BE, a tunnel barrier layer TB disposed on the magnetic reference layer MR, a magnetic free layer MF disposed on the tunnel barrier layer TB, and a cap layer CA disposed on the magnetic free layer MF, but is not limited thereto.

[0084] According to an embodiment of the application, the magnetic reference layer MR, the tunnel barrier layer TB, the magnetic free layer MF, and the cap layer CA can be any suitable material known in the art and can be single or multiple layers. For example, the magnetic reference layer MR can comprise a PtMn antiferromagnetic layer and one or more magnetic material layers of CoFe, NiFe, CoFeB, Ru, or other materials or combinations thereof disposed on the antiferromagnetic layer, but is not limited thereto. The magnetic free layer MF can comprise one or more magnetic material layers that can include CoFe, NiFe, CoFeB, other magnetic material layers, or combinations thereof. The tunnel barrier layer TB can comprise a thin insulator such as AI2O3 or a semiconductor material.

[0085] According to embodiments of the present invention, for example, the bottom electrode layer BE may comprise a tantalum nitride (TaN) layer. According to embodiments of the present invention, for example, the thickness of the bottom electrode layer BE may be between 100 and 200 angstroms, for example, approximately 170 angstroms, but is not limited thereto. According to one embodiment, for example, the top electrode layer TE may comprise a tantalum (Ta) layer with a thickness of approximately 600 angstroms, but is not limited thereto.

[0086] According to an embodiment of the present invention, the memory element MC is fabricated using an ion beam etching (IBE) process. After completing the IBE process, the memory element MC may include a tapered upper structure; for example, the top electrode layer TE may include a flat upper surface S1 and a surrounding sloping surface S2. Next, a chemical vapor deposition (CVD) process can be performed to deposit a silicon nitride capping layer 108 over the entire substrate 100.

[0087] like Figure 4 As shown, an anisotropic dry etching process is then performed to etch the silicon nitride capping layer 108 until the intermetallic dielectric layer 106 is exposed, thus forming a spacer wall 108S covering the sidewalls of the memory element MC. According to an embodiment of the invention, the spacer wall 108S surrounds the top electrode layer TE. According to an embodiment of the invention, the spacer wall 108S directly contacts one sidewall of the top electrode layer TE. The tapered upper structure of the memory element MC may include the spacer wall 108S.

[0088] According to an embodiment of the present invention, the spacer wall 108S has an inclined top surface S3 that connects upwardly to the inclined surface S2 of the top electrode layer TE. According to an embodiment of the present invention, the inclined top surface S3 of the spacer wall 108S is lower than the inclined surface S2 of the top electrode layer TE. According to an embodiment of the present invention, the spacer wall 108S includes a nearly vertical sidewall S4 located between the inclined top surface S3 and the upper surface 106a of the intermetallic dielectric layer 106. According to an embodiment of the present invention, a gap GP is located between the sidewall S4 and the upper surface 106a of the intermetallic dielectric layer 106.

[0089] like Figure 5As shown, another chemical vapor deposition process is then performed to deposit a gap-filling dielectric layer 110, such as a silicon oxide layer, but not limited to it, over the substrate 100. Then, an etch-back process can be performed to etch the gap-filling dielectric layer 110 until the flat upper surface S1 and inclined surface S2 of the top electrode layer TE, and the inclined top surface S3 of the gap wall 108S, are exposed, and the upper surface 106a of the intermetallic dielectric layer 106 within the logic region LR is exposed. After completing the etch-back process, the remaining gap-filling dielectric layer 110 fills the gap GP between the sidewall S4 and the upper surface 106a of the intermetallic dielectric layer 106. According to an embodiment of the invention, at this point, the gap-filling dielectric layer 110 includes a recessed top surface 110a, wherein the lowest point of the recessed top surface 110a is lower than a bottom surface S5 of the top electrode layer TE (or the interface between the top electrode layer TE and the capping layer CA).

[0090] like Figure 6 As shown, a conductive capping layer 120 is then deposited across the entire surface. For example, the conductive capping layer 120 may comprise titanium, titanium nitride, tantalum, or tantalum nitride, but is not limited thereto. According to an embodiment of the invention, the conductive capping layer 120 covers and directly contacts the flat upper surface S1 and inclined surface S2 of the exposed top electrode layer TE, the inclined top surface S3 of the spacer wall 108S, the recessed top surface 110a of the gap-filling dielectric layer 110, and the upper surface 106a of the intermetallic dielectric layer 106 within the logic region LR. According to an embodiment of the invention, the conductive capping layer 120 covers and directly contacts one sidewall surface 110b of the gap-filling dielectric layer 110 at the interface between the memory cell region CR and the logic region LR.

[0091] like Figure 7 , Figure 7A and Figure 7B As shown, a patterned photoresist PR is then formed on the conductive capping layer 120. According to an embodiment of the invention, the patterned photoresist PR covers each row of memory elements MC in the X direction. According to an embodiment of the invention, the patterned photoresist PR has an opening OP extending along the X direction. According to an embodiment of the invention, the patterned photoresist PR does not cover the conductive capping layer 120 within the logic region LR.

[0092] like Figure 8A and Figure 8BAs shown, an etching process is then performed to remove the conductive capping layer 120 that is not covered by the patterned photoresist PR. According to an embodiment of the invention, the etching process may include an anisotropic dry etching process, but is not limited thereto. According to an embodiment of the invention, the conductive capping layer 120 and a portion of the intermetallic dielectric layer 106 within the logic region LR can be removed. According to an embodiment of the invention, within the memory cell region CR, a portion of the gap-filling dielectric layer 110 can be removed to form a recessed trench R, thereby forming a patterned conductive capping layer 120P.

[0093] like Figure 9A and Figure 9B As shown, the remaining patterned photoresist PR is then removed. Next, a chemical vapor deposition process is performed to deposit an intermetallic dielectric layer 130 over the substrate 100. According to an embodiment of the invention, the intermetallic dielectric layer 130 may be an ultra-low dielectric constant (ULK) dielectric layer. According to an embodiment of the invention, the intermetallic dielectric layer 130 covers and directly contacts the patterned conductive capping layer 120P, fills the gaps between the patterned conductive capping layers 120P with dielectric layer 110, and the intermetallic dielectric layer 106 within the logic region LR. According to an embodiment of the invention, the intermetallic dielectric layer 130 fills the recessed trench R. According to an embodiment of the invention, the thickness t of the intermetallic dielectric layer 130 directly above the patterned conductive capping layer 120P may be approximately 2000–5000 angstroms. Subsequently, a planarization process can be performed on the intermetallic dielectric layer 130.

[0094] like Figure 10A and Figure 10B As shown, a metallization process is then performed to form metal interconnects 130MC and 130ML in the intermetallic dielectric layer 130. Metal interconnects 130MC and 130ML may be located in the third metal interconnect layer M3, but are not limited thereto. Metal interconnect 130MC is formed within the memory cell region CR and is electrically connected to the top electrode layer TE of each memory element MC via a patterned conductive capping layer 120P. Figure 10A and Figure 10B As can be seen, the metal interconnect 130MC comprises multiple parallel metal interconnects 130MC1 and 130MC2, extending along the X direction. Within the logic region LR, the metal interconnect 130ML is electrically connected to the underlying metal interconnect 102ML via a conductive via 130VL. The conductive via 130VL can be a second-layer via V2 belonging to the metal interconnect structure.

[0095] According to an embodiment of the present application, the metal interconnects 130MC and 130ML comprise a copper damascene structure. In addition, the metal interconnect 130MC comprises a downward tooth-like structure 130MT surrounding the top electrode layer TE and the spacer 108S. The downward tooth-like structure 130MI can also be observed at the junction of the memory cell region CR and the logic region LR. After the metal interconnects 130MC and 130ML are completed, a doped nitrogen silicon carbide layer 134 can be deposited on the metal interconnects 130MC and 130ML and the intermetal dielectric layer 130.

[0096] As shown in FIG. 13, a metal interconnect 140MC and a metal interconnect 140ML can be formed in the intermetal dielectric layer 140. According to an embodiment of the present application, the metal interconnect 140MC and the metal interconnect 140ML can be formed in the fourth metal interconnect layer M4, but are not limited to this. Figure 11A Figure 11B As shown in FIG. 13, a metal interconnect 140MC and a metal interconnect 140ML can be formed in the intermetal dielectric layer 140. According to an embodiment of the present application, the metal interconnect 140MC and the metal interconnect 140ML can be formed in the fourth metal interconnect layer M4, but are not limited to this. Figure 11A Figure 11B As shown in FIG. 13, a metal interconnect 140MC and a metal interconnect 140ML can be formed in the intermetal dielectric layer 140. According to an embodiment of the present application, the metal interconnect 140MC and the metal interconnect 140ML can be formed in the fourth metal interconnect layer M4, but are not limited to this.

[0097] The advantages of the present application include at least: (1) avoiding the control problem in planarizing the ultra low dielectric constant layer; and (2) introducing the conductive cap layer and forming the metal interconnects 130MC and 130ML in the intermetal dielectric layer 130, which can avoid the problem of negative slope profile on the via sidewall in the past via formation and the occurrence of copper hole and other defects.

[0098] The above description is only preferred embodiments of the present application. Any equivalent changes and modifications made according to the claims of the present application should be covered by the scope of the present application.​​

Claims

1. A semiconductor device, characterized by comprising: A memory element disposed on a substrate, wherein the memory element comprises a tapered upper end structure, wherein the tapered upper end structure comprises a top electrode layer and a spacer around the top electrode layer; A gap fill dielectric layer disposed around the spacer; A conductive cap layer covering the top electrode layer and the spacer, the conductive cap layer extending to a sidewall surface of the gap fill dielectric layer at an interface between a memory cell region and a logic region; An intermetal dielectric layer on the conductive cap layer; and A metal interconnect disposed in the intermetal dielectric layer and electrically connected to the top electrode layer through the conductive cap layer. The memory element comprises a magnetic tunnel junction structure under the top electrode layer.

2. The semiconductor device according to claim 1, wherein The magnetic tunnel junction structure comprises a magnetic reference layer on a bottom electrode layer, a tunneling layer on the magnetic reference layer, a magnetic free layer on the tunneling layer, and an upper cap layer on the magnetic free layer.

3. The semiconductor device according to claim 2, wherein The top electrode layer comprises tantalum.

4. The semiconductor device according to claim 1, wherein The spacer directly contacts a sidewall of the top electrode layer.

5. The semiconductor device according to claim 1, wherein The spacer comprises silicon nitride.

6. The semiconductor device according to claim 1, wherein The gap fill dielectric layer comprises a silicon oxide layer.

7. The semiconductor device according to claim 1, wherein The gap fill dielectric layer comprises a recessed top surface with a lowest point lower than a bottom surface of the top electrode layer.

8. The semiconductor device according to claim 1, wherein The conductive cap layer comprises titanium, titanium nitride, tantalum, or tantalum nitride.

9. The semiconductor device according to claim 1, wherein The conductive cap layer directly contacts the top electrode layer and the spacer.

10. The semiconductor device according to claim 1, wherein The metal interconnect comprises a copper damascene structure.

11. The semiconductor device according to claim 1, wherein The metal interconnect comprises a downwardly-directed toothed structure around the top electrode layer and the spacer.

12. The semiconductor device according to claim 1, wherein A substrate comprising a memory cell region and a logic region; 13. A semiconductor device, characterized by comprising: A first intermetal dielectric layer disposed on the substrate and covering the memory cell region and the logic region; A memory element disposed on the first intermetal dielectric layer within the memory cell region, wherein the memory element comprises a tapered upper end structure, wherein the tapered upper end structure comprises a top electrode layer and a spacer around the top electrode; A gap fill dielectric layer disposed around the spacer; A conductive cap layer covering the top electrode layer and the spacer, wherein the conductive cap layer extends to a sidewall surface of the gap fill dielectric layer at an interface between the memory cell region and the logic region; A second intermetal dielectric layer disposed on the conductive cap layer and the first intermetal dielectric layer; and A metal interconnect disposed in the second intermetal dielectric layer and electrically connected to the top electrode layer through the conductive cap layer. The conductive cap layer does not cover an upper surface of the first intermetal dielectric layer within the logic region. The conductive cap layer comprises titanium, titanium nitride, tantalum, or tantalum nitride.

14. The semiconductor device according to claim 13, wherein The conductive cap layer directly contacts the top electrode layer and the spacer.

15. The semiconductor device according to claim 13, wherein The metal interconnect comprises a copper damascene structure.

16. The semiconductor device according to claim 13, wherein The metal interconnect comprises a downwardly-directed toothed structure around the top electrode layer and the spacer.

17. The semiconductor device according to claim 13, wherein The memory element comprises a magnetic tunnel junction structure under the top electrode layer.

18. The semiconductor device according to claim 13, wherein ​ 19. The semiconductor device according to claim 13, wherein ​ 20. The semiconductor device according to claim 19, wherein The magnetic tunnel junction structure includes a magnetic reference layer on a bottom electrode layer, a tunneling layer on the magnetic reference layer, a magnetic free layer on the tunneling layer, and a cap layer on the magnetic free layer.

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