Semiconductor test structure

Abstract

The utility model provides a semiconductor test structure, comprising at least two first active regions located in a substrate; the at least one first gate structure extends from the at least two first active regions to the substrate at the peripheries of the first active regions; in a plurality of intersecting regions of at least one first gate structure and the two first active regions, the first gate structure in one intersecting region is a first gate of a pull-down transistor to be tested, and the first active regions on the two sides of the first gate are a first source / drain region and a second source / drain region of the pull-down transistor to be tested respectively; the first gate structures in other intersection areas are second gates of at least one auxiliary pull-down transistor; the first metal interconnection structure is electrically connected with the first source / drain region, the second metal interconnection structure is electrically connected with the second source / drain region, and the third metal interconnection structure is electrically connected with the first grid electrode and the second grid electrode. According to the utility model, the test result of the grid inversion leakage current of the pull-down transistor to be tested is more accurate.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field, especially relates to a semiconductor test structure. BACKGROUND

[0002] The leakage of pull down transistor (PD) in static random-access memory (SRAM) generally includes four-terminal leakage (corresponding to drain off leakage current Idoff, source off leakage current Isoff, gate off leakage current Igoff and body off leakage current Iboff) and gate inversion leakage (corresponding to gate inversion leakage current Iginv). Wherein, the gate inversion leakage current is generally small, and it will be affected by machine test precision, process local variation and layout design, resulting in inaccurate test of the gate inversion leakage current;Especially for low leakage devices, it requires smaller leakage and more accurate test of the gate inversion leakage current.

[0003] Therefore, how to make the test result of the gate inversion leakage current accurate is a technical problem to be solved. UTILITY MODEL CONTENT

[0004] The utility model discloses a semiconductor test structure, make the test result of the gate inversion leakage current of pull down transistor to be measured more accurate.

[0005] To achieve the above object, the utility model provides a semiconductor test structure, comprising:

[0006] Substrate;

[0007] At least two first active regions are located in the substrate, and the at least two first active regions extend in a first direction and are arranged at intervals in a second direction;

[0008] At least one first gate structure extends from the at least two first active regions to the substrate outside the first active region, and the at least one first gate structure extends in the second direction, and the first direction is different from the second direction;In the multiple intersection regions of the at least one first gate structure and the at least two first active regions, the first gate structure of one of the intersection regions is the first gate of a pull down transistor to be measured, and the first active regions on both sides of the first gate are the first source / drain region and the second source / drain region of the pull down transistor to be measured respectively, and the first gate structure of other intersection regions is the second gate of at least one auxiliary pull down transistor;

[0009] a first metal interconnect structure electrically connected to the first source / drain region, a second metal interconnect structure electrically connected to the second source / drain region, and a third metal interconnect structure electrically connected to the first gate and the second gate of the at least one auxiliary pull-down transistor.

[0010] Optionally, the first direction is perpendicular to the second direction.

[0011] Optionally, the first metal interconnect structure, the second metal interconnect structure and the third metal interconnect structure each comprise a contact plug, at least one metal interconnect layer, at least one via plug and a pad, the bottommost metal interconnect layer is electrically connected to the first source / drain region, the second source / drain region and the first gate and the second gate of the at least one auxiliary pull-down transistor through the contact plug respectively, the metal interconnect layers of adjacent layers are electrically connected through the via plug, and the topmost metal interconnect layer is electrically connected to the pad through the via plug.

[0012] Optionally, when the first gate and at least one second gate are located on the same first gate structure, the first gate and at least one second gate are electrically connected to the same bottommost metal interconnect layer through the same contact plug; and / or, when the first gate and at least one second gate are located on different first gate structures, the first gate and at least one second gate are electrically connected to the same bottommost metal interconnect layer through different contact plugs.

[0013] Optionally, the semiconductor test structure further comprises:

[0014] at least one second active region located in the substrate outside the at least two first active regions, the at least one second active region extending in the first direction; the at least one first gate structure further extends to the at least one second active region, and the first gate structure at the intersection region of the at least one first gate structure and the at least one second active region is a third gate of at least one dummy transistor.

[0015] Optionally, the semiconductor test structure further comprises:

[0016] a gate cutting structure located in the at least one first gate structure between the at least two first active regions and the at least one second active region, so that the pull-down transistor to be tested and the at least one auxiliary pull-down transistor are isolated from the at least one dummy transistor by the gate cutting structure.

[0017] Optionally, the semiconductor test structure further comprises:

[0018] at least one second gate structure extending from the at least two first active regions outside the at least one first gate structure to the at least one second active region and to the substrate outside the first and second active regions, the at least one second gate structure extending in the second direction; the second gate structure at the intersection of the at least one second gate structure and the at least two first active regions and at the intersection of the at least one second gate structure and the at least one second active region being a third gate of at least one dummy transistor.

[0019] Optionally, the dummy transistor is a pass transistor, a pull-up transistor or a pull-down transistor.

[0020] Optionally, the semiconductor test structure further comprises:

[0021] a body region extending from the top surface of the substrate into the substrate, the at least two first active regions and the at least one second active region being located in the body region;

[0022] a body contact region located in the body region outside the at least two first active regions and the at least one second active region;

[0023] a fourth metal interconnect structure electrically connected to the body contact region.

[0024] Optionally, the semiconductor test structure further comprises:

[0025] a shallow trench isolation structure located in the substrate outside the first and second active regions.

[0026] Compared with the prior art, the semiconductor test structure has the following advantages: in the plurality of intersection regions of the at least one first gate structure and the at least two first active regions, the first gate structure of one of the intersection regions is the first gate of the to-be-tested pull-down transistor, the first active regions on both sides of the first gate are the first source / drain region and the second source / drain region of the to-be-tested pull-down transistor respectively, and the first gate structures of the other intersection regions are the second gates of at least one auxiliary pull-down transistor; the first metal interconnection structure is electrically connected with the first source / drain region, the second metal interconnection structure is electrically connected with the second source / drain region, and the third metal interconnection structure is electrically connected with the first gate and the second gates of the at least one auxiliary pull-down transistor, that is, at least one auxiliary pull-down transistor of the same type is connected in parallel on the to-be-tested pull-down transistor which needs to test the gate inversion leakage current, so that the sum of the gate inversion leakage currents of the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor can be tested, that is, the sum of the gate inversion leakage currents of at least two pull-down transistors is tested at the same time, and the gate inversion leakage current of a single to-be-tested pull-down transistor can be obtained by dividing the sum of the gate inversion leakage currents by the total number of pull-down transistors; since the gate inversion leakage current of a single to-be-tested pull-down transistor is small, by connecting at least one auxiliary pull-down transistor in parallel on the to-be-tested pull-down transistor, the test result of the sum of the gate inversion leakage currents of the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor tested by the machine is more accurate than the test result of the gate inversion leakage current of a single to-be-tested pull-down transistor, so that the gate inversion leakage current of a single to-be-tested pull-down transistor obtained by dividing the sum of the measured gate inversion leakage currents by the total number of pull-down transistors is more accurate, the test value is closer to the actual value, and the influence of the machine test precision and the process local fluctuation on the test result is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a layout schematic diagram of a semiconductor test structure of an embodiment of the utility model;

[0028] Figure 2 is a layout schematic diagram of a semiconductor test structure of another embodiment of the utility model.

[0029] In the drawings, Figures 1-2 The reference signs in the drawings are explained as follows:

[0030] 11-first active region; 12-second active region; 13-first gate structure; 14-second gate structure; 151-contact plug; 152-metal interconnection layer; 153-via plug; 16-gate cut structure. DETAILED DESCRIPTION

[0031] To make the purposes, advantages and characteristics of the present application more clear, the semiconductor test structure provided by the present application is described in further detail as follows. It should be noted that all the drawings are in a very simplified form and all use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0032] The semiconductor test structure provided by an embodiment of the present application comprises: a substrate; at least two first active regions located in the substrate, the at least two first active regions extending in a first direction and being arranged at intervals in a second direction; at least one first gate structure extending from the at least two first active regions to the substrate outside the first active regions, the at least one first gate structure extending in the second direction, the first direction being different from the second direction; in a plurality of intersection regions of the at least one first gate structure and the at least two first active regions, the first gate structure of one of the intersection regions is a first gate of a to-be-tested pull-down transistor, the first active regions on both sides of the first gate are a first source / drain region and a second source / drain region of the to-be-tested pull-down transistor respectively, and the first gate structures of the other intersection regions are second gates of at least one auxiliary pull-down transistor; a first metal interconnection structure, a second metal interconnection structure and a third metal interconnection structure, the first metal interconnection structure being electrically connected to the first source / drain region, the second metal interconnection structure being electrically connected to the second source / drain region, and the third metal interconnection structure being electrically connected to the first gate and the second gates of the at least one auxiliary pull-down transistor.

[0033] Reference will be made to Figures 1-2 The semiconductor test structure provided by the embodiment is described in further detail.

[0034] The substrate (not shown) can be composed of any appropriate semiconductor material, including but not limited to: silicon, germanium, silicon germanium, silicon carbon germanium, silicon carbide and other semiconductors.

[0035] The at least two first active regions 11 are located in the substrate, the at least two first active regions 11 extending in a first direction X and being arranged at intervals in a second direction Y. Figure 1 And Figure 2 In the embodiment shown, two first active regions 11 (namely AA2 and AA3) are shown.

[0036] At least one first gate structure 13 extends from the at least two first active regions 11 to the substrate surrounding the first active regions 11. The at least one first gate structure 13 extends in the second direction Y, where the first direction X is different from the second direction Y. In a plurality of intersecting regions between the at least one first gate structure 13 and the at least two first active regions 11, the first gate structure 13 in one of the intersecting regions is the first gate of a pull-down transistor under test, and the first active regions 11 on both sides of the first gate are the first source / drain region and the second source / drain region of the pull-down transistor under test, respectively. The first gate structure 13 in the other intersecting regions besides one of the intersecting regions is the second gate of at least one auxiliary pull-down transistor, and the first active regions 11 on both sides of the second gate are the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor, respectively.

[0037] Preferably, the first direction X is perpendicular to the second direction Y.

[0038] The intersection region between the first gate structure 13 and the first active region 11 refers to the overlapping region between the projection of the first gate structure 13 on the substrate and the first active region 11.

[0039] exist Figure 1 In the illustrated embodiment, a first gate structure 13 (i.e., G2) is shown. In the two intersecting regions of G2 and AA2 and AA3 respectively, the first gate structure 13 in the intersection region of G2 and AA3 is the first gate of the pull-down transistor under test. AA3 on both sides of the first gate is the first source / drain region and the second source / drain region of the pull-down transistor under test, respectively. The first gate structure 13 in the intersection region of G2 and AA2 is the second gate of the auxiliary pull-down transistor. AA2 on both sides of the second gate is the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor, respectively. Figure 2 In the illustrated embodiment, two first gate structures 13 (i.e., G2 and G3) are shown. In the four intersection regions of G2 and G3 with AA2 and AA3 respectively, the first gate structure 13 in the intersection region of G2 and AA3 is the first gate of the pull-down transistor under test. The AA3 on both sides of the first gate is the first source / drain region and the second source / drain region of the pull-down transistor under test, respectively. The first gate structure 13 in the intersection regions of G2 and AA2, G3 and AA2, and G3 and AA3 are all the second gates of the auxiliary pull-down transistor. The AA2 or AA3 on both sides of the second gate is the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor, respectively.

[0040] Wherein, when the number of the first gate structures 13 is at least two, the pull-down transistors under test on adjacent first gate structures 13 and the auxiliary pull-down transistors share a source / drain region, and the auxiliary pull-down transistors on adjacent first gate structures 13 also share a source / drain region. For example, in Figure 2 In the illustrated embodiment, taking the left and right sides of the intersection region of G2 and AA3 as the first source / drain region and the second source / drain region respectively, the left and right sides of the intersection region of G3 and AA3 as the fourth source / drain region and the third source / drain region respectively, the left and right sides of the intersection region of G2 and AA2 as the third source / drain region and the fourth source / drain region respectively, and the left and right sides of the intersection region of G3 and AA2 as the fourth source / drain region and the third source / drain region respectively, the second source / drain region on the right side of the intersection region of G2 and AA3 is the fourth source / drain region on the left side of the intersection region of G3 and AA3 (i.e., the pull-down transistor under test and the auxiliary pull-down transistor share the second source / drain region or the fourth source / drain region), and the fourth source / drain region on the right side of the intersection region of G2 and AA2 is the fourth source / drain region on the left side of the intersection region of G3 and AA2 (i.e., the two auxiliary pull-down transistors share the fourth source / drain region).

[0041] The first and third source / drain regions are source regions, and the second and fourth source / drain regions are drain regions; or, the first and third source / drain regions are drain regions, and the second and fourth source / drain regions are source regions.

[0042] The first metal interconnect structure is electrically connected to the first source / drain region, the second metal interconnect structure is electrically connected to the second source / drain region, and the third metal interconnect structure is electrically connected to the first gate and the second gate of the at least one auxiliary pull-down transistor. Therefore, the first metal interconnect structure is used to electrically lead out the first source / drain region, the second metal interconnect structure is used to electrically lead out the second source / drain region, and the third metal interconnect structure is used to electrically lead out the first gate and all of the second gates.

[0043] In an embodiment, the first metal interconnect structure, the second metal interconnect structure and the third metal interconnect structure each include a contact plug 151, at least one metal interconnect layer 152, at least one via plug 153 and a pad (not shown), the bottommost metal interconnect layer 152 of the first metal interconnect structure, the second metal interconnect structure and the third metal interconnect structure is respectively electrically connected with the first source / drain region, the second source / drain region and the second gate of the at least one auxiliary pull-down transistor through the corresponding contact plug 151, the metal interconnect layers 152 of the adjacent layers of the first metal interconnect structure, the second metal interconnect structure and the third metal interconnect structure are electrically connected through the corresponding via plug 153, and the topmost metal interconnect layer 152 is electrically connected with the corresponding pad through the corresponding via plug 153, so that the pad can be contacted by a probe for testing or an external power supply can be connected through the pad.

[0044] In the embodiment shown in FIG. 1, the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor are not provided with metal interconnect structures, i.e., no electrically connected contact plug 151, metal interconnect layer 152, via plug 153 and pad (such as the first metal interconnect structure and the second metal interconnect structure shown in FIG. 1). Figure 1 and Figure 2 In the embodiment shown in FIG. 1, the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor are not provided with metal interconnect structures, i.e., no electrically connected contact plug 151, metal interconnect layer 152, via plug 153 and pad (such as the first metal interconnect structure and the second metal interconnect structure shown in FIG. 1). Figure 2 In the embodiment shown in FIG. 1, the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor are not provided with metal interconnect structures, i.e., no electrically connected contact plug 151, metal interconnect layer 152, via plug 153 and pad (such as the first metal interconnect structure and the second metal interconnect structure shown in FIG. 1). Figure 2 In the embodiment shown in FIG. 1, the third source / drain region and the fourth source / drain region of the auxiliary pull-down transistor are not provided with metal interconnect structures, i.e., no electrically connected contact plug 151, metal interconnect layer 152, via plug 153 and pad (such as the first metal interconnect structure and the second metal interconnect structure shown in FIG. 1).

[0045] when the first gate and at least one of the second gates are located on the same one of the first gate structures 13, the first gate and at least one of the second gates are electrically connected to the same bottommost one of the metal interconnect layers 152 in the third metal interconnect structure through the same one of the contact plugs 151 in the third metal interconnect structure; and / or, when the first gate and at least one of the second gates are located on different ones of the first gate structures 13, the first gate and at least one of the second gates are electrically connected to the same bottommost one of the metal interconnect layers 152 in the third metal interconnect structure through different ones of the contact plugs 151 in the third metal interconnect structure.

[0046] wherein, in Figure 1 In the embodiment shown, the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G2 and AA2 are located on the same one of the first gate structures 13 (i.e., G2), and the first gate and the second gate are electrically connected to the same bottommost one of the metal interconnect layers 152 through the same one of the contact plugs 151; in Figure 2 In the embodiment shown, the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G2 and AA2 are located on the same one of the first gate structures 13 (i.e., G2), the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G3 and AA2, and the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G3 and AA3 are located on different ones of the first gate structures 13 (i.e., on G2 and G3, respectively), the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G2 and AA2 are electrically connected to the same bottommost one of the metal interconnect layers 152 through the same one of the contact plugs 151, the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G3 and AA2, and the first gate at the intersection of G2 and AA3 and the second gate at the intersection of G3 and AA3 are electrically connected to the same bottommost one of the metal interconnect layers 152 through different ones of the contact plugs 151, and the second gate at the intersection of G3 and AA2 and the second gate at the intersection of G3 and AA3 share the same one of the contact plugs 151, the first gate at the intersection of G2 and AA3, the second gate at the intersection of G2 and AA2, the second gate at the intersection of G3 and AA2, and the second gate at the intersection of G3 and AA3 are electrically connected to the same bottommost one of the metal interconnect layers 152.

[0047] In an embodiment, the semiconductor test structure further comprises: at least one second active region 12 located in the substrate outside the at least two first active regions 11, the at least one second active region 12 extending in the first direction X; the at least one first gate structure 13 further extends onto the at least one second active region 12, the first gate structure 13 at the intersection region of the at least one first gate structure 13 and the at least one second active region 12 being a third gate of at least one dummy transistor. The second active region 12 on the two sides of the third gate is a fifth source / drain region and a sixth source / drain region respectively.

[0048] The intersection region of the first gate structure 13 and the second active region 12 refers to the overlapping region of the projection of the first gate structure 13 on the substrate and the second active region 12.

[0049] In an embodiment, the semiconductor test structure further comprises: at least one second gate structure 14 extending from the at least two first active regions 11 outside the at least one first gate structure 13 onto the at least one second active region 12 and the substrate outside the first active region 11 and the second active region 12, the at least one second gate structure 14 extending in the second direction Y; the second gate structure 14 at the intersection region of the at least one second gate structure 14 and the at least two first active regions 11 and at the intersection region of the at least one second gate structure 14 and the at least one second active region 12 being a third gate of at least one dummy transistor, the first active region 11 or the second active region 12 on the two sides of the third gate being a fifth source / drain region and a sixth source / drain region respectively.

[0050] The intersection region of the second gate structure 14 and the first active region 11 and the second active region 12 respectively refers to the overlapping region of the projection of the second gate structure 14 on the substrate and the first active region 11 and the second active region 12 respectively.

[0051] The fifth source / drain region is a source region and the sixth source / drain region is a drain region; or, the fifth source / drain region is a drain region and the sixth source / drain region is a source region.

[0052] In an embodiment, the first active region 11 and the second active region 12 are formed by the same process, and the first gate structure 13 and the second gate structure 14 are formed by the same process.

[0053] The first gate structure 13 and the second gate structure 14 can each comprise a gate dielectric layer and a gate electrode layer stacked from bottom to top.

[0054] The virtual transistor can be a transmission gate transistor, a pull-up transistor, or a pull-down transistor. The widths of the active regions of the pull-down transistor, the transmission gate transistor, and the pull-up transistor decrease sequentially in the second direction Y.

[0055] In the embodiment shown in Figure 1, eight second active regions 12 (i.e., AA1, AA4, AA5, AA6, AA7, AA8, AA9, and AA10) extending in the first direction X and spaced apart in the second direction Y are illustrated, and three second gate structures 14 (i.e., G1, G3, and G4) extending in the second direction Y and spaced apart in the first direction X are also illustrated. Based on the rule that the widths of the active regions of the pull-down transistor, the transmission gate transistor, and the pull-up transistor in the virtual transistor decrease sequentially in the second direction Y, the second gate structures 14 in the intersection regions of G1 and AA6, G1 and AA7, G3 and AA2, G3 and AA3, G4 and AA6, and G4 and AA7 are the pull-down transistors. The third gate of the transistor, the second gate structure 14 of the intersection regions of G1 and AA2, G1 and AA3, G3 and AA6, G3 and AA7, G4 and AA2, G4 and AA3, and the first gate structure 13 of the intersection regions of G2 and AA6, G2 and AA7 are the third gate of the transmission gate transistor. The second gate structure 14 of the intersection regions of G1 and AA10, G1 and AA9, G3 and AA1, G3 and AA4, G4 and AA5, G4 and AA8, and the first gate structure 13 of the intersection regions of G2 and AA1, G2 and AA4 are the third gate of the pull-up transistor.

[0056] and Figure 1 Compared to the embodiments shown, Figure 2 The difference in the illustrated embodiment is that two second gate structures 14 (i.e., G1 and G4) extending in the second direction Y and spaced apart in the first direction X are shown. The first gate structure 13 in the intersection region of G3 and AA2 and the intersection region of G3 and AA3 is the second gate of the auxiliary pull-down transistor. The first gate structure 13 in the intersection region of G3 and AA6 and the intersection region of G3 and AA7 is the third gate of the transmission gate transistor. The first gate structure 13 in the intersection region of G3 and AA1 and the intersection region of G3 and AA4 is the third gate of the pull-up transistor.

[0057] The adjacent dummy transistors can share a source / drain region, the adjacent to-be-measured pull-down transistors and the dummy transistors can share a source / drain region, and the adjacent auxiliary pull-down transistors and the dummy transistors can share a source / drain region.

[0058] Preferably, the semiconductor test structure further comprises: a gate cutting structure 16 located in the at least one first gate structure 13 between the at least two first active regions 11 and the at least one second active region 12, i.e., the gate cutting structure 16 cuts off the at least one first gate structure 13 between the at least two first active regions 11 and the at least one second active region 12, so that the to-be-measured pull-down transistors and the at least one auxiliary pull-down transistor are isolated from the at least one dummy transistor by the gate cutting structure 16.

[0059] wherein, in the embodiment shown in FIG. 1, the gate cutting structure 16 cuts off at least G2 between AA1 and AA2 and G2 between AA3 and AA4; and in the embodiment shown in FIG. 2, the gate cutting structure 16 cuts off at least G2 and G3 between AA1 and AA2 and at least G2 and G3 between AA3 and AA4. Figure 1 In the embodiment shown in FIG. 1, the gate cutting structure 16 cuts off at least G2 between AA1 and AA2 and G2 between AA3 and AA4; and in the embodiment shown in FIG. 2, the gate cutting structure 16 cuts off at least G2 and G3 between AA1 and AA2 and at least G2 and G3 between AA3 and AA4. Figure 2 In the embodiment shown in FIG. 1, the gate cutting structure 16 cuts off at least G2 between AA1 and AA2 and G2 between AA3 and AA4; and in the embodiment shown in FIG. 2, the gate cutting structure 16 cuts off at least G2 and G3 between AA1 and AA2 and at least G2 and G3 between AA3 and AA4.

[0060] It should be noted that the gate cutting structure 16 can also be arranged in the at least one first gate structure 13 between the adjacent second active regions 12 (for example, G2 between AA7 and AA9 shown in FIG. 1), the at least one second gate structure 14 between the adjacent second active regions 12 (for example, G3 between AA7 and AA8 shown in FIG. 1), the at least one second gate structure 14 between the adjacent first active regions 11, the at least one second gate structure 14 between the adjacent first active regions 11 and second active regions 12 (for example, G1 between AA1 and AA2 shown in FIG. 1), so that the structural composition of the semiconductor test structure is close to the device structural composition of an actual product. Figure 1 It should be noted that the gate cutting structure 16 can also be arranged in the at least one first gate structure 13 between the adjacent second active regions 12 (for example, G2 between AA7 and AA9 shown in FIG. 1), the at least one second gate structure 14 between the adjacent second active regions 12 (for example, G3 between AA7 and AA8 shown in FIG. 1), the at least one second gate structure 14 between the adjacent first active regions 11, the at least one second gate structure 14 between the adjacent first active regions 11 and second active regions 12 (for example, G1 between AA1 and AA2 shown in FIG. 1), so that the structural composition of the semiconductor test structure is close to the device structural composition of an actual product. Figure 1 It should be noted that the gate cutting structure 16 can also be arranged in the at least one first gate structure 13 between the adjacent second active regions 12 (for example, G2 between AA7 and AA9 shown in FIG. 1), the at least one second gate structure 14 between the adjacent second active regions 12 (for example, G3 between AA7 and AA8 shown in FIG. 1), the at least one second gate structure 14 between the adjacent first active regions 11, the at least one second gate structure 14 between the adjacent first active regions 11 and second active regions 12 (for example, G1 between AA1 and AA2 shown in FIG. 1), so that the structural composition of the semiconductor test structure is close to the device structural composition of an actual product. Figure 1 It should be noted that the gate cutting structure 16 can also be arranged in the at least one first gate structure 13 between the adjacent second active regions 12 (for example, G2 between AA7 and AA9 shown in FIG. 1), the at least one second gate structure 14 between the adjacent second active regions 12 (for example, G3 between AA7 and AA8 shown in FIG. 1), the at least one second gate structure 14 between the adjacent first active regions 11, the at least one second gate structure 14 between the adjacent first active regions 11 and second active regions 12 (for example, G1 between AA1 and AA2 shown in FIG. 1), so that the structural composition of the semiconductor test structure is close to the device structural composition of an actual product.

[0061] The material of the gate cutting structure 16 can be a nitrogen-containing material (for example, SiN, SiOCN, or SiON) or an oxygen-containing material such as SiO x (x is a positive integer).

[0062] In some embodiments, the gate cut structure 16 is formed by a cut metal gate (CMG) process. The CMG process refers to a manufacturing process in which, after a metal gate (e.g., a high-k metal gate) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut by an etching process to separate the metal gate into two or more gate segments; each gate segment functions as a metal gate of a single transistor; and then an isolation material is filled into a trench between adjacent portions of the metal gate.

[0063] The gate cut structure 16 cuts off the at least one first gate structure 13 located between the at least two first active regions 11 and the at least one second active region 12, and no metal interconnection structure (i.e., no electrically connected contact plug 151, metal interconnection layer 152, via plug 153, and pad) is disposed on the fifth source / drain region, the sixth source / drain region, and the third gate of the virtual transistor, i.e., the fifth source / drain region, the sixth source / drain region, and the third gate of the virtual transistor are not electrically led out. Figure 1 and Figure 2 The fifth source / drain region, the sixth source / drain region, and the third gate of the virtual transistor are disposed on the AA4 on the left side of the intersection region of G2 and AA4, and extend from the AA4 to the G1 on the AA6 through the AA10; or, the fifth source / drain region, the sixth source / drain region, and the third gate of the virtual transistor are disposed on the AA4 on the right side of the intersection region of G2 and AA4, and extend from the AA4 to the G3 on the AA7 through the AA5 and AA6. Figure 2 The fifth source / drain region, the sixth source / drain region, and the third gate of the virtual transistor are not electrically led out.

[0064] It should be noted that the metal interconnection structure (i.e., the first metal interconnection structure or the second metal interconnection structure) can be disposed on the source / drain region shared by the to-be-tested pull-down transistor and the virtual transistor; for example, in the embodiment shown in Figure 1 In the embodiment shown in FIG. 1, the AA2 between G1 and G2 and between G2 and G3 is the source / drain region shared by the to-be-tested pull-down transistor and the virtual transistor, and the first metal interconnection structure or the second metal interconnection structure can be disposed thereon.

[0065] Due to the semiconductor test structure comprising the at least one second active region 12 and the at least one second gate structure 14, the semiconductor test structure further comprises the at least one dummy transistor in addition to the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor, so that the test environment outside the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor in the semiconductor test structure is the same as or close to the test environment outside the to-be-tested pull-down transistor in the device structure of the actual product, thereby making the test result of the gate inverse subthreshold current more accurate.

[0066] In addition, due to the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor being isolated from the at least one dummy transistor by the gate cut structure 16, the first gate and the second gate are prevented from being electrically connected to the third gate on the at least one first gate structure 13, thereby avoiding the at least one dummy transistor affecting the test result of the gate inverse subthreshold current of the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor (for example, avoiding the absolute value of the tested gate inverse subthreshold current being too high), thereby reducing the influence of layout design on the test result of the gate inverse subthreshold current.

[0067] The semiconductor test structure further comprises:

[0068] a body region (not shown) extending from the top surface of the substrate into the substrate, the at least two first active regions 11 and the at least one second active region 12 being located in the body region;

[0069] a body contact region (not shown) located in the body region outside the at least two first active regions 11 and the at least one second active region 12;

[0070] a fourth metal interconnection structure (not shown) electrically connecting the body contact region.

[0071] wherein the doping type of the first source / drain region, the second source / drain region, the third source / drain region, the fourth source / drain region, the fifth source / drain region and the sixth source / drain region is opposite to the doping type of the body region; the doping type of the body contact region is the same as the doping type of the body region, and the doping concentration of the body contact region is greater than the doping concentration of the body region, and the body contact region is used to lead out the body region.

[0072] The fourth metal interconnect structure can also include the electrically connected contact plug 151, the at least one metal interconnect layer 152, the at least one via plug 153, and the pad, the bulk contact region being electrically connected to the bottommost metal interconnect layer 152 through the contact plug 151.

[0073] The semiconductor test structure further includes a shallow trench isolation structure (not shown) in the substrate outside the first active region 11 and the second active region 12.

[0074] The shallow trench isolation structure is in the bulk region outside the first active region 11 and the second active region 12, the first active region 11 being isolated from the second active region 12 by the shallow trench isolation structure, the first active region 11 and the second active region 12 being isolated from the bulk contact region by the shallow trench isolation structure.

[0075] The semiconductor test structure further includes an interlayer dielectric layer (not shown) on the substrate, the interlayer dielectric layer covering the first active region 11, the second active region 12, the first gate structure 13, the second gate structure 14, and the gate cut structure 16, the contact plug 151, the at least one metal interconnect layer 152, and the at least one via plug 153 in the first metal interconnect structure, the second metal interconnect structure, the third metal interconnect structure, and the fourth metal interconnect structure being in the interlayer dielectric layer, the pad in the first metal interconnect structure, the second metal interconnect structure, the third metal interconnect structure, and the fourth metal interconnect structure being on the surface of the interlayer dielectric layer.

[0076] In testing the gate reverse-type leakage current, a reverse-type voltage can be applied to the third metal interconnect structure, the first metal interconnect structure, the second metal interconnect structure, and the fourth metal interconnect structure being grounded or floating.

[0077] From the above, the semiconductor test structure, because in the at least one first gate structure 13 with the at least two first active area 11 multiple intersection area, one of the intersection area first gate structure 13 is the first gate of the pull-down transistor to be measured, the first active area 11 of both sides of the first gate is the first source / drain area and the second source / drain area of the pull-down transistor to be measured, other intersection area first gate structure 13 is the second gate of at least one auxiliary pull-down transistor;The first metal interconnection structure is electrically connected to the first source / drain area, the second metal interconnection structure is electrically connected to the second source / drain area, the third metal interconnection structure is electrically connected to the first gate and the second gate of the at least one auxiliary pull-down transistor, that is, at least one transistor type same auxiliary pull-down transistor is connected in parallel on the pull-down transistor to be measured which needs to test the gate inversion leakage current, so that the sum of the gate inversion leakage current of the pull-down transistor to be measured and the at least one auxiliary pull-down transistor can be tested, that is, the sum of the gate inversion leakage current of at least two pull-down transistors is tested at the same time, and the sum of the gate inversion leakage current is divided by the total number of pull-down transistors (that is, the total number of the pull-down transistor to be measured and the at least one auxiliary pull-down transistor) to obtain the gate inversion leakage current of a single pull-down transistor to be measured;Since the gate inversion leakage current of a single pull-down transistor to be measured is small, by connecting at least one auxiliary pull-down transistor in parallel on the pull-down transistor to be measured, the sum of the gate inversion leakage current of the pull-down transistor to be measured and the at least one auxiliary pull-down transistor is greater than the value of the gate inversion leakage current of a single pull-down transistor to be measured, and the test result of testing the gate inversion leakage current of a single pull-down transistor to be measured is more accurate, so that the gate inversion leakage current obtained by dividing the sum of the measured gate inversion leakage current by the total number of pull-down transistors is more accurate, the test value is closer to the actual value, and the influence of machine test precision and process local fluctuation on the test result is reduced. Wherein, the more the number of the at least one auxiliary pull-down transistor, the more accurate the gate inversion leakage current of the pull-down transistor to be measured.

[0078] And, the third source / drain area and the fourth source / drain area of the auxiliary pull-down transistor are not electrically connected, which can also reduce other leakage channels, further making the measured gate inversion leakage current more accurate.

[0079] The above description is only a description of the preferred embodiment of the utility model, and does not limit the scope of the utility model, any change and modification made by the ordinary skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A semiconductor test structure, characterized by, The semiconductor test structure comprises: a substrate; at least two first active regions located in the substrate, the at least two first active regions extending in a first direction and being spaced apart in a second direction; at least one first gate structure extending from the at least two first active regions to the substrate outside the at least two first active regions, the at least one first gate structure extending in the second direction, the first direction being different from the second direction; in a plurality of intersection regions of the at least one first gate structure and the at least two first active regions, a first gate structure in one of the intersection regions is a first gate of a to-be-tested pull-down transistor, first source / drain regions and second source / drain regions of the to-be-tested pull-down transistor are respectively located on two sides of the first gate, and first gate structures in other intersection regions are second gates of at least one auxiliary pull-down transistor; a first metal interconnection structure, a second metal interconnection structure and a third metal interconnection structure, the first metal interconnection structure being electrically connected to the first source / drain regions, the second metal interconnection structure being electrically connected to the second source / drain regions, and the third metal interconnection structure being electrically connected to the first gate and the second gates of the at least one auxiliary pull-down transistor.

2. The semiconductor test structure of claim 1, wherein, The first direction is perpendicular to the second direction.

3. The semiconductor test structure of claim 1, wherein, The first metal interconnection structure, the second metal interconnection structure and the third metal interconnection structure each comprise a contact plug, at least one metal interconnection layer, at least one via plug and a pad, the metal interconnection layer at the bottom is electrically connected to the first source / drain regions, the second source / drain regions, the first gate and the second gates of the at least one auxiliary pull-down transistor through the contact plug, the metal interconnection layers at adjacent layers are electrically connected through the via plug, and the metal interconnection layer at the top is electrically connected to the pad through the via plug.

4. The semiconductor test structure of claim 3, wherein, When the first gate and at least one second gate are located on the same first gate structure, the first gate and at least one second gate are electrically connected to the same metal interconnection layer at the bottom through the same contact plug; and / or when the first gate and at least one second gate are located on different first gate structures, the first gate and at least one second gate are electrically connected to the same metal interconnection layer at the bottom through different contact plugs.

5. The semiconductor test structure of claim 1, wherein, The semiconductor test structure further comprises: at least one second active region located in the substrate outside the at least two first active regions, the at least one second active region extending in the first direction; the at least one first gate structure further extends to the at least one second active region, and a first gate structure in an intersection region of the at least one first gate structure and the at least one second active region is a third gate of at least one virtual transistor.

6. The semiconductor test structure of claim 5, wherein, The semiconductor test structure further comprises: a gate cut structure in the at least one first gate structure between the at least two first active regions and the at least one second active region, so that the to-be-tested pull-down transistor and the at least one auxiliary pull-down transistor are isolated from the at least one dummy transistor by the gate cut structure.

7. The semiconductor test structure of claim 5, wherein, The semiconductor test structure further comprises: at least one second gate structure extending from the at least two first active regions outside the at least one first gate structure to the at least one second active region and the substrate outside the first and second active regions, the at least one second gate structure extending in the second direction; the second gate structure at the intersection region of the at least one second gate structure and the at least two first active regions and the intersection region of the at least one second active region is a third gate of at least one dummy transistor.

8. The semiconductor test structure of claim 7, wherein, The dummy transistor is a pass transistor, a pull-up transistor or a pull-down transistor.

9. The semiconductor test structure of claim 5, wherein, The semiconductor test structure further comprises: a body region extending from the top surface of the substrate into the substrate, the at least two first active regions and the at least one second active region being located in the body region; a body contact region located in the body region outside the at least two first active regions and the at least one second active region; a fourth metal interconnection structure electrically connected to the body contact region.

10. The semiconductor test structure of claim 5, wherein, The semiconductor test structure further comprises: a shallow trench isolation structure located in the substrate outside the first and second active regions. a shallow trench isolation structure located in the substrate outside the first and second active regions.

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