Manufacturing method of groove-based heterogeneous interlayer step soldermask structure and semiconductor device

Abstract

This invention discloses a method for fabricating a trench-based heterogeneous sandwich stepped solder resist structure and a semiconductor device. The semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a trench-based heterogeneous sandwich stepped solder resist structure. In the trench-based heterogeneous sandwich stepped solder resist structure, trenches are formed around the electrical connection structure of the pads formed by the metal interconnect layer. An insulating dielectric layer covers the passivation layer and part or all of the trenches to form a first stepped structure, and a solder resist layer covers the insulating dielectric layer and part or all of the trenches to form a second stepped structure. By utilizing the composite sandwich structure formed by the trench-based reinforced insulating dielectric layer and solder resist layer, multiple barriers can be formed against the intrusion of moisture and solder, effectively delaying or blocking the migration path of moisture along the interface between the passivation layer and the solder resist layer, significantly improving the moisture intrusion protection capability, and effectively preventing PI peeling.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for fabricating a trench-based heterojunction stepped solder resist structure and a semiconductor device thereof. Background Technology

[0002] Silicon carbide (SiC) MOSFET power devices are widely used in power electronics due to their high voltage withstand capability, low loss, and high frequency characteristics. During the device packaging process, the NiPdAu plating treatment of the source pads and subsequent module packaging are critical steps affecting device reliability. Current technologies primarily employ a scheme of forming a single-layer PI2 solder resist after NiPdAu plating, but this scheme has the following problems: First, the interfacial bonding strength between the polyimide (PI) solder resist layer and the underlying dielectric layer is limited, making PI peeling prone to occur during electroless plating and encapsulation. Second, micro-gaps exist at the interface between the PI solder resist layer and the electroless plating metal layer, allowing molten solder to easily penetrate along these gaps during high-temperature reflow soldering, potentially leading to electrical short circuits. Third, moisture can gradually penetrate inward along the interface between the PI layer and the underlying structure, easily inducing metal migration and corrosion failure under high-temperature and high-humidity bias test conditions.

[0003] While there are solutions that apply trenches to the solder mask layer, such as forming trenches on the solder mask layer of a circuit board corresponding to the cutting path to avoid the solder mask layer melting during laser cutting, these trenches are mainly used for cutting process optimization, not to block the intrusion of moisture and solder. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a trench-based heterogeneous sandwich stepped solder resist structure and a semiconductor device thereon, so as to solve the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: This application provides a trench-based heterojunction stepped solder resist structure applied to the source pad region of a semiconductor device. The semiconductor device includes a semiconductor substrate, a metal interconnect layer located above the semiconductor substrate, and a passivation layer, comprising: At least one trench is formed around the periphery of the metal interconnect layer; An insulating dielectric layer covering the passivation layer and part or all of the trenches; A solder resist layer covering the insulating dielectric layer and part or all of the trenches; A metal plating layer is electrically connected to the metal interconnect layer and abuts against the solder resist layer.

[0006] The aforementioned trench-based heterogeneous sandwich stepped solder resist structure has trenches around the electrical connection structure of the solder pads formed by the metal interconnect layer. The first stepped structure is formed by the insulating dielectric layer covering the passivation layer and part or all of the trenches, and the second stepped structure is formed by the solder resist layer covering the insulating dielectric layer and part or all of the trenches. By utilizing the composite sandwich structure formed by the trench-based reinforced insulating dielectric layer and solder resist layer, multiple barriers can be formed against the intrusion of moisture and solder, effectively delaying or blocking the migration path of moisture along the interface between the passivation layer and the solder resist layer, significantly improving the moisture intrusion protection capability, and effectively preventing the occurrence of PI peeling.

[0007] In one preferred embodiment, the sidewalls of the trench are arc surfaces or slopes formed by isotropic etching.

[0008] In one preferred embodiment, the bottom of the trench extends to the interlayer dielectric layer beneath the passivation layer.

[0009] In one preferred embodiment, the metal interconnect layer has at least three trenches.

[0010] In one preferred embodiment, the trench is arranged in a ring around the metal interconnect layer.

[0011] In one preferred embodiment, an adhesion enhancement layer is provided between the insulating dielectric layer and the solder resist layer; The adhesion enhancement layer is used to improve the bonding strength between the insulating dielectric layer and the solder resist layer.

[0012] In one preferred embodiment, the metal interconnect layer is an alloy layer.

[0013] In one preferred embodiment, the metal interconnect layer is an AlCu layer.

[0014] In one preferred embodiment, the electroplated metal layer is a NiPdAu stacked structure.

[0015] In one preferred embodiment, the insulating dielectric layer is an inorganic dielectric layer, and the solder resist layer is an organic dielectric layer.

[0016] In one preferred embodiment, the inorganic dielectric layer is an OX layer or a SIN layer.

[0017] In one preferred embodiment, the organic dielectric layer is a semiconductor packaging material layer.

[0018] In one preferred embodiment, the semiconductor packaging material layer is a polyimide layer.

[0019] This application also provides a semiconductor device, including a semiconductor substrate, a metal interconnect layer located above the semiconductor substrate, a passivation layer, and a trench-based heterojunction stepped solder resist structure.

[0020] The aforementioned semiconductor device includes a semiconductor substrate, a metal interconnect layer located above the semiconductor substrate, a passivation layer, and a trench-based heterojunction stepped solder resist structure. In the trench-based heterojunction stepped solder resist structure, trenches are formed around the electrical connection structure of the pads formed by the metal interconnect layer. A first stepped structure is formed by an insulating dielectric layer covering the passivation layer and part or all of the trenches, and a second stepped structure is formed by a solder resist layer covering the insulating dielectric layer and part or all of the trenches. Utilizing the trench-based reinforced composite sandwich structure formed by the insulating dielectric layer and the solder resist layer, multiple barriers can be formed against the intrusion of moisture and solder, effectively delaying or blocking the migration path of moisture along the interface between the passivation layer and the solder resist layer, significantly improving the moisture intrusion protection capability and effectively preventing PI peeling. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings. Figure 1 This is a cross-sectional schematic diagram of a groove-based heterogeneous sandwich stepped resist welding structure according to an embodiment of the application. Figure 2 This is a three-dimensional schematic diagram of a groove-based heterogeneous sandwich stepped resist welding structure according to an embodiment of the application. Figure 3 A cross-sectional schematic diagram of a groove-based heterogeneous sandwich stepped resist welding structure according to another application embodiment; Figure 4 A three-dimensional schematic diagram of a groove-based heterogeneous sandwich stepped resist welding structure according to another embodiment of the application; Figure 5 A flowchart illustrating a method for fabricating a groove-based heterogeneous sandwich stepped resist welding structure according to an embodiment of the application; Figure 6 A schematic diagram of the single-groove process flow for the fabrication method of a groove-based heterogeneous sandwich stepped resist welding structure according to an embodiment of the application. Figure 7 This is a schematic diagram of the multi-groove process flow for a method of fabricating a grooved heterogeneous sandwich stepped resist welding structure according to an embodiment of the application. Figure 8 This is a schematic diagram of a single-groove MT photomask; Figure 9 This is a schematic diagram of a multi-groove MT mask. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] To facilitate understanding of the embodiments of this application, further explanation and description will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application. In the drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0024] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “(the)” are also intended to include the plural forms. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0025] This embodiment provides a groove-based heterogeneous sandwich stepped resist welding structure.

[0026] Figure 1 This is a schematic cross-sectional view of a groove-based heterogeneous sandwich stepped weld resistance structure according to an embodiment of the application, as shown below. Figure 1 As shown, a trench-based heterojunction stepped solder mask structure of one embodiment is applied to the source pad region of a semiconductor device. The semiconductor device includes a semiconductor substrate, a metal interconnect layer 100 located above the semiconductor substrate, and a passivation layer, including: At least one trench 101 is formed around the periphery of the metal interconnect layer 100; An insulating dielectric layer 102 covering the passivation layer and part or all of the trenches 101; A solder resist layer 103 covering the insulating dielectric layer 102 and part or all of the trench 101; The electroplated metal layer 104 is electrically connected to the metal interconnect layer 100 and abuts against the solder resist layer 103.

[0027] The semiconductor substrate can be a silicon carbide substrate. An interlayer dielectric layer is formed above the semiconductor substrate to provide electrical isolation within the device. A metal interconnect layer 100, made of a conductive material such as aluminum or copper, is formed above the interlayer dielectric layer to provide electrical connections within the device. A passivation layer (PAS) is formed above the interlayer dielectric layer to protect the device surface.

[0028] like Figure 1 As shown, trench 101 is disposed on the surface of metal interconnect layer 100 and located on the periphery of metal interconnect layer 100. Trench 101 extends downward from the upper surface of metal interconnect layer 100.

[0029] Preferably, the depth of the groove 101 is about 3-5 μm and the width is about 1.5-2.5 μm.

[0030] Preferably, the sidewall of the trench 101 is an arc surface or a slope formed by isotropic etching.

[0031] The trench 101 can be formed by photolithography etching. Since etching has isotropic etching characteristics, the sidewalls of the trench 101 form arc surfaces or slopes to enhance the coverage performance and anchoring effect of the insulating dielectric layer 102.

[0032] Preferably, the bottom of the trench 101 extends to the interlayer dielectric layer below the passivation layer.

[0033] The bottom of trench 101 extends into the interlayer dielectric layer beneath the passivation layer, forming a deeper moisture barrier. Preferably, the distance between trench 101 and the edge of the source pad is approximately 10-20 μm.

[0034] Preferably, Figure 2 This is a three-dimensional schematic diagram of a trench-based heterogeneous sandwich stepped resist welding structure according to an embodiment of the application, as shown below. Figure 2 As shown, the trench 101 is arranged in a ring around the metal interconnect layer 100, forming a closed moisture barrier path.

[0035] like Figure 1As shown, the insulating dielectric layer 102 is disposed above the passivation layer and the trench 101. Preferably, the insulating dielectric layer 102 comprises one or more inorganic dielectric layers; wherein, multiple inorganic dielectric layers are stacked or compositely disposed. The inorganic dielectric layer is an OX (oxide semiconductor) layer or a SIN (silicon nitride) layer. When the insulating dielectric layer 102 comprises one inorganic dielectric layer, either an OX layer or a SIN layer may be selected. When the insulating dielectric layer 102 comprises multiple inorganic dielectric layers, the insulating dielectric layer 102 is a composite structure, which may be formed by stacking or compositely distributing multiple inorganic dielectric layers. Preferably, the composite arrangement includes material composite and structural composite.

[0036] Preferably, the insulating dielectric layer 102 comprises a silicon oxide layer and a silicon nitride layer stacked together. The thickness of the silicon oxide layer is 300-500 Å, and the thickness of the silicon nitride layer is 300-500 Å. The silicon oxide layer has good insulation properties and interfacial characteristics, while the silicon nitride layer has excellent moisture barrier properties and high density. The insulating dielectric layer 102 formed by the composite of these two layers can effectively block the penetration of moisture.

[0037] like Figure 1 As shown, the insulating dielectric layer 102 covers at least a portion of the upper surface of the passivation layer and at least a portion of the inner wall of the trench 101. Due to the presence of the trench 101, the insulating dielectric layer 102 forms a first step structure at the location of the trench 101, which together constitutes a moisture intrusion path extension structure to block the migration path of moisture along the interface between the passivation layer and the insulating dielectric layer 102.

[0038] Preferably, an adhesion enhancement layer is provided between the insulating dielectric layer 102 and the solder resist layer 103; The adhesion enhancement layer is used to improve the bonding strength between the insulating dielectric layer 102 and the solder resist layer 103. Preferably, the adhesion enhancement layer is a hexamethyldisilazane (HMDS) layer, used to improve the bonding strength between the insulating dielectric layer 102 and the first solder resist layer 103, and further prevent PI peeling.

[0039] like Figure 1 As shown, the solder resist layer 103 is disposed above the insulating dielectric layer 102 and the trench 101. The insulating dielectric layer 102 is an organic dielectric layer, preferably a semiconductor packaging material layer, and more preferably made of polyimide material, formed by coating, exposure, development and curing processes, with a thickness of approximately 10-15 μm. The bonding of the solder resist layer 103 with the trench 101 and the insulating dielectric layer 102 forms a second-step structure, which together constitutes a multi-layer moisture intrusion path extension structure. The presence of the first-step structure and the second-step structure transforms the moisture intrusion path from a simple linear shape to a complex zigzag shape, significantly extending the intrusion path length and effectively delaying or preventing moisture intrusion.

[0040] like Figure 1 As shown, the insulating dielectric layer 102 and the solder resist layer 103 form a stepped structure. According to preferred materials, an inorganic / organic composite interface is formed between the insulating dielectric layer 102 and the solder resist layer 103. Due to the significant difference in properties between the two materials, this composite interface provides good protection against the intrusion of moisture and solder. The solder resist layer 103 covers the edge portions of the insulating dielectric layer 102 and the electroless metallized layer 104, forming an interlayer step between the insulating dielectric layer 102 and the solder resist layer 103. This stepped structure extends the path length for moisture and solder intrusion, increasing the difficulty of intrusion and effectively preventing solder and moisture intrusion.

[0041] In this embodiment, the thinner insulating dielectric layer 102 serves as the underlayer, exhibiting lower curing shrinkage and less internal stress. The stepped structure buffers and disperses thermal stress generated during temperature changes, effectively preventing PI peeling.

[0042] like Figure 1 As shown, the electroplated metal layer 104 is electrically connected to the metal interconnect layer 100 and abuts against the solder resist layer 103. Preferably, the electroplated metal layer 104 is a NiPdAu stacked structure.

[0043] Preferably, both the insulating dielectric layer 102 and the solder resist layer 103 have solder resist openings, which expose part of the upper surface of the electroplated metal layer 104, so that the electroplated metal layer 104 can contact the external solder to achieve electrical connection.

[0044] As one of the preferred embodiments, Figure 3 This is a cross-sectional schematic diagram of a groove-based heterogeneous sandwich stepped weld resistance structure according to another application embodiment, as shown below. Figure 3 As shown, the metal interconnect layer 100 has at least three trenches 101.

[0045] The multi-groove design 101 further extends the moisture migration path, enhances moisture intrusion protection, and more effectively prevents PI peeling. Considering both cost and reliability, the optimal groove 101 design consists of three grooves.

[0046] like Figure 4 A three-dimensional schematic diagram of a trench-based heterogeneous sandwich stepped solder mask structure is shown in another embodiment of the application. Multiple trenches 101 surround the metal interconnect layer 100. The multiple trenches 101 and the solder mask layer 103 together constitute a multi-pathway blocking structure for moisture intrusion. The gaps between adjacent trenches 101 and the stepped structure together form a tortuous path for moisture intrusion. The multiple trenches 101 are used to progressively block the migration of moisture along the interface between the passivation layer and the solder mask layer 103.

[0047] Preferably, the depth of the first groove 101 surrounding the inner ring is 2-32 μm and the width is 1.5-2.5 μm; the depth of the groove 101 surrounding the outer ring is 3-4 μm and the width is 2-3 μm. The spacing between adjacent grooves 101 is 6-10 μm.

[0048] The metal interconnect layer 100 is made of a material that is easy to etch, preferably an alloy layer. As a preferred embodiment, the metal interconnect layer 100 is an AlCu (aluminum-copper alloy) layer.

[0049] In any of the above embodiments, the trench-based heterogeneous sandwich stepped solder resist structure has a trench 101 formed around the pad electrical connection structure formed by the metal interconnect layer 100. The first stepped structure is formed by the insulating dielectric layer 102 covering the passivation layer and part or all of the trench 101. The second stepped structure is formed by the solder resist layer 103 covering the insulating dielectric layer 102 and part or all of the trench 101. By utilizing the composite sandwich structure formed by the trench-based reinforced insulating dielectric layer 102 and solder resist layer 103, multiple barriers can be formed against the intrusion of moisture and solder, effectively delaying or blocking the migration path of moisture along the interface between the passivation layer and the solder resist layer 103, significantly improving the moisture intrusion protection capability, and effectively preventing the occurrence of PI peeling.

[0050] This application also provides a semiconductor device, including a semiconductor substrate, a metal interconnect layer 100 located above the semiconductor substrate, a passivation layer, and a trench-based heterojunction stepped solder resist structure. In the trench-based heterojunction stepped solder resist structure, a trench 101 is formed around the pad electrical connection structure formed by the metal interconnect layer 100. An insulating dielectric layer 102 covers the passivation layer and part or all of the trench 101 to form a first stepped structure, and a solder resist layer 103 covers the insulating dielectric layer 102 and part or all of the trench 101 to form a second stepped structure. By utilizing the composite sandwich structure formed by the trench-based reinforced insulating dielectric layer 102 and solder resist layer 103, multiple barriers can be formed against the intrusion of moisture and solder, effectively delaying or blocking the migration path of moisture along the interface between the passivation layer and the solder resist layer 103, significantly improving the moisture intrusion protection capability, and effectively preventing PI peeling.

[0051] This application also provides a method for fabricating a groove-based heterogeneous sandwich stepped resist welding structure.

[0052] Figure 5 This is a flowchart illustrating a method for fabricating a trench-based heterogeneous sandwich stepped resist welding structure according to an embodiment of the application. Figure 5 As shown, a method for fabricating a trench-based heterogeneous sandwich stepped weld resist structure according to an embodiment of the application includes steps S100 to S102: S100, at least one trench 101 is etched on the metal interconnect layer 100; S101, an insulating dielectric layer 102 and a solder resist layer 103 are sequentially covered on the metal interconnect layer 100 and the passivation layer, and an opening is left to accommodate the electroless metal plating layer 104. S102, a chemically plated metal layer 104 is formed at the opening.

[0053] Figure 6 This is a schematic diagram of the single-groove process flow for a method of fabricating a groove-based heterogeneous sandwich stepped weld resist structure according to an embodiment of the application. Figure 7 This is a schematic diagram of the multi-groove process flow for a method of fabricating a grooved heterogeneous sandwich stepped weld resist structure according to an embodiment of the application. Figure 6 As shown in Figure 7, based on a semiconductor wafer that has completed the front-end process, a semiconductor substrate, an interlayer dielectric layer, a metal interconnect layer 100, and a passivation layer have been formed on the wafer.

[0054] A trench 101 is formed above the metal interconnect layer 100. For example... Figure 8 As shown in the schematic diagram of the single trench 101MT photomask, specifically, photoresist is coated on the surface of the metal interconnect layer 100, and a photoresist pattern is formed by exposure and development. This pattern defines the position and shape of the trench 101. Using the photoresist pattern as a mask, the metal interconnect layer 100 is etched using a wet etching process. Due to the isotropic nature of wet etching, the etched trench 101 has curved sidewalls. After etching, the photoresist is removed.

[0055] Preferably, when it is necessary to form multiple trenches 101 above the metal interconnect layer 100, such as Figure 9 As shown in the schematic diagram of the multi-groove 101MT photomask, multiple grooves 101 are etched using the same process.

[0056] like Figure 6 As shown in Figure 7, an insulating dielectric layer 102 and a solder resist layer 103 are simultaneously formed above the passivation layer and the trench 101, and both the insulating dielectric layer 102 and the solder resist layer 103 are simultaneously etched to leave solder resist openings. Specifically, a photosensitive polyimide precursor solution is coated using a spin-coating process, and after pre-baking, exposure, development, and curing processes, a polyimide solder resist layer 103 is formed. The polyimide solder resist layer 103 covers the upper surface of the passivation layer and the inner wall of the trench 101, forming a stepped structure at the location of the trench 101. Specifically, solder resist openings are formed in the polyimide solder resist layer 103 using photolithography and etching processes, and the solder resist openings expose part of the upper surface of the electroless plating metal layer 104.

[0057] Preferably, the etching angle is controlled between 70-80° horizontally to ensure that the solder resist layer 103 covers the insulating dielectric layer 102 in the solder resist opening. At the same time, the gravity of the electroplated metal layer 104 is used to abut and maintain the stability of the solder resist layer 103 and the insulating dielectric layer 102, thereby improving the stability of the solder resist layer 103 and the step structure.

[0058] like Figure 6 As shown in Figure 7, a chemically plated metal layer 104 is formed at the solder resist opening position of the insulating dielectric layer 102 and the solder resist layer 103.

[0059] By following the above steps, the groove-based heterogeneous sandwich stepped weld resistance structure of any embodiment of this application can be obtained.

[0060] During the testing process, it was found that the solder resist structure of this embodiment enhances the solder resist effect and extends the moisture intrusion path through the following mechanism: (1) Interface migration blocking mechanism: The migration of moisture at the interface between the polyimide solder resist layer 103 and the metal interconnect layer 100 is the main pathway for moisture intrusion. In this embodiment, the trench 101 forms a "trench" on the upper surface of the metal interconnect layer 100, so that the continuous interface is cut off at the trench 101, and the moisture cannot continue to migrate horizontally along the original interface, but must cross the trench 101 downwards.

[0061] In the case of multiple trenches 101, multiple trenches 101 form multiple "trenches" on the upper surface of the metal interconnect layer 100, cutting off the continuous metal interconnect layer 100 / PI interface at multiple locations one by one. When moisture migrates along the interface, it first encounters the first trench 101, where the interface is blocked; after crossing the first trench 101, the moisture migrates horizontally along the interval area for a distance, and then encounters the second trench 101, where the interface is blocked again; this process repeats, and the moisture needs to cross each trench 101 step by step to continue to penetrate inward.

[0062] (2) Path extension mechanism: The depth H and width W of the trench 101 add an extra path length for moisture intrusion. According to Fick's first law, the diffusion flux is inversely proportional to the diffusion path length. The extension of the path directly leads to a decrease in the moisture diffusion flux.

[0063] In the case of multiple grooves 101, let there be a total of n grooves 101, the depth of the i-th groove 101 be Hi, and the distance between adjacent grooves 101 be Di. Then, the total increase in path length required for moisture to cross all grooves 101 is approximately Σ(2Hi) + ΣDi. As the number of grooves 101 increases, the path length increases approximately linearly.

[0064] (3) Anchoring reinforcement mechanism: The arc sidewall of the trench 101 provides more contact area and more complex anchoring structure for the insulating dielectric layer 102, which significantly enhances the bonding strength between the insulating dielectric layer 102 and the underlying structure and effectively prevents PI peeling.

[0065] In the case of multiple grooves 101, the arc-shaped sidewalls of multiple grooves 101 provide a large number of anchoring points for the insulating dielectric layer 102, forming a "comb-like" anchoring structure, which significantly enhances the bonding strength between the insulating dielectric layer 102 and the underlying structure.

[0066] (4) Solder intrusion blocking mechanism: During the packaging reflow soldering process, when the wetting front of the molten solder reaches the trench 101, the geometric change caused by the step structure makes it difficult for the solder to continue wetting upwards, thus playing a blocking role. The trench 101 acts as the first moisture barrier, and the PI step acts as the second barrier. The two work together to achieve a highly efficient moisture and solder protection effect with a small chip area.

[0067] In the case of multiple grooves 101, the wetting front of the molten solder is blocked for the first time when it encounters the first step formed by the first groove 101; even if it breaks through the first line of defense, it is blocked for the second time when it encounters the second step formed by the second groove 101; this process repeats, and the continuous blocking formed by multiple steps greatly improves the reliability of the solder resist.

[0068] (5) Gradual decay mechanism of moisture concentration: When there are multiple trenches 101, when moisture crosses each trench 101, some moisture will be captured or blocked by the trench 101 structure and will not be able to continue to penetrate inward. After the gradual decay of multiple trenches 101, the moisture concentration reaching the sensitive area inside the device has been greatly reduced.

[0069] (6) Composite layer solder resist mechanism: Based on the preferred materials, an inorganic / organic composite interface is formed between the insulating dielectric layer 102 and the solder resist layer 103. Due to the significant difference in properties between the two materials, this composite interface has a good blocking effect against the intrusion of moisture and solder. The solder resist layer 103 covers the edge portion of the insulating dielectric layer 102 and the electroplated metal layer 104, forming an interlayer step between the insulating dielectric layer 102 and the solder resist layer 103. This step structure extends the path length for moisture and solder intrusion, increasing the difficulty of intrusion, thereby effectively preventing solder intrusion and moisture intrusion.

[0070] The method for fabricating a trench-based heterogeneous sandwich stepped solder resist structure according to any embodiment of this application can be widely applied in the manufacturing and packaging process of silicon carbide MOSFET power devices. It has the advantages of low process cost and good protection effect, and possesses good prospects for industrial application and economic value. The trench 101 fabrication process is highly compatible with existing semiconductor manufacturing processes, requiring only the addition of the trench 101 pattern to the existing photomask, without the need for additional complex equipment and processes, resulting in low process cost and ease of implementation.

[0071] The following points should be noted regarding this application: (1) The accompanying drawings of the embodiments of this application only involve the structures involved in the embodiments of this application. Other structures can be referred to the general design.

[0072] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0073] (3) Where there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other to obtain new embodiments. The above are only specific implementations of this application, but the protection scope of this application is not limited thereto, and the protection scope of this application shall be determined by the protection scope of the claims.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

[0076] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure, characterized in that, Including the following steps: At least one trench is etched into the metal interconnect layer; An insulating dielectric layer and a solder resist layer are sequentially covered on the metal interconnect layer and the passivation layer, with an opening left to accommodate the electroless metal plating layer. A chemically plated metal layer is formed at the opening.

2. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to claim 1, characterized in that, The sidewalls of the trench are arc surfaces or inclined surfaces formed by isotropic etching.

3. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to claim 1, characterized in that, The bottom of the trench extends to the interlayer dielectric layer beneath the passivation layer.

4. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to claim 1, characterized in that, The metal interconnect layer has at least three trenches.

5. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to any one of claims 1 to 4, characterized in that, The trench is arranged in a ring around the metal interconnect layer.

6. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to any one of claims 1 to 4, characterized in that, The metal interconnect layer is an alloy layer.

7. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to claim 1, characterized in that, An adhesion enhancement layer is provided between the insulating dielectric layer and the solder resist layer; The adhesion enhancement layer is used to improve the bonding strength between the insulating dielectric layer and the solder resist layer.

8. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to claim 1, characterized in that, The electroplated metal layer has a NiPdAu stacked structure.

9. The method for fabricating a groove-based heterogeneous sandwich stepped weld resistance structure according to claim 1, characterized in that, The insulating dielectric layer is an inorganic dielectric layer, and the solder resist layer is an organic dielectric layer.

10. A semiconductor device, characterized in that, The trench-based heterostructured step solder resist structure includes a semiconductor substrate, a metal interconnect layer located above the semiconductor substrate, a passivation layer, and is fabricated using the method for fabricating a trench-based heterostructured step solder resist structure as described in any one of claims 1 to 9.

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