Digital signal processing device and control method of digital signal processing device
By using buffer memory and delay unit in a digital signal processing device, combined with the control of sampling period and burst length, audio data with multiple delay time combinations is generated, which solves the delay time limitation caused by burst transmission in the prior art and achieves high-quality audio effects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KAWAI MUSICAL INSTR MFG CO LTD
- Filing Date
- 2021-10-12
- Publication Date
- 2026-06-05
AI Technical Summary
In existing technologies, the burst transmission using DRAM limits the delay time of acoustic waveform data to a multiple of the burst length, making it impossible to achieve high-quality results, especially when multiple delayed signals are strongly correlated periodically.
Using a first buffer memory, a second buffer memory, DRAM, and a delay unit, the writing and reading of audio data are controlled by a control unit. By combining the delay time of the sampling period and the burst length, audio data with multiple delay time combinations is generated.
It enables the combination of audio data delay times in units of sampling periods to generate high-quality reverb effects, avoiding the periodicity problem of burst length multiple limitations.
Smart Images
Figure CN114363769B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a digital signal processing apparatus and a control method for the digital signal processing apparatus. Background Technology
[0002] Patent Document 1 describes an address circuit for performing virtual shifting within a digital signal processing device. The address circuit combines an auxiliary index register with an index register, sets the auxiliary index register to a value identical to the lower bit of the index register, retrieves the upper address from the index register, retrieves the lower address from the auxiliary index register, performs normal index modification, and sets the auxiliary index register to the value obtained by adding the lower bit of the index register to the pointer, performing address modification for virtual shifting.
[0003] Patent Document 2 describes an address generation circuit having a first counter and a second counter. A clearing unit selectively clears the contents of the second counter to zero based on a counting control signal for the first counter. An adder adds the output of the first counter to the output of the second counter.
[0004] Patent Document 3 describes a digital signal processing apparatus for acoustic waveform data, comprising a waveform signal processing unit and a memory access unit. The waveform signal processing unit performs waveform signal processing to apply effects to the acoustic waveform data using M time-division waveform signal processings (M being an integer of 2 or more). The memory access unit, for a DRAM that has K external memory banks corresponding to K time-division waveform signal processings (K being an integer of 2 or more, less than M) to delay the acoustic waveform data during waveform signal processing, can access the K memory banks at K staggered timings. When a write or read request is received from one of the K time-division waveform signal processings, for the DRAM, a control signal for writing or reading the corresponding memory bank is output according to the timing at which memory access can begin, thereby performing the writing or reading of acoustic waveform data.
[0005] Existing technical documents
[0006] Patent documents
[0007] Patent Document 1: Japanese Patent Application Publication No. 58-2935
[0008] Patent Document 2: Japanese Patent Application Publication No. 62-57067
[0009] Patent document 3 Japanese Patent Application Publication No. 2003-108122 Summary of the Invention
[0010] The problem that the invention aims to solve
[0011] In Patent Document 3, the acoustic waveform data is delayed in order to apply an effect. However, if burst transmission of DRAM is used, the delay time of the acoustic waveform data is limited to a multiple of the burst length. When multiple delayed signals are all multiples of the burst length, strong correlation occurs due to their periodicity, making it impossible to achieve a high-quality effect.
[0012] The object of the present invention is to generate audio data having a delay time that is a combination of a delay time that is a multiple of the burst length relative to the sampling period and a delay time in units of the sampling period.
[0013] Methods for solving problems
[0014] The digital signal processing apparatus of the present invention comprises: a first buffer memory for storing audio data; a second buffer memory for storing audio data; a DRAM for burst transmission of audio data of burst length; a delay unit for delaying audio data in units of sampling periods; and a control unit that controls the sequential writing of audio data word by word into the first buffer memory according to the sampling period, burst transmission of the audio data of burst length from the first buffer memory to the DRAM, and controls the burst transmission of the audio data of burst length from the DRAM to the second buffer memory, and sequential output of audio data word by word from the second buffer memory to the delay unit according to the sampling period, wherein the delay time of the audio data output by the delay unit is determined by a combination of delay times in units of multiple sampling periods depending on the burst length of the DRAM and delay times in units of the sampling period of the delay unit.
[0015] The present invention discloses a control method for a digital signal processing apparatus, the digital signal processing apparatus comprising: a first buffer memory for storing audio data; a second buffer memory for storing audio data; a DRAM for burst transmission of audio data of burst length; and a delay unit for delaying audio data in units of sampling periods. The control method includes the following steps: sequentially writing audio data word by word into the first buffer memory according to the sampling period; controlling the burst transmission of audio data of the burst length from the first buffer memory to the DRAM; controlling the burst transmission of audio data of the burst length from the DRAM to the second buffer memory; and sequentially outputting audio data word by word from the second buffer memory to the delay unit according to the sampling period, wherein the delay time of the audio data output by the delay unit is determined by a combination of delay times in units of multiple sampling periods depending on the burst length of the DRAM and delay times in units of the sampling period of the delay unit.
[0016] Invention Effects
[0017] According to the present invention, it is possible to generate audio data having a delay time that is a combination of a delay time that is a multiple of the burst length relative to the sampling period and a delay time in units of the sampling period. Attached Figure Description
[0018] Figure 1 This is a diagram showing a structural example of a digital signal processing apparatus according to this embodiment.
[0019] Figure 2 This is a diagram illustrating the method of accessing the first buffer memory.
[0020] Figure 3 This is a diagram illustrating the method of accessing the second buffer memory.
[0021] Label Explanation
[0022] 100 Digital Signal Processing Device
[0023] 101 CPU
[0024] 102 Program ROM
[0025] 103 Working RAM
[0026] 104 bus
[0027] 105 Analog / Digital Converter
[0028] 106 DSP
[0029] 107 Buffer Memory
[0030] 108 Digital-to-Analog Converters
[0031] 109 bus
[0032] 110, 111 SDRAM
[0033] 112 Shift Register
[0034] 113 Selector
[0035] 114 Delay section Detailed Implementation
[0036] Figure 1 This diagram illustrates a structural example of the digital signal processing apparatus 100 according to this embodiment. The digital signal processing apparatus 100 is, for example, a device for implementing reverb effects. When an original sound is generated, the direct tone and delayed tone of the original sound are combined and reach the human ear. The direct tone is the sound of the original sound directly reaching the human ear. The delayed tone is a plurality of delayed tones with different delay times generated due to the original sound being reflected by various objects. The digital signal processing apparatus 100 generates multiple delayed signals with different delay times for the audio data of the original sound, and combines the audio data of the original sound with the multiple delayed signals, thereby achieving reverb.
[0037] The digital signal processing apparatus 100 includes a CPU 101, a program ROM 102, a working RAM 103, a bus 104, an analog-to-digital converter 105, a DSP 106, first and second buffer memories 107, a digital-to-analog converter 108, a bus 109, SDRAM 110, SDRAM 111, and a delay unit 114. The delay unit 114 includes a shift register 112 and a selector 113. The control method of the digital signal processing apparatus 100 will be described below.
[0038] Each of the first buffer memory 107 and the second buffer memory 107 is capable of inputting and outputting 32-bit (1 word) wide audio data to the bus 109. The first buffer memory 107 and the second buffer memory 107 are, for example, SRAM (Static Random Access Memory) and are capable of storing audio data.
[0039] SDRAM110 and 111 are synchronous dynamic random access memory, a type of DRAM (Dynamic Random Access Memory). SDRAM 110 and 111 are, for example, DDR3 SDRAM.
[0040] The SDRAM110 is capable of inputting and outputting 16-bit (1 word) audio data to bus 109.
[0041] The first and second buffer memories 107 are respectively capable of inputting and outputting 32-bit (1 word) audio data to SDRAMs 110 and 111 via bus 109. The 16-bit audio data input and output by SDRAM 110 is the high-order 16 bits of the 32-bit audio data input and output by the first or second buffer memory 107. The 16-bit audio data input and output by SDRAM 111 is the low-order 16 bits of the 32-bit audio data input and output by the first or second buffer memory 107.
[0042] SDRAMs 110 and 111 are capable of burst-transmitting audio data of burst lengths of two words or more to the first and second buffer memories 107 via bus 109. That is, SDRAMs 110 and 111, based on a single address, transmit audio data of a burst length of words at high speed to each of the first and second buffer memories 107 consecutively via bus 109. The burst length can be, for example, four words or eight words. The following explanation uses the case of an eight-word burst length as an example.
[0043] CPU 101 is a central processing unit. Program ROM (Read-Only Memory) 102 stores the program. Working RAM (Random Access Memory) 103 functions as the working area of CPU 101. CPU 101 expands the program stored in Program ROM 102 into Working RAM 103 and controls DSP 106 by executing the program expanded into Working RAM 103. DSP 106 is a digital signal processor, a type of control unit.
[0044] The analog-to-digital converter 105 takes an analog audio signal input from a microphone or other source and converts it into one digit (32 bits) of digital audio data according to the sampling period. The audio data is musical tone data or sound data.
[0045] The DSP 106 writes the digital audio data converted by the analog-to-digital converter 105 word by word into the first buffer memory 107 according to the sampling period. In addition, the DSP 106 can also replace the analog-to-digital converter 105 to input digital audio data from a music generation device or an audio receiving device.
[0046] Next, DSP106 controls the transmission of audio data of burst length (8 words) from the first buffer memory 107 to SDRAMs 110 and 111. DSP106 writes audio data of burst length (8 words) to the addresses indicated by the write pointers of SDRAMs 110 and 111.
[0047] Next, DSP 106 controls the burst transfer of audio data (8 words) from SDRAM 110 and 111 to the second buffer memory 107. Simultaneously, DSP 106 controls the reading of the burst-length audio data (8 words) from the addresses indicated by the read pointers of SDRAM 110 and 111, performing the burst transfer. Through this burst transfer, DSP 106 writes the burst-length audio data (8 words) into the second buffer memory 107.
[0048] The difference between the address represented by the write pointer and the address represented by the read pointer of SDRAM110 and 111 corresponds to the delay time of the delayed signal relative to the original tone. This delay time is a multiple (a multiple of 8) of the burst length of the sampling period.
[0049] SRAM can also be used to generate delayed signals instead of SDRAM110 and 111, but a large capacity SRAM is required to generate delayed signals with long delay times. SRAM is more expensive than SDRAM110 and 111. Therefore, in this embodiment, using SDRAM110 and 111 to generate delayed signals reduces costs. Furthermore, by using burst transmissions of SDRAM110 and 111, many delayed signals can be generated in real time and at high speed.
[0050] Next, the DSP106 reads the audio data transmitted to the second buffer memory 107 in units of one word according to the sampling period, and outputs the read audio data to the delay unit 114.
[0051] The delay unit 114 has a shift register 112 and a selector 113, which delays the audio data read from the second buffer memory 107 by a sampling period, and outputs the delayed audio data as a delayed signal to the DSP 106.
[0052] Shift register 112 includes multiple registers for storing audio data read from second buffer memory 107, and shifts the audio data stored in the multiple registers in units of sampling periods. Selector 113 selects at least one output data from the multiple registers and outputs the selected output data as a delayed signal relative to the original sound to DSP 106. The selection by selector 113 corresponds to the delay time of the delayed signal relative to the original sound.
[0053] Next, DSP106 synthesizes the original audio data converted by analog-to-digital converter 105 with the aforementioned delayed signal, and outputs the synthesized audio data to digital-to-analog converter 108. Alternatively, DSP106 may not be required to synthesize the audio data; the synthesis can be performed by an external device.
[0054] The digital-to-analog converter 108 converts one digit (32 bits) of digital audio data into an analog audio signal according to the sampling period, and outputs the analog audio signal to the audio system. The audio system has an amplifier and a speaker; the amplifier amplifies the audio signal, and the speaker emits the amplified audio signal. This produces a sound with a reverberation effect on the original audio.
[0055] Figure 2 This diagram illustrates the access method of the first buffer memory 107. The first buffer memory 107 is a ring buffer capable of storing 8 words of audio data. The sampling periods T0 to T8 are the sampling periods of the analog-to-digital converter 105.
[0056] During the sampling period T0, the DSP106 writes one word of audio data W(0) converted by the analog-to-digital converter 105 to the first address of the first buffer memory 107.
[0057] The sampling period T1 is the sampling period one sampling period after the sampling period T0. In the sampling period T1, the DSP106 writes one word of audio data W(1) converted by the analog-to-digital converter 105 to the second address of the first buffer memory 107.
[0058] The sampling period T2 is the sampling period two sampling periods after the sampling period T0. In the sampling period T2, the DSP106 writes one word of audio data W(2) converted by the analog-to-digital converter 105 to the third address of the first buffer memory 107.
[0059] Similarly, during sampling periods T3 to T6, DSP106 writes the audio data W(3) to W(6) of one word converted by analog-to-digital converter 105 to the 4th to 7th addresses of the first buffer memory 107, respectively.
[0060] The sampling period T7 is the sampling period seven sampling periods after the sampling period T0. In the sampling period T7, the DSP106 writes one word of audio data W(7) converted by the analog-to-digital converter 105 to the 8th address of the first buffer memory 107.
[0061] DSP106 transmits the eight words of audio data W(0)~W(7) stored in the first buffer memory 107 in a burst to SDRAM110 and 111 according to the sampling period T7, and writes the eight words of audio data W(0)~W(7) into SDRAM110 and 111.
[0062] The sampling period T8(T0) is the sampling period 8 sampling periods after the sampling period T0. In the sampling period T8(T0), the DSP106 writes (overwrites) one word of audio data W(8) converted by the analog-to-digital converter 105 to the first address of the first buffer memory 107.
[0063] Similarly, during sampling periods T9 to T15, DSP106 writes (overwrites) the audio data W(9) to W(15) of one word converted by analog-to-digital converter 105 to the second to eighth addresses of the first buffer memory 107, respectively.
[0064] Then, the DSP106 transmits the eight words of audio data W(8) to W(15) stored in the first buffer memory 107 in a burst to SDRAM110 and 111 according to the sampling period T15, and writes the eight words of audio data W(8) to W(15) into SDRAM110 and 111.
[0065] Similarly, DSP106 transmits the audio data stored in the first buffer memory 107 in bursts of 8 words to SDRAM110 and 111 every 8 sampling cycles.
[0066] As described above, the DSP106 is controlled in the following manner: during the sampling periods T0 to T8, the audio data converted by the analog-to-digital converter 105 is written word by word into the first buffer memory 107. During the eight sampling periods, audio data of burst length is transmitted from the first buffer memory 107 to the SDRAM 110 and 111.
[0067] Figure 3 This diagram illustrates the access method of the second buffer memory 107. The second buffer memory 107 is a ring buffer capable of storing 8 words of audio data. The sampling periods T0 to T3 are the sampling periods of the analog-to-digital converter 105, respectively.
[0068] The delay unit 114 includes a shift register 112 and a selector 113. The shift register 112 includes seven registers 112a to 112g for storing audio data, and shifts the audio data stored in the seven registers 112a to 112g in units of sampling period. The selector 113 selects either the audio data output from the second buffer memory 107 or the output data from the seven registers 112a to 112g.
[0069] During the sampling period T0, DSP106 transmits the audio data W(0) to W(7) bursts of the burst length (8 words) stored in SDRAM110 and 111 to the second buffer memory 107.
[0070] exist Figure 2 In this process, DSP106 writes the audio data stored in the first buffer memory 107 to the addresses indicated by the write pointers of SDRAMs 110 and 111. Figure 3 During the sampling period T0, the DSP106 reads audio data from the addresses indicated by the read pointers of SDRAM110 and 111. The difference between the addresses indicated by the write pointers of SDRAM110 and 111 and the addresses indicated by the read pointers corresponds to the delay time of the delayed signal relative to the original sound. This delay time is a multiple of 8 of the sampling period (a multiple of the number of burst lengths).
[0071] During the sampling period T0, DSP106 reads one word of audio data W(0) stored in the first address of the second buffer memory 107, and outputs the read audio data W(0) to shift register 112 and selector 113. The audio data W(0) is stored in register 112g of shift register 112.
[0072] During sampling period T1, DSP106 reads audio data W(1) stored in the second address of the second buffer memory 107 and outputs the read audio data W(1) to shift register 112 and selector 113. Shift register 112 shifts the audio data stored in registers 112a to 112g. Audio data W(0) is stored in register 112f. Audio data W(1) is stored in register 112g.
[0073] During sampling period T2, DSP106 reads one word of audio data W(2) stored in the third address of the second buffer memory 107 and outputs the read audio data W(2) to shift register 112 and selector 113. Shift register 112 shifts the audio data stored in registers 112a to 112g. Audio data W(0) is stored in register 112e. Audio data W(1) is stored in register 112f. Audio data W(2) is stored in register 112g.
[0074] During sampling period T3, DSP106 reads one word of audio data W(3) stored at address 4 of the second buffer memory 107 and outputs the read audio data W(3) to shift register 112 and selector 113. Shift register 112 shifts the audio data stored in registers 112a to 112g. Audio data W(0) is stored in register 112d. Audio data W(1) is stored in register 112e. Audio data W(2) is stored in register 112f. Audio data W(3) is stored in register 112g.
[0075] Similarly, during sampling periods T4 to T6, DSP106 reads audio data W(4) to W(6) stored in the second buffer memory 107 and outputs the read audio data W(4) to W(6) to shift register 112 and selector 113.
[0076] During sampling period T7, DSP106 reads one word of audio data W(7) stored at address 8 of the second buffer memory 107 and outputs the read audio data W(7) to shift register 112 and selector 113. Shift register 112 shifts the audio data stored in registers 112a to 112g. Audio data W(0) to W(7) are stored in registers 112a to 112g respectively.
[0077] Then, the digital signal processing device 100 repeats the above-described sampling period T0 to T7. The DSP 106 controls the transmission of audio data with a burst length of 8 words from the SDRAM 110 and 111 to the second buffer memory 107 in 8 sampling periods, and outputs audio data word by word from the second buffer memory 107 to the delay unit 114 according to the sampling period.
[0078] Shift register 112 shifts the audio data stored in the seven registers 112a to 112g in units of sampling period. The seven registers 112a to 112b each output their stored audio data to selector 113.
[0079] Selector 113 selects either the audio data read from the second buffer memory 107 or the output data from the seven registers 112a to 112g, based on the set delay time, and outputs the delayed signal for the original sound to DSP 106.
[0080] When selector 113 selects audio data read from second buffer memory 107 and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time that is a multiple of 8 of the sampling period.
[0081] Furthermore, when selector 113 selects audio data output from register 112g and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 1.
[0082] Furthermore, when selector 113 selects audio data output from register 112f and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 2.
[0083] Furthermore, when selector 113 selects audio data output from register 112e and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 3.
[0084] Furthermore, when selector 113 selects audio data output from register 112d and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 4.
[0085] Furthermore, when selector 113 selects audio data output from register 112c and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 5.
[0086] Furthermore, when selector 113 selects audio data output from register 112b and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 6.
[0087] Furthermore, when selector 113 selects audio data output from register 112a and outputs the selected audio data to DSP 106, it can generate a delayed signal with a delay time of (a multiple of 8 of the sampling period) + (sampling period) × 7.
[0088] As described above, the delay unit 114 is capable of generating not only delay signals with delay times that are multiples of 8 of the sampling period (multiples of the burst length), but also delay signals with delay times in units of the sampling period. The delay time of the audio data output by the delay unit 114 is determined by a combination of delay times in units of multiple sampling periods that depend on the burst lengths of the SDRAMs 110 and 111, and delay times in units of the sampling period of the delay unit 114.
[0089] Furthermore, the delay unit 114 is not limited to using the shift register 112 and the selector 113. For example, the delay unit 114 may also use SRAM random access to delay the audio data in units of sampling periods.
[0090] The DSP106 receives a delay signal from the selector 113 and synthesizes the original audio data converted by the analog-to-digital converter 105 and the delay signal. The delay unit 114 generates multiple delay signals with different delay times through time-division processing. By synthesizing the original audio data and multiple delay signals, the DSP106 can achieve high-quality reverberation.
[0091] When multiple delayed signals are all multiples of the burst length of the sampling period, strong correlation occurs due to their periodicity, making it impossible to achieve high-quality reverberation. According to this embodiment, the delay unit 114 can generate not only delayed signals with delay times that are multiples of the burst length of the sampling period, but also delayed signals with delay times in units of the sampling period, thus achieving high-quality reverberation.
[0092] It should be noted that the above embodiments are merely specific examples illustrating the implementation of the present invention, and the technical scope of the present invention should not be limited by these embodiments. That is, the present invention can be implemented in various forms without departing from its technical concept or its main features.
Claims
1. A digital signal processing device, characterized in that, The digital signal processing device has: An analog-to-digital converter that transforms analog audio signals into digital audio data according to the sampling period; The first buffer memory used to store audio data; A second buffer memory for storing audio data; DRAM for burst transmission of audio data of burst length; A delay unit that delays audio data by the sampling period; as well as The control unit controls the sequential writing of audio data word by word into the first buffer memory according to the sampling period, the burst transmission of audio data of the specified burst length from the first buffer memory to the DRAM, and controls the burst transmission of audio data of the specified burst length from the DRAM to the second buffer memory, and outputs audio data word by word from the second buffer memory to the delay unit according to the sampling period. The delay time of the audio data output by the delay unit is determined by a combination of delay times in units of multiple sampling periods that depend on the burst length of the DRAM and delay times in units of the sampling period of the delay unit.
2. The digital signal processing apparatus according to claim 1, characterized in that, The delay unit has: A shift register comprising a plurality of registers for storing the audio data output from the second buffer memory, and the shift register shifting the audio data stored in the plurality of registers in units of the sampling period; and The selector selects at least one output data from the output data of the plurality of registers.
3. The digital signal processing apparatus according to claim 2, characterized in that, The selector selects either the audio data output from the second buffer memory or the output data from the plurality of registers.
4. The digital signal processing apparatus according to any one of claims 1 to 3, characterized in that, The DRAM mentioned is SDRAM.
5. A control method for a digital signal processing device, the digital signal processing device comprising: An analog-to-digital converter that transforms analog audio signals into digital audio data according to the sampling period; The first buffer memory used to store audio data; A second buffer memory for storing audio data; DRAM for burst transmission of audio data of burst length; and A delay unit that delays audio data by the sampling period. Its features are, The control method for the digital signal processing device includes the following steps: The audio data is written word by word sequentially into the first buffer memory according to the sampling period. Control is performed to transfer audio data of the burst length from the first buffer memory to the DRAM burst; Control is performed to burst-transfer audio data of the burst length from the DRAM to the second buffer memory; Audio data is output word by word sequentially from the second buffer memory to the delay unit according to the sampling period. The delay time of the audio data output by the delay unit is determined by a combination of delay times in units of multiple sampling periods that depend on the burst length of the DRAM and delay times in units of the sampling period of the delay unit.