Adaptive memory system

Abstract

This application relates to an adaptive memory system. The described devices and methods control the voltage or temperature of a memory domain to balance memory performance and energy usage. In some aspects, an adaptive controller monitors memory performance metrics of a host processor corresponding to commands made to a memory domain of a memory system, the memory domain including a memory domain operating at a low temperature. Based on the memory performance metrics, the adaptive controller can determine a memory performance requirement, such as a latency requirement or a bandwidth requirement, of the host processor for the memory domain. The adaptive controller can use the determined performance requirement to alter the voltage or temperature of the memory domain to achieve memory access performance tailored to meet the requirement of the host processor. By doing so, the adaptive controller can manage various settings of the memory domain to address short-term or long-term changes in memory performance requirements.

Description

Technical Field

[0001] This application relates to an adaptive memory system. Background Technology

[0002] Computers typically include processors that store data in the computer's main memory. For example, when a program on a computer executes on the processor, the processor accesses main memory to store or load data from main memory. Therefore, the performance of a program executing on a computer may depend on the processor's ability to access main memory for the data used by the program. The processor's ability to access main memory may be limited by the configuration of main memory (e.g., topology, timing, or bus width). Therefore, the processor's ability to access main memory may be limited by the configuration of the memory, which can affect the performance of programs executing on the computer. Summary of the Invention

[0003] One aspect of this application relates to an apparatus comprising: a memory array; at least one interface configured to be coupled to an interconnect of a host system and to receive commands issued to the memory array via the interconnect; and an adaptive controller configured to be coupled to the host system via the at least one interface, the adaptive controller being configured to: receive from the host system via the at least one interface one or more memory performance metrics relating to the commands issued to a domain of the memory array; determine memory performance requirements of the domain based on the one or more memory performance metrics received from the host system; and change at least one of a voltage setting or a temperature setting of the domain based on the memory performance requirements of the domain.

[0004] Another aspect of this application relates to an apparatus comprising: a memory array including one or more memory domains; a host coupled to the memory array, the host including one or more performance counters indicating corresponding memory performance metrics of the one or more memory domains; and an adaptive controller including an interface configured to access the one or more performance counters of the processor, the adaptive controller being configured to: monitor the corresponding memory performance metric corresponding to one of the one or more memory domains via the one or more performance counters of the host; determine a memory performance requirement for the memory domain based on the corresponding memory performance metric; determine a voltage or temperature for the memory domain based on the memory performance requirement of the memory domain; and change a voltage setting or temperature setting of the memory domain using the voltage or temperature determined for the memory domain.

[0005] Another aspect of this application relates to a method comprising: receiving, via a host interface of an adaptive controller, one or more memory performance metrics relating to a command issued by a host to a memory domain of a memory array coupled to the host via an interconnect; determining, by the adaptive controller, a memory performance requirement of the memory domain based on the one or more memory performance metrics; and changing, by the adaptive controller, a voltage setting or a temperature setting of the memory domain based on the memory performance requirement of the memory domain.

[0006] Another aspect of this application relates to a method comprising: during a first time interval, receiving one or more memory performance metrics regarding a command issued by a host to a memory domain of a memory array coupled to the host; during a second time interval, predicting a memory performance requirement of the memory domain based on the one or more memory performance metrics; and before or during the second time interval, changing a voltage setting or a temperature setting of the memory domain based on the memory performance requirement of the memory domain.

[0007] Another aspect of this application relates to an apparatus comprising: a memory array including one or more memory domains; a host coupled to the memory array, the host including one or more programs configured for quantum processing; a control processor coupled to the memory array, the control processor including a quantum execution unit configured to manage the execution of the one or more programs and one or more performance counters indicating corresponding memory performance metrics of the one or more memory domains; a quantum processing substrate coupled to the quantum execution unit of the control processor, the quantum processing substrate being configured to execute the one or more programs; and an adaptive controller including an interface configured to access the one or more performance counters of the control processor, the adaptive controller being configured to: monitor the corresponding memory performance metric corresponding to one of the one or more memory domains via the one or more performance counters of the control processor; determine a memory performance requirement for the memory domain based on the corresponding memory performance metric; determine a voltage or temperature for the memory domain based on the memory performance requirement of the memory domain; and change the voltage setting or temperature setting of the memory domain using the voltage or temperature determined for the memory domain. Attached Figure Description

[0008] The following figures illustrate the apparatus and techniques of an adaptive memory system. The same reference numerals are used throughout the figures to indicate similar features and components:

[0009] Figure 1 An exemplary device for implementing an adaptive memory system is shown;

[0010] Figure 2 An exemplary adaptive memory system is shown, in which the host processor is coupled to the cryogenic memory via a multi-bus interconnect.

[0011] Figure 3 An example of a temperature-controlled memory domain in an adaptive memory system implemented according to one or more aspects is shown;

[0012] Figure 4 An exemplary configuration of an adaptive controller that can implement multiple aspects of an adaptive memory system is shown;

[0013] Figure 5 An exemplary configuration of a memory demand predictor that can predict the performance of a temperature-controlled memory domain is shown.

[0014] Figure 6 An example of a memory demand predictor with voltage and temperature time intervals is shown;

[0015] Figure 7 An exemplary configuration of adaptive control logic is shown, which modifies the settings of the temperature control memory domain based on one or more aspects.

[0016] Figure 8 An exemplary server device is shown that can implement multiple aspects of an adaptive memory system;

[0017] Figure 9 An exemplary quantum computing device is shown that can implement multiple aspects of an adaptive memory system;

[0018] Figure 10 An exemplary method for changing the voltage or temperature settings of a temperature control memory domain is described based on one or more aspects.

[0019] Figure 11 An exemplary method for changing the settings of a temperature-controlled memory domain based on memory performance metrics from previous memory accesses is described.

[0020] Figure 12 A flowchart depicts an exemplary approach for an adaptive controller to be implemented in a temperature-controlled memory domain based on predicted memory requirements;

[0021] Figure 13A An exemplary method for configuring voltage-time windows for a temperature-controlled memory domain is described.

[0022] Figure 13B An exemplary method for configuring temperature time windows for a temperature-controlled memory domain is described.

[0023] Figure 14 An exemplary method for adjusting the error correction code settings of a temperature-controlled memory domain is described; and

[0024] Figure 15 An exemplary method for adjusting the error correction code of a temperature-controlled memory domain based on the memory error rate is described. Detailed Implementation

[0025] Overview

[0026] Computers use processors, which are communication-coupled to memory, to provide services and features. When a computer's program executes on the processor, the processor accesses main memory to store program data in or load program data from main memory. Therefore, the performance of a program executing on a computer can depend on the processor's ability to access main memory for the data used by the program. The processor's ability to access main memory may be limited by the configuration of the main memory (e.g., frequency or voltage settings), which can be static and determined at the time the computer is designed or manufactured. In some cases, a computer's main memory is configured to provide memory access suitable for programs with specific memory access patterns. However, most computers execute multiple programs with correspondingly different memory access patterns or programs with memory access patterns that change over time. Therefore, for a static configuration, the access provided to the computer's main memory often does not match the memory access patterns of many programs, which can impair the performance of these programs when they execute on the computer.

[0027] Compared to the aforementioned memory designs with static configurations, this disclosure describes several aspects of an adaptive memory system in which host access to the memory domain alters operating parameters or conditions of the memory domain. For example, an adaptive controller of the memory system can monitor memory performance metrics regarding host access to a temperature-controlled memory domain. Based on these performance metrics, the adaptive controller can determine (e.g., predict) the memory performance requirements of the temperature-controlled memory domain. The adaptive controller can then modify the voltage or temperature settings of the temperature-controlled memory domain based on the determined performance requirements. In some cases, the adaptive controller increases the voltage setting or decreases the temperature setting of the temperature-controlled memory domain to improve its performance, for example, when the performance requirements exceed the performance provided by current operating conditions. In other cases, the adaptive controller decreases the voltage setting or increases the temperature setting of the temperature-controlled memory domain to reduce its energy consumption, for example, when the performance requirements are less than the performance provided by current operating conditions. Therefore, the adaptive controller can balance memory performance and energy consumption of the temperature-controlled memory domain based on host access to improve the energy efficiency of the computing system relative to a given performance level.

[0028] In the context of memory performance relative to temperature, the voltage sensitivity of some memory technologies, such as Dynamic Random Access Memory (DRAM), may be higher at temperatures below room temperature. Furthermore, low operating temperatures can also affect the semiconductor-level physical characteristics of memory devices, where cooled (e.g., cryogenic) memory exhibits significantly reduced latency and power consumption. In several ways, this enables adaptive controllers to use the voltage and / or temperature of the memory domain to control and optimize the performance of the memory domain in response to short-term or long-term variations in memory access (e.g., access intensity). For example, an adaptive controller can adjust the voltage for short-term variations in memory access intensity and the temperature for long-term variations. Because some memory operations and software execution phases of the host are sensitive to bandwidth or latency while others are not, host memory sensitivity (e.g., bandwidth or latency sensitivity) is variable, and the adaptive controller can monitor said host memory sensitivity through host memory performance metrics or the host processor. Based on the host or software memory sensitivity, the adaptive controller can determine (e.g., predict) the memory performance requirements of the memory domain. The adaptive controller can use these memory performance requirements to adapt the performance of the memory domain to variations in memory sensitivity by controlling the voltage or temperature of the memory domain. Furthermore, there are energy costs associated with cooling the memory domain, which can be traded off against memory performance by adjusting temperature (e.g., cooling power levels). Therefore, the described adaptive controller can balance memory performance and energy consumption based on the constantly changing memory performance requirements of the software executing on the host, thereby reducing the cost of operating computing systems such as large data centers or quantum computers.

[0029] In several ways, the adaptive controller modifies the voltage or temperature of a temperature-controlled memory domain to balance memory performance and energy usage. In some implementations, the adaptive controller monitors memory performance metrics of the host processor corresponding to commands or requests made to a memory domain of the memory system (e.g., a temperature-controlled memory domain), which includes memory domains operating at low temperatures. Based on the memory performance metrics, the adaptive controller can determine (e.g., predict) the host processor's memory performance requirements for the memory domain, such as latency or bandwidth requirements. The adaptive controller can use the determined memory performance requirements to modify the voltage or temperature of the memory domain to achieve memory access performance tailored to meet the host processor's memory performance requirements. Alternatively or additionally, the adaptive controller can adjust error correction codes applied to the data in the memory domain to address changes in memory reliability due to changes in memory voltage or temperature. By doing so, the adaptive controller can manage various settings of the memory domain to address short-term or long-term variations in memory performance requirements. These are just a few exemplary aspects of adaptive memory systems, while other aspects of adaptive memory systems are described herein. Exemplary Operating Environment

[0030] Figure 1 An exemplary device 100 is shown that can implement an adaptive memory system. Device 100 can be implemented as, for example, at least one electronic device. Exemplary electronic device implementations of device 100 include a notebook computer 100-1, a desktop computer 100-2, a server computer 100-3, a server cluster 100-4, and a quantum computing system 100-5. Other device examples include entertainment devices, such as set-top boxes or smart TVs; motherboards or blade servers; rack-based computing and / or memory resources; consumer appliances; vehicles; industrial equipment; and so on. Each type of electronic device includes one or more components to provide some computing functions, services, or features.

[0031] In an exemplary embodiment, device 100 includes at least one host 102 (e.g., a host system or host device), at least one processor 104, and an adaptive memory controller 106 (adaptive controller 106). Device 100 also includes at least one memory controller 108, at least one interconnect 110, and a memory system 112 (e.g., a memory array) including at least one cryogenic memory 114. Interconnect 110 logically couples host 102 to memory system 112 and enables host 102 or its components to transfer data to or from memory system 112. In the illustrated example, memory system 112 of device 100 includes cryogenic memories 0 114-0 to cryogenic memories n 114-n, where n is any suitable integer. An example of cryogenic memory 114 may include one or more memory devices 116, cooling devices 118, voltage regulators 120, clock circuitry (not shown), sensors (not shown), etc. Typically, the cooling device 118 of the cryogenic storage 114 provides a thermal domain, and one or more storage devices 116 are grouped into said thermal domain as a temperature-controlled storage domain (or region). One or more storage devices 116 may also operate from a voltage domain provided by the voltage regulator 120 (e.g., sharing an operating voltage), such that the temperature or voltage of the temperature-controlled storage domain can be independently configured by the adaptive controller 106. Figure 1 As shown, the cryogenic storage 114-0 is implemented with a storage device 116-0, a cooling device 118-0, and a voltage regulator 120-0, which correspond to a temperature-controlled storage domain of the storage system 112. Other examples of the storage system 112 and the temperature-controlled storage domain are described herein.

[0032] The cryogenic memory 114 can be implemented using memory devices 116 of any suitable type, configuration, quantity, or combination. The memory devices 116 of the cryogenic memory 114 can include dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), flash memory, etc. In some cases, the memory device 116 includes three-dimensional (3D) stacked DRAM devices, such as high-bandwidth memory (HBM) devices or hybrid memory cube (HMC) devices. Additionally or alternatively, the memory device 116 can include storage-type memory devices, such as those employing 3DXPoint. TM Or a phase-change memory (PCM) memory device. The memory device 116 of the cryogenic memory 114 can be configured or organized as an array of devices, modules (e.g., dual in-line memory modules (DIMMs)), cards, chips, dies, etc. These are just a few examples of cryogenic memories 114, while other cryogenic memories are described herein.

[0033] like Figure 1As shown, host 102 or host system 102 includes processor 104, adaptive controller 106, and memory controller 108. Although not shown, host 102 may also include one or more cache memories coupled to processor 104. The processor is coupled to adaptive controller 106 and directly or indirectly coupled to memory controller 108. Host 102 is coupled to memory system 112 via interconnect 110. In various aspects, adaptive controller 106 may also be coupled to memory controller 108 and / or interconnect 110.

[0034] The components depicted in device 100 represent an exemplary computing architecture including an adaptive memory system. Memory system 112 is logically coupled to host 102 via interconnect 110 and can be used as the main memory for processor 104 of device 100. The indicated interconnect 110, and other interconnects that communicatively couple various components together, enable data transfer between the components. Interconnect examples include buses, switching structures, one or more wires carrying voltage or current signals, etc.

[0035] Although the specific implementation of device 100 is Figure 1 The device 100 is depicted and described herein, but it can be implemented in alternative ways. For example, device 100 may include multiple memory systems 112 (e.g., cryogenic memory racks) coupled to host 102 via separate respective interconnects 110. In some embodiments, the memory systems 112 are coupled to host 102 via a first interconnect 110 and to an interface of a quantum processor or quantum substrate via a second interconnect 110. Other examples of these and other devices are depicted and described herein. Nevertheless, the components described herein can be implemented in alternative ways, including in distributed or shared memory systems. Furthermore, a given device 100 may contain more, fewer, or different components.

[0036] Figure 2 Generally, an exemplary embodiment of an adaptive memory system is shown in 200, in which a processor 104 (e.g., a host processor) of a device (e.g., device 100) is coupled to a memory system 112 via a multibus interconnect 110. In this example, an adaptive controller 106 is implemented separately from the host 102 on which the processor 104 is implemented and coupled to the host via a host interface. Thus, the adaptive controller 106 can be implemented as a separate component, part of the memory system 112, or part of the interconnect 110 between the host 102 and the memory system 112. In other embodiments, the processor 104 and the adaptive controller 106 are on the same host 102 (e.g., device 100). Figure 1 It can be implemented on the host 102 and can share the logical or processing resources of the host 102.

[0037] Host 102 is coupled to memory system 112 via interconnect 110, enabling processor 104 to transfer data to or from memory system 112. Here, interconnect 110 is implemented as a multi-bus interconnect 110 with multiple buses 202, including bus 0 202-0, bus 1 202-1, bus 2 202-2 to bus m 202-m, where m is any suitable integer. Although not shown, the interconnect buses 202 can be further divided into at least an address bus and a data bus for memory transactions via interconnect 110. Thus, processor 104 or memory controller 108 can communicate memory address information via the address bus of interconnect 110 and communicate data via the data bus. Memory requests, such as commands, messages, or instructions, can be communicated on interconnect 110, bus 202, address bus, data bus, command bus (not shown), or a combination thereof.

[0038] The interconnect 110 or bus 202 coupling host 102 to memory system 112 can be configured to operate on any suitable type of interface or protocol. In some cases, interconnect 110 includes a serialization interface, such as a serializer / deserializer (SerDes-based) memory interface, which includes serialization and deserialization components at the respective endpoints of interconnect 110 or bus 202. Through the SerDes-based memory interface, host 102 can implement split transaction memory access protocols to store data to or read data from memory system 112. Furthermore, the SerDes-based memory interface can operate at a fixed high frequency, independent of the latency or bandwidth of the cryogenic memory 114 of memory system 112. In other embodiments, interconnect 110 or bus 202 can be configured as a bus-based (e.g., DDR-compliant) interface, enabling host 102 and memory system 112 to exchange data or other information via parallel transfer operations. During the initialization or crossover of the operation settings of interconnect 110, the memory controller 108 of host 102 can retrain and configure the SerDes-based or bus-based interconnect 110.

[0039] Interconnect 110 can also operate according to one or more standards. Exemplary standards include DRAM standards published by the Joint Electronic Devices Engineering Committee (JEDEC) (e.g., Double Data Rate (DDR), DDR2, DDR3, DDR4, DDR5, etc.); stacked memory standards, such as HBM or HMC standards; peripheral component interconnect (PCI) standards, such as PCIe standards; compute fast link (CXL) standards; HyperTransport™ standards; InfiniBand standards; and external serial AT accessory (eSATA) standards. In addition to or in lieu of wired connections, interconnect 110 can be or may include wireless connections, such as connections using cellular, wireless local area network (WLAN), wireless personal area network (WPAN), or passive network standard protocols.

[0040] Interconnect 110 directly or indirectly couples the processor 104 of host 102 to the cryogenic memory 114 (e.g., a temperature-controlled memory domain) of memory system 112. Figure 2 As shown, processor 104 is coupled to interconnect 110 via a plurality of respective memory controllers 108-0, 108-1, 108-2 to 108-k, where k is any suitable integer. Buses 202-0 to 202-m of interconnect 110 couple memory controllers 108-0, 108-1, 108-2 to 108-k to respective cryogenic memories 114-0, 114-1, 114-0 to 104-n in memory system 112. In some cases, processor 104 is coupled to each cryogenic memory 114 via a respective memory controller 108 and interconnect bus 202 (e.g., integers k, m, and / or n are equal). In other cases, processor 104 may be coupled to multiple cryogenic memories 114 via memory controller 108 and / or multiple buses 202 (e.g., integers k, m, and / or n are not equal). Therefore, host 102, interconnect 110 and memory system 112 can be configured in various ways to implement multiple aspects of adaptive memory.

[0041] Figure 2The exemplary host 102 includes a processor 104 and memory controllers 108-0 to 108-k of the processor 104 accessing the memory system 112. Thus, in order to access data in a cryogenic memory 114, the processor 104 or the corresponding memory controllers 108-0 to 108-k issue or send a memory request via corresponding buses 202-0 to 202-m of interconnect 110. The processor 104 and memory controllers 108 may be physically separate devices (e.g., separate chips or chiplets) or may be different elements of a single device, such as a central processing unit (CPU), graphics processing unit (GPU), quantum processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc. In several aspects, the processor 104 includes one or more programs 204, at least one cache memory 206 (e.g., data and / or instruction cache), and performance counters 208. The host's programs 204 contain processor-executable instructions that the processor 104 executes to provide the functionality or services of the host 102. Although shown in association with processor 104, program 204 may be stored and loaded from a memory or a data storage device of host 102 (e.g., non-volatile memory). Furthermore, data (not shown) used by program 204 may be stored and loaded from a memory or a data storage device of host 102.

[0042] When program 204 is executed, the processor 104 of host 102 performs memory operations to access data used by the program for operation. Typically, memory operations include read operations that read data stored in memory and write operations that store data in memory. Referring to a read operation, in response to the execution of program 204, processor 104 determines what data program 204 needs, for example, to advance program execution. In some cases, processor 104 generates a memory read instruction for the program's data. To obtain the data for program 204 (e.g., to satisfy a memory read instruction), processor 104 may access cache memory 206 associated with processor 104 (e.g., L1, L2, or L3 cache) or generate a command or request (e.g., a memory access command or memory access request) issued via interconnect 110 to obtain data from memory system 112. If the data for program 204 exists in cache 206 (e.g., a "cache hit"), the data is loaded by processor 104 from cache 206 for use by program 204. In other cases, if the data for program 204 is not found in cache 206 (e.g., a "cache miss"), processor 104 generates a memory request for data issued via interconnect 110 to read data from the memory of host 102 (e.g., memory system 112). In retrospect, one or more cache misses resulting in a memory request for data from the memory of host 102 may degrade the performance of program 204 while processor 104 waits for the memory request to complete.

[0043] The processor 104 of host 102 includes performance counters 208 that track memory performance metrics or statistics associated with memory accesses performed by the processor 104 while executing one or more programs. Typically, memory performance metrics can indicate how the memory sensitivity or memory access performance of a program affects the execution of the program. These memory performance metrics can include any suitable metrics associated with memory access. Examples of memory performance metrics include the amount of time or number of clock cycles that one or more memory read instructions pause the processor 104's reordering buffer, the number of cache misses or cache miss rate for data requested by the processor 104, such as the per-thousand-instruction-kilomiss (MPKI) rate of the processor 104's memory read operations. In some cases, the number of clock cycles indicates the latency sensitivity of accessing temperature-controlled memory domains (e.g., due to excessive latency), and the MPKI indicates the bandwidth sensitivity of accessing temperature-controlled memory domains (e.g., due to bandwidth shortage). Alternatively or additionally, the processor 104 may include memory access information 210 describing or indicating the memory address for which the processor 104 or memory controller 108 issues a memory request. Therefore, performance counter 208 and memory access information 210 can be used to determine the corresponding performance sensitivity or requirement associated with a processor's memory request issued to a different memory domain (e.g., a temperature-controlled memory domain) of host 102.

[0044] like Figure 2 As shown, the adaptive controller 106 may be coupled to the performance counter 208, memory access information 210, and interconnect 110 of the host 102 via corresponding interfaces. In some embodiments, the adaptive controller 106 includes a memory performance monitor 212 that monitors memory performance metrics and memory access information 210 associated with memory requests sent or issued to the memory system 112. The memory performance monitor 212 may receive memory access information 210 (e.g., memory request addresses) from one of the processor 104, memory controllers 108-0 to 108-k, interconnect 110, or buses 202-0 to 202-m. In several aspects, the memory performance monitor 212 receives address information of memory requests issued by the processor 104 to cryogenic memories 114-0 to 114-n via interconnect 110.

[0045] Based on address information, the memory performance monitor 212 associates the corresponding memory performance metrics in the memory performance metrics with the corresponding cryogenic memory 114 (e.g., a temperature-controlled memory domain). Therefore, the memory performance monitor 212 can use the memory performance metrics of the host 104 and the memory access information 210 to determine the memory performance sensitivity or required level on one or more cryogenic memories 114-0 to 114-n. The adaptive controller 106 is also coupled to the memory system 112 so that the adaptive controller 106 can manage various settings of the cryogenic memories 114-0 to 114-n, which may correspond to the respective temperature-controlled memory domains. In several aspects, the adaptive controller 106 manages the settings of the temperature-controlled memory domains based on the memory performance metrics of the host 102 and the memory access information 210 (e.g., memory performance requirements), examples of which are described herein.

[0046] Figure 3 Example 300 illustrates an example of a temperature-controlled memory domain in an adaptive memory system (e.g., memory system 112) characterized by independently controllable voltage and temperature. In this example, host 102 includes processor 104, memory controller 108, and adaptive controller 106, which is coupled to the processor 104 and an array of cryogenic memories 114-0 to 114-n of memory system 112. The memory controller 108 of host 102 couples processor 104 to the corresponding cryogenic memories in cryogenic memories 114-0 to 114-n via buses 202-0 to 202-m of interconnect 110. For visual simplicity, cryogenic memories 114-0 and 114-n, along with their corresponding buses 202-0 and 202-m, are shown as a non-limiting example. The described aspects can be implemented with any suitable host system and temperature-controlled memory system, which may include, compared to reference... Figure 2 The fewer, additional, or different components and / or connections described.

[0047] In several aspects, the cryogenic memory 114 (e.g., 114-0) of the memory system 112 includes one or more memory devices 116 (e.g., 116-0), cooling devices 118 (e.g., 118-0), voltage regulators 120 (e.g., 120-0), clock circuitry (not shown), and sensors 302 (e.g., 302-0). Typically, an adaptive controller 106 is coupled to the cooling devices 118, voltage regulators 120, clock circuitry, and / or sensors 302 of the cryogenic memory 114 of the memory system 112. Therefore, the adaptive controller 106 can adaptively configure the temperature or voltage of the cryogenic memory 114, for example, to adapt the performance of the cryogenic memory 114 to the memory performance requirements of the host 102. To implement various aspects of the adaptive memory, the adaptive controller 106 interacts with the cooling devices 118, voltage regulators 120, sensors 302, or other components of the cryogenic memory 114. Although shown with the same components, each of the cryogenic storage devices 114-0 to 114-n can be configured similarly or differently from each other, having more, fewer, or different components.

[0048] The cooling device 118 (e.g., an active cooling device or system) of the cryogenic storage 114 provides a temperature domain in which one or more storage devices 116 are disposed. Therefore, the cryogenic storage 114, or the storage devices 116 within the temperature domain of the cryogenic storage 114, is shown as a temperature-controlled storage domain 304 of the storage system 112. Although described in the context of cryogenic cooling, the cooling device 118 may comprise any suitable type of cooling device or system that can selectively control (e.g., decrease or increase) the temperature of the storage devices 116. Exemplary cooling devices 118 include fan devices, liquid-based cooling, thermoelectric coolers (e.g., PILTER devices), liquid-gas phase change systems, immersion or bath systems, evaporation systems, etc. In some cases, the cooling device 118 comprises a liquid nitrogen or liquid helium-based cooling device capable of cooling the storage devices 116 to less than 100 K (e.g., a cryogenic range). The cooling device 118 may include a thermostat circuit or control interface through which the adaptive controller changes, adjusts or configures the temperature setting 306 (e.g., a set point register) to control the temperature (e.g., the measured or current temperature) of the temperature control domain 304 of the memory device 116.

[0049] Voltage regulator 120 provides a voltage domain for the operation of one or more memory devices 116. Voltage regulator 120 may include control circuitry or a control interface with a voltage setting 308, which adaptive controller 106 configures to control the operating voltage of the memory devices 116 of the cryogenic storage 114. In other words, adaptive controller 106 can selectively and independently control, change, or regulate the temperature 306 and voltage 308 of the temperature-controlled memory domain 304. In some cases, sensor 302 of the cryogenic storage 114 measures sensor data 310 and provides it to adaptive controller 106, the sensor data indicating the operating conditions of the memory devices 116. For example, for a given temperature-controlled memory domain 304, sensor data 310 may indicate one or more of the following: temperature, operating voltage, operating frequency, amount of energy consumed by cooling device 118, amount of energy consumed by memory device 116 (e.g., memory voltage regulator or power supply), etc. Sensor 302 may be implemented separately from or integrated with the memory device 116, cooling device 118, or voltage regulator 120 of temperature control memory domain 304.

[0050] Figure 4 An exemplary configuration of an adaptive controller 106 coupled to a host processor 104 and a memory system 112 to implement an adaptive memory system is shown at 400. The adaptive controller 106 may include one or more corresponding interfaces (not shown) capable of interacting with components of the host 102, processor 104, interconnect 110, or memory system 112. In some cases, the adaptive controller 106 is implemented as a hardware circuitry and / or firmware logic on another processor of the host 102 or the processor 104. The adaptive controller 106 may include an application programming interface (API) through which configurable settings (e.g., thresholds) of the adaptive controller 106 are exposed via a user interface. Alternatively or additionally, the API may link the adaptive controller 106 to the system manager of the host 102, which may enable the host 102 to synchronize the power-on sequence with the adaptive controller 106 or reset the adaptive controller 106.

[0051] like Figure 4As shown, the adaptive controller 106 includes a memory performance monitor 212 coupled to the processor 104 and adaptive control logic 402 coupled to the memory system 112. Typically, the memory performance monitor 212 monitors memory performance associated with a memory domain (e.g., memory sensitivity) and predicts future memory demands based on that performance. The adaptive control logic 402 can adaptively configure the memory domain to adjust its performance to match the predicted memory demands using the predicted memory demands. In this example, the memory performance monitor 212 is implemented with a demand predictor 404, which includes memory demand prediction logic 406 configured to provide a predicted memory demand 408. In several aspects, the memory performance monitor 212 receives a memory performance metric 410 from the performance counter 208 of the processor 104. Here, the performance metric 410 includes an indication of the MPKI 412 of the instructions of the program 204 executed on the processor 104 and an indication of the pause cycle 414. MPKI 412 can indicate the memory bandwidth sensitivity of a program or processor accessing a temperature-controlled memory domain. Pause cycle 414 can indicate the memory latency sensitivity of a program or processor accessing a temperature-controlled memory domain.

[0052] The memory performance monitor 212 can also receive memory access information 210 from the processor 104 or memory controller 108 of the host 102. The memory access information 210 includes information such as address information 416, which can be used to associate memory requests, performance metrics, or memory sensitivities with corresponding cryogenic memories, temperature-controlled memory domains in cryogenic memories 114, or another memory coupled to the host 102 via interconnect 110. Alternatively or additionally, the memory performance monitor 212 can monitor activity on interconnect 110 (e.g., memory requests or data transactions) to obtain memory access information 210 describing access to the memory system 112 by the processor 104 or program 204.

[0053] In several respects, the memory performance monitor 212 uses performance metrics 410 and optionally memory access information 210 to characterize or analyze the memory access performance or sensitivity of one or more temperature-controlled memory domains 304 of the memory system 112. For example, memory associated with a program 204 (e.g., a virtual page) executing on the processor 104 may be mapped to a temperature-controlled memory domain 304 (or a temperature-controlled memory region). The memory performance monitor 212 may analyze the memory access performance or sensitivity (e.g., memory sensitivity) of the program and / or other programs that access the temperature-controlled memory domain 304 during execution. Using the monitored memory access performance or sensitivity, the prediction logic 406 of the demand forecaster 404 determines a predicted demand 408 for the temperature-controlled memory domain 304 for future time instances. Other instances of memory access demand and predicted demand 408 are described herein.

[0054] Predictive demand 408 is provided to adaptive control logic 402, which can adjust the settings of memory system 112 to adapt the performance of cryogenic memory 114 to changes in program memory sensitivity or requirements. In some cases, adaptive control logic 402 uses predictive demand 408 to change or configure the voltage or temperature settings of cryogenic memory 114 to adjust the bandwidth or latency of its temperature-controlled memory domain. Therefore, adaptive control logic 402 receives predictive demand 408 from memory performance monitor 212 and optionally receives sensor data from sensor 302 of cryogenic memory 114. For example, adaptive control logic 402 may also receive indications of measured temperature, voltage, frequency, or energy consumption of the temperature-controlled memory domain. Based on predictive demand 408 and optionally based on sensor data, adaptive control logic 402 changes or configures the temperature, voltage, frequency, or ECC of cryogenic memory 114. To be able to interact with memory system 112, adaptive control logic 402 may include temperature control block 418, voltage control block 420, frequency control block 422, and ECC control block 424. Typically, any control block may contain registers, circuitry, or interfaces that enable the adaptive control logic 402 to change or configure the corresponding operating parameters (e.g., temperature or voltage) of the cryogenic memory 114 or the temperature-controlled memory domain 304. Other examples of these components are described herein.

[0055] Figure 5 500 was shown Figure 4An exemplary configuration of the adaptive controller 106's memory demand predictor and other components. In several aspects, the memory demand predictor 404 (demand predictor 404) predicts memory performance requirements (e.g., latency or bandwidth) for one or more temperature-controlled memory domains at future points in time. In some embodiments, the demand predictor 404 uses memory performance metrics from previous and / or current time windows for memory performance requirements in subsequent time windows. Alternatively or additionally, the demand predictor 404 may analyze memory performance or sensitivity over multiple time windows to predict memory performance requirements in subsequent time windows.

[0056] Demand predictor 404 includes time windows that can be predefined, statically configured, or dynamically configured when adaptive controller 106 operates to manage the settings of memory system 112. Alternatively, demand predictor 404 can be configured to analyze memory performance or predict demand over durations, time intervals, time periods, etc. In several aspects, demand predictor 404 implements different time windows corresponding to corresponding types of operating parameters (e.g., voltage or temperature) by which the performance of temperature-controlled memory domains can be controlled. In this example, demand predictor 404 includes a programmable voltage time window 502 (voltage time window 502) and a programmable temperature time window 504 (temperature time window 504). In some embodiments, the length of the time window for adjusting the operating parameters of the temperature-controlled memory domain is determined based on the transition time for changing the performance (e.g., latency or bandwidth) of the memory domain using the operating parameters (e.g., voltage or temperature).

[0057] Typically, demand predictor 404 receives indications of memory performance or memory sensitivity from memory performance monitor 212. In this example, demand predictor 404 receives corresponding indications of bandwidth sensitivity 506 or delay sensitivity 508 for the temperature-controlled memory domain for voltage time window 502 and temperature time window 504. Here, the indications of bandwidth sensitivity 506 and delay sensitivity 508 include MPKI 412 and pause period 414, respectively, but demand predictor 404 can use any suitable memory performance metric. Based on the bandwidth sensitivity 506 and / or delay sensitivity 508 of the temperature-controlled memory domain (e.g., historical memory sensitivity), prediction logic 406 predicts memory demand 408 (predicted demand 408), for example, for subsequent or future time windows. In various aspects, predicted demand 408 includes bandwidth demand 510 and delay demand 512 for future time points (e.g., subsequent time windows). Here, the demand predictor 404 predicts the bandwidth demand 510 as the predicted MPKI 514 for the temperature-controlled memory domain and the latency demand 512 as the predicted pause cycle number 516.

[0058] By giving examples, consider Figure 6An exemplary series of voltage time windows 502 and temperature time windows 504 are shown at 600. Typically, the adaptive controller 106 can change the voltage of the temperature-controlled memory domain faster than the temperature of the temperature-controlled memory domain. Therefore, the demand predictor 404 can configure the voltage time window 502 with a shorter duration than the temperature time window 504. In some cases, the adaptive controller 106 calibrates the corresponding duration of the voltage or temperature time window by changing the voltage or temperature setting of the temperature-controlled memory domain. The adaptive controller 106 then monitors the length of time it takes for the operating conditions of the temperature-controlled memory domain to reach the changed voltage or temperature setting. Based on the time length, the adaptive controller 106 configures the length of the time window used to control the operating parameters of the temperature-controlled memory domain.

[0059] The length of the time window can correspond to the rate of change of operating parameters (e.g., voltage or temperature) used to control the temperature-controlled memory domain to affect the performance of the memory domain (e.g., latency or bandwidth). For example, the rate of change of voltage control performed by the adaptive controller 106 can be set in voltage ramp-up / ramp times of 100 microseconds (μs) (e.g., memory latency per ±10 ns). The rate of change of temperature control performed by the adaptive controller 106 can be set in temperature ramp-up / ramp times of 100 milliseconds (ms) (e.g., memory latency per ±10 ns). Reference Figure 6 The time windows are set with similar values, with the voltage time window 502 having a length of 100 μs and the temperature time window 504 having a length of 100 ms. However, the adaptive controller 106 can set the corresponding time window lengths to any suitable value. Alternatively or additionally, the adaptive controller 106 can adjust the ratio of the corresponding lengths of the voltage time window 502 and the temperature time window 504 to implement different types of control curves (e.g., performance or energy-saving curves).

[0060] In several ways, the memory performance monitor 212 records the bandwidth sensitivity 506 and / or delay sensitivity 508 of the temperature-controlled memory domain during each time window. In some cases, the memory performance monitor 212 records the bandwidth sensitivity 506 and / or delay sensitivity 508 of multiple temperature-controlled memory domains of the memory system 112. For example... Figure 6As shown, the memory performance monitor 212 records the bandwidth sensitivity 506 and delay sensitivity 508 for previous and / or current voltage time windows including voltage time windows (V-TW) N-2 502-2, voltage time windows N-1 502-1, and voltage time windows N 502-N. The memory performance monitor 212 also records the bandwidth sensitivity 506 and delay sensitivity 508 for previous and / or current temperature time windows including temperature time windows (T-TW) N-2 504-2, temperature time windows N-1 504-1, and temperature time windows N 504-N. Here, it is noted that for time windows of different lengths, the adaptive controller 106 can implement concurrent and independent mechanisms to monitor, predict, and control the voltage and temperature of the temperature-controlled memory domain.

[0061] Based on the recorded bandwidth sensitivity 506 and / or delay sensitivity 508 of the voltage and temperature time windows, the demand predictor 404 can predict memory demand 408 for subsequent voltage and temperature time windows. In several aspects, the prediction logic 406 of the demand predictor is configured to predict memory demand at future points in time based on machine learning, moving average calculations, or Markov prediction circuits. Moving average calculations can generate predicted memory demand based on the assumption that memory demand in subsequent time windows will resemble that of previous time windows. Markov prediction circuits can predict the most frequently observed memory demand after the current time window or interval N (e.g., the next time window (N+1)). The demand predictor 404 can then invoke the Markov prediction circuit again to predict the most likely value after the time window in which the first prediction was made (e.g., time window N+2 interval).

[0062] exist Figure 6 In the context of the above, demand predictor 404 predicts the forecast demand 408 for the next two time windows based on the recorded bandwidth sensitivity 506 and / or delay sensitivity 508 of the voltage and temperature time windows. Here, demand predictor 404 calls the Markov prediction circuit twice to predict the bandwidth demand 510 and delay demand 512 for the next voltage time window, which includes voltage time window N+1 602-1 and voltage time window N+2 602-2. Demand predictor 404 also predicts the bandwidth demand 510 and delay demand 512 for the next temperature time window, which includes temperature time window N+1 604-1 and temperature time window N+2 604-2. See reference Figure 5 As described, the predicted bandwidth requirement 510 and latency requirement 512 can indicate the predicted MPKI 514 and predicted pause period 516 of the temperature-controlled memory domain.

[0063] return Figure 5The predicted demand 408 generated by the demand forecaster is provided to the adaptive control logic 402 of the adaptive controller 106. Typically, the adaptive control logic 402 uses the predicted demand 408, such as predicting MPKI 514 or predicting pause period 516, to determine whether to change the corresponding operating parameters of the temperature-controlled memory domain to affect the performance of the memory domain. In various embodiments, the adaptive control logic 402 includes a threshold 518 against which the predicted demand 408 can be compared to determine whether or how to change the corresponding operating parameters of the temperature-controlled memory domain. Based on at least the predicted demand 408, the adaptive control logic 402 provides a cryogenic memory setting 520, which the adaptive controller 106 can apply to the temperature-controlled memory domain to affect the performance of the memory domain. For cryogenic memory 114, examples of cryogenic memory settings 520 include temperature 306, voltage 308, frequency 522, or ECC level 524. Other examples of threshold 518 and cryogenic memory settings are described herein.

[0064] Figure 7 An exemplary configuration of adaptive control logic coupled to a temperature-controlled memory domain is shown at 700. Adaptive control logic 402 can be coupled to any suitable number of cryogenic memories 114 in memory system 112. Therefore, adaptive controller 106 can monitor and control multiple cryogenic memories 114 of memory system 112 to implement an adaptive memory system. In several ways, adaptive controller 106 uses control logic 402 to change the settings of the temperature-controlled memory domain based on predicted memory requirements, which can effectively adapt the performance of the memory domain to changes in the memory requirements of programs executing on host 102.

[0065] In this example, adaptive control logic 402 is coupled to cryogenic memory 114, which may be configured similarly or differently from other examples of cryogenic memories described herein. Adaptive control logic 402 is implemented as part of adaptive controller 106 (not shown) and is also capable of accessing predicted demand 408 from demand predictor 404, current cryogenic memory settings 702, and / or sensor data 310. Here, predicted demand 408 includes predicted MPKI 514 and predicted pause period 516 (e.g., time window), and sensor data 310 includes energy metrics 704 describing the energy consumption of cooling device 118 and voltage regulator 120 of cryogenic memory 114. Current cryogenic memory settings 702 may contain setting information for memory system 112, such as previously configured voltage, frequency, ECC, or temperature settings.

[0066] In several ways, the adaptive control logic 402 uses predicted demand 408, such as predicted MPKI 514 or predicted pause period 516, to determine whether to change relevant operating parameters of the temperature-controlled memory domain, such as voltage or temperature, to affect the performance of the memory domain. For example, in response to a predicted demand exceeding current memory performance, the adaptive controller can lower the temperature of the temperature-controlled memory domain or increase the voltage to increase memory bandwidth or reduce memory latency. Alternatively, when the predicted demand is lower than current memory performance, the adaptive controller can increase the temperature of the temperature-controlled memory domain to reduce the energy consumed by the cooling device or voltage regulator of the temperature-controlled memory domain.

[0067] As described above, the adaptive controller can change the voltage of the temperature-controlled memory domain faster than temperature changes. Therefore, in some embodiments, the adaptive controller addresses short-term or rapid changes in memory demand by changing the voltage 308 of the voltage regulator 120, and long-term or slow changes in memory demand by changing the temperature 306 of the cooling device 118. Furthermore, since multiple aspects of memory performance, such as latency and bandwidth, are similarly affected by the control mechanisms of operating parameters (e.g., voltage and temperature), the control mechanisms of the adaptive controller do not need to be decoupled (e.g., they can act on voltage and temperature in parallel). In some cases, the adaptive controller can also adjust the ECC level or ECC layer of the data applied to the temperature-controlled memory domain. For example, when the adaptive controller lowers the voltage or increases the temperature of the memory domain, the memory error rate of the domain may increase. Before entering a less reliable voltage and frequency combination, the adaptive controller can increase the ECC strength of the data by using a stronger ECC scheme or enabling higher-level (e.g., second-level) ECC encoding.

[0068] In several ways, adaptive control logic 402 compares predicted demand with thresholds 518 to determine which operating parameters of the cryogenic memory domain need to be changed or adjusted. In some cases, adaptive control logic 402 may also use or compare energy metrics 704 of the cooling device 118 and voltage regulator 120 of the cryogenic memory domain to weigh energy considerations when determining which operating parameters to adjust. Thus, adaptive control logic 402 may compare predicted MPKI 514 and / or predicted pause period 516 with multiple thresholds 518 to determine or provide cryogenic memory settings 520 for controlling the operating parameters of cryogenic memory 114. The cryogenic memory settings 520 of operating parameters may include values, increments, or decrements of one or more of temperature 306, voltage 308, frequency 522, ECC level 524, etc. In some cases, adaptive control logic 402 determines cryogenic memory settings 520 by increasing or decreasing the current cryogenic memory setting 702 or by measurements of parameters provided by sensor 302.

[0069] By way of example, consider that adaptive control logic 402 can be implemented to control the voltage or temperature of cryogenic memory 114. Here, the control algorithm can use predicted demand from voltage time windows or temperature time windows.

[0070] If (predicted MPKI > BW threshold or predicted pause period > delay threshold)

[0071] If (increase rate > increase rate threshold)

[0072] Increase voltage

[0073] otherwise

[0074] Lower temperature

[0075] Otherwise (the memory operates with acceptable performance).

[0076] If (current temperature <= maximum temperature)

[0077] Increase temperature

[0078] otherwise

[0079] Reduce voltage

[0080] Exemplary control algorithm

[0081] In the exemplary control algorithm, the bandwidth threshold (BW threshold) can be set to the maximum permissible MPKI, indicating insufficient bandwidth, and the latency threshold can be set to the maximum permissible pause cycles per interval due to memory latency. Furthermore, the rate of change threshold can be used to balance regulation associated with short-term and long-term variations in memory demand. In some cases, the rate of change is configured based on voltage regulation or temperature regulation transition time in the temperature-controlled memory domain. Therefore, the control algorithm can be configured based on minimum memory performance (e.g., bandwidth or latency) levels or power savings, for example, by increasing the rate of change threshold to avoid voltage increases that typically consume more energy than temperature reductions.

[0082] To apply the cryogenic memory setting 520, adaptive control logic 402 can use one or more of the temperature control block 418, voltage control block 420, frequency control block 422, and ECC control block 424 to change or adjust the corresponding settings of the cryogenic memory 114. Here, each control block is coupled to a corresponding one of the cooling device 118, voltage regulator 120, clock circuit 706, and ECC setting register (not shown) of the cryogenic memory 114. In several ways, adaptive control logic 402 can change or modify the settings of the cryogenic memory 114 before or during a subsequent time window. By doing so, adaptive control logic 402 can increase the performance of the memory domain before a predicted increase in memory demand occurs, thereby reducing the potential impact on program performance due to insufficient bandwidth or excessive latency of the cryogenic memory. Other examples of control operations are provided, for example, in reference to [reference needed]. Figure 10-15 The method is described in this paper.

[0083] Many aspects of a memory system can be implemented in any suitable device, such as Figure 1 Device 100. As another example. Figure 8 and 9 Exemplary configurations of server equipment and quantum computing equipment are shown respectively. Figure 1 , 8 The exemplary devices of or 9 may be implemented in any suitable combination, similar or different from each other, or with fewer, additional or different components than those shown or described.

[0084] Figure 8 An exemplary server device 802 is shown at 800, comprising a host 102 or host system 102 and a memory system 112-1 implemented in a memory rack 804 (e.g., a cryogenic memory rack). In this example, the host 102 of the server device may be configured similarly to the host 102 of device 100 having a processor 104, an adaptive controller 106, a memory controller 108, an interconnect 110, and a memory system 112-0. In addition to the memory system 112-0, the host 102 may also be a room-temperature memory 806 (RT memory 806) coupled to the processor 104. The RT memory 806 may serve as part of the main memory of the host 102, which may direct memory operations to the RT memory 806 or the memory system 112-0. Alternatively or additionally, the host 102 may also be coupled to the memory system 112-1 of the memory rack 804. In this case, the host 102 may also direct memory operations to the memory system 112-1 of the memory rack 804.

[0085] Server device 802 and memory rack 804 may include or be coupled to rack cooling system 808. Typically, rack cooling systems 808-1 and 808-2 cool the memory system or cryogenic memory 114 and provide temperature control for it. Therefore, adaptive controller 106 may be coupled to rack cooling system 808 to control the temperature of the temperature-controlled memory domain of the memory system of the server device or memory rack.

[0086] In several respects, a server group or server cluster can be implemented using a memory system co-located with host 102 in server device 802 (e.g., server rack) or housed in a separate memory rack 804. To recap, cryogenic memory, or memory operating at low temperatures (e.g., below 100K), consumes less energy than room-temperature memory (e.g., RT memory 806). This reduction in memory energy usage translates into cost savings, which are typically much greater than the costs associated with operating rack cooling system 808 or other server cooling systems. Therefore, the operating cost of a server cluster implemented with one or more memory systems 112 can be lower than that of a room-temperature server cluster.

[0087] These cost savings can be further amplified by an adaptive memory system that manages the operating parameters of the memory system 112 in a server device or memory rack using an adaptive controller 106. Instead of operating the memory system 112 with constant temperature or voltage settings, the adaptive controller 106 can change the temperature or voltage settings based on monitored or predicted memory demand. For example, when the performance of the cryogenic memory 114 exceeds acceptable levels, the adaptive controller 106 can reduce the voltage of the cryogenic memory or increase its temperature to save additional energy and cost until subsequent changes in memory performance (e.g., predicted increases in bandwidth or latency demand). By scaling the energy and cost advantages offered by the adaptive memory system across server groups or data centers, the described aspects can reduce data center energy costs by approximately 10% to 20%.

[0088] Figure 9 An exemplary quantum computing device 902 is shown in 900, which includes a host 102 and a memory system 112 implemented as part of the quantum computing device. The quantum computing device 902 can be used with… Figure 1 The quantum computing system 100-5 is implemented similarly or differently, and may contain more, fewer, or different components. The components of the quantum computing device 902 operate at different corresponding temperatures, instances of which are... Figure 9 As shown in the image.

[0089] In this example, the host 102 of the quantum computing device 902 is configured similarly to the host 102 of the device 100, which has a processor 104, an adaptive controller 106, a memory controller 108, and an interconnect 110-1. Here, the memory system 112 of the quantum computing device 902 is coupled to the host 102 via a first interconnect 110-1 and to the control processor 904 of the quantum computing device via a second interconnect 110-2. In some embodiments, the memory system 112 serves as the memory of the control processor 904 of the quantum computing device 902. Therefore, the memory system 112 and the cryogenic memory 114 (e.g., a temperature-controlled memory domain) can be implemented as a two-port memory, providing access to both the host 102 and the control processor 904. The control processor 904 (e.g., Josephson junction logic) is coupled to the quantum substrate 908 (e.g., superconducting qubits) of the quantum computing device via a control interface 906 (e.g., high-density superwire). In some embodiments, the control processor 904 includes a quantum execution unit through which quantum processing of the quantum substrate 908 is implemented. The control processor 904 may include performance counters that indicate corresponding memory performance metrics for the temperature-controlled memory domain of the memory system 112. Furthermore, the control processor 904 or the second interconnect 110-2 may expose address information available to the adaptive controller 106 to implement the aspects described herein.

[0090] Typically, host 102 can provide various functions of the quantum computing device, such as control, preprocessing, and post-processing functions, directly or indirectly through control processor 904. In several aspects, host 102 stores data of software or applications executed on host 102 to memory system 112 via interconnect 110-1 for quantum processing. Control processor 904 can then access the data in memory system 112 via interconnect 110-2 and cause quantum substrate 908 to process the data. During or upon completion of quantum processing, control processor 904 can store data or result datasets in memory system 112. In several aspects, adaptive controller 106 can obtain memory performance metrics and / or address information from host 102 or control processor 904. Alternatively or additionally, adaptive controller 106 can also monitor memory transactions on either interconnect 110-1 or 110-2 and control the operating parameters of the memory system as described herein. To achieve these aspects, an example of adaptive controller 106 can be implemented in association with control processor 904 of quantum computing device 902.

[0091] Exemplary approach for adaptive memory

[0092] This section references Figure 10-15 The flowcharts and simplified flowcharts illustrate the exemplary method. These descriptions are for illustrative purposes only. Figure 1-9The components, entities, and other aspects described in the text. Figure 10 A flowchart 1000 illustrates an exemplary method for changing the voltage or temperature settings of a temperature-controlled memory domain. Flowchart 1000 includes operations 1002 to 1010, which an adaptive controller 106 can perform to implement aspects of the adaptive memory described herein.

[0093] At 1002, the adaptive controller receives memory performance metrics from the temperature-controlled memory domain. For example, the adaptive controller may receive from the host processor an indication of the number of cycles during which memory read instructions associated with the temperature-controlled memory domain are paused in the reordering buffer, or an indication of the MPKI rate of memory read instructions associated with the temperature-controlled memory domain. The temperature-controlled memory domain may correspond to a cryogenic memory in the memory system associated with the host processor.

[0094] Optionally, at 1004, the adaptive controller receives address information of memory requests made to at least the temperature-controlled memory domain. In some cases, the adaptive controller monitors memory requests issued via interconnects established between the processor and the temperature-controlled memory domain. At 1006, the adaptive controller associates corresponding memory performance metrics from memory performance metrics with the temperature-controlled memory domain based on the address information. In some cases, the adaptive controller determines which memory performance metrics correspond to the temperature-controlled memory domain based on the address of the memory request issued by the host or memory controller.

[0095] In 1008, the adaptive controller predicts the memory performance requirements of the temperature-controlled memory domain based on memory performance metrics. The adaptive controller can use any suitable prediction logic or circuitry, such as machine learning, moving average algorithms, or Markov prediction circuits, to predict the memory performance requirements of the temperature-controlled memory domain. In some cases, the predicted memory performance requirements are the predicted number of processor pause cycles or MPKI expected to occur over a future period.

[0096] In 1010, the adaptive controller changes the voltage or temperature setting of the temperature-controlled memory domain based on predicted memory performance requirements for the temperature-controlled memory domain. Alternatively or additionally, the adaptive controller may change the frequency setting (e.g., to increase bandwidth) or ECC setting of the temperature-controlled memory domain based on predicted memory performance requirements. In some cases, the adaptive controller increases the voltage setting or decreases the temperature setting in response to determining that the predicted memory requirements exceed a performance threshold of the temperature-controlled memory domain. In other cases, the adaptive controller decreases the voltage setting or increases the temperature setting in response to determining that the predicted memory requirements do not exceed a performance threshold of the temperature-controlled memory domain.

[0097] Figure 11A flowchart 1100 depicts an exemplary method for changing settings of a temperature-controlled memory domain based on previously accessed memory performance metrics. Flowchart 1100 includes operations 1102 to 1110, which an adaptive controller 106 can perform to implement aspects of the adaptive memory described herein.

[0098] At 1102, the adaptive controller monitors memory performance metrics of the temperature-controlled memory domain during a first time interval. The adaptive controller may monitor the host processor's performance counters to obtain the memory performance metrics of the temperature-controlled memory domain. In some cases, the adaptive controller uses address information of memory requests issued by the host processor to determine which performance metrics are relevant to memory requests sent to the temperature-controlled memory domain. The time interval may include time intervals configured to control the voltage or temperature of the temperature-controlled memory domain, which may correspond to the time it takes to transition the voltage or temperature of the temperature-controlled memory domain to another setting (e.g., minimum increment or decrement).

[0099] At 1104, the adaptive controller predicts the performance requirements of the temperature-controlled memory domain based on memory performance metrics during the second time interval. The adaptive controller can use any suitable prediction logic or method, such as machine learning, moving average algorithms, or Markov prediction circuits, to predict the memory performance requirements of the temperature-controlled memory domain. In some cases, the predicted memory performance requirements are the predicted number of processor pause cycles or MPKI expected to occur during the second time interval. Alternatively or additionally, the adaptive controller can obtain information or sensor data from the temperature-controlled memory domain indicating current operating conditions or energy usage of the temperature-controlled memory domain.

[0100] In step 1106, the adaptive controller compares the predicted performance requirements with at least one performance requirement threshold for the temperature-controlled memory domain. These performance requirement thresholds may include thresholds for the rate of change of memory requirements, minimum bandwidth thresholds, maximum latency thresholds, maximum temperature thresholds, cooling energy thresholds, and memory energy thresholds.

[0101] Optionally, at 1108, the adaptive controller increases the voltage setting or decreases the temperature setting of the temperature-controlled memory domain within a second time interval based on the comparison in operation 1106. For example, if the predicted demand exceeds one of the performance demand thresholds (e.g., rate of change or MPKI), the adaptive controller increases the voltage setting and / or decreases the temperature setting of the temperature-controlled memory domain to increase the performance of the memory domain. The adaptive controller may change the voltage setting or temperature setting before or during the second time interval to affect the performance of the temperature-controlled memory domain (e.g., latency or bandwidth). Method 1100 can return from operation 1108 to operation 1102 to implement another iteration that changes the settings of the temperature-controlled memory domain based on memory performance metrics.

[0102] Optionally, in 1110, the adaptive controller, based on the comparison in operation 1106, decreases the voltage setting of the temperature-controlled memory domain or increases the temperature setting during a second time interval. For example, if the predicted demand does not exceed one of the performance demand thresholds (e.g., performance, temperature, or energy consumption), the adaptive controller decreases the voltage setting of the temperature-controlled memory domain and / or increases the temperature setting to reduce the energy consumption of the memory domain. The adaptive controller may change the voltage setting or temperature setting before or during the second time interval to affect the energy consumption of the temperature-controlled memory domain. Method 1100 can return from operation 1110 to operation 1102 to implement another iteration that changes the settings of the temperature-controlled memory domain based on memory performance metrics.

[0103] Figure 12 A flowchart 1200 is depicted as an exemplary method for adaptive memory control based on predictive memory demand. Flowchart 1200 includes operations 1202 to 1220, which adaptive control logic 402 implements according to aspects of adaptive memory.

[0104] At 1202, the adaptive control logic receives either a predicted MPKI value or a predicted pause period value. The predicted MPKI or predicted pause period value can be received from the adaptive controller's demand predictor. At 1204, the adaptive control logic compares the predicted MPKI value or predicted pause period value with an MPKI threshold or a pause period threshold, respectively. The maximum MPKI threshold can be configured to indicate insufficient bandwidth available to the software executing on the host. The minimum latency threshold can be configured to indicate excessive latency associated with memory accesses performed by the software executing on the host.

[0105] If the predicted MPKI value exceeds the MPKI threshold or the predicted pause period value exceeds the pause period threshold, the adaptive control logic proceeds from operation 1204 to operation 1206. Alternatively, if the predicted MPKI value does not exceed the MPKI threshold or the predicted pause period value does not exceed the pause period threshold, the adaptive control logic proceeds to operation 1208.

[0106] At 1206, the adaptive control logic compares the predicted rate of increase of the MPKI value or the predicted rate of increase of the pause period value with a rate threshold for the MPKI or a rate threshold for the pause period. If the predicted rate of increase of the MPKI value exceeds the MPKI increase rate threshold or the predicted rate of increase of the pause period value exceeds the pause period rate threshold, the adaptive control logic proceeds from operation 1206 to operation 1210. Alternatively, if the predicted rate of increase of the MPKI value does not exceed the MPKI increase rate threshold or the predicted rate of increase of the pause period value does not exceed the pause period rate threshold, the adaptive control logic proceeds to operation 1212.

[0107] In 1210, the adaptive control logic increases the voltage of the temperature-controlled memory domain. In some cases, an increase rate exceeding a predicted demand threshold indicates a short-term change in memory demand, which can be addressed by increasing the voltage of the temperature-controlled memory domain. Increasing the voltage allows the adaptive controller to increase the operating frequency of the temperature-controlled memory domain, which can increase the bandwidth of the memory domain and / or reduce latency.

[0108] In 1212, the adaptive control logic lowers the temperature of the temperature-controlled memory domain. In some cases, the rate of increase of predicted demand that does not exceed the rate of increase threshold indicates a long-term variation in memory demand, which can be addressed by lowering the temperature of the temperature-controlled memory domain. Lowering the temperature can reduce the latency of the memory domain and / or enable the adaptive controller to increase the operating frequency to increase the bandwidth of the memory domain. The adaptive control logic can return from operation 1210 or operation 1212 to operation 1202 to implement another iteration of the operation of flowchart 1200.

[0109] Alternatively, the adaptive control logic can proceed from operation 1210 or 1212 to operation 1214 to reduce the error correction code scheme or layer applied to the temperature-controlled memory domain. The memory error rate of the temperature-controlled memory domain may decrease when entering a scenario of increased voltage or decreased temperature. Therefore, the adaptive controller can reduce the ECC level or layer applied to the data in the temperature-controlled memory domain to reduce encoding or decoding overhead and further improve memory performance. The adaptive control logic can then return from operation 1214 to operation 1202 to perform another iteration of the operation in flowchart 1200.

[0110] The alternative path from operation 1204 back to operation 1208 is reached when the predicted MPKI value or the predicted pause period value does not exceed the corresponding threshold.

[0111] At 1208, the adaptive control logic compares the current temperature of the temperature-controlled memory domain with the maximum temperature threshold of the temperature-controlled memory domain. If the current temperature of the temperature-controlled memory domain does not exceed the temperature threshold, the adaptive control logic proceeds from operation 1208 to operation 1216. Alternatively, if the current temperature of the temperature-controlled memory domain exceeds the temperature threshold, the adaptive control logic proceeds to operation 1218.

[0112] In step 1216, the adaptive control logic increases the temperature of the temperature-controlled memory domain. By increasing the temperature, the adaptive controller can reduce the power consumption of the cooling device or cooling system of the temperature-controlled memory domain. In step 1218, the adaptive control logic decreases the voltage of the temperature-controlled memory domain. When the temperature of the temperature-controlled memory domain is at its maximum allowable temperature, the adaptive controller can decrease the voltage of the memory as an alternative or additional way to reduce the power consumption of the temperature-controlled memory domain. The adaptive control logic can return from operation 1216 or operation 1218 to operation 1202 to implement another iteration of the operation of flowchart 1200.

[0113] Alternatively, the adaptive control logic can proceed from operation 1216 or 1218 to operation 1220 to increase the ECC scheme or ECC layer applied to the temperature-controlled memory domain. When entering a scenario of decreased voltage or increased temperature, the memory error rate of the temperature-controlled memory domain may increase (e.g., memory performance degrades). Therefore, the adaptive controller can increase the ECC level or ECC layer applied to the data in the temperature-controlled memory domain to reduce the memory error rate of the memory domain at lower voltages or increased temperatures. The adaptive control logic can then return from operation 1220 to operation 1202 to implement another iteration of the operation of flowchart 1200.

[0114] Figure 13A A flowchart 1300 depicts an exemplary method for configuring voltage time intervals in a temperature-controlled memory domain. Flowchart 1300 includes operations 1302 to 1310, which an adaptive controller can perform to implement aspects of the adaptive memory described herein.

[0115] In step 1302, the adaptive controller changes the voltage setting of the temperature control memory domain immediately. The adaptive controller can increase or decrease the voltage setting by a predetermined or minimum amount. In other cases, the adaptive controller can increase or decrease the voltage setting based on the amount of voltage used to change the delay or bandwidth of the memory domain.

[0116] At 1304, the adaptive controller monitors the voltage level of the temperature-controlled memory domain. The adaptive controller can monitor the voltage regulator or sensor in the temperature-controlled memory domain to obtain an indication of the voltage level as it changes based on the voltage setting applied by the adaptive controller. At 1306, the adaptive controller detects, at a second time, that the voltage level of the temperature-controlled memory domain has reached the voltage setting.

[0117] Optionally, in 1308, the adaptive controller verifies changes in the performance metrics of the temperature-controlled memory domain under a voltage setting. In some cases, the adaptive controller verifies whether the voltage change corresponds to a change in the bandwidth or delay of the memory domain. By doing so, the operation of method 1300 also allows for the determination or setting of the amount of voltage that can be used to increase or decrease the voltage setting to achieve a change in memory performance (e.g., bandwidth or delay).

[0118] In 1310, the adaptive controller configures a voltage time window for the temperature-controlled memory domain based on a first time and a second time. By doing so, the adaptive controller can configure the length or duration of the voltage time window, which can be used to monitor memory performance and predict the memory requirements of the memory system.

[0119] Figure 13B A flowchart 1350 illustrates an exemplary method for configuring temperature time intervals for a temperature-controlled memory domain. Flowchart 1350 includes operations 1352 to 1360, which an adaptive controller can perform to implement aspects of the adaptive memory described herein.

[0120] In 1352, the adaptive controller changes the temperature setting of the temperature control memory domain immediately. The adaptive controller can increase or decrease the temperature setting by a predetermined or minimum amount. In other cases, the adaptive controller can increase or decrease the temperature setting based on a temperature offset used to change the delay or bandwidth of the memory domain.

[0121] At 1354, the adaptive controller monitors the temperature level of the temperature-controlled memory domain. The adaptive controller can monitor the cooling system or sensors of the temperature-controlled memory domain to obtain an indication of the temperature level as the temperature changes based on the temperature setting applied by the adaptive controller. At 1356, the adaptive controller detects, at a second time, that the temperature level of the temperature-controlled memory domain has reached the temperature setting.

[0122] Optionally, in 1358, the adaptive controller verifies changes in the performance metrics of the temperature-controlled memory domain under a set temperature. In some cases, the adaptive controller verifies whether the temperature change corresponds to a change in the bandwidth or latency of the memory domain. By doing so, the operation of method 1350 can also be used to determine or set the amount of temperature by which increasing or decreasing the temperature setting achieves a change in memory performance (e.g., bandwidth or latency).

[0123] In 1360, the adaptive controller configures a temperature time window for the temperature-controlled memory domain based on a first time and a second time. By doing so, the adaptive controller can configure the length or duration of the temperature time window, which can be used to monitor memory performance and predict the memory requirements of the memory system.

[0124] Figure 14A flowchart 1400 depicts an exemplary method for adjusting the error correction code (ECC) setting of a temperature-controlled memory domain. Flowchart 1400 includes operations 1402 to 1410, which an adaptive controller can perform to implement aspects of the adaptive memory described herein.

[0125] In 1402, the adaptive controller determines whether to increase the temperature or decrease the voltage of the temperature-controlled memory domain. For example, the adaptive controller may determine to reduce the energy consumption of the temperature-controlled memory domain by increasing the temperature or decreasing the voltage in response to determining that the predicted memory demand for a future time interval or time window does not exceed a threshold.

[0126] At 1404, the adaptive controller adjusts the ECC applied to the data in the temperature-controlled memory domain in response to an increase in temperature or a decrease in voltage. Optionally, at 1406, the adaptive controller recodes the data in the temperature-controlled memory domain using a stronger ECC scheme. The adaptive controller may instruct the host processor or the ECC module of the temperature-controlled memory domain to read the data, recode the data with the stronger ECC scheme, and write the data back to the temperature-controlled memory domain. Optionally, at 1408, the adaptive controller enables a higher level of ECC for the data in the temperature-controlled memory domain. For example, the adaptive controller may enable higher-level ECC encoding, such as a second or third level.

[0127] In 1410, the adaptive controller increases the temperature of the temperature-controlled memory domain or decreases the voltage. In other words, the adaptive controller can adjust the ECC applied to the data before increasing the temperature of the temperature-controlled memory domain or decreasing the voltage. By doing so, the adaptive controller can prevent memory errors that may occur when the temperature-controlled memory domain starts operating under operating conditions that could lead to unreliable operation.

[0128] Figure 15 A flowchart 1500 depicts an exemplary method for adjusting the error correction code of a temperature-controlled memory domain based on the memory error rate. Flowchart 1500 includes operations 1502 to 1512, which an adaptive controller can perform to implement aspects of the adaptive memory.

[0129] In 1502, the adaptive controller increases the temperature or decreases the voltage in the temperature-controlled memory domain. The adaptive controller can increase the temperature or decrease the voltage to reduce the amount of energy consumed by the voltage regulator or cooling device in the temperature-controlled memory domain.

[0130] In the 1504, the adaptive controller monitors the memory error rate associated with data in the temperature-controlled memory domain under increased temperature or decreased voltage. In some cases, increasing the temperature of the temperature-controlled memory domain or decreasing the voltage increases the memory error rate of data written to or read from the memory domain by the host.

[0131] At 1506, the adaptive controller compares the memory error rate to a memory error rate threshold for the temperature-controlled memory domain. In some cases, the adaptive controller configures the memory error rate threshold based on the average or historical memory error rate associated with the memory domain. Alternatively or additionally, the memory error rate threshold may be based on the memory error rate of the temperature-controlled memory domain measured before the temperature or voltage change. If the memory error rate of the data does not exceed the memory error rate threshold, the adaptive controller can return from operation 1506 to operation 1502. Alternatively, if the memory error rate of the data does exceed the memory error rate threshold, the adaptive controller proceeds to operation 1508.

[0132] At 1508, the adaptive controller adjusts the ECC applied to the data in the temperature-controlled memory domain in response to a memory error rate exceeding a memory error rate threshold. Optionally, at 1510, the adaptive controller can re-encode the data in the temperature-controlled memory domain using a stronger ECC scheme. Optionally, at 1512, the adaptive controller enables a higher level of ECC for the data in the temperature-controlled memory domain. The adaptive controller can return from operation 1510 or 1512 to operation 1502 to implement another iteration of method 1500, for example, when the adaptive controller further increases the temperature of the temperature-controlled memory domain or decreases the voltage.

[0133] The order in which operations are shown and / or described in the flowcharts and simplified flowcharts above is not intended to be construed as limiting. Any number or combination of the process operations can be combined or rearranged in any order to implement a given method or alternative method. Operations can also be omitted from or added to the described method. Furthermore, the described operations can be implemented in a fully or partially overlapping manner.

[0134] These methods or aspects of operation can be implemented, for example, in hardware (e.g., a fixed logic circuit system or a processor combined with memory), firmware, or some combination thereof. The methods can be used... Figure 1-9The devices, systems, or components shown in these figures may be implemented using one or more of these methods, and these components may be further subdivided, combined, rearranged, etc. The devices, systems, and components in these figures generally represent firmware, such as executable code or its actions; hardware, such as electronic devices, packaged modules, IC chips, or circuits; software, such as processor-executable instructions; or combinations thereof. The illustrated devices 100, 800, or 900 include, for example, a host 102, an adaptive controller 108, an interconnect 110, and a memory system 112. The host 102 may include a processor 104 and a memory controller 108. The memory system 112 may include one or more cryogenic memories 114, which include a temperature-controlled memory domain 304 accessible via the interconnect 110. The cryogenic memories may include a cooling device 118, a voltage regulator 120, a sensor 302, and / or a clock circuit 706. Therefore, these figures illustrate some of many possible systems or devices capable of implementing the described methods.

[0135] Computer-readable media includes non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of computer programs (e.g., applications) or data from one entity to another. Non-transitory computer storage media can be any available media that is accessible to a computer, such as RAM, ROM, flash memory, EEPROM, optical media, and magnetic media.

[0136] Unless the context otherwise requires, the use of the word “or” herein can be interpreted as the use of “inclusive or”, or a term that allows inclusion or application of one or more items linked by the word “or” (e.g., the phrase “A or B” can be interpreted as allowing only “A”, only “B”, or both “A” and “B”). Furthermore, as used herein, the phrase “at least one” in a list of items refers to any combination of those items containing a single member. For example, “at least one of a, b, or c” can cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c). Additionally, items represented in the figures and terms discussed herein can indicate one or more items or terms, and therefore can be used interchangeably in this written description to indicate items and terms in singular or plural forms.

[0137] in conclusion

[0138] Although embodiments of the adaptive memory system have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as exemplary embodiments of the adaptive memory system.

Claims

1. A memory device comprising: Memory array; At least one interface is configured to be coupled to an interconnect of a host system and to receive commands issued to the memory array via the interconnect; and An adaptive controller, configured to be coupled to the host system via the at least one interface, is configured to: Receive one or more memory performance metrics from the host system via the at least one interface regarding the command issued to the memory domain of the memory array; Based on the one or more memory performance metrics received from the host system, determine the memory performance requirements of the memory domain; and Based on the memory performance requirements of the memory domain, change at least one of the voltage settings or temperature settings of the memory domain.

2. The memory device according to claim 1, wherein: The memory array includes multiple memory domains, and the multiple memory domains contain the memory domains; and The adaptive controller is further configured to: The address information of the command issued by the host system to the plurality of memory domains of the memory array via the interconnect is received via the at least one interface. and Based on the address information, the corresponding memory performance index among the one or more memory performance indicators is associated with the memory domain among the multiple memory domains corresponding to the corresponding memory performance index.

3. The memory device of claim 1, wherein the adaptive controller is further configured to: Based on the changed voltage or temperature settings, determine an error correction code (ECC) scheme for the data stored in the memory domain; and The ECC scheme is applied to the data stored in the memory domain.

4. The memory device of claim 1, wherein the adaptive controller is further configured to: Based on the changed voltage or temperature settings, determine the ECC layer for the data stored in the memory domain; and Enable the ECC layer for the data stored in the memory domain.

5. The memory device of claim 1, wherein the adaptive controller is further configured to: During a first time interval, the one or more memory performance metrics received are the commands issued to the memory domain; During the second time interval, based on the one or more memory performance metrics, the memory performance requirements of the memory domain are determined; and During the second time interval, the voltage setting or the temperature setting of the memory domain is changed based on the memory performance requirements determined for the memory domain.

6. The memory device of claim 5, wherein the adaptive controller is further configured to change the voltage setting or the temperature setting of the memory domain before the start of the second time interval.

7. The memory device of claim 1, wherein the adaptive controller is further configured to: The memory performance requirements of the memory domain are compared with the memory performance threshold of the memory domain; and In response to the memory performance requirement exceeding the memory performance threshold, the voltage setting of the memory domain is increased or the temperature setting is decreased. or In response to the memory performance requirement not exceeding the memory performance threshold, the voltage setting of the memory domain is reduced or the temperature setting is increased.

8. The memory device according to claim 7, wherein: The memory performance threshold includes a first memory performance threshold; The memory performance requirement exceeds the first memory performance threshold; and The adaptive controller is further configured to: Determine the difference between the memory performance requirements and the memory sensitivity level indicated by the one or more memory performance metrics; The difference between the memory performance requirements and the memory sensitivity level is compared with a second memory performance threshold. and In response to the difference between the memory performance requirement and the memory sensitivity level exceeding the second memory performance threshold, the voltage setting of the memory domain is increased; or In response to the fact that the difference between the memory performance requirements and the memory sensitivity level does not exceed the second memory performance threshold, the temperature setting of the memory domain is reduced.

9. The memory device of claim 8, wherein the memory sensitivity level indicated by the one or more memory performance metrics comprises: The bandwidth sensitivity indicated by the MPKI miss rate per thousand instructions of the host system's processor; or The latency sensitivity indicated by the number of cycles of the processor of the host system paused by one or more memory access instructions.

10. The memory device according to claim 7, wherein: The memory performance requirements did not exceed the memory performance threshold; and The adaptive controller is further configured to: The temperature setting of the memory domain is compared with the temperature threshold of the memory domain; and In response to the temperature setting not exceeding the temperature threshold, increase the temperature setting of the memory domain; or In response to the temperature setting exceeding the temperature threshold, the voltage setting of the memory domain is reduced.

11. The memory device according to claim 1, wherein: The one or more memory performance metrics received from the host system include: The amount of time or number of cycles that one or more memory read instructions associated with the memory domain are paused in the reordering buffer; or The MPKI miss rate per thousand instructions for the one or more memory read instructions associated with the memory domain; and The memory performance requirements determined for the memory domain include: The predicted amount of time or predicted number of pause cycles that subsequent memory read instructions associated with the memory domain will pause in the reordering buffer; or The predicted MPKI rate of the subsequent memory read instruction associated with the memory domain.

12. The memory device of claim 1, wherein the adaptive controller is further configured to: The memory performance requirements of the memory domain are determined using a moving average algorithm based on one or more memory performance metrics; or The memory performance requirements of the memory domain are determined using a Markov prediction algorithm based on one or more memory performance metrics.

13. A memory device comprising: A memory array that contains one or more memory domains; A host computer coupled to the memory array, the host computer including a processor, the processor including one or more performance counters indicating corresponding memory performance metrics of the one or more memory domains; and An adaptive controller, including an interface configured to access the one or more performance counters of the processor, the adaptive controller being configured to: The corresponding memory performance metric corresponding to one of the one or more memory domains is monitored via the one or more performance counters of the processor; Based on the corresponding memory performance indicators, determine the memory performance requirements of the memory domain; Based on the memory performance requirements of the memory domain, determine the voltage or temperature for the memory domain; and The voltage or temperature setting of the memory domain is changed using the voltage or temperature determined for the memory domain.

14. The memory device of claim 13, further comprising an interconnect coupling the host to the memory array, wherein: The interface of the adaptive controller includes a first interface; The adaptive controller further includes a second interface to the interconnect; and The adaptive controller is further configured to: The address information of commands issued by the host to the memory array via the interconnect is monitored through the second interface; and Based on the address information, the corresponding memory performance index is associated with the memory domain corresponding to the corresponding memory performance index.

15. The memory device of claim 14, wherein the interconnect coupling the host to the memory array comprises: Bus-based memory interconnect; or Memory interconnect based on serializer / deserializer (SerDes-based).

16. The memory device of claim 15, wherein the SerDes-based memory interconnect is configured to implement a split transaction memory access protocol.

17. The memory device of claim 14, wherein the interconnect includes a plurality of memory interfaces, each of the plurality of memory interfaces coupling the host to a corresponding memory domain of the one or more memory domains.

18. The memory device of claim 17, further comprising a plurality of memory controllers, each of the plurality of memory controllers coupling the host to a corresponding memory interface of the interconnected plurality of memory interfaces.

19. The memory device of claim 13, wherein each of the one or more memory domains of the memory array comprises: At least one memory device configured to store data of the host; A cooling device configured to control the temperature of the at least one memory device based on the temperature setting; and A voltage regulator configured to control the operating voltage of the at least one memory device based on the voltage setting.

20. The memory device of claim 13, wherein the corresponding memory performance metric corresponding to the memory domain includes: The amount of time that one or more memory access instructions associated with the memory domain are paused in the reordering buffer; or MPKI miss rate per thousand instructions associated with the one or more memory access instructions associated with the memory domain.

21. The memory device according to claim 13, wherein: The data in the memory domain is encoded using the Error Correction Code (ECC) scheme; and The adaptive controller is further configured to: Based on the voltage or temperature determined for the memory domain, another ECC scheme is selected for the data in the memory domain; Read the data encoded using the ECC scheme from the memory domain; The data read from the memory domain is re-encoded using the other ECC scheme. and The data encoded using the other ECC scheme is written back to the memory domain.

22. The memory device of claim 21, wherein the adaptive controller is configured to change the voltage setting or the temperature setting of the memory domain after the data encoded with the other ECC scheme is written back to the memory domain.

23. The memory device according to claim 13, wherein: The data in the memory domain is encoded or decoded using a first-level error correction code (ECC); and The adaptive controller is further configured to: Based on the voltage or temperature determined for the memory domain, a second-layer ECC is enabled to encode or decode the data in the memory domain.

24. The memory device of claim 23, wherein the adaptive controller is configured to change the voltage setting or the temperature setting of the memory domain after enabling the second layer ECC to encode or decode the data in the memory domain.

25. A method for performing memory operations, comprising: Receive one or more memory performance metrics via the host interface of the adaptive controller regarding commands issued by the host to a memory domain of a memory array coupled to the host via an interconnect. The adaptive controller determines the memory performance requirements of the memory domain based on one or more memory performance metrics; and The adaptive controller changes the voltage or temperature settings of the memory domain based on the memory performance requirements of the memory domain.

26. The method of claim 25, further comprising: Receive, via the host interface, at least the address information of the command issued by the host to the memory domain; and Based on the address information, one or more memory performance metrics are associated with the memory domain.

27. The method of claim 26, further comprising: The address information of the command issued by the host to the memory domain is obtained via the interconnection interface of the adaptive controller; and Based on the address information, one or more memory performance metrics are associated with the memory domain.

28. The method of claim 25, further comprising: Based on the changed voltage or temperature settings, determine an error correction code (ECC) scheme for the data stored in the memory domain; and The ECC scheme is applied to the data stored in the memory domain.

29. The method of claim 25, further comprising: Based on the changed voltage or temperature settings, determine the error correction code (ECC) layer for the data stored in the memory domain; and Enable the ECC layer for the data stored in the memory domain.

30. The method of claim 25, wherein: The one or more memory performance metrics received via the host interface include: The amount of time or number of cycles that one or more memory read instructions associated with the memory domain are paused in the reordering buffer; or The MPKI miss rate per thousand instructions for the one or more memory read instructions associated with the memory domain; and The memory performance requirements of the memory domain include: The predicted amount of time or predicted number of pause cycles that subsequent memory read instructions associated with the memory domain will pause in the reordering buffer; or The predicted MPKI rate of the subsequent memory read instruction associated with the memory domain.

31. A method for performing memory operations, comprising: During the first time interval, one or more memory performance metrics are received regarding commands issued by the host to a memory domain of a memory array coupled to the host; During the second time interval, based on the one or more memory performance metrics, the memory performance requirements of the memory domain are predicted; and Before or during the second time interval, the voltage or temperature setting of the memory domain is changed based on the memory performance requirements of the memory domain.

32. The method of claim 31, wherein the voltage setting or the temperature setting of the memory domain is changed before the second time interval begins.

33. The method of claim 31, wherein one of the following is used to predict the memory performance requirements: Machine learning; Moving average algorithm; or Markov prediction circuit.

34. The method of claim 31, further comprising determining at least one of the first time interval or the second time interval based on the voltage transition time of the memory domain or the temperature transition time of the memory domain.

35. A memory device comprising: A memory array that contains one or more memory domains; A host computer coupled to the memory array, the host computer containing one or more programs configured for quantum processing; A control processor coupled to the memory array, the control processor comprising quantum execution units configured to manage the execution of the one or more programs and one or more performance counters indicating corresponding memory performance metrics of the one or more memory domains; A quantum processing substrate coupled to the quantum execution unit of the control processor, the quantum processing substrate being configured to execute the one or more programs; and An adaptive controller configured to access an interface of the control processor for one or more performance counters, the adaptive controller being configured to: The corresponding memory performance metric corresponding to one of the one or more memory domains is monitored via the one or more performance counters of the control processor; Based on the corresponding memory performance indicators, determine the memory performance requirements of the memory domain; Based on the memory performance requirements of the memory domain, determine the voltage or temperature for the memory domain; and The voltage or temperature setting of the memory domain is changed using the voltage or temperature determined for the memory domain.

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