UART chip and FPGA chip

Abstract

The present application relates to a UART chip and an FPGA chip, and belongs to the field of chip technology. The UART chip includes: a transceiver, a state control device, and a debugging device; one end of the transceiver is used to be electrically connected to the control device, the other end of the transceiver is electrically connected to one end of the debugging device, and the other end of the debugging device is used to be connected to the SoC chip to be debugged; one end of the state control device is electrically connected to the debugging device, and the other end of the state control device is used to be electrically connected to the SoC chip; the transceiver is used to receive a first debugging signal from the control device and transmit the first debugging signal to the debugging device; the state control device is used to control the debugging device to be in a target setting mode; the debugging device is used to convert the first debugging signal into a debugging command in the target setting mode, and control the SoC chip to execute the debugging command. The present application simplifies the debugging process and improves the debugging efficiency of the SoC chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a UART chip and a FPGA chip. Background Art

[0002] With the development of chip technology, after the system-on-a-Chip (SoC) is designed, the functions of the SoC chip need to be verified and debugged. Among them, the commonly used method is to simulate the prototype of the SoC chip through the field programmable gate array (FPGA), and then verify and debug the functions of the SoC chip. Summary of the invention

[0003] The embodiment of the present application provides a UART chip and an FPGA chip, which can simplify the debugging process and improve the debugging efficiency of the SoC chip. The technical solution is as follows:

[0004] On the one hand, a UART chip is provided, the UART chip comprising: a transceiver, a state control device and a debugging device;

[0005] One end of the transceiver is used to be electrically connected to the control device, the other end of the transceiver is electrically connected to one end of the debugging device, and the other end of the debugging device is used to be connected to the system-on-chip SoC chip to be debugged;

[0006] One end of the state control device is electrically connected to the debugging device, and the other end of the state control device is used to be electrically connected to the SoC chip;

[0007] The transceiver is used to receive a first debugging signal from the control device and transmit the first debugging signal to the debugging device;

[0008] The state control device is used to control the debugging device to be in a target setting mode;

[0009] The debugging device is used to convert the first debugging signal into a debugging command in the target setting mode, and control the SoC chip to execute the debugging command.

[0010] On the other hand, a FPGA chip is provided, the FPGA chip comprising a system on chip SoC chip and a UART chip, the SoC chip being electrically connected to the UART chip;

[0011] The UART chip is a universal asynchronous receiver / transmitter (UART) chip according to any one of claims 1 to 9;

[0012] The SoC chip is used to execute the debugging command based on the read and write timing.

[0013] In the embodiment of the present disclosure, since a debugging device and a state control device are provided in the UART chip, the state control device can set the debugging device to be in a target setting mode, and the debugging device can act as a master device in the target setting mode to convert a first debugging signal of the control device to obtain a debugging command, and control the SoC chip to execute the debugging command, thereby forming a debugging path from the software control of the control device to the hardware circuit of the SoC chip, and the debugging of the SoC chip can be achieved through the debugging path, which does not require additional hardware and software debugging tools, simplifies the debugging process, and improves the debugging efficiency of the SoC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a UART chip shown in an exemplary embodiment of the present application is shown;

[0015] Figure 2 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0016] Figure 3 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0017] Figure 4 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0018] Figure 5 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0019] Figure 6 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0020] Figure 7 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0021] Figure 8 A schematic diagram of a state machine of a decoding module shown in another exemplary embodiment of the present application is shown;

[0022] Fig. 9 A schematic diagram of the structure of a UART chip shown in another exemplary embodiment of the present application is shown;

[0023] Fig.10 A schematic diagram of the structure of a UART chip shown in an exemplary embodiment of the present application is shown;

[0024] Fig.11 A schematic diagram of the structure of an FPGA chip shown in another exemplary embodiment of the present application is shown;

[0025] Fig.12 A schematic diagram of the structure of an FPGA chip shown in another exemplary embodiment of the present application is shown;

[0026] Fig.13 A schematic diagram of the structure of an FPGA chip shown in an exemplary embodiment of the present application is shown.

[0027] 1-Control device

[0028] 2-FPGA chip

[0029] 10-UART chip

[0030] 101-Transceiver

[0031] 1011-Receiving module

[0032] 1012-Sending module

[0033] 102-State control device

[0034] 1021-Frequency Divider Register

[0035] 1022-Status Register

[0036] 103-Debugging device

[0037] 1031-Decoding module

[0038] 10310-Decoding unit

[0039] 10311-Read and Write Registers

[0040] 1032-Timing Generation Module

[0041] 104-RXD port

[0042] 105-TXD port

[0043] 106-First Buffer

[0044] 107-Second Buffer

[0045] 108-Baud Rate Generator

[0046] 109 - RTS port

[0047] 1010-CTS port

[0048] 20-SoC chip

[0049] 201-Processor

[0050] 202-Memory

[0051] 203-AXI Bus Matrix

[0052] 204-AHB Bus Matrix

[0053] 205-Peripheral Equipment

[0054] 30-AHB to APB Connector

[0055] 301-AHB

[0056] 302-APB DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0058] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0059] Please refer to Figure 1 , which shows a structural block diagram of a UART chip 10 provided by an exemplary embodiment of the present application. The UART chip 10 includes: a transceiver 101, a state control device 102 and a debugging device 103;

[0060] One end of the transceiver 101 is used to be electrically connected to the control device 1, and the other end of the transceiver 101 is electrically connected to one end of the debugging device 103, and the other end of the debugging device 103 is used to be connected to the SoC chip 20 to be debugged;

[0061] One end of the state control device 102 is electrically connected to the debugging device 103, and the other end of the state control device 102 is used to be electrically connected to the SoC chip 20;

[0062] The control device 1 includes a personal computer (PC), such as a desktop, an all-in-one computer, a laptop, etc. Accordingly, one end of the transceiver 101 is electrically connected to the PC. A user inputs a debugging command through the control device 1, and based on the debugging command, the control device 1 sends a first debugging signal to the transceiver 101. The types of signals include parallel signals and serial signals, and accordingly, the first debugging signal is a parallel signal.

[0063] The transceiver 101 is used to receive a first debugging signal from the control device 1 , and transmit the first debugging signal to the debugging device 103 .

[0064] The state control device 102 is used to control the debugging device 103 to be in the target setting mode. The working mode of the UART chip 10 includes a default working mode and a target setting mode. Among them, when the UART chip 10 is in the default working mode, the debugging device 103 is in a resting state. At this time, the UART chip 10 acts as a slave device and receives access from the master device on the SoC chip 20. In the target setting mode, the debugging device 103 is in a normal working state. At this time, the UART chip 10 acts as a master device and accesses the slave device on the SoC chip 20. Correspondingly, the target setting mode is the master mode.

[0065] In the embodiment of the present application, the working mode of the debugging device 103 is set by the state control device 102, and the working mode of the debugging device 103 is switched to achieve the switching of the working mode of the UART chip 10, so that the UART chip 10 can realize the master device mode and the slave device mode, thereby increasing the mode selection method of the UART chip 10.

[0066] The debugging device 103 is used to convert the first debugging signal into a debugging command in the target setting mode, and control the SoC chip 20 to execute the debugging command.

[0067] See also Figure 2 The debugging device 103 includes a decoding module 1031 and a timing generation module 1032 .

[0068] One end of the transceiver 101 is used to be electrically connected to the control device 1, the other end of the transceiver 101 is electrically connected to one end of the decoding module 1031, the other end of the decoding module 1031 is electrically connected to one end of the timing generation module 1032, and the other end of the timing generation module 1032 is used to be connected to the SoC chip 20 to be debugged.

[0069] The transceiver 101 is used to receive a first debugging signal from the control device 1, and transmit the first debugging signal to the decoding module 1031. The type of the first debugging signal includes one of a read data signal and a write data signal.

[0070] The decoding module 1031 is used to decode the debugging command based on the first debugging signal, and transmit the debugging command to the timing generation module 1032. The type of the debugging command includes one of a read data command and a write data command.

[0071] The timing generation module 1032 is used to generate a read / write timing corresponding to the debug command, and control the SoC chip 20 to execute the debug command based on the read / write timing. The type of the read / write timing includes one of a read data timing and a write data timing. For example, the type of the first debug signal is a read data signal, and the decoding module 1031 decodes a read data command based on the read data signal, and transmits the read data command to the timing generation module 1032. The timing generation module 1032 generates a read data timing corresponding to the read data command, and controls the SoC chip 20 to execute the read data command based on the read data timing.

[0072] In an embodiment of the present application, a debugging device 103 is set in the UART chip 10, and the decoding module 1031 and the timing generation module 1032 in the debugging device 103 are used to control the SoC chip 20 to execute debugging commands without the need for additional debugging tools. This allows the UART chip 10 to access the internal address of the SoC chip 20 and also to be used as a common transmitter to transmit data, thereby increasing the functionality of the UART chip 10.

[0073] See also Figure 3 , the decoding module 1031 includes: a decoding unit 10310 and a read-write register 10311;

[0074] The decoding unit 10311 is used to decode the command field and the read-write parameters based on the first debug signal, and store the command field and the read-write parameters in the read-write register. The command field includes one of the read field and the write field. For example, the read field is R, indicating read, and the write field is W, indicating write. The read-write parameters include one of the read address parameter, the write address parameter, and the write data parameter. For example, the read address is 80000000.

[0075] The read / write register 10311 includes: a read address register, a read data register, a write address register and a write data register. The read address register is used to store a read address parameter. The write address register is used to store a write address parameter. The write data register is used to store a write data parameter. The read data register is used to store a read data parameter, wherein the read data parameter is the data returned when the SoC chip 20 executes a debug command.

[0076] The timing generation module 1032 is used to read the command field and the read-write parameter from the read-write register 10311 to obtain the debugging command.

[0077] In an embodiment of the present application, a decoding unit and a read-write register are set in the decoding module, so that the decoding module decodes the corresponding command field and read-write parameters according to the first debugging signal, and then drives the timing generation module to generate a read-write timing, so that the decoding operation can be completed through the UART chip 20 without the need for additional debugging tools, thereby reducing the use of debugging tools.

[0078] See also Figure 4 The transceiver device 101 includes a receiving module 1011 and a sending module 1012 .

[0079] One end of the receiving module 1011 and one end of the sending module 1012 are respectively used to be electrically connected to the control device 1 , and the other end of the receiving module 1011 and the other end of the sending module 1012 are respectively electrically connected to one end of the decoding module 1031 .

[0080] The receiving module 1011 is used to receive a first debugging signal and convert the first debugging signal into first data, where the first debugging signal is used to read data or write data.

[0081] As can be seen from the above, the first debugging signal is a parallel signal, and the receiving module 1011 converts the parallel signal into the first data. Correspondingly, the first data is serial data, and the first data includes address parameter information, and the address parameter information is the address information of the address space in the SoC chip 20. For example, if the user needs to read the data stored at the address 8000000 of the SoC chip 20, the address parameter information in the first data is the hexadecimal character of R8000000, where R represents read.

[0082] In response to the first debugging signal for reading data, the timing generation module 1032 is further configured to receive second data read out by the SoC chip 20 and transmit the second data to the decoding module 1031 .

[0083] The decoding module 1031 is further configured to transmit the second data to the sending module 1012 .

[0084] The sending module 1012 is used to convert the second data into a second debugging signal, and send the second debugging signal to the control device 1. The second data is serial data, and the second debugging signal is a parallel signal. Accordingly, the sending module 1012 converts the serial data into a parallel signal, and sends the parallel signal to the control device 1.

[0085] In an embodiment of the present application, a transceiver 101 is provided in the UART chip 10 to convert the parallel signal sent by the control device 1 into serial data, and the serial data sent by the SoC chip 20 is converted into a parallel signal and sent to the control device 1, thereby realizing serial-to-parallel conversion of data transmission and improving the debugging efficiency of the SoC chip 20.

[0086] See also Figure 5 , the UART chip 10 also includes: a receive data (Receive Data, RXD) port 104 and a transmit data (Transmit Data, TXD) port 105;

[0087] One end of the RXD port 104 is electrically connected to the receiving module 1011 , one end of the TXD port 105 is electrically connected to the sending module 1012 , and the other end of the TXD port 105 and the other end of the RXD port 104 are respectively used to be electrically connected to the control device 1 .

[0088] The RXD port 104 is used to receive a first debugging signal from the control device 1 and transmit the first debugging signal to the receiving module 1011 .

[0089] The TXD port 105 is used to receive the second debugging signal of the sending module 1012 and transmit the second debugging signal to the control device 1 .

[0090] In the embodiment of the present application, the RXD port 104 and the TXD port 105 are provided, and the RXD port 104 and the TXD port 105 are connected to the control device 1 , thereby realizing data transmission with the control device 1 .

[0091] See also Figure 6 , the UART chip 10 further includes: a first buffer 106;

[0092] One end of the first buffer 106 is electrically connected to the other end of the receiving module 1011 , and the other end of the first buffer 106 is electrically connected to one end of the decoding module 1031 .

[0093] The first buffer 106 is used to buffer the first data. Accordingly, the first buffer 106 is a receiving buffer, such as a Receive First Input First Output (RXFIFO). In response to the first data being present in the first buffer 106, the state of the first buffer 106 is a non-empty state; in response to the first data not being present in the first buffer 106, the state of the first buffer 106 is an empty state.

[0094] The receiving module 1011 transmits the first data to the first buffer 106, and the first buffer 106 buffers the first data, that is, the state of the first buffer 106 is non-empty. The receiving module 1011 transmits the first data to the first buffer 106 in the order of each data bit. In response to the state of the first buffer 106 being non-empty, the decoding unit 10310 obtains the first data.

[0095] See also Figure 7 , the UART chip 10 further includes: a second buffer 107;

[0096] One end of the second buffer 107 is electrically connected to the other end of the sending module 1012, and the other end of the second buffer 107 is electrically connected to one end of the decoding module 1031;

[0097] The second buffer 107 is used to buffer the second data. Accordingly, the second buffer 107 is a transmission buffer, such as a TXFIFO (Transmit First Input First Output, RXFIFO). In response to the existence of the first data in the second buffer 107, the state of the second buffer 107 is a non-empty state; in response to the absence of the first data in the second buffer 107, the state of the second buffer 107 is an empty state.

[0098] The read data register transmits the second data to the second buffer 107, and the second buffer 107 buffers the second data, that is, the state of the second buffer 107 is non-empty, and in response to the state of the second buffer 107 being non-empty, the sending module 1012 reads the second data. The second data is a read data parameter.

[0099] In an embodiment of the present application, by setting a first buffer 106 and a second buffer 107, a data caching module is added between the transceiver 101 and the debugging device 103 to cache the first data and the second data, thereby avoiding data loss due to untimely processing and improving the security of data transmission of the UART chip 10.

[0100] In a possible implementation, the decoding unit 10310 is used to jump from a first state to a second state, wherein the first state is an idle state, and in the idle state, the decoding unit 10310 jumps to the second state unconditionally. The second state is a command waiting state.

[0101] The decoding unit 10310 is used to receive the first debugging signal in the second state and jump to the third state. In the waiting command state, the decoding module 10310 obtains the first data from the first buffer. The third state is the judgment state.

[0102] The decoding unit 10310 is used to decode the command field in the third state, determine the validity of the command field, and jump to the fourth state in response to the command field being valid; in the judgment state, the decoding unit 10310 decodes the command field from the first data and jumps to the fourth state.

[0103] The decoding unit 10310 is used to decode the read / write parameter in the fourth state and store the read / write parameter in the read / write register. The fourth state is the parameter decoding state.

[0104] In another possible implementation, the decoding unit 10310 is configured to jump from a first state to a second state, wherein the first state is an idle state, and in the idle state, the decoding unit 10310 jumps to the second state unconditionally. The second state is a command waiting state.

[0105] The decoding unit 10310 is used to receive the first debugging signal in the second state and jump to the third state. In the waiting command state, the decoding module 10310 obtains the first data from the first buffer.

[0106] The decoding unit 10310 is used to decode the command field in the third state, determine the validity of the command field, and jump to the fourth state in response to the command field being valid; in the judgment state, the decoding unit 10310 decodes the command field from the first data and jumps to the fourth state. The third state is the judgment state. The fourth state is the decoding state, and the fourth state includes a first sub-state and a second sub-state. The first sub-state is a waiting read address state, and the second sub-state is a waiting write address state. In the judgment state, in response to the command field being a read field, jump to the first sub-state, that is, the waiting read address state. In response to the command field being a write field, jump to the second sub-state, that is, the waiting write address state.

[0107] The decoding unit 10310 is used to decode the read / write parameter in the fourth state and store the read / write parameter in the read / write register. The decoding unit 10310 is used to, in the first sub-state, in response to the read / write parameter being a read address parameter, store the read address parameter in the read address register and jump to the fifth state.

[0108] The decoding unit 10310 is used to, in the second sub-state, in response to the read / write parameter being a write address parameter, store the write address parameter in a write address register and jump to the seventh state.

[0109] Before the fourth state, the decoding unit 10310 is further used to obtain the first data in a waiting address state, wherein the waiting address state includes one of a waiting read address state and a waiting write address state.

[0110] The decoding unit 10310 is used to jump to the sixth state in the fifth state in response to the timing generation module 1032 returning the second data. The fifth state is a state of waiting for the completion of reading data.

[0111] The decoding unit 10310 is used to store the second data in the read data register in the sixth state. The read data register is also used to transmit the second data to the second buffer 107 .

[0112] The decoding unit 10310 is used to, in the seventh state, in response to the read / write parameter being a write data parameter, store the write data parameter in the write data register and jump to the eighth state.

[0113] Before the seventh state, the decoding unit 10310 is also used to obtain the first data in the waiting state for writing data.

[0114] The decoding unit 10310 is used to, in the eighth state, in response to the read / write parameter being a write data parameter, store the write data parameter in the write data register and jump to the ninth state. The write data register is also used to transmit the write data parameter to the timing generation module 1032.

[0115] The decoding unit 10310 is used to jump to the first state in response to the write data completion signal sent by the timing generation module 1032 in the ninth state.

[0116] Please refer to Figure 8 , which shows a state machine diagram of a decoding unit 10310 provided by an exemplary embodiment of the present application.

[0117] The decoding unit 10310 is used to jump from the first state to the second state; wherein the first state is an idle (IDLE) state. When the decoding unit 10310 is in the first state, other modules in the UART chip 10 are also in an idle state. Moreover, the decoding unit 10310 can jump to the second state unconditionally; the second state is a wait command (WAIT_CMD) state.

[0118] The decoding unit 10310 is used to jump to the point state upon receiving the first debugging signal in the second state.

[0119] The second state (WAIT_CMD state): in response to the RXFIFO state being an empty state, the decoding unit 10310 is in a waiting state, waiting for the RXFIFO state to change; in response to the RXFIFO state being a non-empty state, the decoding unit 10310 initiates an operation to read the RXFIFO, reads the first data cached in the RXFIFO, and jumps to the third state; for example, the third state is a judgment (JUDGE_CMD) state.

[0120] The third state (JUDGE_CMD state): the decoding unit 10310 is used to decode the command field in the third state, determine the validity of the command field, and in response to the command field being valid, store the command field in the read-write register 10311, and jump to the fourth state. The fourth state includes the first sub-state and the second sub-state. The decoding unit is used to decode the read-write parameters in the fourth state, and store the read-write parameters in the read-write register 10311. The read-write register 10311 includes a read address register, a write address register, a read data register, and a write data register.

[0121] The decoding unit 10310 is used to judge the first data read, that is, to judge the read character. In response to the read character being the ASCII value of R, that is, indicating a read, read data operation, the decoding unit 10310 enters the waiting for read address (WAIT_RADDR) state. If the read character is the ASCII value of W, that is, indicating a write, write data operation, the decoding unit 10310 enters the waiting for write address (WAIT_WADDR) state. If the read character is other values, it means that the character cached in the RXFIFO is an illegal character, that is, the first debug signal received by the receiving module 1011 is an illegal signal, that is, the first debug signal sent by the control device 1 is an illegal signal, that is, the user has entered an illegal read command in the serial port debugging tool on the control device 1, and the decoding unit 10310 returns to the IDLE state.

[0122] WAIT_RADDR: In response to the RXFIFO status being an empty state, the decoding unit 10310 is in a waiting state, waiting for the read address to enter the RXFIFO; in response to the RXFIFO status being a non-empty state, the decoding unit 10310 initiates an operation to read the RXFIFO, reads the first data cached in the RXFIFO, and jumps to the first sub-state, for example, the read address decoding (RADDR_DECODE) state.

[0123] RADDR_DECODE state: In response to the read character being an ASCII value of 0x0 to 0xf, and the number of characters of the address that has been read is not greater than 8, the decoding unit 10310 jumps to the WAIT_RADDR state, and converts the read ASCII value into a digital value represented by a hexadecimal character, and shifts the digital value left into the read address register. For example, the current value of the read address register is 0x12, the ASCII value read by the decoding unit 10310 is 0x33, and the digital value converted into hexadecimal characters is 3. The number 3 is shifted left into the read address register, and the data in the read address register is 0x123. In a possible implementation, the character cached in the read address register is 0x80000000. In response to the read character being the ASCII value of a carriage return, it indicates that the read address reception is complete, and the decoding unit 10310 enters the waiting for read data completion (WAIT_RDATA_DONE) state. In response to the read character being other ASCII values, or the number of characters of the address that has been read being greater than 8, it indicates that the first debugging signal received by the receiving module 1011 is an illegal signal, that is, the first debugging signal sent by the control device 1 is an illegal signal, that is, the user has entered an illegal read address in the serial port debugging tool on the control device 1, and the decoding unit 10310 jumps to the IDLE state.

[0124] WAIT_RDATA_DONE state: the timing generation module 1032 generates a read data timing based on the read command and the read address sent by the decoding unit 10310. The AHB to APB connector 30 transmits the debug command to the SoC chip 20 based on the read data timing. The SoC chip 20 executes the debug command and returns the second data stored in the address space corresponding to the read address, such as RDATA. The AHB to APB connector 30 transmits the second data to the decoding unit 10310 through the timing generation module 1032, and the state machine jumps to the sixth state, for example, the write TXFIFO (WRITE_TXFIFO) state.

[0125] WRITE_TXFIFO state: the decoding unit 10310 writes the second data into the TXFIFO, for example, the second data is the ASCII value of 0x12345678. In response to the TXFIFO state being a non-empty state, the transmitting module 1012 converts the second data into a parallel signal, transmits it to the RXD of the control device 1 through TXD, completes a data read operation, and the decoding unit 10310 jumps to the IDLE state.

[0126] WAIT_WADDR state: In response to the RXFIFO state being empty, the decoding unit 10310 waits for the write address to enter the RXFIFO. In response to the RXFIFO state being non-empty, the decoding unit 10310 initiates an operation of reading the RXFIFO and jumps to the second sub-state, for example, the write address decoding (WADDR_DECODE) state.

[0127] WADDR_DECODE state: In response to the read character being an ASCII value of 0x0 to 0xf, and the number of characters of the address that has been read is not greater than 8, the decoding unit 10310 jumps to the waiting for write address (WAIT_WADDR) state, and converts the read ASCII value into a digital value represented by a hexadecimal character, and shifts the digital value left into the write address register. For example, the current value of the write address register is 0xab, and the value read by the decoding unit 10310 is 0x63, which is converted into a hexadecimal character represented by c. The character c is shifted left into the write address register, and the data in the write address register is 0xabc. In response to the read character being the ASCII value of a space, it indicates that the write address reception is complete, and the decoding unit 10310 enters the waiting for write data (WAIT_WDATA) state. In response to the read character being other ASCII values, or the number of address characters that have been read being greater than 8, it indicates that the first debugging signal received by the receiving module 1011 is an illegal signal, that is, the first debugging signal sent by the control device 1 is an illegal signal, that is, the user has entered an illegal write address in the serial port debugging tool on the control device 1, and the decoding unit 10310 jumps to the IDLE state.

[0128] WAIT_WDATA state: In response to the RXFIFO state being empty, the decoding unit 10310 waits for write data to enter the RXFIFO. In response to the RXFIFO state being non-empty, the decoding unit 10310 initiates an operation of reading the RXFIFO and jumps to the eighth state, for example, the write data decoding (WDATA_DECODE) state.

[0129] WDATA_DECODE state: In response to the read character being an ASCII value of 0x0 to 0xf, and the number of address characters that have been read is not greater than 8, the decoding unit 10310 jumps to the WAIT_WDATA state, and converts the read ASCII value into a digital value represented by a hexadecimal character, and shifts the digital value left into the write data register. For example, the current value of the write data register is 0x55, and the value read by the decoding unit 10310 is 0x35, which is converted into a digital value represented by a hexadecimal character. The digital value 5 is shifted left into the write data register, and the data in the write address register is 0x555. In response to the read character being the ASCII value of a carriage return, it indicates that the write data reception is complete, and the decoding unit 10310 enters the ninth state, for example, the write data completion (WAIT_WDATA_DONE) state. In response to the read character being other ASCII values, or the number of address characters that have been read is greater than 8, it indicates that the user has entered an illegal write data, and the state machine jumps back to the IDLE state.

[0130] WAIT_WDATA_DONE state: The timing generation module 1032 generates a write data timing based on the write command, write address and write data sent by the decoding unit 10310. The AHB to APB connector 30 transmits the debug command to the SoC chip 20 based on the write data timing, and the SoC chip 20 executes the debug command and writes the content of the write data into the address space corresponding to the write address. In response to the completion of the write operation of the SoC chip 20, the decoding unit 10310 jumps to the IDLE state. For example, if the write command is W, the write address is 80000000, and the write data is aa5555aa, the SoC chip 20 performs the above read operation again. In response to the returned read data being aa5555aa, there is no error in the data written by the SoC chip 20.

[0131] In the embodiment of the present disclosure, since the debugging device 103 and the state control device 102 are set in the UART chip 10, when the SoC chip 20 needs to be debugged, the mode of the debugging device 103 is set through the state control device 102, so that the debugging device 103 is in the target setting mode. At this time, the UART chip 10 acts as the main device to control the SoC chip 20 to execute read and write commands, thereby realizing the path from software to hardware. Without the need for additional hardware and software debugging tools, the verification and debugging of the functions of the SoC chip 20 can be realized, thereby improving the debugging efficiency of the SoC chip 20.

[0132] See also Fig. 9 , the UART chip 10 also includes: a baud rate generator 108;

[0133] One end of the baud rate generator 108 is electrically connected to the receiving module 1011 and the sending module 1012 respectively, and the other end of the baud rate generator 108 is electrically connected to the state control device 102;

[0134] In the related art, during the data transmission between the UART chip 10 and the control device 1, the baud rates of the receiving parties are the same, that is, the baud rate of the UART chip 10 is the same as the baud rate of the control device 1. Accordingly, the baud rate generator 108 is used to generate a target baud rate clock, and the target baud rate clock is the same as the baud rate clock of the control device 1.

[0135] In the embodiment of the present application, a baud rate generator is set so that the baud rate of the UART chip 10 is the same as the baud rate of the control device 1, thereby avoiding data loss caused by different baud rates between the sender and the receiver, and improving the security of data transmission of the UART chip 10.

[0136] See also Fig.10 , the state control device 102 comprises: a frequency division register 1021;

[0137] One end of the frequency division register 1021 is electrically connected to the baud rate generator 108, and the other end of the frequency division register 1021 is used to be electrically connected to the SoC chip 20;

[0138] The SoC chip 20 has a fixed system clock, which is used to drive the SoC chip 20 and the external module to execute commands. In the present application, the baud rate clock of the UART chip 10 is provided by the system clock of the SoC chip 20. Accordingly, the frequency division register 1021 is used to determine the frequency division coefficient based on the system clock of the SoC chip 20 and transmit the frequency division coefficient to the baud rate generator 108.

[0139] The baud rate generator 108 is used to generate a target baud rate clock based on the frequency division coefficient.

[0140] In the embodiment of the present application, by setting the frequency division register 1021, a frequency division coefficient is provided for the baud rate generator to implement the baud rate setting of the UART chip 10, so that the baud rate of the UART chip 10 is the same as the baud rate of the control device 1.

[0141] Continue to see Fig.10 , the state control device 102 further includes: a state register 1022;

[0142] One end of the state register 1022 is electrically connected to the first buffer 106, the second buffer 107 and the decoding module 1031 respectively, and the other end of the state register 1022 is used to be electrically connected to the SoC chip 20;

[0143] The status register 1022 is used to check the status of the UART chip 10, for example, whether the first buffer 106 is full, the status of the decoding module 1031, etc.

[0144] In the embodiment of the present application, the state control device 102 is set to monitor the state of the UART chip 10, and based on the change of the state of the UART chip 10, the corresponding module is set, so that the debugging process of the SoC chip 20 is carried out in an orderly manner.

[0145] Continue to see Fig.10 , the UART chip 10 also includes: a Require To Send (RTS) interface 109 and a Clear To Send (CTS) interface 1010. One end of the RTS interface 109 and one end of the CTS interface 1010 are electrically connected to the status register 1022 respectively. Correspondingly, the USB of the control device 1 includes a Require To Send (RTS) interface and a Clear To Send (CTS) interface. The other end of the RTS interface 109 is used to be electrically connected to the CTS interface 1010 of the control device 1, and the other end of the CTS interface 1010 is used to be electrically connected to the RTS interface 109 of the control device 1.

[0146] In response to the first buffer 106 being filled, the status register 1022 generates a first full message, and sends the first full message to the CTS interface 1010. Based on the first full message, the CTS interface 1010 sends a first full signal to the RTS interface 109 of the control device 1. In response to the first buffer 106 not being filled, the status register 1022 generates a second full message, and sends the second full message to the RTS interface 109. Based on the second full message, the RTS interface 109 sends a second full signal to the CTS interface 1010 of the control device 1. The first full message indicates that the first buffer 106 is filled. The first full message includes an identifier and a full identifier of the first buffer 106. The second full message indicates that the first buffer 106 is not filled. The second full message includes an identifier and a not full identifier of the first buffer 106.

[0147] In the embodiment of the present disclosure, since a debugging device and a state control device are provided in the UART chip, the state control device can set the debugging device to be in a target setting mode, and the debugging device can act as a master device in the target setting mode to convert a first debugging signal of the control device to obtain a debugging command, and control the SoC chip to execute the debugging command, thereby forming a debugging path from the software control of the control device to the hardware circuit of the SoC chip, and the debugging of the SoC chip can be achieved through the debugging path, which does not require additional hardware and software debugging tools, simplifies the debugging process, and improves the debugging efficiency of the SoC chip.

[0148] Please refer to Fig.11 , which shows a structural block diagram of an FPGA chip 2 provided by an exemplary embodiment of the present application. The FPGA chip 2 includes a SoC chip 20 and a UART chip 10;

[0149] The SoC chip 20 is electrically connected to the UART chip 10;

[0150] The UART chip 10 is the above Figure 1-4 The UART chip 10 in the embodiment of the present invention is used for receiving the first debugging signal of the control device 1, converting the first debugging signal into a debugging command, and controlling the SoC chip 20 to execute the debugging command.

[0151] Among them, the RXD port 104 and the TXD port 105 of the UART chip 10 are electrically connected to the first pin and the second pin of the FPGA chip 2 respectively. The first pin and the second pin correspond to the input port and the output port (Input / Output interface, I / O interface) of the SoC chip 20 respectively. In this application, the UART chip 10 uses the UART communication protocol. The control device 1 includes a serial port debugging tool, wherein the serial port debugging tool includes an RXD port 104 and a TXD port 105. For example, USB, USB uses the USB communication protocol. The UART chip 10 needs to be electrically connected to the USB of the control device 1. Correspondingly, the FPGA chip 2 also includes a conversion chip. The conversion chip is electrically connected to the UART chip 10, and the conversion chip is used to convert the UART communication protocol of the UART chip 10 into a USB communication protocol. Correspondingly, the RXD port 104 of the UART chip 10 is electrically connected to the TXD port 105 of the USB, and the TXD port 105 of the UART chip 10 is electrically connected to the RXD port 104 of the USB.

[0152] The SoC chip 20 is used to execute debugging commands based on the read and write timings.

[0153] See also Fig.12 , the FPGA chip 2 also includes an AHB to APB connector 30;

[0154] The SoC chip 20 is electrically connected to the UART chip 10 via an AHB to APB connector 30 .

[0155] The AHB to APB connector 30 includes an AHB301 and an APB302. The AHB to APB connector 30 is used to transmit the debug command to the SoC chip 20 based on the read and write timing of the UART chip 10. In response to the SoC chip 20 needing to transmit the second data, the AHB to APB connector 30 transmits the second data to the UART chip 10. For example, the timing type generated by the timing generation module 1032 is a read data timing, and the SoC chip 20 reads the second data inside the SoC chip 20 based on the read data timing, and transmits the second data to the AHB to APB connector 30, and the AHB to APB connector 30 transmits the second data to the second buffer 107 through the debugging device 103.

[0156] For the SoC chip 20 , the AHB 301 is used as a master device to access the address of the SoC chip 20 . For the UART chip 10 , the APB 302 is used as a slave device to receive access from the UART chip 10 .

[0157] In the embodiment of the present disclosure, since a debugging device and a state control device are provided in the UART chip, the state control device can set the debugging device to be in a target setting mode, and the debugging device can act as a master device in the target setting mode to convert a first debugging signal of the control device to obtain a debugging command, and control the SoC chip to execute the debugging command, thereby forming a debugging path from the software control of the control device to the hardware circuit of the SoC chip, and the debugging of the SoC chip can be achieved through the debugging path, which does not require additional hardware and software debugging tools, simplifies the debugging process, and improves the debugging efficiency of the SoC chip.

[0158] See also Fig.13 , the SoC chip 20 includes: a processor 201, a memory 202, an AXI bus matrix 203 and an AHB bus matrix 204;

[0159] The AHB bus matrix 204 (Bus Matrix) is electrically connected to the AHB to APB connector 30 and the AXI bus matrix 203 respectively;

[0160] The processor 201 and the memory 202 are electrically connected to the AXI bus matrix 203 respectively.

[0161] The AHB bus matrix 204 is used to receive the debugging command transmitted by the AHB to APB connector 30 , and transmit the debugging command to the processor 201 or the memory 202 .

[0162] The processor 201 is a central processing unit (CPU) of the SoC chip 20. The memory 202 includes a read-only memory 202 (ROM), a random access memory 202 (RAM) and a double data rate synchronous dynamic random access memory 202 (DDR SDRAM).

[0163] Continue to see Fig.13 , the SoC chip 20 also includes: a peripheral device 205 (Peripheral).

[0164] In a possible implementation, the UART chip 10 receives the first debugging signal sent by the control device 1, and the receiving module 1011 converts the first debugging signal into first data, wherein the first data includes a driver. The driver is used to drive the CPU. The CPU executes the debugging command based on the driver, for example, controls the memory 202 to store data, etc.

[0165] In the embodiment of the present disclosure, since a debugging device and a state control device are provided in the UART chip, the state control device can set the debugging device to be in a target setting mode, and the debugging device can act as a master device in the target setting mode to convert a first debugging signal of the control device to obtain a debugging command, and control the SoC chip to execute the debugging command, thereby forming a debugging path from the software control of the control device to the hardware circuit of the SoC chip, and the debugging of the SoC chip can be achieved through the debugging path, which does not require additional hardware and software debugging tools, simplifies the debugging process, and improves the debugging efficiency of the SoC chip.

[0166] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more program codes or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0167] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A universal asynchronous receiver / transmitter (UART) chip, characterized in that: The UART chip includes: a transceiver, a state control device and a debugging device, and the debugging device includes a decoding module and a timing generation module; One end of the transceiver is used to be electrically connected to the control device, the other end of the transceiver is electrically connected to one end of the decoding module, the other end of the decoding module is electrically connected to one end of the timing generation module, and the other end of the timing generation module is used to be connected to the system-on-chip SoC chip to be debugged; One end of the state control device is electrically connected to the decoding module, and the other end of the state control device is used to be electrically connected to the SoC chip; The transceiver is used to receive a first debugging signal from the control device and transmit the first debugging signal to the decoding module; The state control device is used to control the decoding module to be in a target setting mode; The decoding module is used for decoding a debugging command based on the first debugging signal in the target setting mode, and transmitting the debugging command to the timing generation module; The timing generation module is used to generate a read / write timing corresponding to the debug command, and control the SoC chip to execute the debug command based on the read / write timing.

2. The UART chip according to claim 1, characterized in that: The decoding module includes: a decoding unit and a read-write register; The decoding unit is used to decode a command field and a read-write parameter based on the first debugging signal, and store the command field and the read-write parameter in the read-write register; The timing generation module is used to read the command field and the read-write parameters from the read-write register to obtain the debugging command.

3. The UART chip according to claim 2, characterized in that: The decoding unit is used to jump from the first state to the second state; The decoding unit is configured to receive the first debugging signal in the second state and jump to a third state; The decoding unit is used to decode the command field in the third state, determine the validity of the command field, and in response to the command field being valid, store the command field in the read-write register and jump to the fourth state; The decoding unit is used to decode the read-write parameters in the fourth state and store the read-write parameters in the read-write register.

4. The UART chip according to claim 1, characterized in that: The transceiver device includes a receiving module and a sending module; One end of the receiving module and one end of the sending module are respectively used to be electrically connected to the control device, and the other end of the receiving module and the other end of the sending module are respectively electrically connected to one end of the decoding module; The receiving module is used to receive the first debugging signal and convert the first debugging signal into first data, wherein the first debugging signal is used to read data or write data; In response to the first debugging signal for reading data, the timing generation module is further used to receive second data read out by the SoC chip and transmit the second data to the decoding module; The decoding module is further used to transmit the second data to the sending module; The sending module is used to convert the second data into a second debugging signal, and send the second debugging signal to the control device.

5. The UART chip according to claim 4, characterized in that: The UART chip also includes: a first buffer; One end of the first buffer is electrically connected to the other end of the receiving module, and the other end of the first buffer is electrically connected to one end of the decoding module; The first buffer is used to cache the first data.

6. The UART chip according to claim 4, characterized in that: The UART chip also includes: a second buffer; One end of the second buffer is electrically connected to the other end of the sending module, and the other end of the second buffer is electrically connected to one end of the decoding module; The second buffer is used to cache the second data.

7. The UART chip according to claim 4, characterized in that: The UART chip also includes: a baud rate generator; One end of the baud rate generator is electrically connected to the receiving module and the sending module respectively, and the other end of the baud rate generator is electrically connected to the state control device; The baud rate generator is used to generate a target baud rate clock, and the target baud rate clock is the same as the baud rate clock of the control device.

8. The UART chip according to claim 7, characterized in that: The state control device comprises: a frequency division register; One end of the frequency division register is electrically connected to the baud rate generator, and the other end of the frequency division register is used to be electrically connected to the SoC chip; The frequency division register is used to determine the frequency division coefficient and transmit the frequency division coefficient to the baud rate generator; The baud rate generator is used to generate the target baud rate clock based on the frequency division coefficient.

9. A field programmable gate array (FPGA) chip, characterized in that: The FPGA chip includes a system on chip (SoC) chip and a UART chip, and the SoC chip is electrically connected to the UART chip; The UART chip is a universal asynchronous receiver / transmitter (UART) chip according to any one of claims 1 to 8; The SoC chip is used to execute the debugging command based on the read and write timing.

10. The FPGA chip according to claim 9, characterized in that: The FPGA chip also includes an advanced high performance bus AHB to advanced peripheral bus APB connector; The SoC chip is electrically connected to the UART chip via the advanced high performance bus AHB to advanced peripheral bus APB connector.

11. The FPGA chip according to claim 10, characterized in that: The SoC chip includes: a processor, a memory, a bus protocol AXI bus matrix and an AHB bus matrix; The AHB bus matrix is ​​electrically connected to the advanced high performance bus AHB to advanced peripheral bus APB connector and the AXI bus matrix respectively; The processor and the memory are electrically connected to the AXI bus matrix respectively.

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