Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising: a substrate substrate; a display area provided on the substrate substrate, comprising a plurality of pixel driving units, each of the plurality of pixel driving units comprising a threshold compensation transistor, a first light-emitting control transistor, an active layer of the threshold compensation transistor comprising a first channel region corresponding to a first gate, a second channel region corresponding to a second gate, and an intermediate region located between the first channel region and the second channel region; a plurality of light shielding patterns, a first end of the plurality of light shielding patterns being used to receive a voltage signal, a second end of at least one of the plurality of light shielding patterns at least partially overlapping with the intermediate region of the threshold compensation transistor of the outermost first pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate substrate. The display substrate can introduce a "small pepper" design structure in the outermost first column of pixel driving units in the display area, reducing the leakage ability of the double-gate transistor.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices have advantages such as thinness, light weight, wide viewing angle, active light emission, continuously adjustable emission color, low cost, fast response speed, low power consumption, low driving voltage, wide operating temperature range, simple manufacturing process, high luminous efficiency, and flexible display. Therefore, they are increasingly widely used in display fields such as mobile phones, tablets, and digital cameras. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; a display area disposed on the substrate, including a plurality of pixel driving units arranged in multiple rows and columns, each of the plurality of pixel driving units including a threshold compensation transistor, a first light-emitting control transistor, and a storage capacitor, the threshold compensation transistor being connected to the first light-emitting control transistor and the storage capacitor respectively, the threshold compensation transistor including a first gate and a second gate, the active layer of the threshold compensation transistor including a first channel region corresponding to the first gate, a second channel region corresponding to the second gate, and an intermediate region located between the first channel region and the second channel region, the first channel region and the second channel region being connected through the intermediate region; a plurality of light-blocking patterns, each light-blocking pattern including a first end and a second end, the first end of the plurality of light-blocking patterns being used to receive a voltage signal, and the second end of at least one of the plurality of light-blocking patterns at least partially overlapping with the intermediate region of the threshold compensation transistor of the outermost first pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate.

[0004] For example, at least one embodiment of the present disclosure provides a display substrate that further includes at least a peripheral region surrounding the display area, a plurality of first power lines located in the display area, and edge traces of the first power lines located in the peripheral region. The plurality of first power lines extend along a first direction and are configured to connect to each column of pixel driving units in the plurality of pixel driving units to provide the first power supply voltage to each column of pixel driving units respectively. The edge traces of the first power lines are configured to connect to the plurality of first power lines to provide the first power supply voltage to the first power lines. The voltage signal includes the first power supply voltage.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of light-blocking patterns include a plurality of first light-blocking patterns; the first power line edge trace includes a first sub-conductor and a second sub-conductor extending along the first direction and disposed opposite to each other, and a third sub-conductor and a fourth sub-conductor extending along the second direction and disposed opposite to each other; the first sub-conductor is disposed on one side close to the first pixel driving unit of the plurality of pixel driving units; the first end of the plurality of first light-blocking patterns is connected to the first sub-conductor to receive the first power supply voltage, and the second end of at least one of the plurality of first light-blocking patterns at least partially overlaps with the middle region of the threshold compensation transistor of the first pixel driving unit of the at least one row of pixel driving units in a direction perpendicular to the substrate.

[0006] For example, the display substrate provided in at least one embodiment of this disclosure further includes: a plurality of signal lines electrically connected to the plurality of pixel driving units, a first electrode pattern located in the peripheral region and electrically connected to at least one of the plurality of signal lines, and a second electrode pattern located in the peripheral region; the first electrode pattern and the second electrode pattern are located on the side of the peripheral region near the outermost first pixel driving unit of the at least one row of pixel driving units; the first electrode pattern and the second electrode pattern at least partially overlap and are insulated from each other in a direction perpendicular to the surface of the substrate.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the first electrode pattern is connected to the signal line through a via to compensate for the load capacitance of the signal line; the second electrode pattern is connected to the first power line through a via to receive the first power supply voltage.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the light blocking pattern further includes: at least one second light blocking pattern; the first end of the at least one second light blocking pattern is connected to and integrally formed with the second electrode pattern, and the second end of the at least one second light blocking pattern at least partially overlaps with the middle region of at least one threshold compensation transistor of the first pixel driving unit of at least one row of pixel driving units adjacent to the second electrode pattern in the second direction in a direction perpendicular to the substrate.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the number of pixels in at least one row of pixel driving units adjacent to the first electrode pattern or the second electrode pattern in the second direction is less than the number of pixels in one row of pixel driving units adjacent to the first electrode pattern or the second electrode pattern in the first direction.

[0010] For example, in the display substrate provided in at least one embodiment of this disclosure, the extending direction of the first light-blocking pattern is not the same as the extending direction of the first sub-conductor. For example, in the display substrate provided in at least one embodiment of this disclosure, the plurality of signal lines include data lines or gate lines.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the data line on the substrate at least partially overlaps with the orthographic projection of the storage capacitor on the substrate.

[0012] For example, the display substrate provided in at least one embodiment of this disclosure further includes a power connection trace located on the side of the peripheral region near the outermost first pixel driving unit of the at least one row of pixel driving units; the power connection trace is connected to the first power line through a via to receive the first power supply voltage; the light blocking pattern further includes at least one third light blocking pattern; the first end of the at least one third light blocking pattern is connected to the power connection trace; the second end of the at least one third light blocking pattern at least partially overlaps with the middle region of the threshold compensation transistor of the first pixel driving unit of the at least one row of pixel driving units adjacent to the power connection trace in the second direction in a direction perpendicular to the substrate.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the number of pixels in each row of pixel driving units adjacent to the power connection trace in the second direction is less than the number of pixels in a row of pixel driving units adjacent to the power connection trace in the first direction.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a first adapter electrode, wherein a first end of the first adapter electrode is connected to the power connection trace via a via, and a second end of the first adapter electrode is connected to the at least one third light-blocking pattern via a via.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the first end of at least one of the plurality of light-blocking patterns is connected to the first power line corresponding to the outermost first pixel driving unit of the at least one row of pixel driving units to receive the first power supply voltage as the voltage signal.

[0016] For example, at least one embodiment of the present disclosure provides a display substrate that further includes an initialization signal line configured to provide an initialization signal to the plurality of pixel driving units; the voltage signal includes the initialization signal.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, each of the plurality of pixel driving units further includes a first reset transistor and a second reset transistor; the first terminal of the first reset transistor is connected to the initialization signal line to receive the initialization signal, the second terminal of the first reset transistor is connected to the threshold compensation transistor, and the gate of the first reset transistor is connected to the first reset signal line to receive a first reset signal; the first terminal of the second reset transistor is connected to the initialization signal line to receive the initialization signal, the second terminal of the second reset transistor is connected to the first light-emitting control transistor, and the gate of the second reset transistor is connected to the second reset signal line to receive a second reset signal.

[0018] For example, the display substrate provided in at least one embodiment of this disclosure further includes a plurality of second transition electrodes, a first insulating layer, a second insulating layer, and a third insulating layer. The first ends of the plurality of second transition electrodes are respectively connected to the initialization signal line to receive the initialization signal. The second ends of the plurality of second transition electrodes are respectively connected to the first electrode of the first reset transistor of the outermost first pixel driving unit of each row pixel driving unit through vias penetrating the first insulating layer, the second insulating layer, and the third insulating layer. The first electrodes of the first reset transistors of the outermost first column pixel driving units are respectively connected to the first ends of the plurality of light-blocking patterns through vias penetrating the first insulating layer and the second insulating layer.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving unit further includes a driving transistor; the active layer of the first reset transistor and the active layer of the driving transistor at least partially overlap with the first power line.

[0020] For example, in the display substrate provided in at least one embodiment of this disclosure, the length of the light blocking pattern corresponding to the outermost first pixel driving unit of each row of pixel driving units is greater than the length of the light blocking patterns corresponding to the pixel driving units other than the outermost first pixel driving unit of each row of pixel driving units.

[0021] For example, in the display substrate provided in at least one embodiment of this disclosure, the light blocking pattern corresponding to the pixel driving unit other than the outermost first pixel driving unit of each row pixel driving unit is connected to the first power line corresponding to each column pixel driving unit.

[0022] At least one embodiment of this disclosure also provides a display device, including the display substrate provided in any embodiment of this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1 This is a planar schematic diagram of a display substrate;

[0025] Figure 2A This is a plan view of a display substrate provided in some embodiments of the present disclosure;

[0026] Figure 2B A plan view of another display substrate provided in some embodiments of this disclosure;

[0027] Figure 2C A plan view of a display substrate provided for at least one embodiment of this disclosure;

[0028] Figure 3 This is a schematic diagram of a display substrate provided for some embodiments of this disclosure;

[0029] Figure 4 This is a schematic diagram of the circuit structure of a pixel driving unit provided in some embodiments of this disclosure;

[0030] Figure 5A for Figure 3 A plan view of the semiconductor pattern of the display substrate shown;

[0031] Figure 5B for Figure 3 The diagram shows a plan view of the first conductive layer of the display substrate.

[0032] Figure 5C for Figure 3 The diagram shows a plan view of the second conductive layer of the display substrate.

[0033] Figure 5D for Figure 3 The diagram shows a plan view of the third conductive layer of the display substrate.

[0034] Figure 6 A plan view of another display substrate provided in some embodiments of this disclosure;

[0035] Figure 7 for Figure 6 A schematic diagram of the stacked structure of the first corner region cor1 shown;

[0036] Figure 8A for Figure 7 A plan view of the semiconductor pattern of the display substrate shown;

[0037] Figure 8B for Figure 7The diagram shows a plan view of the first conductive layer of the display substrate.

[0038] Figure 8C for Figure 7 The diagram shows a plan view of the second conductive layer of the display substrate.

[0039] Figure 8D for Figure 7 The diagram shows a plan view of the third conductive layer of the display substrate.

[0040] Figure 9 for Figure 6 A schematic diagram of the stacked structure of the second corner region cor2 shown;

[0041] Figure 10A for Figure 9 A plan view of the semiconductor pattern of the display substrate shown;

[0042] Figure 10B for Figure 9 The diagram shows a plan view of the first conductive layer of the display substrate.

[0043] Figure 10C for Figure 9 The diagram shows a plan view of the second conductive layer of the display substrate.

[0044] Figure 10D for Figure 9 The diagram shows a plan view of the third conductive layer of the display substrate.

[0045] Figure 11 A schematic diagram of a pixel driving unit provided in some embodiments of this disclosure;

[0046] Figure 12A for Figure 11 A plan view of the semiconductor pattern of the display substrate shown;

[0047] Figure 12B for Figure 11 The diagram shows a plan view of the first conductive layer of the display substrate.

[0048] Figure 12C for Figure 11 The diagram shows a plan view of the second conductive layer of the display substrate.

[0049] Figure 12D for Figure 11 The diagram shows a plan view of the third conductive layer of the display substrate.

[0050] Figure 13 A schematic diagram of a pixel driving unit provided in some embodiments of this disclosure;

[0051] Figure 14A for Figure 13A plan view of the semiconductor pattern of the display substrate shown;

[0052] Figure 14B for Figure 13 The diagram shows a plan view of the first conductive layer of the display substrate.

[0053] Figure 14C for Figure 13 The diagram shows a plan view of the second conductive layer of the display substrate.

[0054] Figure 14D for Figure 13 The diagram shows a plan view of the third conductive layer of the display substrate.

[0055] Figure 15 for Figure 13 The diagram shows a cross-sectional view of the display substrate along the cut line AA'; and

[0056] Figure 16 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0059] OLED display technology boasts strong competitiveness in the display market due to its advantages such as wide viewing angles, high contrast, fast response, low power consumption, foldability, and flexibility. In recent years, flexible display technology has developed rapidly, expanding from its primary application in mobile phones to smaller products like smartwatches and fitness trackers. Small OLED products offer numerous advantages, including portability and excellent display quality, making them highly sought after. However, even slight variations in brightness on small display screens are more easily noticed by users, significantly impacting their experience. Therefore, the uniformity of screen brightness is of paramount importance.

[0060] like Figure 1 As shown, in the 7T1C circuit structure, for the conductive channel of the dual-gate transistor (threshold compensation transistor) T3, during the layout design, it is generally routed through the gate insulating layer (Gate2) to connect the power supply voltage signal of the adjacent left pixel driving unit to block the conductive channel of transistor T3, prevent transistor T3 from leaking current, ensure that 7T1C works better, and prevent the screen from dimming due to current jumps, thus causing uneven screen brightness, commonly known as the "little pepper" design. For example, the "little pepper" design sp1 of transistor T3 that blocks the second column pixel driving unit P2 is connected to the first power line of the first column pixel driving unit P1 to receive the power supply voltage signal of the first column pixel driving unit; the "little pepper" design sp2 of transistor T3 that blocks the third column pixel driving unit P3 is connected to the first power line of the second column pixel driving unit P2 to receive the power supply voltage signal of the second column pixel driving unit; and the "little pepper" design sp3 of transistor T3 that blocks the fourth column pixel driving unit (not shown) is connected to the first power line of the third column pixel driving unit P3 to receive the power supply voltage signal of the third column pixel driving unit.

[0061] This "little chili pepper" design is common in the design of the 7T1C pixel circuit in the display area. However, due to the asymmetry of the 7T1C pixel circuit, the first column of pixel driving units P1 from the left in the display area does not have the "little chili pepper" design (e.g., Figure 1 As shown in the figure, the transistor T3 channel in the first column 7T1C circuit cannot be blocked, so the brightness of this column of pixel circuits will be darker overall, thus making the screen uniformity worse.

[0062] This disclosure provides at least one embodiment of a display substrate, comprising: a substrate; a display area disposed on the substrate, including a plurality of pixel driving units arranged in multiple rows and columns, each of the plurality of pixel driving units including a threshold compensation transistor, a first light-emitting control transistor and a storage capacitor, the threshold compensation transistor being connected to the first light-emitting control transistor and the storage capacitor respectively, the threshold compensation transistor including a first gate and a second gate, the active layer of the threshold compensation transistor including a first channel region corresponding to the first gate, a second channel region corresponding to the second gate and an intermediate region located between the first channel region and the second channel region, the first channel region and the second channel region being connected through the intermediate region; a plurality of light-blocking patterns, each light-blocking pattern including a first end and a second end, the first end of the plurality of light-blocking patterns being used to receive a voltage signal, and the second end of at least one of the plurality of light-blocking patterns at least partially overlapping with the intermediate region of the threshold compensation transistor of the outermost first pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate.

[0063] The display substrate provided in this embodiment can introduce a "little chili pepper" design structure in the first column of pixel driving units on the outermost side of the display area, reduce the leakage current capability of the dual-gate transistor, avoid dark lines appearing on the left edge of the screen, thereby improving the uniformity of the display screen brightness and improving the display quality of the display panel.

[0064] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0065] Figure 2A This is a planar schematic diagram of a display substrate provided for some embodiments of this disclosure. For example... Figure 2A As shown, the display substrate 10 has a display area 101 and a peripheral area 102 that at least partially surrounds (e.g., completely surrounds) the display area 101. For example, the display area 101 of the display substrate 10 can be circular in shape, and the peripheral area 102 surrounds the display area 101 and has an approximately circular outline, thereby giving the display substrate 10 a generally circular shape to meet the actual needs of users for display substrates of different shapes.

[0066] It should be noted that the specific shape of the display substrate is not limited in the embodiments disclosed herein. For example, Figure 2B This is a plan view of another display substrate provided for some embodiments of this disclosure. For example... Figure 2BAs shown, the display substrate 20 has a display area 201 and a peripheral area 202 that at least partially surrounds (e.g., completely surrounds) the display area 201. For example, the display area 201 of the display substrate 20 can be a square with rounded corners, and the peripheral area 202 surrounds the display area 201 and has the same outline as the display area 201, thereby making the display substrate 20 a square with rounded corners. In other embodiments of this disclosure, the display substrate can also be a regular shape such as an ellipse, sector, triangle, rhombus, or pentagon, or it can be other suitable irregular shapes. The embodiments of this disclosure do not limit this.

[0067] Figure 3 This is a schematic diagram of a display substrate provided for at least one embodiment of the present disclosure. Figure 4 This is a schematic diagram of the circuit structure of a pixel driving unit provided in at least one embodiment of the present disclosure. Figures 5A-5D They are respectively Figure 3 The diagram shows a plan view of the semiconductor pattern, first conductive layer, second conductive layer, and third conductive layer of the display substrate. For example, as shown... Figure 3 As shown, the display substrate 10 includes a substrate 100. The display area 101 includes a plurality of pixel driving units P0 arranged in an array on the substrate 100. It should be noted that... Figure 3 Only one pixel driving unit P0 is shown for example. The display area 101 also includes multiple rows and columns of pixel driving units P0. The embodiments of this disclosure are not limited in this respect.

[0068] For example, such as Figure 4 As shown, each of the plurality of pixel driving units P0 includes a threshold compensation transistor T3, a first light-emitting control transistor T5, and a storage capacitor C1. The threshold compensation transistor T3 is connected to both the first light-emitting control transistor T5 and the storage capacitor C1. The first light-emitting control transistor T5 is connected to the light-emitting element 20. For example, as shown... Figure 3 , Figure 5A and Figure 5B As shown, the threshold compensation transistor T3 includes a first gate G31 and a second gate G32. The active layer of the threshold compensation transistor T3 includes a first channel CN1 corresponding to the first gate G31, a second channel region CN2 corresponding to the second gate G32, and an intermediate region CP located between the first channel region CN1 and the second channel region CN2. The first channel region CN1 and the second channel region CN2 are connected through the intermediate region CP.

[0069] like Figure 3 and Figure 5CAs shown, the display substrate 10 also includes a plurality of light-blocking patterns sp (only one light-blocking pattern sp corresponding to a pixel driving unit is shown in the figure, and the embodiments disclosed herein are not limited thereto). For example, each light-blocking pattern sp includes a first end sp111 and a second end sp112. The first end sp111 of the plurality of light-blocking patterns sp is used to receive a voltage signal, and the second end sp112 of at least one of the plurality of light-blocking patterns sp at least partially overlaps with the middle region of the threshold compensation transistor of the outermost first pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate. For example, at least a portion of the second end sp112 of the multiple light-blocking patterns sp at least partially overlaps with the middle region CP of the threshold compensation transistor T3 of the outermost first pixel driving unit (i.e., the leftmost column of pixel driving units in the display area 101) in a direction perpendicular to the substrate 10, thereby blocking the threshold compensation transistor T3 of the leftmost column of pixel driving units in the display area 101, reducing the leakage current capability of the dual-gate transistor, avoiding dark lines on the left edge of the screen, thereby improving the uniformity of the brightness of the display screen and improving the display quality of the display panel.

[0070] It is important to note that the outermost first pixel driving unit of each row is the pixel driving unit located in the outermost first column of each row. That is, the first column pixel driving unit is relative to each row. For the entire arrangement of pixel driving units, the first column pixel driving unit refers to the outermost pixel unit. It is possible that the first pixel driving unit of all rows may not be located in the same column, but since they are all located on the outermost side of each row, they are all called the first column pixel driving unit. The following explanation uses the example of the first column pixel driving unit of each row representing the first pixel driving unit of each row. The following embodiments are the same and will not be repeated.

[0071] For example, the length of the light occlusion pattern corresponding to the outermost first column pixel driving unit of each row pixel driving unit is greater than the length of the light occlusion pattern corresponding to each pixel driving unit except for the outermost first column pixel driving unit of each row pixel driving unit.

[0072] It should be noted that, Figure 3 The light-blocking pattern in the image is the "little chili pepper" design mentioned above. Therefore, the display substrate provided in this embodiment can introduce the "little chili pepper" design structure in the first column of pixel driving units from the left in the display area, reducing the leakage current capability of the dual-gate transistor, avoiding dark lines on the left edge of the screen, thereby improving the uniformity of the display screen brightness and improving the display quality of the display panel.

[0073] Figure 5A for Figure 3 A plan view of the semiconductor pattern of the display substrate shown; Figure 5B for Figure 3 The diagram shows a plan view of the first conductive layer of the display substrate. Figure 5C for Figure 3 The diagram shows a plan view of the second conductive layer of the display substrate. Figure 5D for Figure 3 The diagram shows a plan view of the third conductive layer of the display substrate. The following is in conjunction with... Figures 3 to 5D The display substrate 10 of the present disclosure will be described in detail.

[0074] For example, such as Figures 5A-5D As shown, the first conductive layer LY1 includes a gate line GL, the second conductive layer LY2 includes the second electrode C12 of the storage capacitor C1, and the third conductive layer LY3 includes a first power line ELVDD1. For example, in a direction perpendicular to the substrate 100, a first insulating layer (not shown) is located between the active layer SCP and the first conductive layer LY1, a second insulating layer (not shown) is located between the gate line (i.e., the first conductive layer LY1) and the second conductive layer LY2, and a third insulating layer is located between the second electrode C12 of the storage capacitor C1 (i.e., the second conductive layer LY2) and the third conductive layer LY3.

[0075] For example, the light occlusion pattern corresponding to each pixel driving unit except the outermost first column pixel driving unit is connected to the first power line ELVDD corresponding to each column pixel driving unit.

[0076] For example, such as Figure 4 As shown, the pixel driving unit includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a second light-emitting control transistor T4, a first light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, a storage capacitor C1, and a light-emitting element 20. For example, each transistor and capacitor includes a first terminal and a second terminal. For a description of the connection relationship and working principle of this pixel driving unit, please refer to the descriptions in this field, which will not be repeated here.

[0077] For example, such as Figure 8A As shown, the active layers A6, A3, A5, and A7 of the first reset transistor T6, threshold compensation transistor T3, first light-emitting control transistor T5, and second reset transistor T7 are located in the first semiconductor layer. The active layers A2 and A4 of the data writing transistor T2 and second light-emitting control transistor T4 are located in the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are connected and integrally formed through the active layer A1 of the driving transistor T1.

[0078] For example, such as Figure 3 and 5AAs shown, the active layer A1 of the driving transistor T1 is located on the imaginary line of the active layer A6 of the first reset transistor T6 in the first direction Y1. The active layers A3 and A2 of the threshold compensation transistor T3 and the data writing transistor T2 are located on the left and right sides of the active layer A1 of the driving transistor T1, respectively, and are both located on the side of the active layer A1 of the driving transistor T1 closer to the active layer A6 of the first reset transistor T6. That is, in the second direction Y1, the active layers A3 and A2 of the threshold compensation transistor T3 and the data writing transistor T2 are located above the active layer A1 of the driving transistor T1. The active layers A5 and A4 of the first light-emitting control transistor T5 and the second light-emitting control transistor T4 are located on both sides of the active layer A1 of the driving transistor T1, respectively, and are located on the side of the active layer A1 of the driving transistor T1 away from the active layer A6 of the first reset transistor T6. For example, in the second direction Y1, they are located below the active layer A1 of the driving transistor T1.

[0079] It should be noted that in the embodiments disclosed herein, "up", "down", "left" and "right" are described relative to the up, down, left and right in the accompanying drawings, and are not limited to the display substrate, but can be determined according to the actual situation.

[0080] For example, such as Figure 3 and 5B As shown, the active layer A7 of the second reset transistor T7 is located on the side of the active layer A5 of the first light-emitting control transistor T5 that is away from the active layer of the threshold compensation transistor T3. The threshold compensation transistor T3 includes a first gate G31 extending along the second direction X1 and a second gate G32 extending along the first direction Y1. The first gate G31, the gate G5 of the first light-emitting control transistor T5 extending along the second direction X2, and the gate G7 of the second reset transistor T7 are arranged side by side in the first direction Y1. The gate G2 of the data writing transistor T2 and the gate G4 of the second light-emitting control transistor T4 extend along the second direction X1 and are arranged side by side in the first direction Y1.

[0081] For example, the gate G6 of the first reset transistor T6 and the gate G1 of the drive transistor T1 extend along the second direction X1 and are arranged side by side in the first direction Y1. The gate G1 of the drive transistor T1 is integrally formed with the first plate C11 of the storage capacitor C1.

[0082] For example, the display substrate also includes a gate line GL extending along the second direction Y1, a light emission control signal line EM, a first reset signal line RST1, and a second reset signal line (not shown in the figure, which is integrally formed with the gate of the second reset transistor T7).

[0083] For example, the gate G6 of the first reset transistor T6 is connected to and integrally formed with the first reset signal line RST1; the second gate G32 of the threshold compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to and integrally formed with the gate line GL; the gate G4 of the second light-emitting control transistor T4 and the gate G5 of the first light-emitting control transistor T5 are connected to and integrally formed with the light-emitting control signal line EM; and the gate of the second reset transistor T7 is connected to and integrally formed with the second reset signal line.

[0084] For example, the display substrate also includes a gate line GL, a light emission control signal line EM, a first reset signal line RST1, and a second reset signal line RST2 extending along the second direction Y1. For instance, the gate of the first reset transistor T6 is connected to and integrally formed with the first reset signal line RST1. The second gate G32 of the threshold compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to and integrally formed with the gate line GL. The gate G5 of the first light emission control transistor T5 and the gate G4 of the second light emission control transistor T4 are connected to and integrally formed with the light emission control signal line EM. The gate G7 of the second reset transistor T7 is connected to and integrally formed with the second reset signal line RST2.

[0085] For example, the display substrate also includes a data line DATA, which is connected to the active layer A4 of the data writing transistor T4 and configured to provide a data signal DATA. The orthographic projection of the first power line ELVDD1 on the substrate 100 at least partially overlaps with the orthographic projections of the active layer A6 of the first reset transistor T6 and the active layer A1 of the driving transistor T1 on the substrate 100. The orthographic projection of the data line DATA on the substrate 100 is located on the side of the second semiconductor layer on the substrate 100 away from the orthographic projection of the first power line ELVDD1 on the substrate 100.

[0086] For example, such as Figure 5D As shown, the pixel driving unit also includes a first transfer electrode EC1. The first transfer electrode EC1 is connected to the active layer A7 of the second reset transistor T7 and the second reset signal line RST2 through a via. The orthographic projection of the first transfer electrode EC1 on the substrate 100 is located between the orthographic projections of the active layer A7 of the second reset transistor T7 and the active layer A1 of the driving transistor T1 on the substrate 100.

[0087] For example, refer to Figure 3The gate line GL is configured to provide a scan signal SCAN to the pixel circuit 10. The light emission control signal line EM is configured to provide a light emission control signal EM to the sub-pixel P0. The data line DATA is configured to provide a data signal DATA to the pixel circuit 10. The first power supply line ELVDD1 is configured to provide a constant first power supply voltage ELVDD1 to the pixel circuit 10. The second power supply line ELVSS is configured to provide a constant second power supply voltage ELVSS to the pixel circuit 10, and the first power supply voltage ELVDD1 is greater than the second power supply voltage ELVSS. The initialization signal line Vinit is configured to provide an initialization signal Vinit to the pixel circuit 10. The initialization signal Vinit is a constant voltage signal, the magnitude of which may be, for example, between the first power supply voltage ELVDD1 and the second power supply voltage ELVSS, but is not limited thereto. For example, the initialization signal Vinit may be less than or equal to the second power supply voltage ELVSS. For example, the pixel circuit outputs a drive current to drive the light-emitting element 20 to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the initialization signal Vinit, the first power supply voltage ELVDD1, the second power supply voltage ELVSS, and the light emission control signal EM. The light-emitting element 20 emits red, green, blue, or white light under the drive of its corresponding pixel circuit 10.

[0088] It should be noted that DATA represents both a data line and a data signal, ELVDD1 represents both the first power supply line and the first power supply voltage, ELVDD2 represents the first power supply edge trace, EM represents both the light emission control signal line and the light emission control signal, RST1 represents both the first reset signal line and the first reset signal, RST2 represents both the second reset signal line and the second reset signal, Vinit represents both the initialization signal line and the initialization signal, and ELVSS represents both the second voltage signal line and the second voltage signal.

[0089] like Figure 3 As shown, the driving transistor T1 of the pixel driving unit P0 is electrically connected to the light-emitting element 20, and outputs driving current to drive the light-emitting element 20 to emit light under the control of signals such as scan signal SCAN, data signal DATA, first power supply voltage ELVDD1, and second power supply voltage ELVSS.

[0090] For example, the display panel provided in this embodiment further includes a data driving circuit and a scan driving circuit. The data driving circuit is configured to provide a data signal DATA to the pixel driving unit P0 according to the instructions of the control circuit; the scan driving circuit is configured to provide a light emission control signal EM, a scan signal SCAN, and a first reset control signal RST1 and a second reset signal RST2 to the pixel driving unit P0 according to the instructions of the control circuit. For example, the control circuit includes an external integrated circuit (IC), but is not limited thereto. For example, the scan driving circuit is a GOA (Gate driver On Array) structure mounted on the display panel, or a driver chip (IC) structure bonded to the display panel. For example, different driving circuits can also be used to provide the light emission control signal EM and the scan signal SCAN respectively. For example, the display panel also includes a power supply (not shown in the figure) to provide the above voltage signals, which can be a voltage source or a current source as needed. The power supply is configured to provide the first power supply voltage ELVDD1, the second power supply voltage ELVSS, and the initialization signal Vinit to the sub-pixel P0 through the first power supply line ELVDD1, the second power supply voltage ELVSS, and the initialization signal Vinit respectively.

[0091] like Figure 4 As shown, the second terminal C12 of storage capacitor C1 is electrically connected to the first power supply line ELVDD1, and the first terminal C11 of storage capacitor C1 is electrically connected to the second terminal T32 of threshold compensation transistor T3. The gate T20 of data write transistor T2 is electrically connected to the gate line GL, and the first terminal T21 and the second terminal T22 of data write transistor T2 are electrically connected to the data line DATA and the first terminal T11 of drive transistor T1, respectively. The gate T30 of threshold compensation transistor T3 is electrically connected to the gate line GL, the first terminal T31 of threshold compensation transistor T3 is electrically connected to the second terminal T12 of drive transistor T1, and the second terminal T32 of threshold compensation transistor T3 is electrically connected to the gate T10 of drive transistor T1.

[0092] For example, such as Figure 4 As shown, the gate T40 of the second light-emitting control transistor T4 and the gate T50 of the first light-emitting control transistor T5 are both connected to the light-emitting control signal line EM.

[0093] For example, such as Figure 4As shown, the first electrode T41 and the second electrode T42 of the second light-emitting control transistor T4 are electrically connected to the first power line ELVDD1 and the first electrode T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the first light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T16 and the pixel electrode E1 (which can be the anode of the OLED) of the light-emitting element 20, respectively. The common electrode E2 (which can be the common electrode of the OLED, such as the cathode) of the light-emitting element 20 is electrically connected to the second power line ELVSS.

[0094] For example, such as Figure 3 As shown, the gate T60 of the first reset transistor T6 is electrically connected to the first reset signal line RST1, the first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line Vinit (first initialization signal line 211), and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset signal line RST2, the first electrode T71 of the second reset transistor T7 is electrically connected to the initialization signal line Vinit (second initialization signal line 212), and the second electrode T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0095] Figure 5A The semiconductor pattern SCP is shown. Figure 5B A first conductive layer LY1 is shown, and a first insulating layer G11 is disposed between the first conductive layer LY1 and the semiconductor pattern SCP. Using the first conductive layer LY1 as a mask, the semiconductor pattern SCP is doped, such that the areas of the semiconductor pattern SCP not covered by the first conductive layer LY1 retain semiconductor properties, forming the channel of a thin-film transistor, while the areas of the semiconductor pattern SCP covered by the first conductive layer LY1 are made conductive, forming the source or drain of the thin-film transistor. Figure 5A The active layer formed after the semiconductor pattern SCP is partially conductive is shown.

[0096] like Figure 5B As shown, the first conductive layer LY1 includes a first reset signal line RST1, a second reset signal line (not shown in the figure), a light emission control signal line EM, a gate line GL, and the first electrode C11 of the storage capacitor C1.

[0097] Figure 5CA second conductive layer LY2 is shown, and a second insulating layer is disposed between the second conductive layer LY2 and the first conductive pattern layer LY1. The second conductive layer LY2 includes an initialization signal line Vinit and a second terminal C12 of a storage capacitor C1. The second terminal C12 of the storage capacitor C1 has an opening. An interlayer insulating layer is located between the second conductive layer LY2 and the third conductive layer LY3. Details regarding the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive layer LY1, the second conductive layer LY2, and the third conductive layer LY3 can be found in the descriptions in the art and will not be repeated here.

[0098] Figure 5D The third conductive layer LY3 is shown. The third conductive layer LY3 includes a first power line ELVDD1, a data line DATA, a first connection electrode EC1, a second connection electrode EC2, and a first electrode E1 of the light-emitting element 20.

[0099] It should be noted that the transistors used in some embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In one embodiment of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Therefore, the first and second terminals of all or some transistors in this disclosure can be interchanged as needed. For example, the first terminal of the transistor described in this disclosure can be the source, and the second terminal can be the drain; or, the first terminal of the transistor is the drain, and the second terminal is the source.

[0100] Furthermore, transistors can be classified into N-type and P-type transistors based on their characteristics. This disclosure uses an example where all transistors are P-type. Based on the description and teachings of this disclosure, those skilled in the art can readily conceive of using at least some N-type transistors in the pixel circuit of this disclosure, i.e., using N-type transistors or a combination of N-type and P-type transistors, without any inventive effort. Therefore, these implementations are also within the scope of this disclosure.

[0101] Figure 5A The pixel circuit of 7T1C is used as an example for illustration, and the embodiments of this disclosure include, but are not limited to, this. It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors or capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display base panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T3C structure; the embodiments of this disclosure do not limit this.

[0102] For example, in at least one embodiment of this disclosure, the substrate 100 can be a glass plate, a quartz plate, a metal plate, or a resin-based plate. For example, the material of the substrate can include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the substrate 100 can be a flexible substrate or a non-flexible substrate; the embodiments of this disclosure do not limit this.

[0103] For example, the materials of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may include inorganic insulating materials such as SiNx, SiOx, and SiNxOy, organic insulating materials such as organic resins, or other suitable materials, and the embodiments disclosed herein do not limit this.

[0104] For example, the material of the third conductive layer LY3 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, and the embodiments disclosed herein are not limited thereto. For example, the materials of the first conductive layer LY1 and the second conductive layer LY2 may be the same as the material of the third conductive layer LY3, and will not be described again here.

[0105] For example, the material of the semiconductor layer SCP can include oxide semiconductors, organic semiconductors, amorphous silicon, polycrystalline silicon, etc. For example, oxide semiconductors include metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)), and polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc. The embodiments of this disclosure are not limited in this regard. It should be noted that the source region and drain region mentioned above can be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure are not limited in this regard.

[0106] For example, such as Figure 3 As shown, the display substrate 10 also includes at least a peripheral region 102 surrounding the display area 101, a plurality of first power lines ELVDD1 located in the display area 101, and first power line edge traces ELVDD2 located in the peripheral region 102. For example, the first power line edge traces ELVDD2 are arranged around the display area to provide a first power supply voltage to the first power lines ELVDD1 located in the display area.

[0107] For example, multiple first power lines ELVDD1 extend along a first direction and are configured to connect to each column of pixel driving units in a plurality of pixel driving units to provide a first power supply voltage to each column of pixel driving units respectively; the first power line edge trace ELVDD2 is configured to connect to the multiple first power lines ELVDD1 to provide a first power supply voltage to the first power lines ELVDD1; the voltage signal includes the first power supply voltage.

[0108] For example, multiple light-blocking patterns SP include multiple first light-blocking patterns SP11. For example, as... Figure 2C As shown, the first power line edge trace ELVDD2 includes a first sub-conductor ELVDD21 and a second sub-conductor ELVDD22 extending along a first direction and arranged opposite to each other, and a third sub-conductor ELVDD23 and a fourth sub-conductor ELVDD24 extending along a second direction and arranged opposite to each other.

[0109] For example, the first sub-wire ELVDD21 is disposed on one side of the first column of pixel driving units near the plurality of pixel driving units.

[0110] For example, the first end sp111 of a plurality of first light-blocking patterns sp11 is connected to the first sub-conductor ELVDD21 to receive the first power supply voltage, and the second end sp112 of the plurality of first light-blocking patterns sp11 at least partially overlaps with the middle region CP of each pixel driving unit in the first column of pixel driving units in a direction perpendicular to the substrate 100.

[0111] It should be noted that only the first sub-wire is shown in the figure, and the embodiments disclosed herein are not limited thereto.

[0112] For example, the extension direction of the first light-blocking pattern sp11 is different from the extension direction of the first sub-conductor ELVDD21.

[0113] Figure 6 This is a plan view of another display substrate provided for some embodiments of this disclosure. For example... Figure 6 As shown, the display substrate 10 has a display area 101 and a peripheral area 102 that at least partially surrounds (e.g., completely surrounds) the display area 101. For example, the display area 101 of the display substrate 10 can be a rectangle with rounded corners, and the peripheral area 102 surrounds the display area 101 and has the same outline as the display area 101, thereby making the display substrate 10 a rectangle with rounded corners. The following description uses the display substrate 10 as an example, but the embodiments disclosed herein are not limited thereto.

[0114] like Figure 6 As shown, the display substrate 10 includes a first corner region cor1, a second corner region cor2, a third corner region cor3, and a fourth corner region cor4. For example, the first corner region cor1 and the second corner region cor2 are disposed on one side of the display substrate 10 (e.g., Figure 6 The left side of the display substrate shown); the third corner region cor3 and the fourth corner region cor4 are located on the other side of the display substrate (e.g., the left side of the display substrate); Figure 6(The right side of the display substrate shown). For example, the compensation capacitor is located in any two corner regions of different columns in the first corner region cor1, the second corner region cor2, the third corner region cor3, and the fourth corner region cor4, for example, in the first corner region cor1 and the fourth corner region cor4. For example, the function of this compensation capacitor will be described in detail below.

[0115] Figure 7 for Figure 6 A schematic diagram of the stacked structure of the first corner region cor1 shown; Figure 8A for Figure 7 A plan view of the semiconductor pattern of the display substrate shown; Figure 8B for Figure 7 The diagram shows a plan view of the first conductive layer of the display substrate. Figure 8C for Figure 7 The diagram shows a plan view of the second conductive layer of the display substrate. Figure 8D for Figure 7 The diagram shows a plan view of the third conductive layer of the display substrate. The following is in conjunction with... Figures 7 to 8D The display substrate 10 of the present disclosure will be described in detail.

[0116] For example, the display substrate 10 further includes: multiple signal lines (e.g., the multiple first power lines ELVDD1, first power line edge trace ELVDD2, data line DATA, initialization signal line Vinit, light emission control signal line EM, gate line GL, and first reset signal line RST1) that are electrically connected to multiple pixel driving units respectively, a first electrode pattern C01 that is electrically connected to at least one of the multiple signal lines in the peripheral region, and a second electrode pattern C02 that is located in the peripheral region.

[0117] For example, in embodiments of this disclosure, the signal line is a gate line GL or a data line DATA. It should be noted that... Figures 7 to 8D The present invention uses the data line (DATA) as an example for illustration, but the embodiments disclosed herein are not limited thereto.

[0118] For example, the first electrode pattern C01 and the second electrode pattern C02 are located on the side of the outermost first column of pixel driving units in the peripheral area, close to at least one row of pixel driving units. The first electrode pattern C01 and the second electrode pattern C02 at least partially overlap and are insulated in a direction perpendicular to the surface of the substrate 100 to form a compensation capacitor C0. The capacitance formed between the first electrode pattern C01 and the second electrode pattern C02 can compensate for the transmission load on the signal lines electrically connected to the first electrode pattern C01 (e.g., the transmission load on the signal lines can refer to the transmission resistance of the signal lines, or the capacitance formed between the signal lines and other traces), thereby improving the consistency of the transmission load on multiple signal lines in the display area 101. This improves the signal transmission effect of multiple signal lines in the display area 101, enhances the brightness uniformity and consistency of the provided display image, thereby reducing or avoiding display abnormalities or defects, and improving the display effect.

[0119] For example, such as Figure 7 and Figure 8D As shown, when the signal line is a data line DATA, the transmission load on the data line DATA, which is electrically connected to the first electrode pattern C01, is compensated by the compensation capacitor formed between the first electrode pattern C01 and the second electrode pattern O2, thereby improving the transmission effect of, for example, the data signal transmitted on the data line DATA and enhancing the consistency of the transmission effect of the data signal on multiple data lines in the display area 101.

[0120] For example, the first electrode pattern C01 is located in the first conductive layer LY1, and the second electrode pattern C02 is located in the second conductive layer LY2. For example, the first electrode pattern C01 is connected to a signal line (i.e., a data line DATA) through a via to receive a data signal; the second electrode pattern C02 is connected to a first power line ELVDD1 through a via to receive a first power supply voltage, thereby forming a compensation capacitor between the first electrode pattern C01 and the second electrode pattern C02 to compensate for the load capacitance of the signal line. The connection of the second electrode pattern C02 to the first power line ELVDD1 through a via to receive the first power supply voltage allows the second electrode pattern C02 to have a stable voltage, thereby improving the stability of the compensation capacitor formed between the first electrode pattern C01 and the second electrode pattern C02. Furthermore, this first voltage signal further reduces or avoids interference from other structures or devices on the side of the display substrate 10 located away from the substrate 100 of the second electrode pattern C02 on the electrical signals transmitted on the first electrode pattern C01. For example, the first power supply voltage can be a high-level voltage signal or a low-level voltage signal; the embodiments of this disclosure are not limited in this regard.

[0121] For example, the light-blocking pattern sp further includes at least one second light-blocking pattern sp12. For example, as... Figure 8A and 8C As shown, at least one second light-blocking pattern sp12 has its first end sp121 connected to and integrally formed with the second electrode pattern C02. The second end sp122 of at least one second light-blocking pattern sp12 and the middle region CP of the threshold compensation transistor T3 of the first column of the first row of pixel driving units (e.g., the first row and first column of pixel driving units P0(1,4)) adjacent to the second electrode pattern C02 in the second direction X1 at least partially overlap in a direction perpendicular to the surface of the substrate 100. This allows the introduction of a "little chili pepper" design structure in the outermost first column of pixel driving units in the display area, reducing the leakage current capability of the dual gate transistor T3, avoiding dark lines on the left edge of the screen, thereby improving the uniformity of the display screen brightness and improving the display quality of the display panel.

[0122] For example, at least one row of pixel driving units adjacent to the first electrode pattern C01 or the second electrode pattern C02 in the second direction X1 (e.g., such as...) Figure 6 The number of pixels in the first row pixel driving unit P0(1) shown is less than that of the row of pixel driving units adjacent to the first electrode pattern C01 or the second electrode pattern C02 in the first direction Y1 (e.g., such as...). Figure 6 The number of pixels shown is the number of pixels in the second row pixel driving unit P0(2).

[0123] For example, such as Figure 7 , Figure 8A and Figure 8B As shown, multiple first electrode patterns C01 are spaced apart. For example, in a direction parallel to the surface of the substrate 100, the peripheral region 102 also includes a spacing pattern 190 located between two adjacent first electrode patterns C01 and insulated from each other. The spacing pattern 190 can reduce or avoid signal interference between adjacent first electrode patterns C01 and improve the stability of the electrical signal transmitted on the first electrode pattern C01.

[0124] For example, in some embodiments of this disclosure, the spacer pattern 190 can be electrically connected to the second electrode pattern C02 to receive a first power supply voltage from the first power supply line ELVDD1. This allows for the formation of a capacitor between the spacer pattern 190 and the adjacent first electrode pattern C01 in a plane parallel to the surface of the substrate 100, and further optimizes the layout structure within the peripheral region 102 of the display substrate 10, thereby helping the display substrate 10 achieve a narrow bezel design.

[0125] For example, in some other embodiments of this disclosure, the spacing pattern 190 may be configured to receive a second power supply voltage from a second power supply line different from the first power supply line. This allows the spacing pattern 190 and the adjacent first electrode pattern C01 to form a capacitor in a plane parallel to the surface of the substrate 100, thereby further improving the compensation effect on the transmission load on the data line DATA electrically connected to the first electrode pattern C01, and further improving the stability and consistency of the signal transmission effect of multiple data lines DATA in the display area 101.

[0126] For example, the orthographic projection of the data line DATA on the substrate overlaps at least partially with the orthographic projection of the storage capacitor C1 on the substrate.

[0127] For example, such as Figure 8A As shown, the spacer pattern 190 is located on the semiconductor pattern SCP and can be connected to the second electrode pattern CO2 via vias through a via structure that penetrates at least the first insulating layer, the second insulating layer, and the third insulating layer. The embodiments disclosed herein do not limit this connection. Therefore, by forming the spacer pattern 190 and the active layer of the thin-film transistor in the same layer during the fabrication process (e.g., using the same material layer through a patterning process), the fabrication process of the display substrate 10 can be further simplified, and the fabrication cost of the display substrate 10 can be reduced, thereby facilitating the mass production and application of the display substrate 10.

[0128] For example, in some embodiments of this disclosure, the spacing pattern 19 extends along the first direction Y1 and is elongated; while in other embodiments of this disclosure, the spacing pattern 190 may also extend in a curved, zigzag or other suitable contour, and the shape of the spacing pattern 190 may also be, for example, elliptical, square, zigzag or other suitable regular or irregular shape as needed. The embodiments of this disclosure do not limit this.

[0129] For example, in some embodiments of this disclosure, since the peripheral region 102 with the spacing pattern 190 is provided at least partially surrounding the display region 101 and along the edge of the display region 101, by providing the spacing pattern 190 which is in the same layer as the active layer of the thin film transistor, the excessive etching of the active layer near the edge of the display region 101 during the fabrication of the display substrate 10 can be reduced or avoided, thereby improving the etching uniformity at the boundary position of the display region 101 and achieving a better etching effect.

[0130] It should be noted that, in order to be clear and concise, Figures 7-8D and Figures 3-6 Similar parts are not shown here, and the structure of the pixel driving unit P0 can be found in [reference]. Figures 5A-5D The description will not be repeated here. The following embodiments are the same and will not be repeated.

[0131] It should also be noted that, in order to be clear and concise, Figure 7 Only some pixel driving units P0(1,4)-P0(2,5) located in the first and second rows are shown. The display substrate 10 may also include more pixel driving units P0, and the embodiments disclosed herein are not limited thereto. The following embodiments are the same and will not be described again.

[0132] Figure 9 for Figure 6 A schematic diagram of the stacked structure of the second corner region cor2 shown; Figure 10A for Figure 9 A plan view of the semiconductor pattern of the display substrate shown; Figure 10B for Figure 9 The diagram shows a plan view of the first conductive layer of the display substrate. Figure 10C for Figure 9 The diagram shows a plan view of the second conductive layer of the display substrate. Figure 10D for Figure 9 The diagram shows a plan view of the third conductive layer of the display substrate. The following is in conjunction with... Figures 9 to 10D A display substrate 10 according to another embodiment of the present disclosure will be described in detail.

[0133] For example, such as Figure 9 As shown, the display substrate 10 also includes a power connection trace ELVDD3, located on the side of the peripheral region 102 near the outermost first column of pixel driving units of at least one row of pixel driving units. For example, the power connection trace ELVDD3 is located in the first conductive layer LY1 and is connected to the first power line ELVDD1 and the peripheral first power line edge trace ELVDD2 through a via penetrating the second insulating layer and the third insulating layer to receive the first power supply voltage.

[0134] For example, such as Figure 9 and Figure 10C As shown, the light-blocking pattern sp also includes at least one third light-blocking pattern sp13 located in the second conductive layer LY2. For example, the first end sp131 of the at least one third light-blocking pattern sp13 is connected to the power connection trace ELVDD3, for example, through a via penetrating the third insulating layer; the second end sp132 of the at least one third light-blocking pattern sp13 and the middle region CP of the threshold compensation transistor T3 of the first column of the first row of pixel driving units adjacent to the power connection trace ELVDD3 in the second direction X1 at least partially overlap in the direction perpendicular to the substrate 10, thereby introducing a "small chili pepper" design structure in the outermost first column of pixel driving units of the display area, reducing the leakage current capability of the dual-gate transistor T3, avoiding dark lines on the left edge of the screen, thereby improving the uniformity of the display screen brightness and improving the display quality of the display panel.

[0135] For example, such as Figure 9 As shown, at least one row of pixel driving units (e.g., as shown) adjacent to the power connection trace ELVDD3 in the second direction X1. Figure 9 As shown, the number of pixels in at least one row of pixel driving units located to the left of the second corner region cor2 is less than the number of pixels in one row of pixel driving units adjacent to the power connection trace ELVDD3 in the first direction Y1 (e.g., as shown). Figure 9 As shown, this represents the number of pixels in each row of pixel driving units located on the upper side of the second corner region cor2.

[0136] For example, such as Figure 9 and Figure 10D As shown, the display substrate further includes: a first transition electrode EL1 located in the third conductive layer LY3. For example, the first end EL11 of the first transition electrode EL1 is connected to the power connection trace ELVDD3 through a via penetrating the second insulating layer and the third insulating layer, and the second end EL12 of the first transition electrode EL1 is connected to at least one third light-blocking pattern sp13 through a via penetrating the third insulating layer.

[0137] For example, in Figure 6 In the display substrate shown, the middle region CP of the threshold compensation transistor T3 in the outermost first column of the pixel driving unit of at least one row of pixel driving units located to the left of the first corner region cor1 of the display substrate 10 is blocked by the second end sp122 of the second light blocking pattern sp12 connected to the second electrode pattern C02 of the compensation capacitor in the first corner region cor1; the middle region CP of the threshold compensation transistor T3 in the outermost first column of the pixel driving unit of at least one row of pixel driving units located to the left of the second corner region cor2 of the display substrate 10 is blocked by the third light blocking pattern connected to the power connection trace ELVDD3 in the second corner region cor2. The second end of sp13, sp132, is blocked; the middle region CP of the threshold compensation transistor T3 in the outermost first column of the pixel driving unit of at least one row of pixel driving units located between the first corner region cor1 and the second corner region of the display substrate 10 is blocked by the second end of the first light blocking pattern sp11, sp112, which is connected to the first power line edge trace ELVDD2 in the peripheral region 102. This allows the introduction of a "little chili pepper" design structure in the outermost first column of pixel driving units of the display area, reduces the leakage current capability of the dual gate transistor T3, avoids dark lines on the left edge of the screen, thereby improving the uniformity of the brightness of the display screen and improving the display quality of the display panel.

[0138] Figure 11 A schematic diagram of a pixel driving unit provided for at least one embodiment of this disclosure; Figure 12A for Figure 11 A plan view of the semiconductor pattern of the display substrate shown; Figure 12B for Figure 11 The diagram shows a plan view of the first conductive layer of the display substrate. Figure 12C for Figure 11 The diagram shows a plan view of the second conductive layer of the display substrate. Figure 12D for Figure 11 The diagram shows a plan view of the third conductive layer of the display substrate. The following is in conjunction with... Figures 11 to 12D A display substrate 10 according to an embodiment of the present disclosure will be described in detail.

[0139] For example, such as Figures 11-12D As shown, the first end sp1 of at least one of the multiple light-blocking patterns sp is connected to the first power line ELVDD1 corresponding to the outermost first column of pixel driving units of at least one row of pixel driving units to receive the first power supply voltage as a voltage signal; the second end sp2 of the multiple light-blocking patterns sp and the middle region of the threshold compensation transistor T3 of each pixel driving unit in the first column of pixel driving units at least partially overlap in the direction perpendicular to the substrate 100, thereby enabling the introduction of a "little chili pepper" design structure in the outermost first column of pixel driving units of the display area, reducing the leakage current capability of the dual gate transistor T3, avoiding the appearance of dark lines on the left edge of the screen, thereby improving the uniformity of the brightness of the display screen and improving the display quality of the display panel.

[0140] For example, in an embodiment of this disclosure, the first power line is connected to each column of pixel driving units, and the first end of the light-blocking pattern is connected to the first power line corresponding to each column of pixel driving units, that is, for example, in Figure 7 In the display area shown, the first end of the light-blocking pattern corresponding to the pixel driving unit in the 4th column of the 1st row (the outermost 1st column of the 1st row) is connected to the first power line corresponding to the 4th column of the pixel driving unit. The first end of the light-blocking pattern corresponding to the pixel driving unit in the 1st column of the 2nd row is connected to the first power line corresponding to the 1st column of the pixel driving unit. The first end of the light-blocking pattern corresponding to the pixel driving unit in the 1st column of the 3rd row is connected to the first power line corresponding to the 1st column of the pixel driving unit, and so on. That is, the light-blocking pattern corresponding to the 1st column of the pixel driving unit in each row is connected to the first power line ELVDD1 (located in the display area) corresponding to the 1st column of the pixel driving unit in that row. This avoids the first end of the light-blocking pattern from being connected to the edge trace ELVDD2, the second electrode pattern C02, or the power connection trace ELVDD3 in the surrounding area. This simplifies the manufacturing process of the display substrate and is more conducive to the realization of a narrow bezel on the display substrate.

[0141] It should be noted that, in order to be clear and concise, Figure 11The circuit structure of a single pixel driving unit is used as an example for explanation. The circuit structure of the display substrate with more pixel driving units is similar. Figure 11 The pixel driving unit shown is similar and will not be described again here. For a detailed introduction to pixel driving units, please refer to [link / reference needed]. Figures 5A-5D The relevant descriptions will not be repeated here.

[0142] Figure 13 A schematic diagram of a pixel driving unit provided for at least one embodiment of this disclosure; Figure 14A for Figure 13 A plan view of the semiconductor pattern of the display substrate shown; Figure 14B for Figure 13 The diagram shows a plan view of the first conductive layer of the display substrate. Figure 14C for Figure 13 The diagram shows a plan view of the second conductive layer of the display substrate. Figure 14D for Figure 13 The diagram shows a plan view of the third conductive layer of the display substrate. Figure 15 for Figure 13 The diagram shows a cross-sectional view of the display substrate along the cutoff line AA'. The following is in conjunction with... Figures 13 to 15 A display substrate 10 according to an embodiment of the present disclosure will be described in detail.

[0143] For example, the display substrate 10 also includes an initialization signal line Vinit configured to provide an initialization signal to a plurality of pixel driving units, such as the voltage signal mentioned above, which includes the initialization signal. It should be noted that the voltage signal may also include other constant voltage signals, and the embodiments of this disclosure are not limited thereto.

[0144] For example, such as Figure 4 and Figures 5A-5D As shown, each of the multiple pixel driving units further includes a first reset transistor T6 and a second reset transistor T7; the first terminal of the first reset transistor T6 is connected to the initialization signal line Vinit to receive an initialization signal, the second terminal of the first reset transistor T6 is connected to the threshold compensation transistor T3, and the gate of the first reset transistor T6 is connected to the first reset signal line RST1 to receive a first reset signal; the first terminal of the second reset transistor T7 is connected to the initialization signal line Vinit to receive an initialization signal, the second terminal of the second reset transistor T7 is connected to the first light-emitting control transistor T5 and the light-emitting element 20, and the gate of the second reset transistor T7 is connected to the second reset signal line RST2 to receive a second reset signal.

[0145] For example, the active layer of the first reset transistor T6 and the active layer of the drive transistor T1 at least partially overlap with the first power line ELVDD.

[0146] For a detailed description of this pixel driving unit, please refer to [link / reference needed]. Figures 5A to 5D The description will not be repeated here.

[0147] For example, such as Figures 13-15 As shown, the display substrate also includes multiple second transition electrodes EL2, a first insulating layer 350, a second insulating layer 360, and a third insulating layer 370. The first ends EL21 of the multiple second transition electrodes EL2 are respectively connected to the initialization signal line Vinit through vias penetrating the third insulating layer 370 to receive the initialization signal. The second ends EL22 of the multiple second transition electrodes EL2 are also respectively connected to the first electrode D6 of the first reset transistor T6 in each pixel driving unit of the outermost first column pixel driving unit through vias penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The first electrode D6 of the first reset transistor T6 in each pixel driving unit of the outermost first column pixel driving unit is respectively connected to the first end sp1 of multiple light-blocking patterns sp through vias penetrating the first insulating layer 350 and the second insulating layer 360.

[0148] like Figure 15 As shown, the second end sp2 of multiple light-blocking patterns sp and the middle region cp of the threshold compensation transistor T3 of each pixel driving unit in the outermost first column of pixel driving units overlap at least partially in the direction perpendicular to the substrate 100. This allows the introduction of a "little chili pepper" design structure (i.e., light-blocking pattern sp) in the outermost first column of pixel driving units of the display area, reducing the leakage current capability of the dual-gate transistor T3, avoiding dark lines on the left edge of the screen, thereby improving the uniformity of the display screen brightness and improving the display quality of the display panel.

[0149] For example, in embodiments of this disclosure, the initialization signal line Vinit is connected to each row of pixel driving units, and the first end sp1 of the light occlusion pattern sp is connected to the corresponding initialization signal line Vinit of each row of pixel driving units, that is, for example, in Figure 7In the display area shown, the first end of the light-blocking pattern corresponding to the pixel driving unit in the 1st row and 4th column is connected to the initialization signal line Vinit corresponding to the pixel driving unit in the 1st row. The first end of the light-blocking pattern corresponding to the pixel driving unit in the 2nd row and 1st column is connected to the initialization signal line Vinit corresponding to the pixel driving unit in the 2nd row. The first end of the light-blocking pattern corresponding to the pixel driving unit in the 3rd row and 1st column is connected to the initialization signal line Vinit corresponding to the pixel driving unit in the 3rd row. And so on. That is, the light-blocking pattern corresponding to the pixel driving unit in the 1st column of each row is connected to the initialization signal line Vinit (located in the display area) corresponding to the pixel driving unit in that row. This avoids the first end of the light-blocking pattern from being connected to the first power line edge trace ELVDD2, the second electrode pattern C02, or the power connection trace ELVDD3 in the surrounding area. This simplifies the manufacturing process of the display substrate and is more conducive to the realization of a narrow bezel on the display substrate.

[0150] It should be noted that, in order to be clear and concise, Figure 13 The circuit structure of a single pixel driving unit is used as an example for explanation. The circuit structure of the display substrate with more pixel driving units is similar. Figure 13 The pixel driving unit shown is similar and will not be described again here. For a detailed introduction to pixel driving units, please refer to [link / reference needed]. Figures 5A-5D The relevant descriptions will not be repeated here.

[0151] Figure 16 This is a schematic diagram of a display device provided in at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2, which may include the display substrate 10 / 20 of any of the above embodiments.

[0152] For example, such as Figure 16 As shown, the display device 2 may also include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to a bonding area of ​​the display substrate 10, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

[0153] For example, a control chip can be a central processing unit (CPU), a digital signal processor (DSP), or a system-on-a-chip (SoC). For example, a control chip can also include memory, a power supply module, etc., and achieve power supply and signal input / output functions through separately provided wires and signal lines. For example, a control chip can also include hardware circuitry and computer-executable code. Hardware circuitry can include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; hardware circuitry can also include field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc.

[0154] For example, the display device 2 provided in at least one embodiment of this disclosure can be any product or component with display function, such as an OLED panel, OLED TV, QLED panel, QLED TV, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator. The display device 2 may also include other components, such as data driving circuitry, timing controllers, etc., which are not limited in the embodiments of this disclosure.

[0155] It should be noted that, for clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the display device. To realize the substrate function of the display device, those skilled in the art can provide and set other structures (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.

[0156] For the technical effects of the display device provided in the above embodiments, please refer to the technical effects of the display substrate provided in the embodiments of this disclosure, which will not be repeated here.

[0157] The following points need to be explained:

[0158] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0159] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0160] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; The display area is disposed on the substrate and includes multiple pixel driving units arranged in multiple rows and columns. Each of the multiple pixel driving units includes a threshold compensation transistor, a first light-emitting control transistor, and a storage capacitor. The threshold compensation transistor is connected to the first light-emitting control transistor and the storage capacitor. The threshold compensation transistor includes a first gate and a second gate. The active layer of the threshold compensation transistor includes a first channel region corresponding to the first gate, a second channel region corresponding to the second gate, and an intermediate region located between the first channel region and the second channel region. The first channel region and the second channel region are connected through the intermediate region. Multiple light-blocking patterns, wherein each light-blocking pattern includes a first end and a second end, the first end of the multiple light-blocking patterns is used to receive a voltage signal, and the second end of at least one of the multiple light-blocking patterns at least partially overlaps with the middle region of the threshold compensation transistor of the outermost first pixel driving unit of at least one row of pixel driving units in a direction perpendicular to the substrate. The display substrate further includes at least a peripheral region surrounding the display area; the display substrate further includes a plurality of first power lines located in the display area and edge traces of the first power lines located in the peripheral region, the plurality of first power lines extending along a first direction and configured to connect to each column of pixel driving units in the plurality of pixel driving units to provide a first power voltage to each column of pixel driving units respectively; the edge traces of the first power lines are configured to connect to the plurality of first power lines to provide the first power voltage to the first power lines; the edge traces of the first power lines include a first sub-conductor extending along the first direction; the first sub-conductor is disposed on one side close to the first pixel driving unit of the plurality of pixel driving units; the width of the first sub-conductor is greater than the width of the first power line; The voltage signal includes the first power supply voltage; The plurality of light-blocking patterns include a plurality of first light-blocking patterns and a plurality of fourth light-blocking patterns, wherein the length of the first light-blocking pattern is greater than the length of the fourth light-blocking pattern; The first end of the plurality of first light-blocking patterns is connected to the first sub-conductor, and the second end of at least one of the plurality of first light-blocking patterns at least partially overlaps with the middle region of the threshold compensation transistor of the first pixel driving unit of the at least one row of pixel driving units in a direction perpendicular to the substrate. Each of the fourth light-blocking patterns corresponds to one of the pixel driving units, and its first end is connected to a first power line connected to the corresponding pixel driving unit; the second end of the fourth light-blocking pattern extends to an adjacent pixel driving unit located on the side of the corresponding pixel driving unit away from the first sub-wire, and at least partially overlaps with the middle region of the threshold compensation transistor of the adjacent pixel driving unit in a direction perpendicular to the substrate. The display substrate further includes multiple signal lines electrically connected to the plurality of pixel driving units respectively; no pixel driving units are disposed between the first light blocking pattern and the first sub-conductor, and the signal lines do not overlap with the substrate in a direction perpendicular to the substrate.

2. The display substrate according to claim 1, wherein, The first power line edge routing includes a second sub-conductor extending along the first direction and disposed opposite to the first sub-conductor, and a third and fourth sub-conductors extending along the second direction and disposed opposite to each other.

3. The display substrate according to claim 2, further comprising: A first electrode pattern located in the peripheral area and electrically connected to at least one of the plurality of signal lines, and a second electrode pattern located in the peripheral area; The first electrode pattern and the second electrode pattern are located on the side of the peripheral region closest to the outermost first pixel driving unit of the at least one row of pixel driving units; The first electrode pattern and the second electrode pattern at least partially overlap and are insulated from each other in a direction perpendicular to the surface of the substrate.

4. The display substrate according to claim 3, wherein, The first electrode pattern is connected to the signal line through a via to compensate for the load capacitance of the signal line; The second electrode pattern is connected to the first power line through a via to receive the first power supply voltage.

5. The display substrate according to claim 4, wherein, The light-blocking pattern further includes: at least one second light-blocking pattern; In this configuration, the first end of the at least one second light-blocking pattern is connected to and integrally formed with the second electrode pattern. The second end of the at least one second light-blocking pattern at least partially overlaps with the middle region of at least one threshold compensation transistor of the first pixel driving unit of at least one row of pixel driving units adjacent to the second electrode pattern in the second direction in a direction perpendicular to the substrate.

6. The display substrate according to claim 5, wherein, The number of pixels in at least one row of pixel driving units adjacent to the first electrode pattern or the second electrode pattern in the second direction is less than the number of pixels in one row of pixel driving units adjacent to the first electrode pattern or the second electrode pattern in the first direction.

7. The display substrate according to claim 1, wherein, The extension direction of the first light-blocking pattern is different from the extension direction of the first sub-conductor.

8. The display substrate according to claim 5, wherein, The multiple signal lines include data lines or gate lines.

9. The display substrate according to claim 8, wherein, The orthographic projection of the data line on the substrate at least partially overlaps with the orthographic projection of the storage capacitor on the substrate.

10. The display substrate according to claim 9, further comprising a power connection trace located on the side of the peripheral region near the outermost first pixel driving unit of the at least one row of pixel driving units; The power connection trace is connected to the first power line through a via to receive the first power voltage; The light-blocking pattern further includes at least one third light-blocking pattern; the first end of the at least one third light-blocking pattern is connected to the power connection trace; the second end of the at least one third light-blocking pattern at least partially overlaps with the middle region of the threshold compensation transistor of the first pixel driving unit of at least one row of pixel driving units adjacent to the power connection trace in the second direction in a direction perpendicular to the substrate. The third light-blocking pattern does not overlap with the power connection trace in a direction perpendicular to the substrate.

11. The display substrate according to claim 10, wherein, The number of pixels in each row of pixel driving units adjacent to the power connection trace in the second direction is less than the number of pixels in each row of pixel driving units adjacent to the power connection trace in the first direction.

12. The display substrate according to claim 10, further comprising: The first adapter electrode, wherein the first end of the first adapter electrode is connected to the power connection trace through a via, and the second end of the first adapter electrode is connected to the at least one third light-blocking pattern through a via.

13. The display substrate according to claim 1, wherein, At least one of the plurality of light-blocking patterns has its first end connected to the first power line corresponding to the outermost first pixel driving unit of the at least one row of pixel driving units to receive the first power supply voltage as the voltage signal.

14. The display substrate according to claim 1, further comprising an initialization signal line configured to provide an initialization signal to the plurality of pixel driving units; in, The voltage signal includes the initialization signal.

15. The display substrate according to claim 14, wherein, Each of the plurality of pixel driving units further includes a first reset transistor and a second reset transistor; Wherein, the first terminal of the first reset transistor is connected to the initialization signal line to receive the initialization signal, the second terminal of the first reset transistor is connected to the threshold compensation transistor, and the gate of the first reset transistor is connected to the first reset signal line to receive the first reset signal; The first terminal of the second reset transistor is connected to the initialization signal line to receive the initialization signal, the second terminal of the second reset transistor is connected to the first light-emitting control transistor, and the gate of the second reset transistor is connected to the second reset signal line to receive the second reset signal.

16. The display substrate according to claim 15, further comprising a plurality of second transition electrodes, a first insulating layer, a second insulating layer, and a third insulating layer. in, The first ends of the plurality of second adapter electrodes are respectively connected to the initialization signal line to receive the initialization signal, and the second ends of the plurality of second adapter electrodes are respectively connected to the first electrode of the first reset transistor of the outermost first pixel driving unit of each row pixel driving unit through vias penetrating the first insulating layer, the second insulating layer and the third insulating layer. The first electrode of the first reset transistor of the outermost first pixel driving unit is connected to the first end of the plurality of light-blocking patterns through vias penetrating the first insulating layer and the second insulating layer, respectively.

17. The display substrate according to claim 15, wherein, The pixel driving unit further includes a driving transistor; The active layer of the first reset transistor and the active layer of the drive transistor at least partially overlap with the first power line.

18. The display substrate according to claim 8, wherein, In a direction perpendicular to the substrate, the area where the second light-blocking pattern overlaps with the first power line is greater than the area where the second light-blocking pattern overlaps with the data line.

19. The display substrate according to claim 12, wherein, In a direction perpendicular to the substrate, the signal line that overlaps with the first adapter electrode does not overlap with the power connection trace, and the signal line that overlaps with the power connection trace does not overlap with the first adapter electrode.

20. The display substrate according to claim 2, further comprising a connecting portion extending along the second direction, the connecting portion comprising a first portion and a second portion, the first portion being connected between the first sub-wire and the storage capacitor, and the second portion being connected between the storage capacitors of two adjacent pixel driving units in a row of pixel driving units.

21. A display device comprising the display substrate according to any one of claims 1-20.

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