A management method for fast application and release of pointers
By using two bitmap_ram and 64bit registers in the network security processing chip for cache pointer management, the problem of low efficiency in cache pointer application release in hardware design is solved, and the rapid application release is achieved during data reception and transmission is achieved, and the chip's performance and bandwidth processing capabilities are improved.
Patent Information
- Application Number
- CN202210172825.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-24
- Publication Date
- 2025-05-09
- Estimated Expiration
- 2042-02-24
AI Technical Summary
In hardware design, especially in chip design, the application release efficiency of cache pointers is low, resulting in unpredictable cache idle state, affecting the efficiency of data reception and transmission.
Two bitmap_ram (bitmap_ram0 and bitmap_ram1) are used to store the idle state of the cache pointer, and poll and manage the 64bit registers row_bmap0 and row_bmap1 to ensure the quick application and release of the cache pointer.
It realizes that when data is received and sent, the application and release of cache pointers can be completed when shooting, and improves the chip's performance and bandwidth processing capabilities.
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Figure CN114416380B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of hardware design, and relates to a management method for fast application and release of pointers, and specifically to a management method for application and release of cache pointers in a network security processing chip. Background Art
[0002] Memory pointer request release is generally a concept in software design and is rarely involved in hardware design, especially chip design. In most chip designs, the read-write pointer method is used to write received messages into or read out of the cache. In this way, the idle state of the cache is related to the read-write pointer, and the cache idle state is certain. In some chip designs, due to load balancing problems under the multi-cache processing architecture, or because the message input and output do not follow the first-in-first-out rule, in this scenario, the input message is not stored continuously in the cache, which will cause the cache idle state to be unpredictable. At this time, it is necessary to manage the request release of the cache pointer.
[0003] In software design, pointer application and release mainly focus on memory leaks (pointer application but not release) and repeated memory release (valid pointer is released twice or more).
[0004] In hardware design, in addition to paying attention to the above two issues, you also need to pay attention to the efficiency of pointer release. Whether the pointer release can be completed at the same time as data is received and sent is a major difficulty in pointer management in chip design. Summary of the invention
[0005] 1. Technical issues to be resolved
[0006] The technical problem to be solved by the present invention is how to provide a management method for quickly applying for and releasing a pointer, so as to solve the problem of applying for and releasing a pointer in hardware design.
[0007] (II) Technical solution
[0008] In order to solve the above technical problems, the present invention proposes a management method for pointer rapid application release, the method comprising:
[0009] The two bitmap_rams in the network chip, bitmap_ram0 and bitmap_ram1, are used to store the bitmap table of the cache pointer in the chip. The bitmap table indicates the idle state of the cache pointer. The bit width of each bitmap_ram is 128 and the depth is 64, indicating the state of the cache space with a total size of 8K. Among them, bitmap_ram0(i,j) and bitmap_ram1(i,j) in the i-th row and j-th column indicate the state of the same cache space (128*i+j);
[0010] When bitmap_ram0(i,j)=0 and bitmap_ram1(i,j)=1, it means that the cache space (128*i+j) is free;
[0011] When bitmap_ram0(i,j)=1 and bitmap_ram1(i,j)=0, it means that the cache space (128*i+j) is free;
[0012] When bitmap_ram0(i,j)=1 and bitmap_ram1(i,j)=1, it means that the cache space (128*i+j) is occupied;
[0013] The 64x128 status bits of bitmap_ram0 are initialized to 0; the 64x128 status bits of bitmap_ram1 are initialized to 1;
[0014] Each bit row_bmap0(i) of the 64-bit register row_bmap0 in the network chip indicates whether there is free cache space in the i-th row of bitmap_ram0; when all 128 bits of the i-th row of bitmap_ram0 are 1, the value of row_bmap0(i) is 0; when any bit in the 128 bits is 0, the value of row_bmap0(i) is 1;
[0015] Each bit row_bmap1(i) of the 64-bit register row_bmap1 indicates whether there is free cache space in the i-th row of bitmap_ram1; when all 128 bits of the i-th row of bitmap_ram1 are 1, the value of row_bmap1(i) is 0; when any bit in the 128 bits is 0, the value of row_bmap1(i) is 1;
[0016] After the initialization is completed, the internal polling logic selects the row with row_bmap0(i)=1 in row_bmap0 in ascending order, and reads the status of the 128 cache spaces corresponding to the row from bitmap_ram0 and writes them into the fastch_FIFO, and then writes the status bits of the 128 cache spaces in bitmap_ram0 to 1; when the message applies for free cache space, the status position corresponding to the cache pointer in the fastch_FIFO is set to 1; when all 128 cache spaces in each row of the fastch_FIFO are occupied, the valid row cached in the fastch_FIFO is reduced by 1, and when the number of valid rows cached in the fastch_FIFO reaches the empty waterline, the internal cache logic continues to parse the status of row_bmap0 and add it to the fastch_FIFO;
[0017] After the internal polling logic queries bit0-bit63 of row_bmap0, it switches to the row_bmap1 register and queries bit0-bit63 of row_bmap1, and repeats this process.
[0018] When the internal polling logic searches for a pointer to a free cache space in bitmap_ram0, if there is a pointer to an occupied cache space to be released, the network chip writes 0 to the bit corresponding to the pointer in bitmap_ram1; when the internal polling logic searches for a pointer to a free cache space in bitmap_ram1, if there is a pointer to an occupied cache space to be released, the network chip writes 0 to the bit corresponding to the pointer in bitmap_ram0.
[0019] Furthermore, the network chip is a network security processing chip.
[0020] Furthermore, when bitmap_ram0(i,j)=0 and bitmap_ram1(i,j)=0, illegal values will not appear.
[0021] Furthermore, after power-on evacuation, two blocks of bitmap_ram are initialized.
[0022] Furthermore, after the initialization of the two bitmap_ram blocks is completed, the value of the 64-bit register row_bmap0 is all 1, and the value of row_bmap1 is all 0.
[0023] Furthermore, the depth of the FATCH_FIFO is N and the width is 128 bits, so the states of the N*128 cache spaces corresponding to N different rows will be read and written into the FATCH_FIFO.
[0024] Furthermore, the latch_FIFO is a FIFO that is read and written in each beat, so it can ensure that when a message applies for free cache space, the free cache pointer can be obtained in the beat, and the state position corresponding to the cache pointer in the latch_FIFO is set to 1.
[0025] Furthermore, when the number of valid rows cached in the FATCH_FIFO reaches the empty waterline M, the internal cache logic continues to parse the state of row_bmap0, and reads the state of the (NM)*128 cache spaces corresponding to the NM rows from bitmap_ram0 and writes them into the FATCH_FIFO.
[0026] Further, N=10, M=5.
[0027] Furthermore, when the network chip releases a pointer in bitmap_ram0 or bitmap_ram1, if it is found that the bit corresponding to the released pointer is 0, this is a repeated release of the pointer, and the internal logic will report an alarm.
[0028] (III) Beneficial effects
[0029] The present invention proposes a management method for fast application and release of pointers. The present invention provides a management method for application and release of cache pointers (i.e., the address of each cache space). By maintaining the bitmap table of cache pointers, it is possible to apply for N pointers or release N pointers or apply for N pointers and release N pointers in N consecutive beats (N is an arbitrary value). The cache pointer application and release method of the present invention enables the chip to complete the application and release of cache pointers in the beat when data is received and sent. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of a management method for quickly applying for and releasing a pointer according to the present invention. DETAILED DESCRIPTION
[0031] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.
[0032] The present invention relates to a method for managing the application and release of cache pointers in a network security processing chip. The method for applying and releasing cache pointers in the present invention enables the chip to complete the application and release of cache pointers when data is received and sent. The rapid application and release of cache pointers is the basis for meeting various bandwidth service processing requirements and performance.
[0033] When the network security processing chip (hereinafter referred to as: network chip) is working, it will receive messages of various lengths (64B-15.5K) on the network. These messages occupy a cache space for every 128B (less than 128B is processed as 128B), and are stored in a cache space with a total size of 8K and a total capacity of 1MB (128B*8K).
[0034] When receiving messages of various bandwidth services, the network chip needs to quickly apply for a free buffer for each 128B of data in the message. When the messages of various bandwidth services are output, 128B of data is output, and the buffer space corresponding to the data needs to be quickly released.
[0035] Figure 1 It is a design block diagram of the technical solution of the present invention. Figure 1As shown in the figure, the two bitmap_rams (bitmap_ram0 / bitmap_ram1) in the network chip are used to store the bitmap table of the cache pointer in the chip. The bitmap table indicates the idle state of the cache pointer. The bit width of each bitmap_ram is 128 and the depth is 64, indicating the state of the cache space with a total size of 8K (128x64). Among them, bitmap_ram0(i,j) and bitmap_ram1(i,j) in the i-th row and j-th column indicate the state of the same cache space (128*i+j). The values can be as follows:
[0036] (1) When bitmap_ram0(i,j)=0 and bitmap_ram1(i,j)=0, there will be no illegal values.
[0037] (2) When bitmap_ram0(i,j)=0 and bitmap_ram1(i,j)=1, it means that the cache space (128*i+j) is free;
[0038] (3) When bitmap_ram0(i,j)=1 and bitmap_ram1(i,j)=0, it means that the cache space (128*i+j) is free;
[0039] (4) When bitmap_ram0(i,j)=1 and bitmap_ram1(i,j)=1, it means that the cache space (128*i+j) is occupied;
[0040] After power-on evacuation, the two bitmap_rams are initialized. The 64x128 status bits of bitmap_ram0 are initialized to 0. The 64x128 status bits of bitmap_ram1 are initialized to 1. Since bitmap_ram0(i, j) = 0 and bitmap_ram1(i, j) = 1, the status of the 8K cache space is free at this time.
[0041] exist Figure 1In the network chip, each bit row_bmap0(i) of the 64-bit register row_bmap0 in the network chip indicates whether there is free cache space in the i-th row of bitmap_ram0. When all 128 bits of the i-th row of bitmap_ram0 are 1, the value of row_bmap0(i) is 0; when any bit in the 128 bits is 0, the value of row_bmap0(i) is 1. Similarly, each bit row_bmap1(i) of the 64-bit register row_bmap1 indicates whether there is free cache space in the i-th row of bitmap_ram1. The correspondence between row_bmap1 and bitmap_ram1 is consistent with the correspondence between row_bmap0 and bitmap_ram0, that is, when all 128 bits of the i-th row of bitmap_ram1 are 1, the value of row_bmap1(i) is 0; when any bit in the 128 bits is 0, the value of row_bmap1(i) is 1.
[0042] After the two bitmap_rams are initialized, the value of the 64-bit register row_bmap0 is all 1, and the value of row_bmap1 is all 0.
[0043] After initialization is completed, the internal polling logic selects the row with row_bmap0(i)=1 in row_bmap0 in ascending order, and reads the status of the 128 cache spaces corresponding to the row from bitmap_ram0 and writes them into the fastch_FIFO, and then writes the status bits of the 128 cache spaces in bitmap_ram0 to 1. The depth of the fastch_FIFO is N and the width is 128 bits, so the status of the N*128 cache spaces corresponding to N different rows will be read and written into the fastch_FIFO. In one embodiment, N=10.
[0044] Because the FATCH_FIFO is a FIFO that is read and written in every beat, it can ensure that when a message applies for free cache space, it can obtain the free cache pointer in the beat, and set the status position corresponding to the cache pointer in the FATCH_FIFO to 1. When all 128 cache spaces in each row of the FATCH_FIFO are occupied (all 128-bit status bits are 1), the number of valid rows cached in the FATCH_FIFO is reduced by 1. When the number of valid rows cached in the FATCH_FIFO reaches the empty waterline M, the internal cache logic continues to parse the status of row_bmap0, and reads the status of (NM)*128 cache spaces corresponding to the NM rows from bitmap_ram0 and writes them into the FATCH_FIFO. N>M. Among them, M is 5.
[0045] After the internal polling logic queries bit0-bit63 of row_bmap0, the internal polling logic will switch to the row_bmap1 register and query bit0-bit63 of row_bmap1, and repeat this process.
[0046] When the internal polling logic searches for a pointer to a free cache space in bitmap_ram0, if there is a pointer to an occupied cache space to be released, the network chip writes 0 to the bit corresponding to the pointer in bitmap_ram1. Conversely, when the internal polling logic searches for a pointer to a free cache space in bitmap_ram1, if there is a pointer to an occupied cache space to be released, the bit corresponding to the pointer in bitmap_ram0 is written to 0. This mechanism ensures that the application and release of pointers are performed simultaneously. In bitmap_ram0 and bitmap_ram1, 0 represents free and 1 represents occupied.
[0047] When the network chip releases a pointer in bitmap_ram0 or bitmap_ram1, if it is found that the bit corresponding to the released pointer is 0, this is a repeated release of the pointer, and the internal logic will report an alarm.
[0048] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A pointer quick application release management method, characterized in that: The method includes: The two bitmap_rams in the network chip, bitmap_ram0 and bitmap_ram1, are used to store the bitmap table of the cache pointer in the chip. The bitmap table indicates the idle state of the cache pointer. The bit width of each bitmap_ram is 128 and the depth is 64, indicating the state of the cache space with a total size of 8K. Among them, bitmap_ram0(i,j) and bitmap_ram1(i,j) in the i-th row and j-th column indicate the state of the same cache space (128*i+j); When bitmap_ram0(i,j)=0 and bitmap_ram1(i,j)=1, it means that the cache space (128*i+j) is free; When bitmap_ram0(i,j)=1 and bitmap_ram1(i,j)=0, it means that the cache space (128*i+j) is free; When bitmap_ram0(i,j)=1 and bitmap_ram1(i,j)=1, it means that the cache space (128*i+j) is occupied; The 64x128 status bits of bitmap_ram0 are initialized to 0; the 64x128 status bits of bitmap_ram1 are initialized to 1; Each bit row_bmap0(i) of the 64-bit register row_bmap0 in the network chip indicates whether there is free cache space in the i-th row of bitmap_ram0; when all 128 bits of the i-th row of bitmap_ram0 are 1, the value of row_bmap0(i) is 0; when any bit in the 128 bits is 0, the value of row_bmap0(i) is 1; Each bit row_bmap1(i) of the 64-bit register row_bmap1 indicates whether there is free cache space in the i-th row of bitmap_ram1; when all 128 bits of the i-th row of bitmap_ram1 are 1, the value of row_bmap1(i) is 0; when any bit in the 128 bits is 0, the value of row_bmap1(i) is 1; After the initialization is completed, the internal polling logic selects the row with row_bmap0(i)=1 in row_bmap0 in ascending order, and reads the status of the 128 cache spaces corresponding to the row from bitmap_ram0 and writes them into the fastch_FIFO, and then writes the status bits of the 128 cache spaces in bitmap_ram0 to 1; when the message applies for free cache space, the status position corresponding to the cache pointer in the fastch_FIFO is set to 1; when all 128 cache spaces in each row of the fastch_FIFO are occupied, the valid row cached in the fastch_FIFO is reduced by 1, and when the number of valid rows cached in the fastch_FIFO reaches the empty waterline, the internal cache logic continues to parse the status of row_bmap0 and add it to the fastch_FIFO; After the internal polling logic queries bit0-bit63 of row_bmap0, it switches to the row_bmap1 register and queries bit0-bit63 of row_bmap1, and repeats this process. When the internal polling logic searches for a pointer to a free cache space in bitmap_ram0, if there is a pointer to an occupied cache space to be released, the network chip writes 0 to the bit corresponding to the pointer in bitmap_ram1; when the internal polling logic searches for a pointer to a free cache space in bitmap_ram1, if there is a pointer to an occupied cache space to be released, the network chip writes 0 to the bit corresponding to the pointer in bitmap_ram0.
2. The pointer quick application release management method according to claim 1, characterized in that: The network chip is a network security processing chip.
3. The pointer quick application release management method according to claim 1, characterized in that: When bitmap_ram0(i,j)=0 and bitmap_ram1(i,j)=0, illegal values will not appear.
4. The pointer quick application release management method according to claim 1, characterized in that: After power-on and evacuation, two blocks of bitmap_ram are initialized.
5. The pointer quick application release management method according to claim 1, characterized in that: After the two bitmap_rams are initialized, the value of the 64-bit register row_bmap0 is all 1, and the value of row_bmap1 is all 0.
6. The pointer quick application release management method according to claim 1, characterized in that: The depth of fatch_FIFO is N and the width is 128 bits, so the status of N*128 cache spaces corresponding to N different rows will be read and written into fatch_FIFO.
7. The pointer quick application release management method according to claim 6, characterized in that: Fatch_FIFO is a FIFO that is read and written in every beat, so it can ensure that when a message applies for free cache space, it can obtain the free cache pointer in the beat and set the status position corresponding to the cache pointer in Fatch_FIFO to 1.
8. The pointer rapid application release management method according to claim 6, characterized in that: When the number of valid rows cached in the FATCH_FIFO reaches the empty waterline M, the internal cache logic continues to parse the status of row_bmap0, and reads the status of the (NM)*128 cache spaces corresponding to the NM rows from bitmap_ram0 and writes them into the FATCH_FIFO.
9. The pointer quick application release management method according to claim 8, characterized in that: N=10, M=5.
10. The pointer rapid application release management method according to claim 1, characterized in that: When the network chip releases a pointer in bitmap_ram0 or bitmap_ram1, if it is found that the bit corresponding to the released pointer is 0, this is a repeated release of the pointer, and the internal logic will report an alarm.
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