Display Substrate, Preparation Method Thereof, and Display Device

Abstract

A display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a substrate including a display area and a bonding area at least on one side of the display area; a pixel defining layer located on one side of the substrate and covering both the display area and the bonding area. The shortest distance between the surface of the pixel defining layer on the side away from the substrate in the bonding area and the substrate is less than the shortest distance between the surface of the pixel defining layer on the side away from the substrate in the display area and the substrate. The solution provided in this embodiment reduces the thickness of the pixel defining layer in the bonding area, reduces the step difference between the pixel defining layer and the bonding pad, and can improve the yield of subsequent IC bonding.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, display technologies, and particularly to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] In self-emitting display technologies, whether it is organic light-emitting diode (OLED) or quantum dot light-emitting diode (QLED) display technologies, and whether it is a printing process or an evaporation process, a hole design needs to be made in the pixel to facilitate the entry of the subsequent OLED / QLED evaporation or printing-related light-emitting materials into the hole. In the industry, it is commonly referred to as the pixel definition layer (Pixel Definiton Layer or Bank Layer, abbreviated as PDL). There are requirements for the Bank thickness in the evaporation or printing design. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, which improve the bonding yield.

[0005] On the one hand, embodiments of the present disclosure provide a display substrate, including:

[0006] a substrate including a display area and a bonding area at least on one side of the display area;

[0007] a pixel definition layer located on one side of the substrate and located in the display area and the bonding area, wherein the shortest distance between the surface of the pixel definition layer away from the substrate on the bonding area side and the substrate is less than the shortest distance between the surface of the pixel definition layer away from the substrate on the display area side and the substrate.

[0008] On the other hand, embodiments of the present disclosure provide a method for manufacturing a display substrate, including:

[0009] forming a pixel definition layer with pixel openings on one side of the substrate, the substrate including a display area and a bonding area at least on one side of the display area, the pixel definition layer being disposed in the display area and the bonding area, and the pixel openings being disposed in the display area;

[0010] Coat a photoresist on the side of the pixel definition layer away from the substrate, and perform halftone mask exposure, development, and ashing processes, so that there is no photoresist at the bottom of the pixel opening after development, and at least part of the side wall of the pixel opening is covered with photoresist after ashing; and the exposure degree of the photoresist covering the pixel definition layer in the display area is different from the exposure degree of the photoresist covering the pixel definition layer in the bonding area, so that after ashing, the shortest distance between the surface of the pixel definition layer in the bonding area away from the substrate and the substrate is less than the shortest distance between the surface of the pixel definition layer in the display area away from the substrate and the substrate;

[0011] Strip the photoresist.

[0012] In another aspect, an embodiment of the present disclosure provides a display device, including the above display substrate.

[0013] Embodiments of the present disclosure include a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a substrate including a display area and at least one bonding area located on one side of the display area; a pixel definition layer located on one side of the substrate and located in the display area and the bonding area, wherein the shortest distance between the surface of the pixel definition layer in the bonding area away from the substrate and the substrate is less than the shortest distance between the surface of the pixel definition layer in the display area away from the substrate and the substrate. The solution provided by this embodiment reduces the thickness of the pixel definition layer in the bonding area, reduces the step difference between the pixel definition layer and the bonding pad, and can improve the yield of subsequent IC bonding.

[0014] Other features and advantages of the present invention will be described in the following description, and part of them will become obvious from the description, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the description and the drawings.

[0015] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0016] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the description. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present invention and do not constitute a limitation to the technical solutions.

[0017] Figure 1 A schematic plan view of a display substrate provided for an exemplary embodiment;

[0018] Figure 2 For Figure 1 A cross-sectional view of the display substrate in the AA direction as shown;

[0019] Figure 3 Schematic diagram after forming a gate electrode and a first electrode provided for an exemplary embodiment;

[0020] Figure 4 Schematic diagram after forming an active layer provided for an exemplary embodiment;

[0021] Figure 5 Schematic diagram after forming a source electrode, a drain electrode, and a second electrode provided for an exemplary embodiment;

[0022] Figure 6 Schematic diagram after forming a second insulating layer provided for an exemplary embodiment;

[0023] Figure 7 Schematic diagram after forming a planarization layer provided for an exemplary embodiment;

[0024] Figure 8 Schematic diagram after forming an anode and a third electrode provided for an exemplary embodiment;

[0025] Figure 9 Schematic diagram after forming a pixel definition layer provided for an exemplary embodiment;

[0026] Figure 10 Schematic diagram after ashing treatment provided for an exemplary embodiment;

[0027] Figure 11 Schematic diagram of a display substrate provided for another exemplary embodiment;

[0028] Figure 12 Schematic diagram of a display substrate provided for yet another exemplary embodiment;

[0029] Figure 13 Schematic diagram of a display substrate provided for yet another exemplary embodiment;

[0030] Figure 14 Flowchart of a method for manufacturing a display substrate provided for an embodiment of the present disclosure. Detailed implementation manners

[0031] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

[0032] The steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0033] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this invention pertains.

[0034] In the drawings, for clarity sometimes the sizes of various components, the thicknesses of layers or regions are exaggerated. Therefore, the embodiments of this disclosure are not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.

[0035] The ordinal numbers such as "first", "second", "third", etc. in this disclosure are provided to avoid confusion of components and do not represent any order, quantity or importance.

[0036] In this disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this disclosure. The positional relationship of components changes appropriately according to the directions describing the components. Therefore, it is not limited to the terms described in the disclosure and can be replaced appropriately according to the circumstances.

[0037] In this disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0038] In this disclosure, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region where current mainly flows.

[0039] In the present disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. In the case of using transistors with opposite polarities or when the direction of current flow changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in the present disclosure, the "source electrode" and "drain electrode" may be switched with each other.

[0040] In the present disclosure, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0041] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes the state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes the state where the angle is 85° or more and 95° or less.

[0042] In the present disclosure, "film" and "layer" may be switched with each other. For example, sometimes the "conductive layer" can be changed to the "conductive film". Similarly, sometimes the "insulating film" can be changed to the "insulating layer".

[0043] Currently, the mainstream OLED light-emitting materials are fabricated by evaporation process. The light-emitting layer printing technology is regarded as the development direction of OLED&QLED. Regarding the flow properties of the ink, there are still many difficulties in the current printing technology. Among them, the roughness of the pixel definition layer is one of the difficulties. One direction to improve the roughness of the pixel definition layer is to ensure that there is no residual glue in the opening of the pixel definition layer.

[0044] In the OLED manufacturing process, the organic material is ashed using oxygen plasma (O2 Plasma), resulting in a loss of part of the film thickness of the PDL layer. The evaporation process has low requirements for the surface properties of the material inside the PDL holes. However, in the ink printing process of QLED light-emitting materials, the ink has high requirements for the hydrophobicity of the material surface. The traditional method of removing residual glue will ash the hydrophobic layer on the surface of the PDL layer, reducing the hydrophobicity and affecting the subsequent inkjet effect. In an exemplary embodiment, before the ashing treatment, a photoresist is used to protect the pixel definition layer on the sidewalls of the pixel opening, avoiding the destruction of the hydrophobicity of the sidewalls during the ashing treatment, improving the inkjet effect, and the residual glue in the pixel opening can be removed through the ashing treatment, improving the roughness of the pixel opening.

[0045] In addition, since there is no planarization layer in the bonding area outside the display area, when the target film thickness of the PDL layer is 2.0 μm, due to the fluidity of the glue, the thickness of the PDL layer in the bonding area is about 2.9 μm. This large step difference may cause the bonding integrated circuit (Bonding IC) in the subsequent stage to fail. In an exemplary embodiment, the yield of integrated circuit (IC) bonding can be improved by reducing the thickness of the PDL layer in the bonding area.

[0046] Figure 1 A planar schematic diagram of a display substrate provided for an exemplary embodiment. Figure 2 For Figure 1 A cross-sectional view of the display substrate shown in the AA direction. As Figure 1 、 2 shown, the display substrate includes a substrate 1, and the substrate 1 includes a display area 100 and at least a bonding area 200 located on one side of the display area 100. The display area 100 includes a plurality of sub-pixels 110 distributed in an array, and the bonding area 200 includes a plurality of bonding pads 210. At least one of the plurality of sub-pixels 110 includes a thin-film transistor, a planarization layer, and a light-emitting element sequentially disposed on the substrate 1. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor; the light-emitting element is located on the side of the planarization layer away from the substrate, and the light-emitting element includes an anode. The sub-pixel 110 is connected to the bonding pad 210 through a data line 300, and then the bonding pad 210 is connected to an external driving circuit. Figure 1 Only some of the sub-pixels are schematically shown connected to the bonding pads 210 through the data line 300 in [the figure], and the remaining sub-pixels are similar.

[0047] As Figure 2As shown in the figure, the display substrate provided in this embodiment includes: a substrate 1, and the substrate 1 includes a display area 100 and a bonding area 200 located at least on one side of the display area 100. In a plane perpendicular to the substrate 1 of the display substrate, the display substrate includes: a substrate 1, a gate electrode 2 and a first electrode 3 disposed on the substrate 1, a first insulating layer 4 disposed on a side of the gate electrode 2 and the first electrode 3 away from the substrate 1, an active layer 5 disposed on a side of the first insulating layer 4 away from the substrate 1, a source-drain electrode layer disposed on a side of the active layer 5 away from the substrate 1, and the source-drain electrode layer may include a source electrode 6, a drain electrode 7 and a second electrode 8, a second insulating layer 9 disposed on a side of the source-drain electrode layer away from the substrate 1, a planarization layer 10 disposed on a side of the second insulating layer 9 away from the substrate 1, an anode 11 and a third electrode 12 disposed on a side of the planarization layer 10 away from the substrate 1, and a pixel definition layer 13 disposed on a side of the anode 11 and the third electrode 12 away from the substrate. The planarization layer 10 includes a first planarization layer via P1, and the anode 11 is electrically connected to the drain electrode 7 through the first planarization layer via P1. The second electrode 8 is electrically connected to the first electrode 3 through a first via K1, and the third electrode 12 is electrically connected to the second electrode 8 through a second via K2.

[0048] Among them, the gate electrode 2, the source electrode 6, the drain electrode 7, the planarization layer 10, and the anode 11 may be disposed in the display area 100, the first electrode 3, the second electrode 8, and the third electrode 12 may be disposed in the bonding area 200, and the first insulating layer 4, the second insulating layer 9, and the pixel definition layer 13 may be disposed in the display area 100 and the bonding area 200. The gate electrode 2, the active layer 5, the source electrode 6, and the drain electrode 7 constitute the thin film transistor. In another exemplary embodiment, it may be that the anode 11 is electrically connected to the source electrode 6 through the first planarization layer via P1.

[0049] In an exemplary embodiment, the shortest distance d1 between the surface of the pixel definition layer 13 away from the substrate 1 in the bonding area 200 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel definition layer 13 away from the substrate 1 in the display area 100 and the substrate 1. The solution provided in this embodiment reduces the thickness of the pixel definition layer 13 in the bonding area, reduces the step difference between the pixel definition layer 13 and the third electrode 12, and can improve the yield of subsequent IC bonding. In the present disclosure, the pixel definition layer 13 in the display area 100 refers to: in a plane parallel to the substrate 1, the pixel definition layer 13 whose orthographic projection is located in the display area 100. The pixel definition layer 13 in the bonding area 200 refers to: in a plane parallel to the substrate 1, the pixel definition layer 13 whose orthographic projection is located in the bonding area 200.

[0050] In an exemplary embodiment, 1.5 ≤ d2 / d1 ≤ 1.9. Here, this is only an example, and d2 / d1 can be other values.

[0051] The technical solution of this embodiment will be further described below by showing the preparation process of the substrate in this embodiment. The "lithography process" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and stripping photoresist, which are mature preparation processes in the related art. The "photolithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature preparation processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern". The statement "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same lithography process.

[0052] (1) Coating a flexible material on a glass carrier plate, curing it into a film to form a substrate 1. The substrate 1 includes a display area 100 and a bonding area 200. In the embodiment of this disclosure, the substrate 1 can be a flexible substrate. The flexible material can be materials such as polyimide PI, polyethylene terephthalate PET, or a polymer soft film with surface treatment. In an exemplary embodiment, the substrate 1 can be a single-layer structure or a multi-layer laminated structure. The laminated substrate can include: flexible material / inorganic material / flexible material, flexible material / inorganic material / amorphous silicon / flexible material / inorganic material, etc. The inorganic material can be a barrier film, such as silicon nitride (SiNx) or silicon oxide (SiOx), etc., which is used to improve the water and oxygen resistance of the substrate. Taking the PI / Barrier / PI / Barrier laminated structure as an example, its preparation process can include: first coating a layer of polyimide on a glass carrier plate, depositing a barrier film after curing it into a film, then coating another layer of polyimide on the barrier film, and depositing another barrier film after curing it into a film to form a flexible substrate with a laminated structure.

[0053] (2) Depositing a first metal thin film on the substrate 1, and patterning the first metal thin film through a lithography process to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, where the gate electrode 2 is formed in the display area 100, and the first electrode 3 is formed in the bonding area 200, as Figure 3 shown.

[0054] (3) Deposit the first insulating film and the active layer film in sequence. Pattern the first insulating film through a patterning process to form a first insulating layer 4 pattern provided with a first via K1. Pattern the active layer film to form an active layer 5 pattern. The active layer 5 is formed in the display area 100. The first via K1 exposes the first electrode 3. The first insulating layer 4 covers the display area 100 and the bonding area 200, as Figure 4 shown.

[0055] (4) Deposit a second metal film. Pattern the second metal film through a patterning process to form a source electrode 6, a drain electrode 7, and a second electrode 8. The second electrode 8 is electrically connected to the first electrode 3 through the first via K1. The source electrode 6 and the drain electrode 7 are formed in the display area 100. The second electrode 8 is formed in the bonding area 200. The source electrode 6 and the drain electrode 7 are at least partially disposed on the surface of the active layer 5 to achieve electrical connection with the active layer 5; as Figure 5 shown.

[0056] (5) Deposit a second insulating film. The second insulating film covers the display area 100 and the bonding area 200, as Figure 6 shown;

[0057] (6) Coat a planarizing film. Pattern to form a planarization layer (PLN) 10 and a second insulating layer 9 pattern. A first planarization layer via P1 is formed in the planarization layer 10. The first planarization layer via P1 is formed in the display area 100. The planarizing film and the second insulating film within the first planarization layer via P1 are etched away to expose the surface of the drain electrode 7. The second insulating layer 9 is provided with a second via K2. The second via K2 exposes the second electrode 8; as Figure 7 shown. The planarization layer 10 is formed in the display area 100, and there is no planarization layer 10 in the bonding area 200. In an exemplary embodiment, the planarizing film may be made of an organic material, such as polyimide, etc.;

[0058] In an exemplary embodiment, in a plane parallel to the substrate 1, the orthographic projection of the second electrode 8 is located outside the orthographic projection of the second insulating layer 9. However, the embodiments of the present disclosure are not limited thereto. In a plane parallel to the substrate 1, the orthographic projection of the second electrode 8 may be partially located outside the orthographic projection of the second insulating layer 9. For example, the orthographic projection of the second via K2 may be located within the orthographic projection of the second electrode 8.

[0059] (7) Deposit a transparent conductive film on the substrate on which the foregoing pattern is formed, pattern the transparent conductive film through a patterning process, and form an anode 11 and a third electrode 12 pattern on the flat layer 10. The anode 11 is formed in the display area 100, and the third electrode 12 is formed in the bonding area 200. The anode 11 is connected to the drain electrode 7 through a first flat layer via hole P1 opened on the flat layer 10, and the third electrode 12 is connected to the second electrode 8 through a second via hole K2, as Figure 8 shown. Among them, the transparent conductive film can be indium tin oxide ITO, indium zinc oxide IZO, etc. In an exemplary embodiment, the anode 11 can be a multi-layer structure of ITO / Ag / ITO, IZO / Ag / IZO. The transparent conductive film, Ag film, and transparent conductive film can be deposited in sequence, and then patterned to form the anode 11.

[0060] In an exemplary embodiment, the orthographic projection of the second via hole K2 on the substrate 1 overlaps with the orthographic projection of the first via hole K1 on the substrate 1.

[0061] (8) Coat a pixel definition film on the substrate on which the foregoing pattern is formed, and form a pixel definition layer (PDL) 13 pattern through a mask, exposure, and development process. Pixel openings and bonding openings are opened on the pixel definition layer 13. The pixel openings are formed in the display area 100, and the bonding openings are formed in the bonding area 200. The pixel definition film in the pixel openings is developed away, exposing the surface of the anode 11, and the bonding openings expose the third electrode 12, as Figure 9 shown. After this process, there is glue residue 14 in the pixel openings and bonding openings.

[0062] In an exemplary embodiment, in a plane parallel to the substrate 1, the orthographic projection of the bottom of the bonding opening may be located within the orthographic projection of the third electrode 12. In the solution provided by this embodiment, the side wall of the third electrode 12 is covered by the pixel definition layer 13, which can prevent the side wall of the third electrode 12 from being damaged in subsequent processes. For example, when the third electrode 12 contains Ag, it can prevent Ag from being oxidized when ashing is performed with oxygen in subsequent use.

[0063] In addition, the solution provided by this embodiment can use the third electrode 12 to protect the second electrode 8 and prevent the second electrode 8 from being oxidized in subsequent ashing processes.

[0064] Among them, the pixel definition layer can be prepared from polyimide, acrylic, polyethylene terephthalate, etc.

[0065] (9) A photoresist is coated on the substrate 1 on which the foregoing pattern is formed, and halftone mask (HTM) exposure, development, and ashing processes are performed. Among them, when performing halftone mask exposure, there are various exposure degrees, such that after development, there is no photoresist at the bottom of the pixel opening (the surface of the anode 11 away from the substrate 1) and the bottom of the bonding opening (the surface of the third electrode 12 away from the substrate 1), and the thickness of the photoresist covering the pixel definition layer 13 of the display area 100 is greater than the thickness of the photoresist covering the pixel definition layer 13 of the bonding area 200 (after development, the pixel definition layer 13 of the bonding area 200 may be covered with photoresist, or may not be covered with photoresist); and after ashing, at least part of the side wall of the pixel opening is covered with photoresist, and after ashing, the thickness of the pixel definition layer of the bonding area 200 is reduced after ashing (that is, after ashing, the thickness of the pixel definition layer 13 of the bonding area 200 is less than the thickness of the pixel definition layer 13 of the bonding area 200 before ashing), and the shortest distance d1 between the surface of the pixel definition layer 13 of the bonding area 200 away from the substrate 1 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel definition layer 13 of the display area 100 away from the substrate 1 and the substrate 1. The photoresist residues in the pixel opening and the bonding opening are removed.

[0066] In the solution provided in this embodiment, since the side walls of the pixel openings are protected by photoresist, during the ashing process, the hydrophobic layer on the surface of the pixel definition layer of the side walls will not be ashed, thus not affecting the subsequent inkjet effect. In addition, the photoresist residues can be removed to improve pixel roughness. In addition, the thickness of the pixel definition layer of the bonding area 200 can be reduced to improve the yield of subsequent IC bonding.

[0067] In an exemplary embodiment, before ashing, the pixel definition layer 13 of the display area 100 may include: an opening portion 131 forming the side wall of the pixel opening and a flat portion 132 other than the opening portion 131. The method further includes that after ashing, at least part of the thickness of the flat portion 132 in the direction perpendicular to the substrate is consistent with the thickness before ashing. That is, after ashing, in addition to the side wall (opening portion 131) of the pixel opening being covered with photoresist, the flat portion 132 is covered with photoresist to protect the flat portion 132, so that the pixel definition layer of the display area 100 is not etched during the ashing process. As Figure 10As shown, after ashing, the surface of the pixel definition layer in the display area 100 is covered with photoresist 15 to prevent the pixel definition layer in the display area 100 from being etched away during the ashing process. In an exemplary embodiment, after ashing, in the display area 100, only the sidewalls of the pixel openings are covered with photoresist, and the flat portion 132 is not covered with photoresist. At this time, the thickness of the flat portion 132 in the direction perpendicular to the substrate may decrease during the ashing process. In the solution provided in this embodiment, the sidewalls of the pixel opening area are protected by photoresist, and the hydrophobic layer on the sidewall surface will not be ashed, thus not affecting the subsequent inkjet effect.

[0068] In an exemplary embodiment, when performing halftone mask exposure, the area 101 where the bottom of the pixel opening is located and the area 201 where the bottom of the bonding opening is located may be fully exposed, the display area 100 is not exposed except for the area 101 where the bottom of the pixel opening is located, and the bonding area 200 is partially exposed except for the area 201 where the bottom of the bonding opening is located. Thus, after development, there is no photoresist in the areas 101 and 102, and the thickness of the photoresist covering the area of the display area 100 except for the area 101 is greater than the thickness of the photoresist covering the area of the bonding area 200 except for the area 201. Thus, during the subsequent ashing process, the thickness of the pixel definition layer in the bonding area 200 decreases, and the thickness of at least part of the pixel definition layer in the display area 100 remains unchanged.

[0069] In an exemplary embodiment, as Figure 10 shown, the thickness d3 of the pixel definition layer 13 in the bonding area 200 in the direction perpendicular to the substrate 1 may be 0.8 um to 1 um. When d3 is within this value range, the step difference between the pixel definition layer 13 and the third electrode 12 is small, which can improve the yield of subsequent integrated circuit (IC) bonding. However, the embodiments of the present disclosure are not limited thereto, and the thickness d3 may be other values.

[0070] In an exemplary embodiment, as Figure 10 shown, the thickness d4 of the pixel definition layer 13 in the display area 100 in the direction perpendicular to the substrate 1 is, for example, 2 um to 3 um.

[0071] In an exemplary embodiment, oxygen plasma can be used for ashing, but the embodiments of the present disclosure are not limited thereto, and other gases can be used for ashing.

[0072] (10) Strip the photoresist 15.

[0073] Wet stripping can be adopted, and an organic or inorganic solvent is used to remove the photoresist 15.

[0074] In an exemplary embodiment, the first insulating thin film and the second insulating thin film may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and may be a single-layer structure or a multi-layer composite structure. The first metal thin film and the second metal thin film may be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (MTD), etc., or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), etc., and may be a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo, etc. The active layer thin film may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc.

[0075] In subsequent processes, an organic light-emitting layer, a cathode, a packaging layer, etc. may be sequentially formed in the display area 100 to complete the preparation of the display substrate of this embodiment.

[0076] Among them, the organic light-emitting layer may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The cathode may be made of one of metal materials such as magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), lithium (Li), etc., or an alloy of the above metals. The packaging layer may adopt a stacked structure of inorganic material / organic material / inorganic material.

[0077] The structure shown in this embodiment and its preparation process are merely an exemplary illustration. During actual implementation, the corresponding structure may be changed according to actual needs, and the patterning process may be increased or decreased. For example, the active layer may be disposed on the side of the gate electrode close to the substrate, that is, the display area 100 may include an active layer, a gate electrode, a source electrode, a drain electrode, etc. arranged in sequence.

[0078] Figure 11 Schematic diagram of a display substrate provided for another exemplary embodiment. As Figure 11As shown in the figure, the display substrate provided in this embodiment includes a substrate 1. The substrate 1 includes a display area 100 and a bonding area 200 located at least on one side of the display area 100. In a plane perpendicular to the plane of the substrate 1, the display substrate includes: a substrate 1, a gate electrode 2 disposed on a side of the substrate 1 away from the substrate, and a first electrode 3, a first insulating layer 4 disposed on a side of the gate electrode 2 and the first electrode 3 away from the substrate 1, an active layer 5 disposed on a side of the first insulating layer 4 away from the substrate 1, a source-drain electrode layer disposed on a side of the active layer 5 away from the substrate 1. The source-drain electrode layer includes a source electrode 6, a drain electrode 7, and a second electrode 8, a second insulating layer 9 disposed on a side of the source-drain electrode layer away from the substrate 1, a planarization layer 10 disposed on a side of the second insulating layer 9 away from the substrate 1, an anode 11 and a third electrode 12 disposed on a side of the planarization layer 10 away from the substrate 1, and a pixel definition layer 13 disposed on a side of the anode 11 and the third electrode 12 away from the substrate 1. The anode 11 is electrically connected to the drain electrode 7 through a first planarization layer via hole P1, the second electrode 8 is electrically connected to the first electrode 3 through a first via hole K1, and the third electrode 12 is electrically connected to the second electrode 8 through a second via hole K2. The shortest distance d1 between the surface of the pixel definition layer 13 on the side away from the substrate 1 in the bonding area 200 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel definition layer 13 on the side away from the substrate 1 in the display area 100 and the substrate 1.

[0079] Wherein, in a plane parallel to the plane of the substrate 1, the positive projection of the second electrode 8 overlaps with the positive projection of the second insulating layer 9, that is, a part of the second electrode 8 is exposed by the second via hole K2. In the previous embodiment, in a plane parallel to the plane of the substrate 1, the positive projection of the second electrode 8 is located outside the positive projection of the second insulating layer 9, and the second electrode 8 is completely exposed by the second via hole K2.

[0080] Figure 12 It is a schematic diagram of a display substrate provided for another exemplary embodiment. As Figure 12As shown in the figure, the display substrate provided in this embodiment includes a substrate 1. The substrate 1 includes a display area 100 and a bonding area 200 located at least on one side of the display area 100. Along a plane perpendicular to the substrate 1, the display substrate includes: the substrate 1, a gate electrode 2 and a first electrode 3 disposed on the substrate 1, a first insulating layer 4 disposed on a side of the gate electrode 2 and the first electrode 3 away from the substrate 1, an active layer 5 disposed on a side of the first insulating layer 4 away from the substrate 1, a source-drain electrode layer disposed on a side of the active layer 5 away from the substrate 1. The source-drain electrode layer may include a source electrode 6, a drain electrode 7, and a second electrode 8, a second insulating layer 9 disposed on a side of the source-drain electrode layer away from the substrate 1, a planarization layer 10 disposed on a side of the second insulating layer 9 away from the substrate 1, an anode 11 and a third electrode 12 disposed on a side of the planarization layer 10 away from the substrate 1, and a pixel definition layer 13 disposed on a side of the anode 11 and the third electrode 12 away from the substrate. The anode 11 is electrically connected to the drain electrode 7 through a first planarization layer via hole P1, the third electrode 12 is electrically connected to the second electrode 8 through a third via hole K3, and the third electrode 12 is electrically connected to the first electrode 3 through a fourth via hole K4. The first electrode 3 is disposed in the bonding area 200, the second electrode 8 and the third electrode 12 are at least partially disposed in the bonding area 200, and the second electrode 8 and the third electrode 12 may be partially disposed in the display area 100. The shortest distance d1 between the surface of the pixel definition layer 13 away from the substrate 1 in the bonding area 200 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel definition layer 13 away from the substrate 1 in the display area 100 and the substrate 1.

[0081] The solution provided in this embodiment can form the third via hole K3 and the fourth via hole K4 through a single patterning process. Compared with the previous embodiment, in which the first via hole K1 and the second via hole K2 need to be formed through two patterning processes respectively, one patterning process can be reduced, the process can be simplified, and the cost can be reduced.

[0082] The following briefly describes Figure 12 the preparation process of the display substrate shown in the figure. Some details can be referred to the previous embodiment and will not be elaborated here.

[0083] The preparation process of the display substrate provided in this embodiment includes:

[0084] (1) Coating a flexible material on a glass carrier plate, curing it into a film to form the substrate 1, and the substrate 1 includes a display area 100 and a bonding area 200.

[0085] (2) Deposit a first metal thin film on the substrate 1, pattern the first metal thin film through a patterning process to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in the display area 100 and the first electrode 3 is formed in the bonding area 200.

[0086] (3) Deposit a first insulating thin film and an active layer thin film in sequence, pattern the active layer thin film through a patterning process to form a first insulating layer 4 and an active layer 5 pattern, the active layer 5 is formed in the display area 100, and the first insulating layer 4 covers the display area 100 and the bonding area 200.

[0087] (4) Deposit a second metal thin film, pattern the second metal thin film through a patterning process to form a source electrode 6, a drain electrode 7 and a second electrode 8, the source electrode 6 and the drain electrode 7 are formed in the display area 100, the second electrode 8 is at least partially formed in the bonding area 200, and the source electrode 6 and the drain electrode 7 are at least partially disposed on the surface of the active layer 5 to achieve electrical connection with the active layer 5.

[0088] In an exemplary embodiment, the second electrode 8 is located on a side of the first electrode 3 close to the display area 100.

[0089] (5) Deposit a second insulating thin film, and the second insulating thin film covers the display area 100 and the bonding area 200, as Figure 5 shown;

[0090] (6) Coat a planarizing thin film, pattern to form a planarization layer (PLN) 10 and a second insulating layer 9 pattern. A first planarization layer via hole P1 is formed on the planarization layer 10, and the first planarization layer via hole P1 is formed in the display area 100. The planarizing thin film and the second insulating thin film within the first planarization layer via hole P1 are etched away to expose the surface of the drain electrode 7. The second insulating layer 9 is provided with a third via hole K3 and a fourth via hole K4. The third via hole K3 exposes the second electrode 8, and the fourth via hole K4 exposes the first electrode 3. The planarization layer 10 is formed in the display area 100, and there is no planarization layer 10 in the bonding area 200.

[0091] (7) Deposit a transparent conductive thin film on the substrate on which the foregoing patterns are formed, pattern the transparent conductive thin film through a patterning process to form an anode 11 and a third electrode 12 pattern on the planarization layer 10. The anode 11 is formed in the display area 100, and the third electrode 12 is at least partially formed in the bonding area 200. The anode 11 is electrically connected to the drain electrode 7 through the first planarization layer via hole P1 formed on the planarization layer 10. The third electrode 12 is electrically connected to the second electrode 8 through the third via hole K3 and is electrically connected to the first electrode 3 through the fourth via hole K4.

[0092] (8) Coating a pixel definition film on the substrate on which the foregoing pattern is formed, and forming a pattern of the pixel definition layer (PDL) 13 through processes of masking, exposure, and development. Pixel openings and bonding openings are formed in the pixel definition layer 13. The pixel openings are formed in the display area 100, and the bonding openings are formed in the bonding area 200. The pixel definition film within the pixel openings is developed away to expose the surface of the anode 11, and the bonding openings expose the third electrode 12, as Figure 8 shown. After this process, there is glue residue 14 in the pixel openings and the bonding openings.

[0093] (9) Coating a photoresist on the substrate 1 on which the foregoing pattern is formed, and performing halftone mask exposure, development, and ashing processes. Among them, when performing halftone mask exposure, there are multiple exposure levels, such that after development, there is no photoresist at the bottom of the pixel openings (the surface of the anode 11 away from the substrate 1 side) and at the bottom of the bonding openings (the surface of the third electrode 12 away from the substrate 1 side), and the thickness of the photoresist covering the pixel definition layer 13 in the display area 100 is greater than the thickness of the photoresist covering the pixel definition layer 13 in the bonding area 200 (after development, the pixel definition layer 13 in the bonding area 200 may or may not be covered with photoresist); and such that after ashing, at least part of the sidewalls of the pixel openings are covered with photoresist, and after ashing, the thickness of the pixel definition layer in the bonding area 200 is reduced after ashing (that is, after ashing, the thickness of the pixel definition layer 13 in the bonding area 200 is less than the thickness of the pixel definition layer 13 in the bonding area 200 before ashing), and the shortest distance d1 between the surface of the pixel definition layer 13 in the bonding area 200 away from the substrate 1 side and the substrate 1 is less than the shortest distance d2 between the surface of the pixel definition layer 13 in the display area 100 away from the substrate 1 side and the substrate 1. The glue residue in the pixel openings and the bonding openings is removed.

[0094] In the solution provided in this embodiment, since the sidewalls of the pixel openings are protected by photoresist, when performing ashing, the hydrophobic layer on the surface of the pixel definition layer on the sidewalls will not be ashed, thus not affecting the subsequent inkjet effect. In addition, the glue residue can be removed to improve pixel roughness. In addition, the thickness of the pixel definition layer in the bonding area 200 can be reduced, improving the yield of subsequent IC bonding.

[0095] (10) Stripping the photoresist 15.

[0096] Figure 13Schematic diagram of a display substrate provided for another exemplary embodiment. The display substrate provided in this embodiment may include a substrate 1, the substrate 1 includes a display area 100 and a bonding area 200 located at least on one side of the display area 100. The display area 100 may include a plurality of sub-pixels, and at least one sub-pixel includes a thin-film transistor, a planarization layer, and a light-emitting element sequentially disposed on the substrate. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor; the light-emitting element is located on the side of the planarization layer away from the substrate, and the light-emitting element includes an anode. The thin-film transistor includes an active layer located on the substrate, a gate electrode located on the side of the active layer away from the substrate, and a source electrode and a drain electrode located on the side of the gate electrode away from the substrate, and one of the source electrode and the drain electrode is electrically connected to the anode of the light-emitting element through the first planarization layer via hole. As Figure 13 shown, the display substrate provided in this embodiment may include: a substrate 1, an active layer 5 disposed on the substrate 1, a fourth insulating layer 16 disposed on the side of the active layer 5 away from the substrate 1, a gate electrode 2 and a first electrode 3 disposed on the side of the fourth insulating layer 16 away from the substrate 1, a first insulating layer 4 disposed on the side of the gate electrode 2 and the first electrode 3 away from the substrate 1, a source-drain electrode layer disposed on the side of the first insulating layer 4 away from the substrate 1, the source-drain electrode layer may include a source electrode 6, a drain electrode 7, and a second electrode 8, a second insulating layer 9 disposed on the side of the source-drain electrode layer away from the substrate 1, a planarization layer 10 disposed on the side of the second insulating layer 9 away from the substrate 1, an anode 11 and a third electrode 12 disposed on the side of the planarization layer 10 away from the substrate 1, and a pixel defining layer 13 disposed on the side of the anode 11 and the third electrode 12 away from the substrate. The planarization layer 10 includes a first planarization layer via hole P1, the anode 11 is electrically connected to the drain electrode 7 through the first planarization layer via hole P1, the second electrode 8 is electrically connected to the first electrode 3 through a first via hole K1, the third electrode 12 is electrically connected to the second electrode 8 through a second via hole K2, and the source electrode 6 and the drain electrode 7 are electrically connected to the active layer 5. The shortest distance d1 between the surface of the pixel defining layer 13 away from the substrate 1 in the bonding area 200 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel defining layer 13 away from the substrate 1 in the display area 100 and the substrate 1. In this embodiment, the thin-film transistor includes an active layer 5, a gate electrode 2, a source electrode 6, and a drain electrode 7 sequentially disposed on the substrate 1. For the preparation of the display substrate described in this embodiment, after forming the active layer 5 and the fourth insulating layer 16, the subsequent preparation can refer to the foregoing multiple embodiments and will not be elaborated.

[0097] Figure 14 Flowchart of a method for preparing a display substrate provided for an exemplary embodiment of the present disclosure. As Figure 14As shown, the method for preparing a display substrate provided by an embodiment of the present disclosure may include:

[0098] Step 1401, forming a pixel definition layer provided with pixel openings on a substrate;

[0099] Step 1402, coating a photoresist on a side of the pixel definition layer away from the substrate, performing mask exposure, development, and ashing processes, so that there is no photoresist at the bottom of the pixel opening after development, and at least part of the side wall of the pixel opening is covered with photoresist after ashing;

[0100] Step 1403, stripping the photoresist.

[0101] In the method for preparing a display substrate provided by this embodiment, the side wall of the pixel opening is protected by a photoresist, avoiding the destruction of the hydrophobicity of the surface of the side wall of the pixel opening during the ashing process, thereby improving the subsequent inkjet printing effect. Additionally, the residual glue in the pixel opening can be removed to improve pixel roughness.

[0102] In an exemplary embodiment, the substrate includes a display area and at least one bonding area located on one side of the display area, the pixel definition layer is disposed in the display area and the bonding area, and the pixel openings are disposed in the display area;

[0103] The mask exposure is halftone mask exposure, wherein the exposure degree of the photoresist covering the pixel definition layer in the display area is different from the exposure degree of the photoresist covering the pixel definition layer in the bonding area, so that after ashing, the shortest distance between the surface of the pixel definition layer in the bonding area away from the substrate and the substrate is less than the shortest distance between the surface of the pixel definition layer in the display area away from the substrate and the substrate.

[0104] In an exemplary embodiment, before ashing, the pixel definition layer in the display area includes: an opening portion constituting the side wall of the pixel opening and a flat portion other than the opening portion, and the method further includes that at least part of the thickness of the flat portion in a direction perpendicular to the substrate after ashing is the same as the thickness before ashing.

[0105] In an exemplary embodiment, forming a pixel definition layer provided with pixel openings on a substrate includes:

[0106] Forming a pixel definition layer provided with the pixel openings and bonding openings on the substrate, and the bonding openings are disposed in the bonding area;

[0107] The method further includes that there is no photoresist at the bottom of the bonding opening after development.

[0108] In an exemplary embodiment, before forming a pixel definition layer provided with pixel openings on a substrate, the following steps are further included:

[0109] Form a first electrode on the substrate, and the first electrode is formed in the bonding area;

[0110] Form a first insulating layer provided with a first via on a side of the first electrode away from the substrate, and the first via exposes the first electrode;

[0111] Form a second electrode on a side of the first insulating layer away from the substrate, the second electrode is electrically connected to the first electrode through the first via, and the second electrode is formed in the bonding area;

[0112] Form a second insulating layer on a side of the second electrode away from the substrate;

[0113] Form a planarization layer on a side of the second insulating layer away from the substrate, and form a second via exposing the second electrode;

[0114] Form a third electrode on a side of the planarization layer away from the substrate, the third electrode is formed in the bonding area, the third electrode is electrically connected to the second electrode through the second via, and the bonding opening exposes the third electrode.

[0115] In an exemplary embodiment, before forming a pixel definition layer provided with pixel openings on a substrate, the following steps are further included:

[0116] Form a first electrode on the substrate, and the first electrode is formed in the bonding area;

[0117] Form a first insulating layer on a side of the first electrode away from the substrate;

[0118] Form a second electrode on a side of the first insulating layer away from the substrate; at least part of the second electrode is formed in the bonding area;

[0119] Form a second insulating layer on a side of the second electrode away from the substrate;

[0120] Form a planarization layer on a side of the second insulating layer away from the substrate, and form a third via exposing the second electrode and a fourth via exposing the first electrode;

[0121] Form a third electrode on a side of the planarization layer away from the substrate, at least part of the third electrode is formed in the bonding area, the third electrode is electrically connected to the second electrode through the third via, the third electrode is electrically connected to the first electrode through the fourth via, and the bonding opening exposes the third electrode.

[0122] In an exemplary embodiment, before forming a pixel definition layer provided with pixel openings on a substrate, the following steps are further included:

[0123] A gate electrode is formed between the substrate and the first insulating layer. The gate electrode is formed in the display area, and the gate electrode and the first electrode are formed through the same patterning process.

[0124] A source electrode and a drain electrode are formed between the first insulating layer and the second insulating layer. The source electrode and the drain electrode are formed in the display area, and the source electrode, the drain electrode, and the second electrode are formed through the same patterning process.

[0125] An anode is formed on the side of the planarization layer away from the substrate. The anode is formed in the display area, the pixel opening exposes the anode, and the anode and the third electrode are formed through the same patterning process.

[0126] The embodiments of the present disclosure provide a display substrate, and the display substrate is prepared by using the preparation method of the display substrate described in any one of the above embodiments. The display substrate provided in this embodiment protects the pixel definition layer on the sidewall of the pixel opening, avoids destroying the hydrophobicity of the surface of the pixel definition layer on the sidewall of the pixel opening during ashing treatment, improves the inkjet printing effect, and can remove glue residues and improve pixel roughness.

[0127] In an exemplary embodiment, the display substrate includes a display area and at least a bonding area located on one side of the display area. The pixel definition layer is provided in the display area and the bonding area. The shortest distance between the surface of the pixel definition layer on the side away from the substrate in the bonding area and the substrate is less than the shortest distance between the surface of the pixel definition layer on the side away from the substrate in the display area and the substrate. For the display substrate provided in this embodiment, the thickness of the pixel definition layer in the bonding area is less than the thickness of the pixel definition layer in the display area, which can reduce the step difference between the pixel definition layer and the electrode in the bonding opening and improve the bonding yield.

[0128] In an exemplary embodiment, the thickness of the pixel definition layer in the bonding area in the direction perpendicular to the substrate is 0.8 micrometers to 1 micrometer.

[0129] In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode, and a third electrode sequentially provided on the substrate. The first electrode, the second electrode, and the third electrode are provided in the bonding area. The second electrode is electrically connected to the first electrode through a first via hole, and the third electrode is electrically connected to the second electrode through a second via hole.

[0130] In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode, and a third electrode sequentially disposed on the substrate. The first electrode is disposed in the bonding region, and at least a portion of the second electrode and the third electrode is disposed in the bonding region. The third electrode is electrically connected to the second electrode through a third via hole, and the third electrode is electrically connected to the first electrode through a fourth via hole.

[0131] In an exemplary embodiment, the pixel defining layer further includes a bonding opening exposing the third electrode. In a plane parallel to the substrate, a positive projection of the bottom of the bonding opening may be located within a positive projection of the third electrode.

[0132] Embodiments of the present disclosure further provide a display device including the display substrate of the foregoing embodiment. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component having a display function.

[0133] Although the disclosed embodiments of the present invention are as described above, the above content is only an embodiment adopted for facilitating the understanding of the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, Comprising: A substrate, including a display area and a bonding area at least on one side of the display area; A pixel definition layer, located on one side of the substrate and covering both the display area and the bonding area, wherein the shortest distance from the surface of the pixel definition layer on the side away from the substrate in the bonding area to the substrate is less than the shortest distance from the surface of the pixel definition layer on the side away from the substrate in the display area to the substrate; The thickness of the pixel definition layer in the bonding area in the direction perpendicular to the substrate is 0.8 micrometers to 1 micrometer; The display substrate further includes a first electrode, a second electrode, and a third electrode sequentially disposed on the substrate. The first electrode, the second electrode, and the third electrode are disposed in the bonding area. The second electrode is electrically connected to the first electrode through a first via hole, and the third electrode is electrically connected to the second electrode through a second via hole; alternatively, the first electrode is disposed in the bonding area, the second electrode and the third electrode are at least partially disposed in the bonding area, the third electrode is electrically connected to the second electrode through a third via hole, and the third electrode is electrically connected to the first electrode through a fourth via hole.

2. The display substrate according to claim 1, wherein The shortest distance from the surface of the pixel definition layer on the side away from the substrate in the bonding area to the substrate is d1, and the shortest distance from the surface of the pixel definition layer on the side away from the substrate in the display area to the substrate is d2, where 1.5 ≤ d2 / d1 ≤ 1.

9.

3. The display substrate according to claim 1, wherein The pixel definition layer further includes a bonding opening exposing the third electrode. In a plane parallel to the substrate, the orthographic projection of the bottom of the bonding opening is located within the orthographic projection of the third electrode.

4. The display substrate according to claim 1, wherein The display substrate further includes a plurality of sub-pixels in the display area, and at least one of the plurality of sub-pixels includes a thin film transistor, a planarization layer, and a light-emitting element; The planarization layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor; The light-emitting element is located on the side of the planarization layer away from the substrate, and the light-emitting element includes an anode; The planarization layer includes a first planarization layer via hole; The thin film transistor includes a gate electrode on the substrate, an active layer on the side of the gate electrode away from the substrate, and a source electrode and a drain electrode on the side of the active layer away from the substrate, and one of the source electrode and the drain electrode is electrically connected to the anode of the light-emitting element through the first planarization layer via hole; The third electrode is provided on the same layer as the anode; 5. The display substrate according to claim 4, wherein The first electrode is provided on the same layer as the gate electrode; The second electrode is provided on the same layer as the source electrode or the drain electrode; 6. The display substrate according to claim 1, wherein The display substrate further includes a plurality of sub-pixels in the display area, and at least one of the plurality of sub-pixels includes a thin film transistor, a planarization layer, and a light-emitting element; The planarization layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor; The light-emitting element is located on the side of the planarization layer away from the substrate, and the light-emitting element includes an anode; The planarization layer includes a first planarization layer via hole; The thin film transistor includes an active layer located on the substrate, a gate electrode located on a side of the active layer away from the substrate, and a source electrode and a drain electrode located on a side of the gate electrode away from the substrate, and one of the source electrode and the drain electrode is electrically connected to the anode of the light-emitting element through the first flat layer via hole; The third electrode is disposed on the same layer as the anode, and the first electrode is disposed on the same layer as the gate electrode; the second electrode is disposed on the same layer as the source electrode or the drain electrode.

7. A display device, characterized in that, A display substrate includes any one of claims 1 to 6.

8. A method for preparing a display substrate, characterized in that, Comprising: A pixel defining layer having a pixel opening is formed on one side of a substrate. The substrate includes a display area and a bonding area at least on one side of the display area. The pixel defining layer is disposed in the display area and the bonding area, and the pixel opening is disposed in the display area; A photoresist is coated on a side of the pixel defining layer away from the substrate, and halftone mask exposure, development, and ashing processes are performed such that there is no photoresist at the bottom of the pixel opening after development, and at least a part of the sidewall of the pixel opening is covered with photoresist after ashing; And the exposure degree of the photoresist covering the pixel defining layer in the display area is different from the exposure degree of the photoresist covering the pixel defining layer in the bonding area, so that after the ashing process, the shortest distance between the surface of the pixel defining layer in the bonding area away from the substrate and the substrate is less than the shortest distance between the surface of the pixel defining layer in the display area away from the substrate and the substrate; The photoresist is peeled off.

9. The manufacturing method of the display substrate according to claim 8, characterized in that, Before ashing, the pixel defining layer in the display area includes: an opening portion constituting the sidewall of the pixel opening and a flat portion other than the opening portion. The method further includes that at least a part of the thickness of the flat portion in the direction perpendicular to the substrate after ashing is the same as the thickness before ashing.

10. The method for preparing a display substrate according to claim 8, wherein, Forming the pixel defining layer having the pixel opening on the substrate includes: Forming a pixel defining layer having the pixel opening and a bonding opening on the substrate, and the bonding opening is disposed in the bonding area; The method further includes that there is no photoresist at the bottom of the bonding opening after development.

11. The method for preparing a display substrate according to claim 10, wherein Before forming the pixel defining layer having the pixel opening on the substrate, it further includes: Forming a first electrode on the substrate, and the first electrode is formed in the bonding area; Forming a first insulating layer having a first via hole on a side of the first electrode away from the substrate, and the first via hole exposes the first electrode; Forming a second electrode on a side of the first insulating layer away from the substrate, and the second electrode is electrically connected to the first electrode through the first via hole, and the second electrode is formed in the bonding area; Forming a second insulating layer on a side of the second electrode away from the substrate; Forming a flat layer on a side of the second insulating layer away from the substrate, and forming a second via hole exposing the second electrode; Forming a third electrode on a side of the flat layer away from the substrate, and the third electrode is formed in the bonding area. The third electrode is electrically connected to the second electrode through the second via hole, and the bonding opening exposes the third electrode.

12. The method for preparing a display substrate according to claim 10, wherein Before forming a pixel definition layer provided with pixel openings on a substrate, it further includes: Forming a first electrode on the substrate, the first electrode being formed in the bonding region; Forming a first insulating layer on a side of the first electrode away from the substrate; Forming a second electrode on a side of the first insulating layer away from the substrate, the second electrode being at least partially formed in the bonding region; Forming a second insulating layer on a side of the second electrode away from the substrate; Forming a planarization layer on a side of the second insulating layer away from the substrate, and forming a third via exposing the second electrode and a fourth via exposing the first electrode; Forming a third electrode on a side of the planarization layer away from the substrate, the third electrode being at least partially formed in the bonding region, the third electrode being electrically connected to the second electrode through the third via, the third electrode being electrically connected to the first electrode through the fourth via, and the bonding opening exposing the third electrode.

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