Metal Oxide Thin Film Transistor, Display Panel and Preparation Method Thereof

Abstract

An embodiment of the present application provides a metal oxide thin film transistor, a display panel and a manufacturing method thereof. The metal oxide thin film transistor includes a buffer layer, an active layer, a gate insulating layer, a gate layer and a dielectric layer. The active layer is disposed on one side of the buffer layer, and the material of the active layer is metal oxide. The gate insulating layer is disposed on the side of the active layer away from the buffer layer. The gate layer is disposed on the side of the gate insulating layer away from the active layer. The dielectric layer is disposed on the side of the gate layer away from the buffer layer, and the dielectric layer covers a part of the active layer, a part of the buffer layer and a part of the gate insulating layer. In the direction from the buffer layer to the active layer, the dielectric layer includes a silicon oxide sublayer and a barrier sublayer which are sequentially stacked, and the covering performance of the barrier sublayer is greater than that of the silicon oxide sublayer. In the embodiment of the present application, the barrier sublayer with greater covering performance does not break, avoiding the situation that water vapor enters and affects other devices due to the complete breakage of the dielectric layer.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly relates to a metal oxide thin film transistor, a display panel and a preparation method thereof. Background Art

[0002] A thin film transistor liquid crystal flat panel display is a type of active matrix liquid crystal display device. Each liquid crystal pixel on such a display screen is driven by a thin film transistor integrated behind the pixel. The thin film transistor (TFT, Thin Film Transistor) has an important impact on the responsiveness and color authenticity of the display, and is an important part of such displays. The TFT technology using metal oxide as the channel layer material is currently a research hotspot in the panel technology field. Using this technology, the power consumption of the display screen can be close to that of OLED, the thickness is only 25% higher than that of OLED, and the resolution can reach full high definition (full HD, 1920*1080P) or even ultra high definition (Ultra Definition, resolution 4k*2k) level, while the cost is relatively lower.

[0003] However, during the process of manufacturing a metal oxide thin film transistor, the dielectric layer is prone to slope fracture, resulting in abnormal product performance. Summary of the Invention

[0004] Embodiments of the present application provide a metal oxide thin film transistor, a display panel and a preparation method thereof, which can improve the existing situation of slope fracture of the dielectric layer.

[0005] Embodiments of the present application provide a metal oxide thin film transistor, including:

[0006] A buffer layer;

[0007] An active layer, the active layer is disposed on one side of the buffer layer, and the material of the active layer is metal oxide;

[0008] A gate insulating layer, the gate insulating layer is disposed on the side of the active layer away from the buffer layer;

[0009] A gate layer, the gate layer is disposed on the side of the gate insulating layer away from the active layer;

[0010] A dielectric layer, the dielectric layer is disposed on the side of the gate layer away from the buffer layer, and the dielectric layer covers part of the active layer, part of the buffer layer and part of the gate insulating layer. In the direction from the buffer layer to the active layer, the dielectric layer includes a silicon oxide sub-layer and a barrier sub-layer which are sequentially stacked, and the covering performance of the barrier sub-layer is greater than that of the silicon oxide sub-layer;

[0011] Wherein, the barrier layer includes at least one of silicon oxynitride and silicon nitride, the thickness of the silicon oxide sub-layer is greater than 3000 Å, the thickness of the barrier layer is between 500 Å and 1500 Å, the dielectric layer further includes a silicon oxynitride sub-layer, the silicon oxynitride sub-layer is disposed on a side of the silicon oxide sub-layer away from the barrier layer, and the thickness of the silicon oxynitride sub-layer is greater than or equal to 1500 Å;

[0012] The barrier layer and the silicon oxynitride sub-layer are fabricated by an ammonia-free process.

[0013] Optionally, the dielectric layer located on the active layer includes a plurality of vias, and the metal oxide thin film transistor further includes:

[0014] A light-shielding layer, the light-shielding layer is disposed on a side of the buffer layer away from the active layer, and the light-shielding layer is disposed opposite to the active layer;

[0015] Source and drain electrodes, the source and drain electrodes are disposed on a side of the dielectric layer away from the active layer;

[0016] A metal wire, the metal wire is disposed in the via, one end of the metal wire is connected to the source and drain electrodes, and the other end of the metal wire is connected to the active layer to electrically connect the source and drain electrodes to the active layer.

[0017] An embodiment of the present application further provides a display panel, including the metal oxide thin film transistor described in any one of the above.

[0018] An embodiment of the present application further provides a method for manufacturing a display panel, the method including:

[0019] Providing a substrate;

[0020] Disposing a buffer layer on the substrate;

[0021] Disposing an active layer on the buffer layer;

[0022] Sequentially disposing a patterned gate insulating layer and a gate layer on the active layer;

[0023] Sequentially disposing a silicon oxide sub-layer and a barrier layer on a side of the gate layer away from the buffer layer to form a dielectric layer, the dielectric layer further covers a part of the active layer, a part of the buffer layer, and a part of the gate insulating layer, and the covering performance of the barrier layer is greater than that of the silicon oxide sub-layer;

[0024] Among them, the blocking sub-layer includes at least one of silicon oxynitride and silicon nitride. The thickness of the silicon oxide sub-layer is greater than 3000 Å. The thickness of the blocking sub-layer is between 500 Å and 1500 Å. The dielectric layer further includes a silicon oxynitride sub-layer. The silicon oxynitride sub-layer is disposed on a side of the silicon oxide sub-layer away from the blocking sub-layer, and the thickness of the silicon oxynitride sub-layer is greater than or equal to 1500 Å;

[0025] The blocking sub-layer and the silicon oxynitride sub-layer are fabricated by an ammonia-free process.

[0026] Optionally, an oxide silicon sub-layer and a blocking sub-layer are sequentially disposed on a side of the gate layer away from the buffer layer to form a dielectric layer. The dielectric layer further covers a part of the active layer, a part of the buffer layer, and a part of the gate insulating layer, including:

[0027] A silicon oxynitride layer is disposed on a side of the gate layer away from the buffer layer;

[0028] An oxide silicon layer and a blocking layer are sequentially disposed on a side of the silicon oxynitride layer away from the buffer layer to form a dielectric layer.

[0029] Optionally, preparing the blocking sub-layer includes:

[0030] The blocking sub-layer is prepared by an ammonia-free low-H% process.

[0031] The beneficial effect of the present application is as follows: In the direction from the buffer layer to the active layer, in the embodiments of the present application, the dielectric layer of the metal oxide thin film transistor is set as a stacked silicon oxide sub-layer and blocking sub-layer, and the coverage performance of the blocking sub-layer is greater than that of the silicon oxide sub-layer. When the silicon oxide sub-layer is broken, the blocking sub-layer with greater coverage performance does not break, thereby avoiding the situation that water vapor enters and affects other devices due to the complete breakage of the dielectric layer, and improving the abnormal product performance caused by the breakage of the dielectric layer. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0033] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings. Among them, the same reference numerals in the following description represent the same parts.

[0034] Figure 1 It is a first structural schematic diagram of a metal oxide thin film transistor provided by an embodiment of the present application.

[0035] Figure 2 This is the second structural schematic diagram of the metal oxide thin film transistor provided by the embodiment of the present application.

[0036] Figure 3 This is the process schematic diagram of the preparation method of the display panel provided by the embodiment of the present application.

[0037] Figure 4 is Figure 3 The process schematic diagram of preparing the dielectric layer in the shown preparation method. Detailed implementation manners

[0038] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0039] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0040] The self-luminous properties of organic light-emitting diodes (OLEDs) are receiving increasing attention in active-matrix AMOLED flat-panel displays. TFTs provide driving current for OLED light-emitting devices, and this feature places higher demands on TFT output current and mobility in AMOLEDs. At present, the mainstream TFT technologies that are widely studied are low-temperature polycrystalline silicon (LTPS) technology and metal oxide TFT technology represented by indium gallium zinc oxide (IGZO). In LTPS technology, due to the characteristics of polycrystalline silicon materials, its large-area uniformity is poor, and its main application areas are small and medium-sized display screens. Metal oxide TFT technology represented by IGZO TFT has many advantages: the wide bandgap semiconductor material characteristics make it suitable for the requirements of fully transparent display, the lower process temperature can meet the requirements of using glass substrates or plastic flexible substrates, the large-area uniformity meets the requirements of large-screen display, and the high carrier mobility compared to A-Si:H can meet the requirements of high-definition picture quality of next-generation flat-panel displays.

[0041] At present, most of the research on IGZO TFT adopts the bottom gate device structure, which has the following shortcomings: the over-etching introduced by the BCE process will affect the device characteristics. Although the ESL technology does not have the above problems, the process complexity is increased. At the same time, the existence of the Gtae and S / D overlap area and the overlapping parasitic capacitance limit the application of the bottom gate structure in short channel high PPI and high-speed circuits. The top gate self-aligned device (TGSA) structure can effectively solve the problems caused by the bottom gate device structure. In addition, the gate dielectric layer and gate electrode above the channel effectively cover the channel, which can act as a protective layer for the channel.

[0042] Although the top gate self-aligned structure has lower parasitic capacitance, it is more likely to have ILD (full SiO) climbing crack problems due to excessive Gate / GI Taper when using Gate as Mask to engrave GI, and defects caused by cracks are more common during the RA process.

[0043] Therefore, in order to solve the above problems, the present application proposes a metal oxide thin film transistor, a display panel and a method for manufacturing the same. The present application is further described below in conjunction with the accompanying drawings and implementation examples.

[0044] See also Figure 1 , Figure 1This is the first structural schematic diagram of the metal oxide thin film transistor provided by the embodiments of the present application. The embodiments of the present application provide a metal oxide thin film transistor 100, which includes a buffer layer 10, an active layer 60, a gate insulating layer 40, a gate layer 50, and a dielectric layer 20. The active layer 60 is disposed on one side of the buffer layer 10, and the material of the active layer 60 is a metal oxide. The gate insulating layer 40 is disposed on the side of the active layer 60 away from the buffer layer 10, the gate layer 50 is disposed on the side of the gate insulating layer 40 away from the active layer 60, and the dielectric layer 20 is disposed on the side of the gate layer 50 away from the buffer layer 10, and the dielectric layer 20 covers a part of the active layer 60, a part of the buffer layer 10, and a part of the gate insulating layer 40. In the direction from the buffer layer 10 to the active layer 60, the dielectric layer 20 includes a silicon oxide sub-layer 210 and a barrier sub-layer 220 which are stacked in sequence, and the covering performance of the barrier sub-layer 220 is greater than that of the silicon oxide sub-layer 210. By setting the dielectric layer 20 as the stacked silicon oxide sub-layer 210 and barrier sub-layer 220, and the covering performance of the barrier sub-layer 220 is greater than that of the silicon oxide sub-layer 210, when the silicon oxide sub-layer 210 breaks, the barrier sub-layer 220 with greater covering performance does not break, thereby avoiding the situation that moisture enters and affects other devices due to the complete breakage of the dielectric layer 20, enabling the barrier sub-layer 220 to block the extension of the breakage of the silicon oxide sub-layer 210, and thus avoiding the situation that the product performance is abnormal due to the breakage of the dielectric layer 20.

[0045] It should be noted that the material of the metal oxide of the active layer 60 can be indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO), etc. The embodiments of the present application take the material of the active layer 60 as indium gallium zinc oxide as an example for illustration, and should not be construed as a limitation on the material of the active layer 60.

[0046] In some embodiments, the barrier sub-layer 220 can be composed of silicon oxynitride (SiON), that is, in the direction from the buffer layer 10 to the active layer 60, the dielectric layer 20 includes the silicon oxide sub-layer 210 and silicon oxynitride stacked in sequence. The covering performance of silicon oxynitride is greater than that of silicon oxide. When the silicon oxide sub-layer 210 breaks, silicon oxynitride can cover the breakage of the silicon oxide sub-layer 210, and the silicon oxynitride with greater covering performance does not break, preventing the extension of the breakage, and thus avoiding the influence of the breakage of the silicon oxide sub-layer 210 on other layers. In addition, silicon oxynitride can prevent the problem of external moisture entering the breakage, thereby improving the defective problems caused by the crack of the ILD in the RA process.

[0047] It should be noted that the silicon oxynitride (SiON) needs to meet the requirement of low H%, so as to reduce the influence of the ILD H% on the electrical properties of the IGZO TFT.

[0048] In some embodiments, the barrier sub-layer 220 may be composed of silicon nitride (SiNx). That is, in the direction from the buffer layer 10 to the active layer 60, the dielectric layer 20 includes a silicon oxide sub-layer 210 and silicon nitride stacked in sequence. The coverage performance of silicon nitride is greater than that of silicon oxide, and the barrier performance of silicon nitride is greater than that of silicon oxide. When the silicon oxide sub-layer 210 breaks, the silicon nitride can cover the break of the silicon oxide sub-layer 210, and the silicon nitride with better coverage performance does not break, thus avoiding the influence of the break of the silicon oxide sub-layer 210 on other layers. In addition, the silicon nitride can prevent external water vapor from entering the break, thereby improving the adverse problems caused by the crack of the ILD during the RA process.

[0049] It can be understood that the silicon nitride (SiNx) is fabricated using an ammonia-free process to achieve a low H% process, effectively reducing the problem of excessive leakage current in the active layer 60 caused by hydrogen ion diffusion in the active layer 60, thereby reducing the influence of ILD H% on the electrical properties of the IGZO TFT, and further improving the electrical performance of the metal oxide thin film transistor 100.

[0050] In some embodiments, the barrier sub-layer 220 may be composed of silicon nitride (SiNx) and silicon oxynitride (SiON). That is, in the direction from the buffer layer 10 to the active layer 60, the dielectric layer 20 includes a silicon oxide sub-layer 210 and a barrier sub-layer 220 stacked in sequence. The break of the silicon oxide sub-layer 210 can be covered by the silicon nitride and silicon oxynitride, and the silicon nitride and silicon oxynitride with better coverage performance do not break, thus avoiding the influence of the break of the silicon oxide sub-layer 210 on other layers. It can be understood that the composition, proportion, and position of the silicon nitride and silicon oxynitride in the barrier sub-layer 220 are not specifically limited herein and can be set according to actual situations, and no specific limitations are made here.

[0051] It should be noted that the thickness of the silicon oxide sub-layer 210 is greater than 3000 Å, and the thickness of the barrier sub-layer 220 is between 500 Å and 1500 Å.

[0052] Please continue to refer to Figure 2 , Figure 2 which is the second structural schematic diagram of the metal oxide thin film transistor provided by the embodiment of the present application. The dielectric layer 20 in the metal oxide thin film transistor 100 provided by the embodiment of the present application further includes a silicon oxynitride sub-layer 230, and the silicon oxynitride sub-layer 230 is disposed on the side of the silicon oxide sub-layer 210 away from the barrier sub-layer 220. That is, in the embodiment of the present application, by setting the dielectric layer 20 composed of all SiO in the prior art into a silicon oxynitride sub-layer 230, a silicon oxide sub-layer 210, and a barrier sub-layer 220 stacked in sequence, the situation where other layers are damaged due to the break of the dielectric layer 20 can be avoided.

[0053] Exemplarily, in some embodiments, in the direction from the buffer layer 10 to the active layer 60, the dielectric layer 20 includes a silicon oxynitride sub-layer 230, a silicon oxide sub-layer 210, and silicon oxynitride that are sequentially stacked. The coverage performance of the silicon oxynitride is greater than that of the silicon oxide. When the silicon oxide sub-layer 210 breaks, the silicon oxynitride sub-layer 230 can cover the break of the silicon oxide sub-layer 210, preventing the break of the silicon oxide sub-layer 210 from affecting the underlying TFT channel. The silicon oxynitride in the barrier sub-layer 220 is used to prevent the extension of the break, thereby avoiding the influence of the break of the silicon oxide sub-layer 210 on other layers. In addition, the silicon oxynitride can prevent the problem of external water vapor entering the break, thereby improving the adverse problems caused by the crack of the ILD in the RA process.

[0054] In some other embodiments, in the direction from the buffer layer 10 to the active layer 60, the dielectric layer 20 includes a silicon oxynitride sub-layer 230, a silicon oxide sub-layer 210, and silicon nitride that are sequentially stacked. The coverage performance of the silicon oxynitride is greater than that of the silicon oxide. When the silicon oxide sub-layer 210 breaks, the silicon oxynitride sub-layer 230 can cover the break of the silicon oxide sub-layer 210, preventing the break of the silicon oxide sub-layer 210 from affecting the underlying TFT channel. The coverage performance of the silicon nitride in the barrier sub-layer 220 is greater than that of the silicon oxide, and the barrier performance of the silicon nitride is greater than that of the silicon oxide. When the silicon oxide sub-layer 210 breaks, the silicon nitride can cover the break of the silicon oxide sub-layer 210, preventing the extension of the break, thereby avoiding the influence of the break of the silicon oxide sub-layer 210 on other layers. In addition, the silicon nitride can prevent the problem of external water vapor entering the break, thereby improving the adverse problems caused by the crack of the ILD in the RA process.

[0055] It should be noted that the thickness of the barrier sub-layer 220 is greater than or equal to 1000 Å, the thickness of the silicon oxide sub-layer 210 is greater than or equal to 2500 Å, and the thickness of the silicon oxynitride sub-layer 230 is greater than or equal to 1500 Å.

[0056] The dielectric layer 20 located on the active layer 60 includes a plurality of vias. The metal oxide thin film transistor 100 further includes a light-shielding layer 70, source / drain electrodes 30, and metal wires. Among them, the light-shielding layer 70 is disposed on the side of the buffer layer 10 away from the active layer 60. The light-shielding layer 70 is disposed opposite to the buffer layer 10, and the area of the light-shielding layer 70 is greater than the area of the active layer 60. The source / drain electrodes 30 are disposed on the side of the dielectric layer 20 away from the active layer 60. The metal wires are disposed in the vias. One end of the metal wire is connected to the source / drain electrodes 30, and the other end of the metal wire is connected to the active layer 60 to electrically connect the source / drain electrodes 30 and the active layer 60.

[0057] The embodiment of the present application also provides a display panel, which includes the metal oxide thin film transistor 100 described in any one of the above. For the specific situation of the metal oxide thin film transistor 100, please refer to the above, and details will not be repeated here.

[0058] Please continue to refer to Figure 3 , Figure 3 which is a schematic flow chart of the manufacturing method of the display panel provided by the embodiment of the present application. The embodiment of the present application also provides a manufacturing method of a display panel for manufacturing the above display panel. The specific method flow is as follows:

[0059] 101. Provide a substrate.

[0060] The substrate can be any one of glass, silicon dioxide, polyimide, polyethylene terephthalate, and polyethylene naphthalate. The substrate can be a rigid substrate or a flexible substrate. Exemplarily, the substrate can be a glass substrate or a flexible substrate. It can be understood that the material of the substrate is not specifically limited here and can also be other materials, which will not be listed one by one here, and a suitable substrate can be selected according to actual needs.

[0061] 102. Set a buffer layer on the substrate.

[0062] Set a full-surface buffer layer 10 on the substrate. The material of the buffer layer 10 can be silicon oxide (SiO2).

[0063] 103. Set an active layer on the buffer layer.

[0064] Deposit an IGZO film layer as the active layer 60 on the buffer layer 10, and perform photolithography and etching processes on the active layer 60 to obtain a patterned active layer 60. It can be understood that the active layer 60 can be made of other materials, which is not specifically limited here, and is set according to actual conditions, as long as the material of the active layer 60 is a metal oxide.

[0065] 104. Sequentially set a patterned gate insulating layer and a gate layer on the active layer.

[0066] Deposit and form a gate insulating layer 40 and a gate layer 50 on the active layer 60 in sequence, and use the same photomask to perform photolithography and etching processes on the gate insulating layer 40 and the gate layer 50 to obtain a patterned gate insulating layer 40 and a gate layer 50.

[0067] 105. Sequentially set a silicon oxide sub-layer and a barrier sub-layer on the side of the gate layer away from the buffer layer to form a dielectric layer. The dielectric layer also covers part of the active layer, part of the buffer layer, and part of the gate insulating layer. The covering performance of the barrier sub-layer is greater than that of the silicon oxide sub-layer.

[0068] On the side of the gate layer 50 away from the buffer layer 10, a silicon oxide sub-layer 210 and a barrier sub-layer 220 are sequentially provided to form a dielectric layer 20. It should be noted that the dielectric layer 20 also covers a part of the active layer 60, a part of the buffer layer 10, and a part of the gate insulating layer 40. Among them, the coverage performance of the barrier sub-layer 220 is greater than that of the silicon oxide sub-layer 210.

[0069] It should be noted that the thickness of the silicon oxide sub-layer 210 is greater than 3000 Å, and the thickness of the barrier sub-layer 220 is between 500 Å and 1500 Å.

[0070] Among them, the barrier sub-layer 220 can be composed of silicon oxynitride (SiON), the barrier sub-layer 220 can also be composed of silicon nitride (SiNx), and the barrier sub-layer 220 can also be composed of silicon nitride (SiNx) and silicon oxynitride (SiON).

[0071] It should be noted that in some other embodiments, a silicon oxide sub-layer 210 and a barrier sub-layer 220 are sequentially provided on the side of the gate layer 50 away from the buffer layer 10 to form a dielectric layer 20, and the following steps are also included. Please continue to refer to Figure 4 , Figure 4 For Figure 3 the flow schematic diagram of preparing the dielectric layer in the preparation method shown.

[0072] 201. Set a silicon oxynitride layer on the side of the gate layer away from the buffer layer.

[0073] A silicon oxynitride layer is set on the side of the gate layer 50 away from the buffer layer 10, and this silicon oxynitride layer covers a part of the active layer 60, a part of the buffer layer 10, and a part of the gate insulating layer 40.

[0074] 202. Sequentially set a silicon oxide layer and a barrier layer on the side of the silicon oxynitride layer away from the buffer layer to form a dielectric layer.

[0075] A silicon oxide layer and a barrier layer are sequentially set on the side of the silicon oxynitride layer away from the buffer layer 10 to form a dielectric layer 20. Among them, the thickness of the barrier sub-layer 220 is greater than or equal to 1000 Å, the thickness of the silicon oxide sub-layer 210 is greater than or equal to 2500 Å, and the thickness of the silicon oxynitride sub-layer 230 is greater than or equal to 1500 Å.

[0076] It should be noted that the methods for preparing the barrier sub-layer 220 and the silicon oxynitride layer include an ammonia-free low-H% process. The barrier sub-layer 220 and the silicon oxynitride layer are fabricated using an ammonia-free process to achieve a low-H% process, effectively reducing the problem of excessive leakage in the active layer 60 caused by hydrogen ion diffusion in the active layer 60, thereby reducing the influence of ILD H% on the electrical properties of the IGZO TFT, and further improving the electrical performance of the metal oxide thin film transistor 100.

[0077] By setting the dielectric layer 20 as a stacked silicon oxide sub-layer 210 and a barrier sub-layer 220, and the coverage performance of the barrier sub-layer 220 is greater than that of the silicon oxide sub-layer 210, the barrier sub-layer 220 blocks the extension of the fracture of the silicon oxide sub-layer 210. When the silicon oxide sub-layer 210 fractures, the barrier sub-layer 220 with greater coverage performance does not fracture. Furthermore, it can avoid the situation that moisture enters and affects other devices due to the complete fracture of the dielectric layer 20, and the barrier sub-layer 220 blocks the extension of the fracture of the silicon oxide sub-layer 210, thus avoiding the abnormal product performance caused by the fracture of the dielectric layer 20. At the same time, it can also improve the poor disconnection of the SD ramp caused by the ILD Crack caused by the excessive LS Taper; When the Gate Mask is fully etched for GI, and then the IGZO is conductorized to achieve top-gate self-alignment.

[0078] The above has introduced in detail the metal oxide thin film transistor, display panel and their manufacturing methods provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A metal oxide thin film transistor, characterized in that, Comprising: A buffer layer; An active layer, the active layer being disposed on one side of the buffer layer, and the material of the active layer being a metal oxide; A gate insulating layer, the gate insulating layer being disposed on the side of the active layer away from the buffer layer; A gate layer, the gate layer being disposed on the side of the gate insulating layer away from the active layer; A dielectric layer, the dielectric layer being disposed on the side of the gate layer away from the buffer layer, and the dielectric layer covering a part of the active layer, a part of the buffer layer, and a part of the gate insulating layer. In the direction from the buffer layer to the active layer, the dielectric layer includes a silicon oxide sub-layer and a barrier sub-layer which are sequentially stacked, and the covering performance of the barrier sub-layer is greater than that of the silicon oxide sub-layer; Wherein, the barrier sub-layer includes at least one of silicon oxynitride and silicon nitride, the thickness of the silicon oxide sub-layer is greater than 3000 Å, the thickness of the barrier sub-layer is between 500 Å and 1500 Å, the dielectric layer further includes a silicon oxynitride sub-layer, the silicon oxynitride sub-layer is disposed on the side of the silicon oxide sub-layer away from the barrier sub-layer, and the thickness of the silicon oxynitride sub-layer is greater than or equal to 1500 Å; The barrier sub-layer and the silicon oxynitride sub-layer are fabricated by an ammonia-free process.

2. The metal oxide thin film transistor according to claim 1, characterized in that, The dielectric layer located on the active layer includes a plurality of vias, and the metal oxide thin film transistor further includes: A light-shielding layer, the light-shielding layer being disposed on the side of the buffer layer away from the active layer, and the light-shielding layer being disposed opposite to the active layer; Source and drain electrodes, the source and drain electrodes being disposed on the side of the dielectric layer away from the active layer; A metal wire, the metal wire being disposed in the via, one end of the metal wire being connected to the source and drain electrodes, and the other end of the metal wire being connected to the active layer to electrically connect the source and drain electrodes to the active layer.

3. A display panel, characterized in that, Comprising the metal oxide thin film transistor according to any one of claims 1-2 above.

4. A method for manufacturing a display panel, characterized in that, The method includes: Providing a substrate; Disposing a buffer layer on the substrate; Disposing an active layer on the buffer layer; Sequentially disposing a patterned gate insulating layer and a gate layer on the active layer; Sequentially disposing a silicon oxide sub-layer and a barrier sub-layer on the side of the gate layer away from the buffer layer to form a dielectric layer, the dielectric layer also covering a part of the active layer, a part of the buffer layer, and a part of the gate insulating layer, and the covering performance of the barrier sub-layer is greater than that of the silicon oxide sub-layer; Wherein, the barrier sub-layer includes at least one of silicon oxynitride and silicon nitride, the thickness of the silicon oxide sub-layer is greater than 3000 Å, the thickness of the barrier sub-layer is between 500 Å and 1500 Å, the dielectric layer further includes a silicon oxynitride sub-layer, the silicon oxynitride sub-layer is disposed on the side of the silicon oxide sub-layer away from the barrier sub-layer, and the thickness of the silicon oxynitride sub-layer is greater than or equal to 1500 Å; The barrier sub-layer and the silicon oxynitride sub-layer are fabricated by an ammonia-free process.

5. The manufacturing method according to claim 4, characterized in that, An oxide silicon sub-layer and a barrier sub-layer are sequentially disposed on a side of the gate layer away from the buffer layer to form a dielectric layer, and the dielectric layer also covers a part of the active layer, a part of the buffer layer, and a part of the gate insulating layer, including: A silicon oxynitride layer is disposed on a side of the gate layer away from the buffer layer; An oxide silicon layer and a barrier layer are sequentially disposed on a side of the silicon oxynitride layer away from the buffer layer to form a dielectric layer.

6. The manufacturing method according to claim 4, characterized in that, Preparing the barrier sub-layer includes: Preparing the barrier sub-layer by an ammonia-free low-H% process.

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