Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The thin film transistor group is arranged on the substrate in an array mode and comprises an oxide thin film transistor, the oxide thin film transistor comprises a bottom gate, a first active layer, a top gate and a first source and drain electrode layer, and the first source and drain electrode layer comprises a first source electrode and a first drain electrode; wherein orthographic projections of the first source electrode, the first active layer and the bottom gate on the substrate are at least partially overlapped, and the first source electrode is electrically connected with the first active layer and the bottom gate through a first metal via hole within the range of the overlapped area; the display device comprises the display panel. According to the invention, the number of the metal via holes is reduced, process gaps between the metal via holes are omitted, the problem that layout space is limited is solved, and the problem that via hole coverage is abnormal due to burr lap joint is also avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel that can free up the layout design space of pixel areas, reduce the failure rate of driving circuits, and a display device having the display panel. Background Technology

[0002] Organic Light-Emitting Diode (OLED) display panels offer advantages such as high contrast (pixels do not emit light when displaying black), high response time (short pixel on / off time, no ghosting), wide viewing angle (minimal color / brightness differences when viewed from different angles), and foldable / rollable designs, leading to their increasingly widespread use in display devices. In the driving circuitry of display panels, the mainstream thin-film transistor (TFT) technology includes amorphous silicon (a... Si) technology, Low Temperature Polysilicon (LSP) Silicon (abbreviated as LTPS) technology and oxide semiconductor technology, where the carrier mobility of oxide semiconductors is between that of low-temperature polycrystalline silicon (LTPS) and amorphous silicon (a). Between silicon (Si) and crystalline silicon (Si), the technological advantages lie in extremely low leakage current and minimal hysteresis, which can significantly reduce the power consumption of display panels and improve screen retention issues. With the rapid development of display technology, consumers have increasingly higher demands for high resolution, variable refresh rate (VRR), and low power consumption in display devices. Therefore, low-temperature polycrystalline oxide (LTPO) TFT technology, which combines the advantages of low-temperature polycrystalline silicon (LTPS) and oxide semiconductors (such as indium gallium zinc oxide (IGZO)), has emerged. If oxide thin-film transistors are used as driver thin-film transistors (DTFTs), screen retention and VRR, which are highly correlated with TFT hysteresis, will be significantly improved. Therefore, replacing DTFTs with IGZO devices in LTPO technology is a major development trend.

[0003] In existing display panels using LTPO technology, the limited layout space under high pixel density conditions causes some areas of the TFT devices in the driving circuit to exceed process limits, leading to malfunctions. Specifically, driving transistors using oxide active layers generally employ a BSC (Bottom Source Contact Structure) structure, requiring signal connections between the TFT source, bottom gate, and the source-end doped portion of the oxide active layer. Current designs typically connect the source to the bottom gate and the source-end doped portion of the oxide active layer via two independent metal vias. However, to accommodate the process gaps between these two independent vias, the dimensions of the source, oxide active layer, and bottom gate must be elongated along the carrier conduction direction in the oxide active layer, easily causing some areas of the TFT device to exceed process limits. In addition, under the condition of limited layout space, if the process gap between two independent metal vias is reduced, more burrs will be generated between the two metal vias during actual manufacturing. The overlapping of burrs can easily lead to abnormal via coverage, which in turn affects the normal operation of the TFT device and causes display abnormalities.

[0004] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0005] This application provides a display panel and display device that reduces the number of metal vias, eliminates the process gaps between metal vias, solves the problem of limited layout space, and avoids the problem of abnormal via coverage caused by burr overlap, thereby at least partially solving the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: Substrate; A thin-film transistor array is disposed on the substrate, the thin-film transistor array comprising: An oxide thin-film transistor includes, along the thickness direction of the display panel, a bottom gate, a first active layer above the bottom gate, a top gate above the first active layer, and a first source-drain layer above the top gate, wherein the first source-drain layer includes a first source and a first drain. Wherein, the orthographic projections of the first source electrode, the first active layer, and the bottom gate on the substrate at least partially overlap, and within the overlapping area, the first source electrode is electrically connected to the first active layer and the bottom gate through a first metal via.

[0007] Optionally, within the overlapping area, the number of the first metal vias is one.

[0008] Optionally, the first active layer includes: The first channel section extends along the first direction; The first source-end doped portion is disposed on one side of the extension direction of the first channel portion and is electrically connected to the first source and the bottom gate through the first metal via. The first drain end doped portion is disposed on the other side of the extension direction of the first channel portion and is electrically connected to the first drain electrode through the second metal via.

[0009] Optionally, along the thickness direction of the display panel, the thin-film transistor array further includes: A first interlayer dielectric layer is disposed on one side of the substrate and covers the bottom gate, and a first active layer is disposed on the side of the first interlayer dielectric layer away from the bottom gate; A second gate insulating layer is disposed on the side of the first interlayer dielectric layer away from the bottom gate and covers the first active layer; the top gate is disposed within the second gate insulating layer; and / or the top gate is disposed on the side of the second gate insulating layer away from the first active layer. The second interlayer dielectric layer is disposed on the side of the second gate insulating layer away from the first interlayer dielectric layer and covers the top gate; The first source-drain layer is disposed on the side of the second interlayer dielectric layer away from the top gate.

[0010] Optionally, along the first direction, the first metal via includes: The first bridging portion extends through the second interlayer dielectric layer, the second gate insulating layer, and the first interlayer dielectric layer along the thickness direction of the display panel and is electrically connected to the bottom gate. The second bridging portion extends through the second interlayer dielectric layer and the second gate insulating layer along the thickness direction of the display panel and is electrically connected to the first source end doped portion of the first active layer. The first bridging portion and the second bridging portion together form the first metal via.

[0011] Optionally, along the thickness direction of the display panel, the oxide thin-film transistor further includes: A capacitor electrode is disposed on the side of the second gate insulating layer away from the top gate; the orthogonal projection of the capacitor electrode on the substrate coincides with the orthogonal projection of the top gate on the substrate.

[0012] Optionally, along the thickness direction of the display panel, the second gate insulating layer includes: The third sublayer is disposed on the side of the first interlayer dielectric layer away from the bottom gate and covers the first active layer, and the top gate is disposed on the side of the third sublayer away from the first active layer; The fourth sub-layer is disposed on the side of the third sub-layer away from the first active layer and covers the top gate, and the capacitor electrode is disposed on the side of the fourth sub-layer away from the top gate; The second interlayer dielectric layer is disposed on the side of the fourth sublayer away from the top gate and covers the capacitor electrode.

[0013] Optionally, the display panel further includes: A planarization layer is disposed on the side of the second interlayer dielectric layer away from the top gate and covers the first source-drain layer; A light-emitting layer is disposed on the side of the planar layer away from the second interlayer dielectric layer, and the light-emitting layer includes an array of anodes; A bridging electrode is arrayed within the planarization layer, and the bridging electrode bridges the corresponding first drain and the anode.

[0014] Optionally, the thin-film transistor array further includes: A polycrystalline silicon thin-film transistor, disposed adjacent to the oxide thin-film transistor, includes, along the thickness direction of the display panel: The second active layer is disposed on the substrate and is arranged in a different layer from the oxide thin film transistor; The second gate is disposed on the side of the second active layer away from the substrate and is arranged in a different layer from the oxide thin film transistor; The second source-drain layer is disposed on the side of the second gate away from the second active layer and is disposed in the same layer as the first source-drain layer. The second source-drain layer includes a second source and a second drain.

[0015] According to a second aspect of this application, a display device is also provided, the display device comprising the display panel described in any one of the preceding claims.

[0016] In the display panel of this application embodiment, the first source of the oxide thin-film transistor is electrically connected to the first active layer and the bottom gate through a first metal via. Compared with the prior art, this method combines two independent metal vias, reducing the number of metal vias and eliminating the process gap between the two metal vias. It also eliminates the need to elongate the first source, first active layer, and bottom gate along the first direction, i.e., the carrier conduction direction of the first active layer, thus preventing some areas of the TFT device from exceeding the process limits and solving the problem of limited layout space. This facilitates the design of high pixel density display panels. Furthermore, combining the two independent metal vias into one avoids compressing the process gap between vias, preventing abnormal via coverage caused by burr overlap, ensuring the normal operation of the TFT device, and significantly improving the display effect of the display panel.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a partial structural cross-sectional view of the display panel provided in related technologies; Figure 2 This is a top view schematic diagram of the oxide thin-film transistor structure of a display panel provided in related technologies; Figure 3 It is the switching performance curve of oxide thin film transistors when the gap of the metal via process in the display panel is insufficient, as provided in the related technology; Figure 4 This is a top view of the display panel provided in an exemplary embodiment of this disclosure; Figure 5 This is a partial structural cross-sectional view of the display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is a top view of the oxide thin-film transistor structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 7 yes Figure 5 A magnified view of a local structure of an oxide thin-film transistor.

[0021] Explanation of reference numerals in the attached figures: 100 - Display panel; 101 - Substrate; 1011 - Array area; 1012 - Peripheral area; 102 - Barrier layer; 103 - Buffer layer; 104 - First gate insulating layer; 1041 - First sub-layer; 1042 - Second sub-layer; 105 - First interlayer dielectric layer; 106 - Second gate insulating layer; 1061 - Third sub-layer; 1062 - Fourth sub-layer; 107 - Second interlayer dielectric layer; 108 - Planarization layer; 1081 - First planarization layer; 1082 - Second planarization layer; 1083 - Third planarization layer; 109 - Light-emitting layer; 1091 - Pixel definition layer; 10911 - Pixel aperture; 1092 - Barrier structure; 1093 - Anode; 1094 - Third bridging metal via; 110 - Sub-pixel; 10-Thin-film transistor array; 1-Oxide thin-film transistor; 11-Bottom gate; 12-First active layer; 121-First channel portion; 122-First source doped portion; 123-First drain doped portion; 13-Top gate; 14-First source; 15-First drain; 16-First metal via; 161-First bridging portion; 162-Second bridging portion; 17-Second metal via; 18-Capacitor electrode; 2-Polysilicon thin-film transistor; 21-Second active layer; 211-Second channel; 212-Second source doped portion; 213-Second drain doped portion; 22-Second gate; 23-Second source; 24-Second drain; 25-Third metal via; 26-Fourth metal via; 3-Bridging electrode; 31-First bridging electrode; 311-First bridging metal hole; 32-Second bridging electrode; 321-Second bridging metal hole; 4-Metal via A; 41-Process clearance. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0023] Driver transistors using oxide semiconductors typically employ a BSC (base-semiconductor grid) structure, requiring signal connections between the TFT source and the bottom gate, as well as the doped portion of the oxide semiconductor source. Please refer to [link / reference needed]. Figure 1 and Figure 2In existing designs, an oxide thin-film transistor 1 includes a bottom gate 11, a first active layer 12 disposed on the bottom gate 11, a top gate 13 disposed on the first active layer 12, and a first source-drain layer disposed on the top gate 13. The first source-drain layer includes a first source 14 and a first drain 15. The first source 14 is connected to the source-end doped portions of the bottom gate 11 and the first active layer 12 through two independent metal vias A4, respectively, to achieve signal connection among the three. However, in order to accommodate the process gap 41 between the two independent metal vias A4, the dimensions of the first source 14, the first active layer 12, and the bottom gate 11 need to be elongated along the carrier conduction direction in the first active layer 12, which can easily cause some areas of the TFT device to exceed the process limits. In addition, as Figure 3 As shown, under the condition of limited layout space, if the process gap 41 between the two independent metal vias A4 is reduced, more burrs will appear between the two metal vias A4 due to process issues during actual manufacturing. This burr overlap can easily lead to abnormal via coverage, thus affecting the normal operation of the TFT device and causing display abnormalities. Figure 3 As can be seen intuitively, when the gate voltage is below the threshold (e.g., -15V to -5V), the drain current does not remain at a low level, but instead fluctuates significantly, failing to maintain the cutoff state of the TFT device; after the gate voltage exceeds the threshold, the drain current changes irregularly with the gate voltage, exhibiting a chaotic fluctuating curve.

[0024] To facilitate readers' understanding of the technical solution of this application, the length direction of the display panel 100 is defined as the X-axis direction, the width direction of the display panel 100 is defined as the Y-axis direction, and the thickness direction of the display panel 100 is defined as the Z-axis direction.

[0025] In view of this, please refer to Figures 4 to 5 In a first aspect, this application provides a display panel 100, which includes a substrate 101, a thin-film transistor array 10 (e.g., ...), and a display panel 100 comprising a substrate 101, a thin-film transistor array 10, ... Figure 5As shown in the diagram, the substrate 101 can be a rigid substrate 101 made of glass or a flexible substrate 101 made of polyimide (PI). An array region 1011 and a peripheral region 1012 adjacent to the array region 1011 can be defined on the substrate 101. The array region 1011 is the functional area on the substrate 101 where the thin-film transistor group 10 is formed. Specifically, the pattern boundary can be defined using photolithography to ensure the electrical performance of each TFT device in the thin-film transistor group 10. The peripheral region 1012 refers to the wiring area surrounding the array region 1011. Specifically, it can be formed by extending a metal layer to form a wiring channel, which undertakes the signal transmission function. The thin-film transistor group 10 is patterned on the substrate 101 and arrayed within the array region 1011. The thin-film transistor group 10 is used to control the on / off state of corresponding sub-pixels 110 on the display panel 100. For example, the sub-pixels 110 of the display panel 100 can be arranged in a matrix in a row and column manner along the length direction of the display panel 100 (taking the X-axis direction as an example in this embodiment, and will not be described again below) and the width direction of the display panel 100 (taking the Y-axis direction as an example in this embodiment, and will not be described again below).

[0026] Specifically, please refer to Figure 5 The thin-film transistor group 10 includes an oxide thin-film transistor 1. Each thin-film transistor group 10 may have only one oxide thin-film transistor 1 or multiple oxide thin-film transistors 1. This application does not make a specific limitation on this. In this embodiment, an oxide thin-film transistor 1 is used as an example for illustration. It can be used as a driving transistor DTFT in the thin-film transistor group 10.

[0027] Along the thickness direction of the display panel 100, i.e. the Z-axis direction, the oxide thin film transistor 1 includes a bottom gate 11 located in the lower layer and relatively close to the substrate 101, a first active layer 12 located above the bottom gate 11, a top gate 13 located above the first active layer 12, and a first source-drain layer located above the top gate 13. The first source-drain layer includes a first source 14 and a first drain 15. The first active layer 12 is an oxide semiconductor layer. In this embodiment, the material of the first active layer 12 is indium gallium zinc oxide (IGZO) as an example. When IGZO is used as the active layer material, it has the following core advantages: First, it has low hysteresis (the voltage curve deviation during the conduction and turn-off process of the oxide thin film transistor 1 is small), which can significantly improve the ghosting problem (the problem of the previous image remaining after the screen switch) and the variable refresh rate (VRR) performance of the display panel 100, making the display of the display panel 100 more stable at different refresh rates; Second, it has low leakage current, which can significantly reduce the standby power consumption of the display panel 100, making it suitable for wearable devices, mobile phones and other battery life-sensitive products; Third, it has good material stability and strong process compatibility, making it a key material for the driving transistor DTFT.

[0028] The first source electrode 14, the first active layer 12, and the bottom gate 11 have at least partial overlap in their orthogonal projections on the substrate 101. Within the overlap region, the first source electrode 14 is electrically connected to the first active layer 12 and the bottom gate 11 through the first metal via 16.

[0029] For specific implementation details, please refer to [link / reference]. Figure 5 and Figure 6 In order to enable the first source 14 to connect downward to the bottom gate 11 via the first active layer 12 which is located in the middle, along the carrier conduction direction in the oxide thin film transistor 1 (taking the X-axis direction as an example in this embodiment, which will not be described again below), both the bottom gate 11 and the first source 14 extend outward beyond the end of the first active layer 12 at least partially, ensuring that the first metal via 16 can simultaneously connect the first source 14 with the first active layer 12 and the bottom gate 11 within the overlapping area.

[0030] Please see Figure 5 and Figure 6 In the display panel 100 provided in this application embodiment, the first source 14 of the oxide thin film transistor 1 is electrically connected to the first active layer 12 and the bottom gate 11 through the first metal via 16. Compared with the prior art, the two independent metal vias A4 are merged, reducing the number of metal vias and eliminating the process gap 41 between the two metal vias A4. Therefore, it is not necessary to stretch the first source 14, the first active layer 12, and the bottom gate 11 along the carrier conduction direction of the first active layer 12, i.e., the X-axis direction. This significantly reduces the layout size of the source signal connection area of ​​the oxide thin film transistor 1, breaking through the layout space limitation in high pixel density scenarios and adapting to the compact structure requirements of flexible OLEDs, wearable devices, etc.

[0031] In addition, the display panel 100 provided in this application merges the two independent metal vias A4 in the source signal connection area of ​​the oxide thin film transistor 1 into one, which structurally avoids the abnormal burr overlap caused by the reduction of the process gap 41 between the metal vias A. Without changing the BSC structure characteristics of the oxide thin film transistor 1, the normal operation of the oxide thin film transistor 1 is guaranteed, and the display effect of the display panel 100 is significantly improved.

[0032] Please see Figure 6 In some embodiments, in the display panel 100 provided in this application, the number of first metal vias 16 in the overlapping area is one, that is, the first source 14 is electrically connected to the first active layer 12 and the bottom gate 11 through a single first metal via 16, which can minimize the number of first metal vias 16 and further reduce the space occupied by the first metal vias 16 in the overlapping area.

[0033] For example, the first active layer 12 can be configured to extend along the X-axis direction, and the bottom gate 11 below the first active layer 12 can also be configured to extend along the X-axis direction, with the orthographic projection of the first active layer 12 onto the substrate 101 located within the orthographic projection of the bottom gate 11 onto the substrate 101. The top gate 13 above the first active layer 12 can be configured to extend along the Y-axis direction, and the top gate 13 is laterally arranged at the middle position of the first active layer 12. The first source 14 and the first drain 15 above the top gate 13 can also be configured to extend along the X-axis direction, wherein the first source 14 is located above one side of the top gate 13 along its length direction, and the first drain 15 is located above the other side of the top gate 13 along its length direction.

[0034] In the X-axis direction, the end of the first source 14 that is away from the top gate 13 is defined as the first end, and the length of the first end from the edge of the top gate 13 is defined as L1 mm; the end of the bottom gate 11 that is away from the top gate 13 and on the same side as the first end is defined as the second end, and the length of the second end from the edge of the top gate 13 is defined as L2 mm.

[0035] Please see Figure 2 In the prior art, in the X-axis direction, the end of the first source 14 that is away from the top gate 13 is defined as the first end A, and the length of the first end A from the edge of the top gate 13 is defined as LA1 mm; the end of the bottom gate 11 that is away from the top gate 13 and on the same side as the first end A is defined as the second end A, and the length of the second end A from the edge of the top gate 13 is defined as LA2 mm.

[0036] In the display panel 100 provided in this application, the first source 14 of the oxide thin-film transistor 1 is electrically connected to the first active layer 12 and the bottom gate 11 through a separate first metal via 16. Compared with the prior art, this method combines two independent metal vias A4, reducing the number of metal vias and eliminating the process gap 41 between the two metal vias A4. This results in a significantly smaller size ratio of the single first metal via 16 in the X-axis direction compared to the prior art where two metal vias A4 occupy the same X-axis. Thus, the technical solution of this application significantly reduces the space occupied by the first metal via 16 in the overlapping area in the X-axis direction, allowing the first end of the first source 14 and the second end of the bottom gate 11 to be recessed along the X-axis direction. This makes the length of L1 significantly smaller than the length of LA1 and the length of L2 significantly smaller than the length of LA2, thereby significantly reducing the layout size of the source signal connection area of ​​the oxide thin-film transistor 1 and overcoming the layout space limitations in high pixel density scenarios. For some embodiments, please refer to... Figure 7In the display panel 100 provided in this application, the first active layer 12 includes a first channel portion 121, a first source-end doped portion 122, and a first drain-end doped portion 123. The first channel portion 121 extends along a first direction. In this embodiment, the first direction is described using the X-axis direction as an example. The first direction is the carrier conduction direction in the first active layer 12. The first channel portion 121 is the core region for carrier (electron or hole) migration in the first active layer 12. Its material can be undoped indium gallium zinc oxide (IGZO) or a lightly doped material mainly composed of IGZO. This application does not specifically limit this.

[0037] The first source-end doped portion 122 is disposed on one side of the extension direction of the first channel portion 121 (taking the left side of the extension direction of the first channel portion 121 as an example in this embodiment), and is electrically connected to the first source electrode 14 and the bottom gate 11 through the first metal via 16, so that the first source-end doped portion 122 can be at the same potential as the bottom gate 11, which can reduce the hysteresis effect of the oxide thin film transistor 1 and improve the variable refresh rate (VRR) performance. The first drain-end doped portion 123 is disposed on the other side of the extension direction of the first channel portion 121 (taking the right side of the extension direction of the first channel portion 121 as an example in this embodiment), and is electrically connected to the first drain electrode 15 through the second metal via 17. The first drain electrode 15 can be connected to the anode 1093 of the corresponding sub-pixel 110 of the display panel 100 (e.g., ...). Figure 4 Electrical connection (as shown in the diagram).

[0038] Specifically, the orthographic projection of the top gate 13 on the substrate 101 coincides with the orthographic projection of the first channel portion 121 on the substrate 101, and is located within the orthographic projection of the bottom gate 11 on the substrate 101. The first source-end doped portion 122 is the interface for current injection into the first active layer 12, and is directly connected to the upper first source 14 and the lower bottom gate 11 through the first metal via 16, achieving "source-bottom gate at the same potential". The first drain-end doped portion 123 is the interface for current output from the first active layer 12, and is connected to the upper first drain 15 through the second metal via 17. The first channel portion 121 is the core hub for current regulation. The carrier concentration in the first channel portion 121 is regulated by the voltage of the upper top gate 13 and the lower bottom gate 11, wherein the bottom gate 11 can be used as the main control gate, and the top gate 13 can be used as an auxiliary gate. When the bottom gate 11 and top gate 13 do not receive a driving signal, the first channel portion 121 is in a high-resistivity state, and there is no carrier migration inside. At this time, the corresponding sub-pixel 110 does not emit light. When the bottom gate 11 and top gate 13 receive a driving signal, the first channel portion 121 is turned on, and the current of the first source 14 flows into the first source end doped portion 122 through the first metal via 16. After flowing through the first channel portion 121 to the first drain end doped portion 123, it flows through the second metal via 17 to the first drain 15, and finally flows to the anode 1093 of the corresponding sub-pixel 110, thereby driving the sub-pixel 110 to emit light.

[0039] Furthermore, in order to reduce the contact impedance between the first source-end doped portion 122 and the bottom gate 11 and the first source electrode 14, and to improve signal transmission efficiency, the material of the first source-end doped portion 122 can be a heavily doped material containing indium gallium zinc oxide (IGZO). In specific implementations, atmospheric heat treatment (such as hydrogen atmosphere), ion implantation (such as phosphorus or germanium ions), or plasma treatment can be used to introduce a high concentration of oxygen vacancies or N-type impurities into the left end of the first active layer 12 near the first source electrode 14, forming a stable, heavily doped first source-end doped portion 122.

[0040] Similarly, in order to reduce the contact impedance between the first drain doped portion 123 and the first drain electrode 15 and improve signal transmission efficiency, the material of the first drain doped portion 123 can also be a heavily doped material containing indium gallium zinc oxide (IGZO). In specific implementations, atmospheric heat treatment (such as hydrogen atmosphere), ion implantation (such as phosphorus or germanium ions), or plasma treatment can be used to introduce a high concentration of oxygen vacancies or N-type impurities into the right end of the first active layer 12 near the first drain electrode 15 to form a stable, heavily doped first drain doped portion 123.

[0041] Through the above technical solution, the display panel 100 provided in this application embodiment realizes efficient driving control of sub-pixels 110 by oxide thin film transistor 1. With the "dual gate coordinated regulation" effect of top gate 13 and bottom gate 11, the hysteresis voltage can be reduced to below 0.1V, which significantly improves the variable refresh rate (VRR) performance and significantly reduces the risk of ghosting in the display panel 100.

[0042] In some embodiments, please refer to Figure 5 The display panel 100 provided in this application includes, along the thickness direction (Z-axis) of the display panel 100, a thin-film transistor group 10 further comprising a first interlayer dielectric layer 105, a second gate insulating layer 106, and a second interlayer dielectric layer 107. The first interlayer dielectric layer 105 is disposed on one side of the substrate 101 and covers the bottom gate 11. The first active layer 12 is disposed on the side of the first interlayer dielectric layer 105 away from the bottom gate 11. The material of the first interlayer dielectric layer 105 may be silicon oxide (SiO2) or silicon nitride (SiN). x Materials such as silicon oxynitride (SiON) are used to isolate the bottom gate 11 and the first active layer 12 through the first interlayer dielectric layer 105, avoiding interlayer short circuits. The first interlayer dielectric layer 105 can also provide an insulating substrate for etching the first metal hole, ensuring the independence of the conductive channel of the first metal hole.

[0043] The second gate insulating layer 106 is disposed on the side of the first interlayer dielectric layer 105 away from the bottom gate 11 and covers the first active layer 12. The top gate 13 may be disposed within the second gate insulating layer 106; or, the top gate 13 may also be disposed on the side of the second gate insulating layer 106 away from the first active layer 12.

[0044] The second interlayer dielectric layer 107 is disposed on the side of the second gate insulating layer 106 away from the first interlayer dielectric layer 105 and covers the top gate 13. The first source / drain layer is disposed on the side of the second interlayer dielectric layer 107 away from the top gate 13. The material of the second interlayer dielectric layer 107 can also be silicon oxide (SiO2) or silicon nitride (SiN). x Materials such as silicon oxynitride (SiON) are used to isolate the top gate 13 from the first source-drain layer through the second interlayer dielectric layer 107, avoiding interlayer short circuits and providing insulation support for the metal wiring of the first source-drain layer. This prevents electrical crosstalk between the first source 14 and the first drain 15 of the first source-drain layer and the surrounding electrodes, wiring, and the lower top gate 13 and the first active layer 12, ensuring the stability of the device electrical performance of the oxide thin film transistor 1.

[0045] In some embodiments, please refer to Figure 7In the display panel 100 provided in this application, along the first direction, i.e. the X-axis direction, the first metal via 16 includes a first bridging portion 161 and a second bridging portion 162. The first bridging portion 161 penetrates the second interlayer dielectric layer 107, the second gate insulating layer 106, and the first interlayer dielectric layer 105 along the thickness direction of the display panel 100 and is electrically connected to the bottom gate 11. The second bridging portion 162 penetrates the second interlayer dielectric layer 107 and the second gate insulating layer 106 along the thickness direction of the display panel 100 and is electrically connected to the first source doped portion 122. The first bridging portion 161 and the second bridging portion 162 together form the first metal via 16.

[0046] Specifically, the first metal via 16 is a single-hole structure. As can be seen from the figure, its cross-sectional shape in the thickness direction of the display panel 100 is approximately a "V" shape. The left half, bottom, and lower part of the right half of the "V" shape constitute the first bridging portion 161 of the first metal via 16. The bottom of the "V" shape directly contacts the bottom gate 11, and the electrical connection between the first source 14 and the bottom gate 11 can be achieved through the left half of the "V" shape. The lower part of the right half of the "V" shape extends to the end of the first source doped portion 122, and is electrically connected to the left half of the "V" shape through the bottom of the "V" shape.

[0047] The upper right half of the "V"-shaped structure forms the second bridging portion 162 of the first metal via 16. The second bridging portion 162 directly contacts the first source-end doped portion 122 at the bottom of the "V"-shaped structure, achieving an electrical connection between the first source 14 and the bottom gate 11. Simultaneously, the second bridging portion 162 connects to the first bridging portion 161 at the end of the first source-end doped portion 122, thereby electrically connecting the first source 14 to the bottom gate 11 and the first source-end doped portion 122 through the first bridging portion 161 and the second bridging portion 162 of the first metal via 16.

[0048] For example, the first metal via 16 and the second metal via 17 can be fabricated in the following two steps: Step 1: Using Deep Ultraviolet Lithography (DUV) or Electron Beam Lithography (EBL), mask patterns for the first metal via 16 and the second metal via 17 are defined on the surface of the second interlayer dielectric layer 107. This ensures that the left side of the first metal via 16 is aligned with the bottom gate 11 and the right side with the first source doped portion 122, and that the second metal via 17 is aligned with the first drain doped portion 123. Then, a dry etching process is used to etch the second interlayer dielectric layer 107, the second gate insulating layer 106, and the first interlayer dielectric layer 105 to form the first and second vias. The bottom of the first via exposes the bottom gate 11, and the lower right side of the first via exposes the end position of the first source doped portion 122. The second via is etched only to penetrate the second gate insulating layer 106 and expose the first drain doped portion 123.

[0049] Step 2: Using Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD) processes, a metal material (such as molybdenum / aluminum / molybdenum (Mo / Al / Mo), molybdenum / titanium (Mo / Ti), etc.) is deposited on the second interlayer dielectric layer 107 with the first via formed to form a source / drain metal layer. At least a portion of the metal material of the source / drain metal layer is deposited on the hole walls and bottom surfaces of the first and second vias, thereby obtaining the first metal via 16 and the second metal via 17.

[0050] The formed metal layer can be further patterned to form the first source 14 and the first drain 15 of the oxide thin film transistor 1. The first source 14 is electrically connected to the first source doped portion 122 and the bottom gate 11 of the first active layer 12 through the first metal via 16, and the first drain 15 is electrically connected to the first drain doped portion 123 of the first active layer 12 through the second metal via 17.

[0051] In some embodiments, please refer to Figure 5 and Figure 7The display panel 100 provided in this application includes an oxide thin-film transistor 18 along its thickness direction, i.e., the Z-axis direction. The capacitor electrode 18 is disposed on the side of the second gate insulating layer 106 away from the substrate 101. The orthogonal projection of the capacitor electrode 18 onto the substrate 101 coincides with the orthogonal projection of the top gate 13 onto the substrate 101, ensuring that the size of the capacitor electrode 18 can cover the lower top gate 13 and the first channel portion 121 of the first active layer 12. The top gate 13 and the capacitor electrode 18 are isolated by the second gate insulating layer 106 to prevent interlayer short circuits.

[0052] Through the above technical solution, in the display panel 100 provided in this application embodiment, the capacitor electrode 18 and the lower top gate 13 cooperate to form the upper and lower plates of a storage capacitor, so that the top gate 13 can be reused as the lower plate of the storage capacitor. The storage capacitor can be used to store the grayscale voltage signal of the pixel, ensuring that the pixels of the display panel 100 are stable and do not flicker, thus ensuring the display effect of the display panel 100.

[0053] In specific implementation, the metal materials of the top gate 13 and the bottom gate 11 can be the same or different, and the metal materials of the top gate 13 and the capacitor electrode 18 can be the same or different. This application does not make specific limitations in this regard.

[0054] In some embodiments, please refer to Figure 5 and Figure 7 The display panel 100 provided in this application has a second gate insulating layer 106 along the thickness direction of the display panel 100, i.e., the Z-axis direction, including a third sub-layer 1061 and a fourth sub-layer 1062. The third sub-layer 1061 is disposed on the side of the first interlayer dielectric layer 105 away from the bottom gate 11 and covers the first active layer 12. The top gate 13 is disposed on the side of the third sub-layer 1061 away from the first active layer 12, so as to isolate the first active layer 12 and the top gate 13 through the third sub-layer 1061.

[0055] The fourth sub-layer 1062 is disposed on the side of the third sub-layer 1061 away from the first active layer 12 and covers the top gate 13. The capacitor electrode 18 is disposed on the side of the fourth sub-layer 1062 away from the top gate 13, so as to isolate the top gate 13 and the capacitor electrode 18 through the fourth sub-layer 1062.

[0056] The second interlayer dielectric layer 107 is disposed on the side of the fourth sublayer 1062 away from the top gate 13 and covers the capacitor electrode 18, so as to isolate the capacitor electrode 18 from the first source and drain layer through the second interlayer dielectric layer 107.

[0057] Through the above technical solution, the display panel 100 provided in this application embodiment isolates the bottom gate 11, the first active layer 12, the top gate 13, and the capacitor electrode 18 through the stacked first interlayer dielectric layer 105, the third sublayer 1061, the fourth sublayer 1062, and the second interlayer dielectric layer 107, thereby improving the reliability of interlayer insulation, avoiding gate leakage current, significantly improving the electric field control accuracy, and further improving the device electrical performance of the oxide thin film transistor 1.

[0058] In some embodiments, please refer to Figure 5 In the display panel 100 provided in this application, the thin-film transistor group 10 further includes a polysilicon thin-film transistor 2, which is disposed adjacent to the oxide thin-film transistor 1. Each thin-film transistor group 10 may have only one polysilicon thin-film transistor 2, or multiple polysilicon thin-film transistors 2 may be disposed simultaneously. This application does not specifically limit this. In this embodiment, a single polysilicon thin-film transistor 2 is used as an example. It can be used as a switching transistor in the thin-film transistor group 10 and can be used to output on / off control signals to the bottom gate 11 or top gate 13 of the oxide thin-film transistor 1. In specific implementation, the thin-film transistor group 10 consisting of a polysilicon thin-film transistor 2 and an oxide thin-film transistor 1 can be combined with a storage capacitor to form a "2T1C" driving unit that drives the corresponding sub-pixel 110.

[0059] Specifically, along the thickness direction of the display panel 100, i.e., the Z-axis direction, the polysilicon thin-film transistor 2 includes a second active layer 21, a second gate 22, and a second source / drain layer. The second active layer 21 is disposed on the substrate 101, and the second active layer 21 and the oxide thin-film transistor 1 are arranged in a different layer to avoid signal interference between the polysilicon thin-film transistor 2 and the oxide thin-film transistor 1 during signal transmission, thus ensuring the stable electrical performance of the second active layer 21. The second active layer 21 is a polysilicon semiconductor layer. In this embodiment, the material of the second active layer 21 is illustrated using low-temperature polysilicon (LTPS) as an example. When LTPS is used as an active layer material, its core advantage is high carrier mobility (fast movement speed of electrons and holes), which can significantly improve the switching response speed. When used as a switching transistor, it can achieve a higher refresh rate.

[0060] The second gate 22 is disposed on the side of the second active layer 21 away from the substrate 101, and the second gate 22 and the oxide thin film transistor 1 are arranged in different layers to avoid signal interference between the polysilicon thin film transistor 2 and the oxide thin film transistor 1 during signal transmission, thereby ensuring the stable electrical performance of the second gate 22.

[0061] The second source-drain layer is disposed on the side of the second gate 22 away from the second active layer 21, and the second source 23 layer is disposed on the same layer as the first source-drain layer. The second source-drain layer includes a second source 23 and a second drain 24.

[0062] Furthermore, the second active layer 21 includes a second channel portion 211, a second source-end doped portion 212, and a second drain-end doped portion 213. The second channel portion 211 is the core region for carrier (electron or hole) migration in the second active layer 21. Its material can be undoped low-temperature polycrystalline silicon LTPS or a lightly doped material mainly composed of low-temperature polycrystalline silicon LTPS. This application does not make specific limitations on this.

[0063] The second source-end doped portion 212 is disposed on one side of the extension direction of the second channel portion 211 (in this embodiment, the left side of the extension direction of the second channel portion 211 is taken as an example), and is electrically connected to the second source electrode 23 through the third metal via 25.

[0064] The second drain doped portion 213 is disposed on the other side of the extension direction of the second channel portion 211 (taking the right side of the extension direction of the second channel portion 211 as an example in this embodiment), and is electrically connected to the second drain electrode 24 through the fourth metal via 26.

[0065] Specifically, the orthographic projection of the second gate 22 onto the substrate 101 coincides with the orthographic projection of the second channel portion 211 onto the substrate 101. The second source-end doped portion 212 serves as the interface for current injection into the second active layer 21, and is connected to the upper second source 23 via the third metal via 25. The second drain-end doped portion 213 serves as the interface for current output from the second active layer 21, and is connected to the upper second drain 24 via the fourth metal via 26. The second channel portion 211 is the core hub for current regulation, and the carrier concentration in the second channel portion 211 is regulated by the upper second gate 22.

[0066] The second gate 22 can be connected to the scan line in the driving circuit to receive the gating signal; the second source 23 can be connected to the data line in the driving circuit to receive the grayscale voltage signal of the sub-pixel 110; the second drain 24 can be connected to the bottom gate 11 of the oxide thin film transistor 1 as the main control gate, and the second drain 24 is also connected to the signal terminal of the storage capacitor. Correspondingly, the bottom gate 11 of the oxide thin film transistor 1 is also connected to the signal terminal of the storage capacitor to receive the grayscale voltage signal held by the storage capacitor. Through the above technical solution, in the display panel 100 provided in this application embodiment, when the second gate 22 does not receive a gating signal from the scan line, the second channel portion 211 is in a high-resistivity state and there is no carrier migration inside. At this time, the polysilicon thin film transistor 2 will not output a driving signal to the oxide thin film transistor 1, and the sub-pixel 110 does not emit light.

[0067] When the second gate 22 receives a gating signal from the scan line, the second channel 211 is turned on. The data line of the driving circuit outputs the grayscale voltage signal (Vdata) corresponding to the sub-pixel 110 to the second source 23, and outputs it to the bottom gate 11 of the oxide thin film transistor 1 and the storage capacitor through the turned-on second channel 211 and the second drain 24. Since the first source doped portion 122 of the oxide thin film transistor 1 is connected to the bottom gate 11 through the first metal via 16, the potential of the first source 14 is synchronously charged to Vdata along with the bottom gate 11, forming an initial coupling state. Then, the scan line voltage drops to a low level (VGL), the polysilicon thin film transistor 2 used as a switching transistor is turned off, the data line is disconnected from the bottom gate 11, and the storage capacitor plays a role at this time, locking the voltage of the bottom gate 11 and avoiding voltage decay due to leakage current. The first source 14 is coupled to the bottom gate 11 through the first source doped portion 122, ensuring that the potential of the first source 14 remains synchronous and stable with the potential of the bottom gate 11. Then, the positive power supply (VDD) supplies power to the anode 1093 of the corresponding sub-pixel 110 through the first drain 15, and the sub-pixel 110 emits light. The gate-source voltage (Vgs) of the oxide thin film transistor 1 is determined by the difference between the potential of the bottom gate 11 (Vg2) and the potential of the first source 14 (Vs2). During the emission of light by the sub-pixel 110, the potential of the first source 14 (Vs2) will change slightly. At this time, the potential of the bottom gate 11 (Vg2) will change synchronously, which can ensure that the gate-source voltage (Vgs) remains constant. The constant gate-source voltage (Vgs) can ensure the stability of the output current (Ids) of the oxide thin film transistor 1.

[0068] A stable current flows directly through the first drain 15 to the anode 1093 of the sub-pixel 110, enabling the sub-pixel 110 to emit light stably according to the corresponding grayscale, effectively suppressing brightness drift and display unevenness, and further improving the display effect of the display panel 100. In addition, the thin-film transistor group 10 of this application combines the high-speed switching control effect of polysilicon thin-film transistor 2 as a switching transistor and the low-power effect of oxide thin-film transistor 1 as a driving transistor, taking into account the market demand for high pixel density and variable refresh rate.

[0069] In addition, by setting the second source-drain layer and the first source-drain layer in the same layer, the first metal via 16, the second metal via 17, the third metal via 25 and the fourth metal via 26 can be formed by the same etching process, and the first source-drain layer and the second source-drain layer can be formed by the same deposition and etching process, which reduces the process complexity and manufacturing cost of the display panel 100.

[0070] Furthermore, in order to reduce the contact impedance between the second source-end doped portion 212 and the second source electrode 23 and improve signal transmission efficiency, the material of the second source-end doped portion 212 can be a heavily doped material containing low-temperature polycrystalline silicon (LTPS). In specific implementations, atmospheric heat treatment (such as hydrogen atmosphere), ion implantation (such as phosphorus or germanium ions), or plasma treatment can be used to introduce a high concentration of oxygen vacancies or N-type impurities into the left end of the second active layer 21 near the second source electrode 23 to form a stable, heavily doped second source-end doped portion 212.

[0071] Similarly, in order to reduce the contact impedance between the second drain doped portion 213 and the second drain electrode 24 and improve signal transmission efficiency, the material of the second drain doped portion 213 can also be a heavily doped material containing low-temperature polycrystalline silicon (LTPS). In specific implementations, atmospheric heat treatment (such as hydrogen atmosphere), ion implantation (such as phosphorus or germanium ions), or plasma treatment can be used to introduce a high concentration of oxygen vacancies or N-type impurities into the right end of the second active layer 21 near the second drain electrode 24 to form a stable, heavily doped second drain doped portion 213.

[0072] In some embodiments, please refer to Figure 5 In the display panel 100 provided in this application, along the thickness direction of the display panel 100, i.e. the Z-axis direction, the thin film transistor group 10 further includes a first gate insulating layer 104, which is disposed between the substrate 101 and the bottom gate 11.

[0073] Specifically, the first gate insulating layer 104 includes a first sub-layer 1041 and a second sub-layer 1042. The first sub-layer 1041 is disposed on one side of the substrate 101 and covers the second active layer 21. The second gate 22 is disposed on the side of the first sub-layer 1041 away from the second active layer 21, so as to isolate the second active layer 21 and the second gate 22 through the first sub-layer 1041. The second sub-layer 1042 is disposed on the side of the first sub-layer 1041 away from the second active layer 21 and covers the second gate 22. The bottom gate 11 is disposed on the side of the second sub-layer 1042 away from the second gate 22, so as to isolate the second gate 22 and the bottom gate 11 through the second sub-layer 1042.

[0074] Through the above technical solution, the display panel 100 provided in this embodiment of the application arranges the polysilicon thin-film transistor 2 and the oxide thin-film transistor 1 in layers, except for the source and drain layers. The second gate 22 and the second active layer 21 are positioned on the lower side of the oxide thin-film transistor 1. This layered layout eliminates the need to expand the lateral space of the thin-film transistor group 10. Combined with the size optimization of the oxide thin-film transistor 1 in the source signal connection area, it further frees up layout design space, which is beneficial for the high pixel density design of the display panel 100. Furthermore, the first gate insulating layer 104 insulates and isolates the bottom gate 11 of the oxide thin-film transistor 1 from the second gate 22 of the polysilicon thin-film transistor 2, effectively avoiding signal crosstalk between the switching transistor and the driving transistor during operation, and ensuring the stability and reliability of the operation of the polysilicon thin-film transistor 2 and the oxide thin-film transistor 1.

[0075] In some embodiments, please refer to Figure 5 and Figure 7 The display panel 100 provided in this application further includes a planarization layer 108, a light-emitting layer 109, and bridging electrodes 3 along its thickness direction. The planarization layer 108 is disposed on the side of the second interlayer dielectric layer 107 away from the top gate 13 and covers the first source / drain layer and the second source / drain layer. The light-emitting layer 109 is disposed on the side of the planarization layer 108 away from the second interlayer dielectric layer 107, and includes an array of anodes 1093. The bridging electrodes 3 are arrayed within the planarization layer 108, and the bridging electrodes 3 bridge the corresponding first drain 15 and anode 1093.

[0076] Specifically, the planarization layer 108 serves as an auxiliary insulating and supporting structure, further isolating the first source-drain layer, the second source-drain layer, and the upper light-emitting layer 109 to prevent signal crosstalk between the thin-film transistor group 10 and the upper light-emitting layer 109. Furthermore, the planarization layer 108 also smooths the upper interface, providing a supporting foundation for the fabrication of the light-emitting layer 109. Additionally, the bridging electrode 3 is disposed within the planarization layer 108 to prevent it from being exposed to the external environment and subjected to oxidation, corrosion, etc.

[0077] The light-emitting layer 109 includes light-emitting units (not shown in the figure) arranged in an array within the array area 1011. Each light-emitting unit corresponds to a sub-pixel 110 of the display panel 100. The light-emitting unit can be an organic light-emitting diode (OLED). The anode 1093 is the bottom electrode of the light-emitting unit and is connected to the first drain 15 of the oxide thin film transistor 1 below through the bridging electrode 3, serving as an interface for injecting charge carriers (holes) into the light-emitting unit.

[0078] Furthermore, the light-emitting layer 109 also includes a pixel definition layer 1091. The pixel definition layer 1091 is disposed on the side of the planarization layer 108 away from the second interlayer dielectric layer 107 and covers the anode 1093. The pixel definition layer 1091 can be made of an organic insulating material (such as resin). Pixel openings 10911 for defining individual sub-pixels 110 are arrayed on the pixel definition layer 1091. The pixel openings 10911 expose the anode 1093 of the light-emitting unit. The pixel openings 10911 can be precisely aligned with the underlying oxide thin-film transistors 1, ensuring that each sub-pixel 110 emits light independently under the control of the corresponding thin-film transistor group 10. A barrier structure 1092 is provided at the edge of the pixel opening 10911. The barrier structure 1092 defines the light-emitting area of ​​the pixel opening 10911, and the light-emitting unit is located within the space formed by the barrier structure 1092 and the pixel opening 10911.

[0079] Through the above technical solutions, the display panel 100 provided in this embodiment of the application, wherein the oxide thin-film transistor 1 outputs a stable current (Ids) to the anode 1093 of the corresponding light-emitting unit above through the first drain 15 and the bridging electrode 3, so that the light-emitting unit emits light stably, effectively suppressing brightness drift and display unevenness, and ensuring the display effect of the display panel 100. In addition, the thin-film transistor group 10 of this application combines the high-speed switching control effect of the polysilicon thin-film transistor 2 used as a switching transistor and the low power consumption effect of the oxide thin-film transistor 1 used as a driving transistor, taking into account the market demand for high pixel density and variable refresh rate.

[0080] In some embodiments, please refer to Figure 5 and Figure 7 In the display panel 100 provided in this application, the planarization layer 108 and the bridging electrode 3 can be configured as a multi-layer structure. For example, along the thickness direction of the display panel 100, i.e., the Z-axis direction, the bridging electrode 3 includes a first bridging electrode 31 and a second bridging electrode 32, and the planarization layer 108 includes a first planarization layer 1081, a second planarization layer 1082, and a third planarization layer 1083. The first planarization layer 1081 is disposed on the side of the second interlayer dielectric layer 107 away from the fourth sub-layer 1062, and the array of first bridging electrodes 31 is disposed on the side of the first planarization layer 1081 away from the second interlayer dielectric layer 107.

[0081] The second planarization layer 1082 is disposed on the side of the first planarization layer 1081 away from the second interlayer dielectric layer 107 and covers the first bridging electrode 31. The second bridging electrode 32 array is disposed on the side of the second planarization layer 1082 away from the first planarization layer 1081, and the second bridging electrode 32 is precisely aligned with the first bridging electrode 31.

[0082] A third planarization layer 1083 is disposed on the side of the second planarization layer 1082 away from the first planarization layer 1081 and covers the second bridging electrode 32. An array of anodes 1093 is disposed on the third planarization layer 1083, and the anodes 1093 are at least partially aligned with the second bridging electrode 32 and the first bridging electrode 31. A pixel definition layer 1091 is disposed on the side of the third planarization layer 1083 away from the second planarization layer 1082 and covers the anodes 1093.

[0083] Please refer to Figure 7 The first bridging electrode 31 is connected to the lower first drain electrode 15 through the first bridging metal hole 311 penetrating the first planarization layer 1081; the second bridging electrode 32 is connected to the lower first bridging electrode 31 through the second bridging metal hole 321 penetrating the second planarization layer 1082, and the second bridging electrode 32 is connected to the upper anode 1093 through the third bridging metal hole 1094 penetrating the third planarization layer 1083.

[0084] Through the above technical solutions, the display panel 100 provided in this application embodiment has designed the bridging electrode 3 as a multi-layer structure that is precisely aligned in the thickness direction of the display panel 100, which increases the wiring space of the display panel 100 in the planarization layer 108, effectively avoiding problems such as wiring crossover and hole position conflict when wiring in a single layer, and can adapt to the wiring requirements of the display panel 100 with high pixel density.

[0085] In some embodiments, please refer to Figure 5 The display panel 100 provided in this application further includes a barrier layer 102 and a buffer layer 103. The barrier layer 102 is disposed on one side of the substrate 101, the buffer layer 103 is disposed on the side of the barrier layer 102 away from the substrate 101, the second active layer 21 is disposed on the side of the buffer layer 103 away from the barrier layer 102, and the first sub-layer 1041 is disposed on the side of the buffer layer 103 away from the barrier layer 102 and covers the second active layer 21. The barrier layer 102 can prevent impurity ions in the substrate 101 from diffusing upward into the thin-film transistor group 10, preventing impurity ions from affecting the semiconductor material characteristics of the first active layer 12 and the second active layer 21, avoiding interference with the electrical performance of the TFT device, and extending the service life of the TFT device. In specific implementations, the material of the barrier layer 102 can be silicon nitride (SiN). x A composite material of silicon dioxide (SiO2) and barrier layer 102, or the barrier layer 102 may also be silicon nitride (SiN). x A composite layer structure of ) and silicon dioxide (SiO2).

[0086] The buffer layer 103 can further isolate impurity ions from diffusing to the upper layer, and the buffer layer 103 can effectively alleviate the difference in thermal expansion coefficients between the upper structure and the substrate 101, reduce process stress, and provide a uniform interface for the subsequent fabrication of the thin-film transistor group 10. In specific implementation, the material of the buffer layer 103 can be silicon oxide (SiO2) or silicon oxynitride (SiON).

[0087] According to a second aspect of this application, a display device (not shown in the figures) is also provided, which includes the aforementioned display panel 100. This display device possesses all the beneficial effects of the aforementioned display panel 100, which will not be elaborated upon herein.

[0088] The display device may be a wearable device (such as a smart bracelet, smartwatch, virtual reality (VR) device), a mobile phone (such as a smartphone), an e-book, an e-newspaper, a television set, a portable computer, an electronic billboard, an outdoor screen, a foldable and rollable flexible display device, and a lighting device, etc., and this disclosure does not specifically limit it.

[0089] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0090] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0091] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0092] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A thin-film transistor array disposed on the substrate, comprising: An oxide thin-film transistor includes, along the thickness direction of the display panel, a bottom gate, a first active layer above the bottom gate, a top gate above the first active layer, and a first source-drain layer above the top gate, wherein the first source-drain layer includes a first source and a first drain. Wherein, the orthographic projections of the first source electrode, the first active layer, and the bottom gate on the substrate at least partially overlap, and within the overlapping area, the first source electrode is electrically connected to the first active layer and the bottom gate through a first metal via.

2. The display panel according to claim 1, characterized in that, Within the overlapping area, the number of the first metal vias is one.

3. The display panel according to claim 1, characterized in that, The first active layer includes: The first channel section extends along the first direction; The first source-end doped portion is disposed on one side of the extension direction of the first channel portion and is electrically connected to the first source and the bottom gate through the first metal via. The first drain end doped portion is disposed on the other side of the extension direction of the first channel portion and is electrically connected to the first drain electrode through the second metal via.

4. The display panel according to claim 3, characterized in that, Along the thickness direction of the display panel, the thin-film transistor array further includes: A first interlayer dielectric layer is disposed on one side of the substrate and covers the bottom gate, and a first active layer is disposed on the side of the first interlayer dielectric layer away from the bottom gate; A second gate insulating layer is disposed on the side of the first interlayer dielectric layer away from the bottom gate and covers the first active layer; the top gate is disposed within the second gate insulating layer; and / or the top gate is disposed on the side of the second gate insulating layer away from the first active layer. The second interlayer dielectric layer is disposed on the side of the second gate insulating layer away from the first interlayer dielectric layer and covers the top gate; The first source-drain layer is disposed on the side of the second interlayer dielectric layer away from the top gate.

5. The display panel according to claim 4, characterized in that, Along the first direction, the first metal via includes: The first bridging portion extends through the second interlayer dielectric layer, the second gate insulating layer, and the first interlayer dielectric layer along the thickness direction of the display panel and is electrically connected to the bottom gate. The second bridging portion extends through the second interlayer dielectric layer and the second gate insulating layer along the thickness direction of the display panel and is electrically connected to the first source end doped portion of the first active layer. The first bridging portion and the second bridging portion together form the first metal via.

6. The display panel according to claim 4, characterized in that, Along the thickness direction of the display panel, the oxide thin-film transistor further includes: A capacitor electrode is disposed on the side of the second gate insulating layer away from the top gate; the orthogonal projection of the capacitor electrode on the substrate coincides with the orthogonal projection of the top gate on the substrate.

7. The display panel according to claim 6, characterized in that, Along the thickness direction of the display panel, the second gate insulating layer includes: The third sublayer is disposed on the side of the first interlayer dielectric layer away from the bottom gate and covers the first active layer, and the top gate is disposed on the side of the third sublayer away from the first active layer; The fourth sub-layer is disposed on the side of the third sub-layer away from the first active layer and covers the top gate, and the capacitor electrode is disposed on the side of the fourth sub-layer away from the top gate; The second interlayer dielectric layer is disposed on the side of the fourth sublayer away from the top gate and covers the capacitor electrode.

8. The display panel according to claim 4, characterized in that, The display panel also includes: A planarization layer is disposed on the side of the second interlayer dielectric layer away from the top gate and covers the first source-drain layer; A light-emitting layer is disposed on the side of the planar layer away from the second interlayer dielectric layer, and the light-emitting layer includes an array of anodes; A bridging electrode is arrayed within the planarization layer, and the bridging electrode bridges the corresponding first drain and the anode.

9. The display panel according to claim 1, characterized in that, The thin-film transistor array further includes: A polycrystalline silicon thin-film transistor, disposed adjacent to the oxide thin-film transistor, includes, along the thickness direction of the display panel: The second active layer is disposed on the substrate and is arranged in a different layer from the oxide thin film transistor; The second gate is disposed on the side of the second active layer away from the substrate and is arranged in a different layer from the oxide thin film transistor; The second source-drain layer is disposed on the side of the second gate away from the second active layer and is disposed in the same layer as the first source-drain layer. The second source-drain layer includes a second source and a second drain.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

Images