Array substrate, method for preparing same, and display device

Abstract

Embodiments of the present application provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a substrate, a metal oxide semiconductor layer, and a first gate metal layer stacked along the thickness direction of the array substrate. An oxide thin film transistor is provided in the array substrate. The metal oxide semiconductor layer is used to form an active layer of the oxide thin film transistor, and the first gate metal layer is used to form a first gate of the oxide thin film transistor. The array substrate further includes a first hydrogen absorption layer. Along the thickness direction of the array substrate, the first hydrogen absorption layer is located between the first gate metal layer and the metal oxide semiconductor layer, and / or the first hydrogen absorption layer is located on a side of the first gate metal layer facing away from the metal oxide semiconductor layer. Along the thickness direction of the array substrate, a positive projection of the first hydrogen absorption layer on the substrate at least partially overlaps a positive projection of the first gate of the oxide thin film transistor on the substrate. Embodiments of the present application can improve the reliability of the oxide thin film transistor and the array substrate.

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to an array substrate, a preparation method thereof, and a display device. Background Art

[0002] A pixel driving circuit is provided in the array substrate, and the pixel driving circuit can be used to drive a light-emitting element to emit light. At least some thin film transistors (TFTs) in the pixel driving circuit can be oxide thin film transistors. Oxide thin film transistors have advantages such as small leakage current and good uniformity, which can keep the display panel in good display effect. Therefore, oxide thin film transistors are applied to wearable device products.

[0003] However, the electrical properties and reliability of oxide thin film transistors are unstable, which easily leads to the failure of the array substrate. Summary of the Invention

[0004] Embodiments of this application provide an array substrate, a preparation method thereof, and a display device, which can solve the problem of unstable electrical properties and reliability of oxide thin film transistors.

[0005] In a first aspect, embodiments of this application provide an array substrate. The array substrate includes a substrate, a metal oxide semiconductor layer, and a first gate metal layer stacked along the thickness direction of the array substrate. An oxide thin film transistor is provided in the array substrate. The metal oxide semiconductor layer is used to form an active layer of the oxide thin film transistor, and the first gate metal layer is used to form a first gate of the oxide thin film transistor. The array substrate further includes a first hydrogen-absorbing layer. Along the thickness direction of the array substrate, the first hydrogen-absorbing layer is located between the first gate metal layer and the metal oxide semiconductor layer, and / or the first hydrogen-absorbing layer is located on a side of the first gate metal layer facing away from the metal oxide semiconductor layer. Along the thickness direction of the array substrate, a positive projection of the first hydrogen-absorbing layer on the substrate at least partially overlaps with a positive projection of the first gate of the oxide thin film transistor on the substrate.

[0006] According to an implementation manner of the first aspect of this application, the array substrate further includes: a second gate metal layer. Along the thickness direction of the array substrate, the second gate metal layer is located between the substrate and the metal oxide semiconductor layer, and the second gate metal layer is used to form a second gate of the oxide thin film transistor. A second hydrogen-absorbing layer. Along the thickness direction of the array substrate, the second hydrogen-absorbing layer is located between the second gate metal layer and the substrate, and / or between the second gate metal layer and the metal oxide semiconductor layer, and a positive projection of the second hydrogen-absorbing layer on the substrate at least partially overlaps with a positive projection of the second gate of the oxide thin film transistor on the substrate.

[0007] In this way, on the one hand, by providing a second hydrogen-absorbing layer between the second gate metal layer and the substrate or between the second gate metal layer and the metal oxide semiconductor layer, hydrogen diffused in the film layer below the metal oxide semiconductor layer can be adsorbed, effectively preventing hydrogen in the film layer below the metal oxide semiconductor layer from diffusing into the metal oxide semiconductor layer, thereby further improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate. On the other hand, since the second hydrogen-absorbing layer does not reuse the second gate of the oxide thin film transistor, the performance change of the second gate of the oxide thin film transistor caused by hydrogen adsorption can be avoided, thereby ensuring the stable performance of the oxide thin film transistor, which is beneficial to ensuring the stability of the circuit in the array substrate.

[0008] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes a buffer layer. Along the thickness direction of the array substrate, the buffer layer is located between the substrate and the second gate metal layer, the second hydrogen-absorbing layer is located in the buffer layer, and the second hydrogen-absorbing layer is covered by the buffer layer.

[0009] In this way, by disposing the second hydrogen-absorbing layer in the buffer layer, hydrogen generated in the buffer layer can be preferably adsorbed, blocking the diffusion of hydrogen from the source and preventing hydrogen generated in the buffer layer from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate.

[0010] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes a buffer layer. Along the thickness direction of the array substrate, the buffer layer is located between the substrate and the metal oxide semiconductor layer, both the second gate metal layer and the second hydrogen-absorbing layer are located in the buffer layer, and both the second gate metal layer and the second hydrogen-absorbing layer are covered by the buffer layer.

[0011] In this way, by disposing the second hydrogen-absorbing layer in the buffer layer, hydrogen generated in the buffer layer can be preferably adsorbed, blocking the diffusion of hydrogen from the source and preventing hydrogen generated in the buffer layer from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate.

[0012] According to any of the foregoing embodiments of the first aspect of the present application, the first hydrogen-absorbing layer and the first gate metal layer are adjacent film layers, and the orthographic projection of the first hydrogen-absorbing layer on the substrate overlaps with the orthographic projection of the first gate of the oxide thin film transistor on the substrate.

[0013] In this way, since the pattern shapes of the first hydrogen-absorbing layer and the first gate metal layer are the same or similar, and the first hydrogen-absorbing layer and the first gate metal layer are adjacent film layers, the first hydrogen-absorbing layer and the first gate metal layer can be fabricated through the same mask, without the need to additionally add a new mask, which is beneficial to simplifying the production process and reducing the production cost.

[0014] According to any of the foregoing embodiments of the first aspect of the present application, the second hydrogen absorption layer and the second gate metal layer are adjacent film layers, and the orthographic projection of the second hydrogen absorption layer on the substrate overlaps with the orthographic projection of the second gate of the oxide thin film transistor on the substrate.

[0015] In this way, since the pattern shapes of the second hydrogen absorption layer and the second gate metal layer are the same or similar, and the second hydrogen absorption layer and the second gate metal layer are adjacent film layers, the second hydrogen absorption layer and the second gate metal layer can be fabricated through the same mask plate, without the need to additionally add a new mask plate, which is beneficial to simplifying the production process and reducing the production cost.

[0016] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate is provided with a first electrode of the light-emitting element, and the first electrode is electrically connected to the oxide thin film transistor through a via hole; the first electrode includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked, and in the thickness direction of the array substrate, the third conductive layer is located on the side of the second conductive layer facing the substrate; the first hydrogen absorption layer multiplexes the third conductive layer.

[0017] In this way, by multiplexing the third conductive layer with the first hydrogen absorption layer, on the basis of improving the electrical properties and reliability of the oxide thin film transistor, the production process of the array substrate can be simplified, that is, there is no need to additionally add a process for setting the first hydrogen absorption layer, and only the material of the original third conductive layer needs to be replaced with a hydrogen-absorbing material, which is beneficial to reducing the thickness of the array substrate and the production cost.

[0018] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes: a first electrode of the light-emitting element, in the thickness direction of the array substrate, the first electrode is located on the side of the first gate metal layer away from the substrate; a source-drain metal layer, in the thickness direction of the array substrate, the source-drain metal layer is located between the first gate metal layer and the first electrode, and the source-drain metal layer is used to form the source and drain of the oxide thin film transistor, and the first electrode is electrically connected to the source or drain of the oxide thin film transistor through a via hole; a target metal layer, in the thickness direction of the array substrate, the target metal layer is located between the source-drain metal layer and the first electrode; the target metal layer includes at least one sub-metal layer, and the first hydrogen absorption layer multiplexes one sub-metal layer.

[0019] In this way, by multiplexing one sub-metal layer in the target metal layer with the first hydrogen absorption layer, on the basis of improving the electrical properties and reliability of the oxide thin film transistor, the production process of the array substrate can be simplified, that is, there is no need to additionally add a process for setting the first hydrogen absorption layer, and only the material of one sub-metal layer in the original target metal layer needs to be replaced with a hydrogen-absorbing material, which is beneficial to reducing the thickness of the array substrate and the production cost.

[0020] According to any of the foregoing embodiments of the first aspect of the present application, the target metal layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer that are sequentially stacked. Along the thickness direction of the array substrate, the third sub-metal layer is located on the side of the second sub-metal layer facing the substrate, and the first hydrogen absorption layer multiplexes the third sub-metal layer.

[0021] According to any of the foregoing embodiments of the first aspect of the present application, the first hydrogen absorption layer includes a plurality of hydrogen absorption units arranged at intervals, and each hydrogen absorption unit corresponds to an oxide thin film transistor. Along the thickness direction of the array substrate, the orthographic projection of the hydrogen absorption unit on the substrate covers the orthographic projection of the oxide thin film transistor on the substrate.

[0022] In this way, a corresponding hydrogen absorption unit is provided for each oxide thin film transistor. Since the hydrogen absorption unit completely blocks the oxide thin film transistor, hydrogen can be effectively prevented from entering the channel region of the oxide thin film transistor through gaps or unblocked areas, and the channel region of the oxide thin film transistor can be better protected from the influence of hydrogen.

[0023] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes: an interlayer dielectric layer. Along the thickness direction of the array substrate, the interlayer dielectric layer is located on the side of the first gate metal layer away from the metal oxide semiconductor layer and covers the first gate metal layer; a source-drain metal layer. Along the thickness direction of the array substrate, the source-drain metal layer is located on the side of the interlayer dielectric layer away from the first gate metal layer, and the source-drain metal layer is used to form the source and drain of the oxide thin film transistor; a source-drain insulating layer. Along the thickness direction of the array substrate, the source-drain insulating layer is located on the side of the source-drain metal layer away from the interlayer dielectric layer and covers the source-drain metal layer.

[0024] According to any of the foregoing embodiments of the first aspect of the present application, the material of the source-drain insulating layer includes silicon nitride.

[0025] In this way, by preparing the source-drain insulating layer with silicon nitride, since the compactness of silicon nitride is good, hydrogen in the film layer above the source-drain insulating layer can be effectively blocked from diffusing to the metal oxide semiconductor layer below the source-drain insulating layer, further improving the electrical properties and reliability of the oxide thin film transistor.

[0026] According to any of the foregoing embodiments of the first aspect of the present application, the interlayer dielectric layer includes at least two sub-interlayer dielectric layers stacked, and among them, the material of at least one sub-interlayer dielectric layer includes silicon nitride.

[0027] In this way, by preparing the sub-interlayer dielectric layer with silicon nitride, since the compactness of silicon nitride is good, hydrogen in the film layer above the sub-interlayer dielectric layer can be effectively blocked from diffusing to the metal oxide semiconductor layer below the sub-interlayer dielectric layer, further improving the electrical properties and reliability of the oxide thin film transistor.

[0028] According to any one of the foregoing embodiments of the first aspect of the present application, at least one of the first gate metal layer and the second gate metal layer is a stacked structure of titanium and molybdenum.

[0029] In this way, since titanium is extremely easy to react with hydrogen when heated, at least one of the first gate metal layer and the second gate metal layer adopts a stacked structure of titanium and molybdenum, which can further adsorb hydrogen, further prevent hydrogen from diffusing into the metal oxide semiconductor layer, and improve the electrical properties and reliability of the oxide thin film transistor.

[0030] According to any one of the foregoing embodiments of the first aspect of the present application, the material of the first hydrogen absorption layer includes a metal oxide. During the formation of the first hydrogen absorption layer, the proportion of oxygen in the introduced gas is greater than 50%.

[0031] In this way, by making the proportion of oxygen in the introduced gas greater than 50% during the formation of the first hydrogen absorption layer, the oxygen vacancies in the prepared first hydrogen absorption layer can be lower, and the number of carriers can be less. Subsequently, hydrogen ions can be easily captured, hydrogen can be better adsorbed, and the hydrogen adsorption capacity can also be increased.

[0032] According to any one of the foregoing embodiments of the first aspect of the present application, the material of the second hydrogen absorption layer includes a metal oxide. During the formation of the second hydrogen absorption layer, the proportion of oxygen in the introduced gas is greater than 50%.

[0033] In this way, by making the proportion of oxygen in the introduced gas greater than 50% during the formation of the second hydrogen absorption layer, the oxygen vacancies in the prepared second hydrogen absorption layer can be lower, and the number of carriers can be less. Subsequently, hydrogen ions can be easily captured, hydrogen can be better adsorbed, and the hydrogen adsorption capacity can also be increased.

[0034] In a second aspect, an embodiment of the present application provides a method for manufacturing an array substrate. The array substrate includes the array substrate provided in the first aspect. The manufacturing method includes: providing a substrate; sequentially forming a metal oxide semiconductor layer and a first gate metal layer on one side of the substrate. The metal oxide semiconductor layer is used to form the active layer of the oxide thin film transistor, and the first gate metal layer is used to form the first gate of the oxide thin film transistor; before forming the first gate metal layer, a first hydrogen absorption layer is formed on the side of the metal oxide semiconductor layer away from the substrate, and / or after forming the first gate metal layer, a first hydrogen absorption layer is formed on the side of the first gate metal layer away from the metal oxide semiconductor layer; along the thickness direction of the array substrate, the orthographic projection of the first hydrogen absorption layer on the substrate at least partially overlaps with the orthographic projection of the first gate of the oxide thin film transistor on the substrate.

[0035] In a third aspect, an embodiment of the present application provides a display device, and the display device includes the array substrate provided in the first aspect.

[0036] On the one hand, for the array substrate, its preparation method, and the display device according to the embodiments of the present application, by providing a first hydrogen-absorbing layer between the first gate metal layer and the metal oxide semiconductor layer and / or on the side of the first gate metal layer facing away from the metal oxide semiconductor layer, the hydrogen diffused in the film layer above the metal oxide semiconductor layer can be adsorbed, effectively preventing the hydrogen in the film layer above the metal oxide semiconductor layer from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin-film transistor, and further improving the reliability of the array substrate. On the other hand, since the first hydrogen-absorbing layer does not reuse the first gate of the oxide thin-film transistor, the performance change of the first gate of the oxide thin-film transistor caused by hydrogen adsorption can be avoided, and thus the performance of the oxide thin-film transistor can be ensured to be stable, which is beneficial to ensuring the stability of the circuit in the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0038] Figure 1 FIG. is a partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0039] Figure 2 FIG. is another partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0040] Figure 3 FIG. is yet another partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0041] Figure 4 FIG. is yet another partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0042] Figure 5 FIG. is yet another partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0043] Figure 6 FIG. is yet another partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0044] Figure 7 FIG. is yet another partial cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application;

[0045] Figure 8 FIG. is a top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0046] Figure 9Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application;

[0047] Figure 10 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application;

[0048] Figure 11 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application;

[0049] Figure 12 A flowchart of a preparation method of the array substrate provided by the embodiment of the present application;

[0050] Figure 13 A structural schematic diagram of the display device provided by the embodiment of the present application. Detailed implementation manners

[0051] The features and exemplary embodiments of various aspects of the present application will be described in detail below. For the purpose of making the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than limiting the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0052] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0053] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0054] It should be noted that the transistor in the embodiments of the present application can be an N-type transistor, but is not limited to an N-type transistor and can also be replaced with a P-type transistor. For an N-type transistor, the conduction level is a high level and the cut-off level is a low level. That is, when the gate of the N-type transistor is at a high level, conduction occurs between its first pole and second pole; when the gate of the N-type transistor is at a low level, the conduction between its first pole and second pole is turned off. For a P-type transistor, the conduction level is a low level and the cut-off level is a high level. That is, when the control electrode of the P-type transistor is at a low level, conduction occurs between its first pole and second pole; when the control terminal of the P-type transistor is at a high level, the conduction between its first pole and second pole is turned off. In specific implementation, the gate of each of the above transistors serves as its control electrode. And, according to the signal of the gate of each transistor and its type, its first pole can be used as the source electrode and the second pole as the drain electrode, or its first pole can be used as the drain electrode and the second pole as the source electrode, without distinction here. In addition, the conduction level and cut-off level in the embodiments of the present invention are both general references. The conduction level refers to any level that can make the transistor conduct, and the cut-off level refers to any level that can make the transistor cut off / turn off.

[0055] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or can also mean that two components are electrically connected via one or more other components.

[0056] Without departing from the spirit or scope of the present application, various modifications and variations can be made to the present application, which will be obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0057] Before elaborating on the technical solutions provided in the embodiments of the present application, for the convenience of understanding the embodiments of the present application, the present application first specifically describes the problems existing in the prior art:

[0058] As mentioned above, oxide thin-film transistors have advantages such as small leakage current and good uniformity, and can keep the display panel in a good display effect. Therefore, oxide thin-film transistors are applied to wearable device products. However, through long-term research by the inventors of the present application, it is found that oxide thin-film transistors are sensitive to water, oxygen, and hydrogen. Specifically, when the hydrogen content in the active layer (or channel region) of the oxide thin-film transistor is relatively high, it will cause the active layer (or channel region) of the oxide thin-film transistor to exhibit a conductorization effect, thereby resulting in poor electrical properties and reliability of the oxide thin-film transistor.

[0059] Some film layers with a relatively high hydrogen content are provided in the array substrate. For example, a film layer prepared using silicon nitride (where a large number of hydrogen bonds are contained in the silicon nitride) has hydrogen in these film layers that is extremely likely to diffuse into the active layer (or channel region) of the oxide thin film transistor in the form of hydrogen ions during some high-temperature processes. As a result, the active layer (or channel region) of the oxide thin film transistor exhibits a conduction effect, causing the threshold voltage Vth of the oxide thin film transistor to be negatively biased, and further resulting in poor electrical properties and reliability of the oxide thin film transistor.

[0060] In view of the above research findings of the inventors, the embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display device, which can solve the technical problem of unstable electrical properties and reliability of the oxide thin film transistors in the array substrate in the related art.

[0061] The technical concept of the embodiments of the present application is as follows: By providing a first hydrogen-absorbing layer between the first gate metal layer and the metal oxide semiconductor layer, and / or on a side of the first gate metal layer facing away from the metal oxide semiconductor layer, the hydrogen diffused from the film layer above the metal oxide semiconductor layer can be adsorbed, effectively preventing the hydrogen in the film layer above the metal oxide semiconductor layer from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate and avoiding the failure of the array substrate.

[0062] First, the array substrate provided by the embodiments of the present application will be introduced below.

[0063] Figure 1 FIG. is a partial cross-sectional schematic diagram of the array substrate provided by the embodiments of the present application. As Figure 1 shown, the array substrate 10 provided by the embodiments of the present application may include a substrate 101, a metal oxide semiconductor layer 102, and a first gate metal layer 103 stacked along the thickness direction Z of the array substrate. It should be noted that other film layers may also be included between the substrate 101 and the metal oxide semiconductor layer 102. Similarly, other film layers may also be included between the metal oxide semiconductor layer 102 and the first gate metal layer 103, and the embodiments of the present application do not limit this. The substrate 101 mainly serves as a support. Exemplarily, the substrate 101 may be a rigid substrate made of materials such as glass, or a flexible substrate made of materials such as polyethylene terephthalate (PET), polyarylate, or polyimide (PI).

[0064] It can be understood that an oxide thin-film transistor T is provided in the array substrate 10, and the metal oxide semiconductor layer 102 can be used to form the active layer of the oxide thin-film transistor T. Among them, the active layer of the oxide thin-film transistor T can include a channel region b and a source region s and a drain region d respectively located on opposite sides of the channel region b. The source region s and the drain region d can be obtained by ion doping of a semiconductor material, and the channel region b retains semiconductor characteristics. Exemplarily, the material of the metal oxide semiconductor layer 102 includes but is not limited to indium gallium zinc oxide (IGZO). The first gate metal layer 103 can be used to form the first gate g1 of the oxide thin-film transistor T. Exemplarily, the first gate metal layer 103 includes but is not limited to a single layer or multiple layers composed of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (MO), or chromium (Cr).

[0065] In the embodiment of the present application, the array substrate 10 may further include a first hydrogen absorption layer H1, and the material of the first hydrogen absorption layer H1 can be a hydrogen absorption material. Exemplarily, the material of the first hydrogen absorption layer H1 includes but is not limited to metal oxides such as indium gallium zinc oxide IGZO, indium tin oxide ITO, or indium tin zinc oxide ITZO.

[0066] As Figure 1 shown, along the thickness direction Z of the array substrate, the first hydrogen absorption layer H1 can be located between the first gate metal layer 103 and the metal oxide semiconductor layer 102, so as to adsorb the hydrogen diffused in the film layer (such as the encapsulation layer) above the metal oxide semiconductor layer 102, effectively preventing the hydrogen in the film layer above the metal oxide semiconductor layer 102 from diffusing into the metal oxide semiconductor layer 102. Figure 2 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 2 shown, the first hydrogen absorption layer H1 can also be located on the side of the first gate metal layer 103 away from the metal oxide semiconductor layer 102, and can also adsorb the hydrogen diffused in the film layer (such as the encapsulation layer) above the metal oxide semiconductor layer 102, effectively preventing the hydrogen in the film layer above the metal oxide semiconductor layer 102 from diffusing into the metal oxide semiconductor layer 102.

[0067] It can be understood that the first hydrogen absorption layer H1 can be located both between the first gate metal layer 103 and the metal oxide semiconductor layer 102 and on the side of the first gate metal layer 103 away from the metal oxide semiconductor layer 102 at the same time.

[0068] Continue to refer to Figure 1 Or Figure 2As shown, along the thickness direction Z of the array substrate, the orthographic projection of the first hydrogen absorption layer H1 on the substrate 101 may at least partially overlap with the orthographic projection of the first gate g1 of the oxide thin film transistor T on the substrate 101. Since the orthographic projection of the first gate g1 of the oxide thin film transistor T on the substrate 101 overlaps with the orthographic projection of the channel region b of the oxide thin film transistor T on the substrate 101, when the orthographic projection of the first hydrogen absorption layer H1 at least partially overlaps with the orthographic projection of the first gate g1 (or the channel region b) of the oxide thin film transistor T, the first hydrogen absorption layer H1 can block the path of hydrogen diffusion to the channel region b, adsorb hydrogen well, and effectively prevent hydrogen in the film layer above the metal oxide semiconductor layer 102 from diffusing into the channel region b.

[0069] For the array substrate according to the embodiment of the present application, on the one hand, by providing the first hydrogen absorption layer between the first gate metal layer and the metal oxide semiconductor layer and / or on the side of the first gate metal layer facing away from the metal oxide semiconductor layer, the hydrogen diffused in the film layer above the metal oxide semiconductor layer can be adsorbed, effectively preventing the hydrogen in the film layer above the metal oxide semiconductor layer from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate. On the other hand, since the first hydrogen absorption layer does not reuse the first gate of the oxide thin film transistor, the performance change of the first gate of the oxide thin film transistor caused by hydrogen adsorption can be avoided, and thus the performance of the oxide thin film transistor can be ensured to be stable, which is beneficial to ensuring the stability of the circuit in the array substrate.

[0070] Figure 3 is another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 3 shown, according to some embodiments of the present application, optionally, the array substrate 10 may further include a second gate metal layer 301 and a second hydrogen absorption layer H2. Along the thickness direction Z of the array substrate, the second gate metal layer 301 may be located between the substrate 101 and the metal oxide semiconductor layer 102, and the second gate metal layer 301 may be used to form the second gate g2 of the oxide thin film transistor T. That is, the oxide thin film transistor T may be a double-gate structure, the first gate g1 may be the top gate of the oxide thin film transistor T, and the second gate g2 may be the bottom gate of the oxide thin film transistor T. Exemplarily, the second gate metal layer 301 includes but is not limited to a single layer or multiple layers composed of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (MO), or chromium (Cr). The material of the second hydrogen absorption layer H2 may be a hydrogen absorption material. Exemplarily, the material of the second hydrogen absorption layer H2 includes but is not limited to metal oxides such as indium gallium zinc oxide IGZO, indium tin oxide ITO, or indium tin zinc oxide ITZO.

[0071] AsFigure 3 As shown, along the thickness direction Z of the array substrate, the second hydrogen-absorbing layer H2 can be located between the second gate metal layer 301 and the substrate 101, that is, below the second gate metal layer 301, so as to adsorb hydrogen diffused in the film layer (such as the buffer layer) below the metal oxide semiconductor layer 102, effectively preventing hydrogen in the film layer below the metal oxide semiconductor layer 102 from diffusing into the metal oxide semiconductor layer 102. Of course, in other embodiments, the second hydrogen-absorbing layer H2 can also be located between the second gate metal layer 301 and the metal oxide semiconductor layer 102, that is, above the second gate metal layer 301, and can also adsorb hydrogen diffused in the film layer (such as the buffer layer) below the metal oxide semiconductor layer 102, effectively preventing hydrogen in the film layer below the metal oxide semiconductor layer 102 from diffusing into the metal oxide semiconductor layer 102.

[0072] It can be understood that the second hydrogen-absorbing layer H2 can be located between the second gate metal layer 301 and the substrate 101 and between the second gate metal layer 301 and the metal oxide semiconductor layer 102 at the same time.

[0073] Continue to refer to Figure 3 , along the thickness direction Z of the array substrate, the orthographic projection of the second hydrogen-absorbing layer H2 on the substrate 101 can at least partially overlap with the orthographic projection of the second gate g2 of the oxide thin film transistor T on the substrate 101. Since the orthographic projection of the second gate g2 of the oxide thin film transistor T on the substrate 101 overlaps with the orthographic projection of the channel region b of the oxide thin film transistor T on the substrate 101, when the orthographic projection of the second hydrogen-absorbing layer H2 at least partially overlaps with the orthographic projection of the second gate g2 (or the channel region b) of the oxide thin film transistor T, the second hydrogen-absorbing layer H2 can block the path of hydrogen diffusion to the channel region b, preferably adsorb hydrogen, and effectively prevent hydrogen in the film layer below the metal oxide semiconductor layer 102 from diffusing into the channel region b.

[0074] In this way, on the one hand, by providing the second hydrogen-absorbing layer between the second gate metal layer and the substrate, and / or between the second gate metal layer and the metal oxide semiconductor layer, hydrogen diffused in the film layer below the metal oxide semiconductor layer can be adsorbed, effectively preventing hydrogen in the film layer below the metal oxide semiconductor layer from diffusing into the metal oxide semiconductor layer, thereby further improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate; on the other hand, since the second hydrogen-absorbing layer does not reuse the second gate of the oxide thin film transistor, the performance change of the second gate of the oxide thin film transistor caused by hydrogen adsorption can be avoided, and thus the performance stability of the oxide thin film transistor can be ensured, which is beneficial to ensuring the stability of the circuit in the array substrate.

[0075] Figure 4Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 4 shown, different from the embodiment shown in Figure 3 , according to some other embodiments of the present application, optionally, the array substrate 10 may further include a buffer layer 401. Along the thickness direction Z of the array substrate, the buffer layer 401 may be located between the substrate 101 and the second gate metal layer 301. Among them, the buffer layer 401 may include a single layer or multiple layers, and the embodiments of the present application do not limit this. The second hydrogen absorption layer H2 may be located in the buffer layer 401, and the second hydrogen absorption layer H2 may be covered by the buffer layer 401. For example, in some examples, the buffer layer 401 may include a stacked first buffer layer 401a and a second buffer layer 401b. The material of the first buffer layer 401a may be silicon nitride, and the material of the second buffer layer 401b may be silicon oxide. The second hydrogen absorption layer H2 may be located in the first buffer layer 401a, and the second hydrogen absorption layer H2 may be covered by the first buffer layer 401a.

[0076] Since the material of the buffer layer 401 contains silicon nitride, during some high-temperature processes, the buffer layer 401 will release hydrogen when heated.

[0077] In this way, by arranging the second hydrogen absorption layer in the buffer layer, the hydrogen generated in the buffer layer can be preferably adsorbed, blocking the diffusion of hydrogen from the source and avoiding the hydrogen generated in the buffer layer from diffusing to the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate.

[0078] Figure 5 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 5 shown, different from the embodiment shown in Figure 4 , according to some other embodiments of the present application, optionally, the buffer layer 401 may cover the second gate metal layer 301 and the second hydrogen absorption layer at the same time.

[0079] Specifically, along the thickness direction Z of the array substrate, the buffer layer 401 may be located between the substrate 101 and the metal oxide semiconductor layer 102. The second gate metal layer 301 and the second hydrogen absorption layer H2 may both be located in the buffer layer 401, and the second gate metal layer 301 and the second hydrogen absorption layer H2 may both be covered by the buffer layer 401. For example, in some examples, the buffer layer 401 may include a stacked first buffer layer 401a and a second buffer layer 401b. The material of the first buffer layer 401a may be silicon nitride, and the material of the second buffer layer 401b may be silicon oxide. The second gate metal layer 301 and the second hydrogen absorption layer H2 may both be located in the first buffer layer 401a, and the second gate metal layer 301 and the second hydrogen absorption layer H2 may both be covered by the first buffer layer 401a.

[0080] In this way, by disposing the second hydrogen absorption layer in the buffer layer, the hydrogen generated in the buffer layer can be preferably adsorbed, the diffusion of hydrogen can be blocked from the source, and the hydrogen generated in the buffer layer can be prevented from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate.

[0081] Continue to refer to Figure 1 Or Figure 2 As shown, according to some embodiments of the present application, optionally, the first hydrogen absorption layer H1 and the first gate metal layer 103 may be adjacent film layers. For example, the first hydrogen absorption layer H1 may be located above the first gate metal layer 103 (i.e., on the side away from the substrate 101) and adjacent to the first gate metal layer 103. Again, for example, the first hydrogen absorption layer H1 may also be located below the first gate metal layer 103 (i.e., on the side close to the substrate 101) and adjacent to the first gate metal layer 103. The orthographic projection of the first hydrogen absorption layer H1 on the substrate 101 may overlap with the orthographic projection of the first gate g1 of the oxide thin film transistor T on the substrate 101.

[0082] In this way, since the first hydrogen absorption layer and the first gate metal layer have the same pattern shape and the first hydrogen absorption layer and the first gate metal layer are adjacent film layers, the first hydrogen absorption layer and the first gate metal layer can be prepared through the same mask plate without additionally adding a new mask plate, which is beneficial to simplifying the production process and reducing the production cost. For example, in some examples, the first hydrogen absorption layer can be realized only by adding a wet etching process (i.e., a chemical etching process) without additionally adding a new mask plate.

[0083] Continue to refer to Figure 3 As shown, according to some embodiments of the present application, optionally, the second hydrogen absorption layer H2 and the second gate metal layer 301 may be adjacent film layers. For example, the second hydrogen absorption layer H2 may be located above the second gate metal layer 301 (i.e., on the side away from the substrate 101) and adjacent to the second gate metal layer 301. Again, for example, the second hydrogen absorption layer H2 may also be located below the second gate metal layer 301 (i.e., on the side close to the substrate 101) and adjacent to the second gate metal layer 301. The orthographic projection of the second hydrogen absorption layer H2 on the substrate 101 may overlap with the orthographic projection of the second gate g2 of the oxide thin film transistor T on the substrate 101.

[0084] In this way, since the second hydrogen-absorbing layer and the second gate metal layer have the same pattern shape and are adjacent film layers, the second hydrogen-absorbing layer and the second gate metal layer can be fabricated using the same mask, eliminating the need for an additional new mask. This simplifies the production process and reduces production costs. For example, in some embodiments, the second hydrogen-absorbing layer can be achieved merely by adding a wet etching process (i.e., a chemical etching process) without the need for an additional new mask.

[0085] Figure 6 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 6 shown, according to some embodiments of the present application, optionally, the array substrate 10 is provided with a first electrode RE of the light-emitting element. Among them, the first electrode RE of the light-emitting element can be the anode of the light-emitting element. The first electrode RE is electrically connected to the oxide thin-film transistor T through a via hole. It should be noted that when there are multiple oxide thin-film transistors T in the pixel driving circuit, the first electrode RE can be electrically connected to only one oxide thin-film transistor T in the pixel driving circuit through a via hole. For example, when the pixel driving circuit is a 7T1C pixel driving circuit, the first electrode RE can be electrically connected to only one oxide thin-film transistor T in the 7T1C pixel driving circuit through a via hole.

[0086] Continue to refer to Figure 6 , the first electrode RE may include a first conductive layer 601, a second conductive layer 602, and a third conductive layer 603 that are sequentially stacked. Along the thickness direction Z of the array substrate, the third conductive layer 603 is located on the side of the second conductive layer 602 facing the substrate 101. The first hydrogen-absorbing layer H1 can reuse the third conductive layer 603. For example, in some embodiments, the material of the original third conductive layer 603 can be replaced with the material used to prepare the first hydrogen-absorbing layer H1, so that the third conductive layer 603 has the property of adsorbing hydrogen.

[0087] For example, the material of the first conductive layer 601 is ITO, the material of the second conductive layer 602 is silver (Ag), and the material of the original third conductive layer 603 is ITO. Then, the material of the third conductive layer 603 can be replaced from ITO to IGZO, so that the third conductive layer 603 has better hydrogen adsorption performance.

[0088] In this way, by reusing the third conductive layer for the first hydrogen-absorbing layer, on the basis of improving the electrical properties and reliability of the oxide thin-film transistor, the production process of the array substrate can be simplified, that is, there is no need to additionally add a process for setting the first hydrogen-absorbing layer, and only the material of the original third conductive layer needs to be replaced with a hydrogen-absorbing material, which is beneficial to reducing the thickness of the array substrate and lowering the production cost.

[0089] It should be noted that in some embodiments, on the basis that a first hydrogen absorption layer H1 can be disposed between the first gate metal layer 103 and the metal oxide semiconductor layer 102, and / or on the side of the first gate metal layer 103 away from the metal oxide semiconductor layer 102, the material of the third conductive layer 603 can be replaced with the same material as the first hydrogen absorption layer H1 (such as IGZO). In this way, not only can the first hydrogen absorption layer H1 adsorb hydrogen, but also the third conductive layer 603 can adsorb hydrogen, thereby better improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate.

[0090] Figure 7 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 7 shown, according to some embodiments of the present application, optionally, along the thickness direction Z of the array substrate, the first electrode RE of the light-emitting element can be located on the side of the first gate metal layer 103 away from the substrate 101. The array substrate 10 may further include a source-drain metal layer 701 and a target metal layer 702. Along the thickness direction Z of the array substrate, the source-drain metal layer 701 can be located between the first gate metal layer 103 and the first electrode RE of the light-emitting element. The source-drain metal layer 701 can be used to form the source and drain of the oxide thin film transistor T. The first electrode RE of the light-emitting element can be electrically connected to the source or drain of the oxide thin film transistor T through a via hole. Along the thickness direction Z of the array substrate, the target metal layer 702 can be located between the source-drain metal layer 701 and the first electrode RE of the light-emitting element. The target metal layer 702 may include at least one sub-metal layer, that is, the target metal layer 702 can be a single layer or multiple layers. The first hydrogen absorption layer H1 can reuse a sub-metal layer. For example, in some embodiments, the material of the sub-metal layer in the original target metal layer can be replaced with the material used to prepare the first hydrogen absorption layer H1, so that the sub-metal layer in the target metal layer has the performance of adsorbing hydrogen.

[0091] In this way, by reusing a sub-metal layer in the target metal layer for the first hydrogen absorption layer, on the basis of improving the electrical properties and reliability of the oxide thin film transistor, the production process of the array substrate can be simplified, that is, there is no need to additionally add a process for setting the first hydrogen absorption layer, and only the material of a sub-metal layer in the original target metal layer needs to be replaced with a hydrogen-absorbing material, which is beneficial to reducing the thickness of the array substrate and the production cost.

[0092] Continue to refer to Figure 7, in some specific embodiments, optionally, the target metal layer 702 may include a first sub-metal layer 702a, a second sub-metal layer 702b, and a third sub-metal layer 702c that are sequentially stacked. Along the thickness direction Z of the array substrate, the third sub-metal layer 702c may be located on the side of the second sub-metal layer 702b facing the substrate 101. The first hydrogen absorption layer H1 may reuse the third sub-metal layer 702c. That is, the material of the original third sub-metal layer 702c may be replaced with the material used to prepare the first hydrogen absorption layer H1, so that the third sub-metal layer 702c has the property of adsorbing hydrogen.

[0093] For example, the material of the first sub-metal layer 702a is titanium (Ti), the material of the second sub-metal layer 702b is aluminum (Al), and the material of the original third sub-metal layer 702c is Ti. Then, the material of the third sub-metal layer 702c can be replaced from Ti to IGZO, so that the third sub-metal layer 702c has better hydrogen adsorption performance.

[0094] In this way, by reusing the third sub-metal layer for the first hydrogen absorption layer, on the basis of improving the electrical properties and reliability of the oxide thin-film transistor, the production process of the array substrate can be simplified. That is, there is no need to additionally set the process of the first hydrogen absorption layer. Only the material of the original third sub-metal layer needs to be replaced with a hydrogen-absorbing material, which is beneficial to reducing the thickness of the array substrate and lowering the production cost.

[0095] Figure 8 This is a top view schematic diagram of the array substrate provided by the embodiment of the present application. Combining Figure 7 and Figure 8 shown, according to some embodiments of the present application, optionally, the first hydrogen absorption layer H1 may include a plurality of hydrogen absorption units 801 arranged at intervals. Each hydrogen absorption unit 801 may correspond to an oxide thin-film transistor T. Along the thickness direction Z of the array substrate, the orthographic projection of the hydrogen absorption unit 801 on the substrate 101 may cover the orthographic projection of the oxide thin-film transistor T on the substrate 101, that is, the hydrogen absorption unit 801 may completely block the thin-film transistor T.

[0096] In this way, a corresponding hydrogen absorption unit is provided for each oxide thin-film transistor. Since the hydrogen absorption unit completely blocks the oxide thin-film transistor, hydrogen can be effectively prevented from entering the channel region of the oxide thin-film transistor through gaps or unblocked areas, and the channel region of the oxide thin-film transistor can be better protected from the influence of hydrogen.

[0097] Figure 9 This is another partial cross-sectional schematic diagram of the array substrate provided by the embodiment of the present application. As Figure 9As shown, according to some embodiments of the present application, optionally, the array substrate 10 may further include an interlayer dielectric layer ILD, a source-drain metal layer 701, and a source-drain insulating layer PVX. Along the thickness direction Z of the array substrate, the interlayer dielectric layer ILD may be located on the side of the first gate metal layer 103 away from the metal oxide semiconductor layer 102, and the interlayer dielectric layer ILD may cover the first gate metal layer 103. Along the thickness direction Z of the array substrate, the source-drain metal layer 701 may be located on the side of the interlayer dielectric layer ILD away from the first gate metal layer 103. The source-drain metal layer 701 is used to form the source and drain of the oxide thin film transistor T. Along the thickness direction Z of the array substrate, the source-drain insulating layer PVX may be located on the side of the source-drain metal layer 701 away from the interlayer dielectric layer ILD, and the source-drain insulating layer PVX may cover the source-drain metal layer 701.

[0098] Continue to refer to Figure 9 , in some specific embodiments, optionally, the material of the source-drain insulating layer PVX may include silicon nitride.

[0099] In this way, by using silicon nitride to prepare the source-drain insulating layer PVX, i.e., the planarization layer, due to the good compactness of silicon nitride, it can effectively block the diffusion of hydrogen in the film layer above the source-drain insulating layer PVX to the metal oxide semiconductor layer below the source-drain insulating layer PVX, further improving the electrical properties and reliability of the oxide thin film transistor.

[0100] Figure 10 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiments of the present application. As Figure 10 shown, different from the embodiment shown in T , according to some other embodiments of the present application, optionally, the interlayer dielectric layer ILD includes at least two sub-interlayer dielectric layers stacked. For example, in the example shown in Figure 9 , the interlayer dielectric layer ILD may include a first sub-interlayer dielectric layer ILD1 and a second sub-interlayer dielectric layer ILD2 stacked. Among them, the material of at least one sub-interlayer dielectric layer may include silicon nitride. For example, the material of the second sub-interlayer dielectric layer ILD2 may include silicon nitride.

[0101] In this way, by using silicon nitride to prepare the sub-interlayer dielectric layer, due to the good compactness of silicon nitride, it can effectively block the diffusion of hydrogen in the film layer above the sub-interlayer dielectric layer to the metal oxide semiconductor layer below the sub-interlayer dielectric layer, further improving the electrical properties and reliability of the oxide thin film transistor.

[0102] Figure 10 Another partial cross-sectional schematic diagram of the array substrate provided by the embodiments of the present application. As Figure 11As shown, according to some embodiments of the present application, optionally, at least one of the first gate metal layer 103 and the second gate metal layer 301 may be a stacked structure of titanium and molybdenum. That is, it may be that only the first gate metal layer 103 adopts the stacked structure of titanium and molybdenum, or only the second gate metal layer 301 adopts the stacked structure of titanium and molybdenum, or both the first gate metal layer 103 and the second gate metal layer 301 adopt the stacked structure of titanium and molybdenum.

[0103] Taking the case where both the first gate metal layer 103 and the second gate metal layer 301 adopt the stacked structure of titanium and molybdenum as an example, both the first gate metal layer 103 and the second gate metal layer 301 may include two stacked sub-metal layers, where the material of one sub-metal layer is titanium and the material of the other sub-metal layer is molybdenum, thus forming a stacked structure of titanium and molybdenum.

[0104] In this way, since titanium is extremely easy to react with hydrogen when heated, at least one of the first gate metal layer and the second gate metal layer adopting the stacked structure of titanium and molybdenum can further adsorb hydrogen, further prevent hydrogen from diffusing into the metal oxide semiconductor layer, and improve the electrical properties and reliability of the oxide thin film transistor.

[0105] According to some embodiments of the present application, optionally, the material of the first hydrogen absorption layer H1 may include metal oxides, such as indium gallium zinc oxide IGZO, indium tin oxide ITO, indium tin zinc oxide ITZO and other metal oxides. The inventors of the present application further found that when the proportion of oxygen in the gas introduced during the formation of the first hydrogen absorption layer (abbreviated as PO2) is greater than 50%, the oxygen vacancies in the formed first hydrogen absorption layer are lower, the number of carriers is less, and a better low-conductivity material can be formed. In this way, hydrogen ions can be easily captured subsequently, hydrogen can be better adsorbed, and the hydrogen adsorption capacity can also be increased.

[0106] Therefore, in view of the above findings, in some examples, optionally, the material of the first hydrogen absorption layer includes metal oxides, and the proportion of oxygen in the gas introduced during the formation of the first hydrogen absorption layer is greater than 50%.

[0107] In this way, by making the proportion of oxygen in the gas introduced during the formation of the first hydrogen absorption layer greater than 50%, the oxygen vacancies in the prepared first hydrogen absorption layer can be made lower, the number of carriers is less, so that hydrogen ions can be easily captured subsequently, hydrogen can be better adsorbed, and the hydrogen adsorption capacity can also be increased.

[0108] Similarly, in some embodiments, optionally, the material of the second hydrogen absorption layer H2 includes metal oxides, and the proportion of oxygen in the gas introduced during the formation of the second hydrogen absorption layer is greater than 50%.

[0109] In this way, by making the proportion of oxygen in the introduced gas greater than 50% during the formation of the second hydrogen absorption layer, the oxygen vacancies in the prepared second hydrogen absorption layer can be made lower, and the number of carriers can be less. In this way, hydrogen ions can be easily captured subsequently, hydrogen can be adsorbed better, and the hydrogen adsorption capacity can also be increased.

[0110] Further discovered by the inventors of the present application, when the thickness of the first hydrogen absorption layer H1 is greater than 500 Å, on the one hand, the increase in the thickness of the first hydrogen absorption layer H1 will result in a larger number of carriers in the first hydrogen absorption layer, which is not conducive to hydrogen adsorption; on the other hand, it will also cause waste of materials and increase production costs.

[0111] Therefore, in view of the above discovery, in some examples, optionally, the thickness of the first hydrogen absorption layer H1 can be less than 500 Å, so as to improve the hydrogen adsorption ability of the first hydrogen absorption layer H1 and reduce production costs.

[0112] Similarly, the thickness of the second hydrogen absorption layer H2 can be less than 500 Å, so as to improve the hydrogen adsorption ability of the second hydrogen absorption layer H2 and reduce production costs.

[0113] Based on the array substrate 10 provided in the above embodiments, correspondingly, the present application also provides a preparation method for an array substrate. The preparation method for the array substrate provided in the embodiments of the present application can be used to prepare the array substrate 10 provided in the above embodiments. Please refer to the following embodiments.

[0114] Figure 11 It is a schematic flow chart of a preparation method for an array substrate provided in an embodiment of the present application. As Figure 12 shown, the preparation method for the array substrate provided in the embodiments of the present application may include the following steps S101 to S103.

[0115] S101. Provide a substrate.

[0116] S102. Sequentially form a metal oxide semiconductor layer and a first gate metal layer on one side of the substrate. The metal oxide semiconductor layer is used to form the active layer of the oxide thin film transistor, and the first gate metal layer is used to form the first gate of the oxide thin film transistor.

[0117] S103. Before forming the first gate metal layer, form a first hydrogen absorption layer on the side of the metal oxide semiconductor layer away from the substrate, and / or after forming the first gate metal layer, form a first hydrogen absorption layer on the side of the first gate metal layer away from the metal oxide semiconductor layer.

[0118] Along the thickness direction of the array substrate, the orthographic projection of the first hydrogen absorption layer on the substrate at least partially overlaps with the orthographic projection of the first gate of the oxide thin film transistor on the substrate.

[0119] For the specific processes of the above steps S101 to S103, please refer to the description in the above text Figure 12 and Figure 1 the description in the relevant part. For the sake of brief description, it will not be elaborated here

[0120] On the one hand, in the method for manufacturing an array substrate according to an embodiment of the present application, by providing a first hydrogen-absorbing layer between the first gate metal layer and the metal oxide semiconductor layer, and / or on the side of the first gate metal layer facing away from the metal oxide semiconductor layer, the hydrogen diffused in the film layer above the metal oxide semiconductor layer can be adsorbed, effectively preventing the hydrogen in the film layer above the metal oxide semiconductor layer from diffusing into the metal oxide semiconductor layer, thereby improving the electrical properties and reliability of the oxide thin film transistor, and further improving the reliability of the array substrate. On the other hand, since the first hydrogen-absorbing layer does not reuse the first gate of the oxide thin film transistor, the performance change of the first gate of the oxide thin film transistor caused by hydrogen adsorption can be avoided, thereby ensuring the stable performance of the oxide thin film transistor and being beneficial to ensuring the stability of the circuit in the array substrate

[0121] It should be noted that the method for manufacturing an array substrate provided by the embodiment of the present application has the same or corresponding technical features as those of the array substrate 10 provided by the above embodiment, and can achieve the same or corresponding technical effects as those of the array substrate 10. For the sake of brief description, it will not be elaborated here

[0122] Based on the array substrate 10 provided by the above embodiment, correspondingly, the present application further provides a display device, including the array substrate 10 provided by the present application. Please refer to Figure 2 , Figure 13 which is a schematic structural diagram of a display device provided by an embodiment of the present application Figure 13 The provided display device 1000 includes the array substrate 10 provided by any one of the above embodiments of the present application Figure 13 Figure 13 Taking a mobile phone as an example for illustration, it can be understood that the display device provided by the embodiment of the present application can be other display devices with a display function such as wearable products, computers, televisions, in-vehicle display devices, etc. The present application does not make specific limitations thereto. The display device provided by the embodiment of the present application has the beneficial effects of the array substrate 10 provided by the embodiment of the present application. Specifically, reference can be made to the specific descriptions of the array substrate 10 in the above embodiments. This embodiment will not be elaborated here

[0123] It should be understood that the circuit structure and cross-sectional structure of the array substrate 10 provided in the drawings of the embodiment of the present application are only some examples and are not used to limit the present application. In addition, the above embodiments provided by the present application can be combined with each other without conflict

[0124] According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

[0125] As described above, the above is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, modules, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of the present application.

Claims

1. An array substrate, characterized in that, The array substrate includes a substrate, a metal oxide semiconductor layer, and a first gate metal layer stacked in the thickness direction of the array substrate. An oxide thin film transistor is provided in the array substrate. The metal oxide semiconductor layer is used to form the active layer of the oxide thin film transistor, and the first gate metal layer is used to form the first gate of the oxide thin film transistor; The array substrate further includes a first hydrogen absorption layer. Along the thickness direction of the array substrate, the first hydrogen absorption layer is located between the first gate metal layer and the metal oxide semiconductor layer, and / or the first hydrogen absorption layer is located on a side of the first gate metal layer facing away from the metal oxide semiconductor layer; Along the thickness direction of the array substrate, a positive projection of the first hydrogen absorption layer on the substrate at least partially overlaps a positive projection of the first gate of the oxide thin film transistor on the substrate; The array substrate is provided with a first electrode of a light emitting element, and the first electrode is electrically connected to the oxide thin film transistor through a via hole; The first electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence. Along the thickness direction of the array substrate, the third conductive layer is located on a side of the second conductive layer facing the substrate; The first hydrogen absorption layer multiplexes the third conductive layer.

2. The array substrate according to claim 1, wherein The array substrate further includes: A second gate metal layer. Along the thickness direction of the array substrate, the second gate metal layer is located between the substrate and the metal oxide semiconductor layer. The second gate metal layer is used to form the second gate of the oxide thin film transistor; A second hydrogen absorption layer. Along the thickness direction of the array substrate, the second hydrogen absorption layer is located between the second gate metal layer and the substrate, and / or between the second gate metal layer and the metal oxide semiconductor layer, and a positive projection of the second hydrogen absorption layer on the substrate at least partially overlaps a positive projection of the second gate of the oxide thin film transistor on the substrate.

3. The array substrate according to claim 2, wherein The array substrate further includes a buffer layer. Along the thickness direction of the array substrate, the buffer layer is located between the substrate and the second gate metal layer. The second hydrogen absorption layer is located in the buffer layer and is covered by the buffer layer.

4. The array substrate according to claim 2, wherein The array substrate further includes a buffer layer. Along the thickness direction of the array substrate, the buffer layer is located between the substrate and the metal oxide semiconductor layer. The second gate metal layer and the second hydrogen absorption layer are both located in the buffer layer and are both covered by the buffer layer.

5. The array substrate according to claim 1, wherein The first hydrogen absorption layer and the first gate metal layer are adjacent film layers, and a positive projection of the first hydrogen absorption layer on the substrate overlaps a positive projection of the first gate of the oxide thin film transistor on the substrate.

6. The array substrate according to claim 2, wherein The second hydrogen absorption layer and the second gate metal layer are adjacent film layers, and a positive projection of the second hydrogen absorption layer on the substrate overlaps a positive projection of the second gate of the oxide thin film transistor on the substrate.

7. The array substrate according to claim 1, wherein The array substrate further includes: a first electrode of the light-emitting element, along the thickness direction of the array substrate, the first electrode is located on a side of the first gate metal layer away from the substrate; a source-drain metal layer, along the thickness direction of the array substrate, the source-drain metal layer is located between the first gate metal layer and the first electrode, the source-drain metal layer is used to form a source and a drain of the oxide thin film transistor, and the first electrode is electrically connected to the source or the drain of the oxide thin film transistor through a via; a target metal layer, along the thickness direction of the array substrate, the target metal layer is located between the source-drain metal layer and the first electrode; the target metal layer includes at least one sub-metal layer, and the first hydrogen absorption layer multiplexes one of the sub-metal layers.

8. The array substrate according to claim 7, wherein the target metal layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer that are sequentially stacked, along the thickness direction of the array substrate, the third sub-metal layer is located on a side of the second sub-metal layer facing the substrate, and the first hydrogen absorption layer multiplexes the third sub-metal layer.

9. The array substrate according to claim 7, wherein the first hydrogen absorption layer includes a plurality of hydrogen absorption units arranged at intervals, each hydrogen absorption unit corresponds to one oxide thin film transistor, and along the thickness direction of the array substrate, a positive projection of the hydrogen absorption unit on the substrate covers a positive projection of the oxide thin film transistor on the substrate.

10. The array substrate according to claim 1, wherein The array substrate further includes: an interlayer dielectric layer, along the thickness direction of the array substrate, the interlayer dielectric layer is located on a side of the first gate metal layer away from the metal oxide semiconductor layer and covers the first gate metal layer; a source-drain metal layer, along the thickness direction of the array substrate, the source-drain metal layer is located on a side of the interlayer dielectric layer away from the first gate metal layer, and the source-drain metal layer is used to form a source and a drain of the oxide thin film transistor; a source-drain insulating layer, along the thickness direction of the array substrate, the source-drain insulating layer is located on a side of the source-drain metal layer away from the interlayer dielectric layer and covers the source-drain metal layer.

11. The array substrate according to claim 10, wherein the material of the source-drain insulating layer includes silicon nitride.

12. The array substrate according to claim 10, wherein the interlayer dielectric layer includes at least two sub-interlayer dielectric layers stacked, and among them, the material of at least one sub-interlayer dielectric layer includes silicon nitride.

13. The array substrate according to claim 2, wherein At least one of the first gate metal layer and the second gate metal layer is a stacked structure of titanium-molybdenum.

14. The array substrate according to claim 13, wherein The material of the first hydrogen absorption layer includes metal oxide. During the formation of the first hydrogen absorption layer, the proportion of oxygen in the introduced gas is greater than 50%.

15. The array substrate according to claim 13, wherein The material of the second hydrogen absorption layer includes metal oxide. During the formation of the second hydrogen absorption layer, the proportion of oxygen in the introduced gas is greater than 50%.

16. A method for preparing an array substrate, characterized in that, The array substrate includes the array substrate according to any one of claims 1-15, and the manufacturing method includes: Providing a substrate; Successively forming a metal oxide semiconductor layer and a first gate metal layer on one side of the substrate. The metal oxide semiconductor layer is used to form the active layer of the oxide thin film transistor, and the first gate metal layer is used to form the first gate of the oxide thin film transistor; Before forming the first gate metal layer, forming a first hydrogen absorption layer on the side of the metal oxide semiconductor layer away from the substrate, and / or after forming the first gate metal layer, forming a first hydrogen absorption layer on the side of the first gate metal layer away from the metal oxide semiconductor layer; Along the thickness direction of the array substrate, the orthographic projection of the first hydrogen absorption layer on the substrate at least partially overlaps with the orthographic projection of the first gate of the oxide thin film transistor on the substrate.

17. A display device, characterized in that, Including the array substrate according to any one of claims 1-15.

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