Oxide thin film transistor and preparation method thereof

Abstract

The invention provides an oxide thin film transistor and a preparation method thereof. The composite active layer at least comprises a first layer and a second layer which are stacked on the substrate and are arranged in a contact manner; the source and drain electrode layer is arranged on the substrate and is electrically connected with the composite active layer; wherein lattice constant difference exists between the first layer and the second layer; the second layer is a metal oxide semiconductor, and the proportion of metal atoms of the second layer is monotonically decreased from the substrate side to the top surface. The lattice constant difference of the first layer and the second layer enables lattice mismatch of the first layer and the second layer to introduce compressive strain in the second layer, the energy band structure of the second layer is optimized, the interface defect density is reduced, and carrier scattering is reduced; the proportion of metal atoms in the second layer is monotonically decreased to form a built-in electric field, carriers are guided to be directionally transmitted, scattering paths are reduced, and the carrier mobility is remarkably improved through the synergistic effect of the two.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an oxide thin-film transistor and a method for fabricating the same. Background Technology

[0002] In recent years, metal oxide thin-film transistors have received increasing attention due to their advantages such as high mobility, good light transmittance, stable thin-film structure, low fabrication temperature, and low cost.

[0003] However, despite the industrialization of metal oxide thin-film transistors, further improvements in their carrier mobility still face multiple bottlenecks. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide an oxide thin-film transistor and its fabrication method, thereby solving the problem of how to improve the mobility of oxide thin-film transistors in the prior art.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide an oxide thin-film transistor, comprising: Substrate; The composite active layer includes at least a first layer and a second layer stacked on a substrate and in contact with each other; The source and drain layers are disposed on the substrate and electrically connected to the composite active layer; The first and second layers have different lattice constants; the second layer is a metal oxide semiconductor, and the proportion of metal atoms in the second layer decreases monotonically from the substrate side to the top surface.

[0006] In some embodiments, the first layer comprises a metal oxide doped with an active metal element, and the thickness of the first layer is 10-20 nm; the thickness of the second layer is 60-120 nm; and the lattice constant difference between the first layer and the second layer is 0.94%-1.28%.

[0007] In some embodiments, the second layer is indium gallium zinc oxide, and the first layer is zinc oxide doped with aluminum.

[0008] In some embodiments, aluminum accounts for 1% to 3% of all metal atoms in the first layer.

[0009] In some embodiments, the atomic ratio of In:Ga:Zn in the second layer is (3~5):(1~2):(1~3).

[0010] In some embodiments, the composite active layer further includes a third layer located on the surface of the second layer away from the first layer; the source and drain layers are at least partially located on the side surface of the third layer away from the substrate; the thickness of the third layer is 2-5 nm.

[0011] In some embodiments, the third layer, the second layer, and the first layer all comprise the same metal oxide.

[0012] In some embodiments, the third layer is zinc oxide.

[0013] In some embodiments, the oxide thin-film transistor further includes an insulating layer disposed between the substrate and the first layer; the insulating layer includes a first insulating layer and a second insulating layer sequentially stacked on the substrate; the thickness of the first insulating layer is 5~10nm; the thickness of the second insulating layer is 3~8nm; the dielectric constant of the first insulating layer is a preset value, the preset value being 18~25; The second insulating layer is located on the surface of the first layer away from the second layer.

[0014] To address the aforementioned technical problems, the second technical solution provided in this application is: a method for fabricating an oxide thin-film transistor, comprising: Provide a substrate; A composite active layer is deposited on a substrate; the composite active layer includes at least a first layer and a second layer stacked and in contact; there is a difference in lattice constant between the first layer and the second layer; the second layer is a metal oxide semiconductor, and the proportion of metal atoms in the second layer decreases monotonically from the substrate side to the top surface; Forming source and drain layers.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides an oxide thin-film transistor and its fabrication method. The oxide thin-film transistor includes a substrate, a composite active layer, and source / drain layers. The composite active layer includes at least a first layer and a second layer stacked on the substrate and in contact with each other; the source / drain layers are disposed on the substrate and electrically connected to the composite active layer; wherein, there is a difference in lattice constant between the first layer and the second layer; the second layer is a metal-oxide semiconductor, and the proportion of metal atoms in the second layer decreases monotonically from the substrate side to the top surface. The difference in lattice constant between the first layer and the second layer causes lattice mismatch between the first layer and the second layer to introduce compressive strain in the second layer, optimizing the band structure of the second layer, reducing the interface defect density, and thus reducing carrier scattering; the monotonically decreasing proportion of metal atoms in the second layer forms a built-in electric field, guiding the directional transport of carriers and reducing scattering paths. The synergistic effect of these two factors significantly improves carrier mobility. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the first embodiment of the oxide thin-film transistor provided in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the oxide thin-film transistor provided in this application; Figure 3 This is a schematic diagram of the structure of the third embodiment of the oxide thin-film transistor provided in this application; Figure 4 This is a schematic flowchart of one embodiment of the method for fabricating an oxide thin-film transistor provided in this application. Figure 5 This is a schematic flowchart of another embodiment of the method for fabricating oxide thin-film transistors provided in this application.

[0018] Explanation of icon numbers: 100, Oxide thin film transistor; 10, Substrate; 20, Composite active layer; 21, First layer; 22, Second layer; 23, Third layer; 30, Source-drain layer; 31, Source; 32, Drain; 40, Insulating layer; 41, First insulating layer; 42, Second insulating layer; 50, Gate. Detailed Implementation

[0019] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] Existing research indicates that traditional IGZO structures suffer from numerous interface defects, a single carrier transport channel, and disordered crystal structure. For example, at the interface between the gate insulating layer and the IGZO active layer, a large number of interface states exist due to lattice mismatch and fabrication limitations. These interface states become carrier scattering centers, severely hindering efficient carrier transport. Simultaneously, oxygen vacancy defects within the IGZO can form donor levels, making it difficult to precisely control the carrier concentration and affecting the stability of the mobility. Current methods for improving the mobility of IGZO have limitations. For example, simply increasing the annealing temperature can reduce some defects, but it leads to uncontrollable changes in the material structure and cannot effectively solve interface state problems. Similarly, while doping techniques can adjust carrier concentration, they introduce new impurities and defects, reducing material purity and making it difficult to achieve a significant increase in mobility. Furthermore, most existing structural designs only consider a single aspect and lack systematic optimization for improving the overall performance of IGZO materials, thus failing to meet the higher mobility requirements of high-end electronic devices.

[0025] Please see Figures 1 to 3 , Figure 1This is a schematic diagram of the structure of the first embodiment of the oxide thin-film transistor provided in this application. Figure 2 This is a schematic diagram of the structure of the second embodiment of the oxide thin-film transistor provided in this application. Figure 3 This is a schematic diagram of the structure of the third embodiment of the oxide thin-film transistor provided in this application.

[0026] This application provides an oxide thin-film transistor 100, which includes a substrate 10, a composite active layer 20, and a source / drain layer 30. The composite active layer 20 includes at least a first layer 21 and a second layer 22 stacked on the substrate 10 and in contact with each other; the source / drain layer 30 is disposed on the substrate 10 and electrically connected to the composite active layer 20; wherein, the first layer 21 and the second layer 22 have a difference in lattice constant; the second layer 22 is a metal oxide semiconductor, and the proportion of metal atoms in the second layer 22 decreases monotonically from the substrate 10 side to the top surface.

[0027] The difference in lattice constants between the first layer 21 and the second layer 22 causes a lattice mismatch between the first layer 21 and the second layer 22, which introduces compressive strain into the second layer 22, optimizes the band structure of the second layer 22, reduces the interface defect density, and thus reduces carrier scattering. The monotonically decreasing proportion of metal atoms in the second layer 22 forms a built-in electric field, which guides the directional transport of carriers and reduces the scattering path. The synergistic effect of the two significantly improves the carrier mobility.

[0028] The substrate 10 can be a rigid substrate or a flexible substrate.

[0029] For example, the substrate 10 is a quartz glass substrate, which has good chemical and thermal stability and can provide stable support for the device.

[0030] Due to the difference in lattice constants between the first layer 21 and the second layer 22, compressive strain is introduced to optimize the band structure and reduce the interface defect density. The built-in electric field formed by the monotonically decreasing proportion of metal atoms in the second layer 22 guides the directional transport of charge carriers, reduces scattering, and thus significantly improves mobility, achieving a 6-8 fold improvement on a quartz glass substrate, thereby enhancing the stability of device performance.

[0031] For example, substrate 10 is a flexible substrate, such as flexible polyimide (PI). The flexible polyimide substrate gives the device the property of being flexible, making it suitable for the field of flexible electronics.

[0032] For example, the source-drain layer 30 is disposed on the side of the second layer 22 away from the first layer 21. That is, in this embodiment, the composite active layer 20 is a two-layer structure, including only the first layer 21 and the second layer 22.

[0033] The source-drain layer 30 includes a source 31 and a drain 32 spaced apart.

[0034] There are no restrictions on the materials for the source and drain layers 30 here; they can be selected according to actual needs.

[0035] For example, the source / drain layer 30 is a double-layer metal structure. One layer of the double-layer metal structure is a titanium (Ti) layer, and the other layer is a gold (Au) layer. The thickness of the Ti layer is 10~20nm, and the thickness of the Au layer is 80~120nm.

[0036] In other embodiments, the source / drain layer 30 can be a single-layer structure or a multi-layer structure.

[0037] In some embodiments, the first layer 21 comprises a metal oxide doped with an active metal element, and the thickness of the first layer 21 is 10~20 nm; the thickness of the second layer 22 is 60~120 nm; and the lattice constant difference between the first layer 21 and the second layer 22 is 0.94%~1.28%.

[0038] Limiting the thickness of the first layer 21 to 10~20nm can avoid the formation of mismatch dislocations.

[0039] The thickness of the second layer 22 is limited to 60~120nm to balance the crystal quality and carrier transport performance of the second layer 22.

[0040] Active metal elements are doped into the first layer 21 to provide free electrons to the conduction band, thereby increasing the electron density in the first layer 21.

[0041] The first layer 21 and the second layer 22 may include the same metal oxide composition to form a small band shift, which helps the directional transport of charge carriers.

[0042] For example, the lattice constant of the first layer 21 is 3.249±0.002Å, and the second layer 22 locally exhibits a short-range ordered structure with an equivalent in-plane lattice constant of 3.280±0.005Å. The difference between the two is between 0.94% and 1.28%. The first layer 21 will apply compressive strain to the second layer 22, causing the conduction band bottom of the second layer 22 to split, forming new energy levels and improving carrier mobility.

[0043] In some embodiments, the second layer 22 is indium gallium zinc oxide, and the first layer 21 is zinc oxide doped with aluminum.

[0044] Both the second layer 22 and the first layer 21 include zinc oxide components to form a small band shift, which assists in the directional transport of charge carriers.

[0045] In some embodiments, aluminum in the first layer 21 accounts for 1% to 3% of all metal atoms.

[0046] For example, the first layer 21 is zinc oxide doped with aluminum.

[0047] By controlling the aluminum doping concentration in the first layer 21 to the range of 1% to 3%, compressive strain is effectively introduced, causing moderate compression of the lattice in the second layer 22, optimizing the band structure and reducing carrier scattering centers, thereby significantly improving mobility.

[0048] In some embodiments, the atomic ratio of In:Ga:Zn in the second layer 22 is (3~5):(1~2):(1~3).

[0049] For example, the second layer 22 is indium gallium zinc oxide. The second layer 22 includes In (indium), Ga (gallium), and Zn (zinc).

[0050] The monotonically decreasing distribution of the In:Ga:Zn atomic ratio in the second layer 22 forms a stable built-in electric field, which guides the charge carriers to propagate in a specific direction, effectively reducing the scattering loss of charge carriers during the propagation process.

[0051] The material of the second layer 22 is not limited to indium gallium zinc oxide. For example, the second layer 22 can also be indium zinc oxide (IZO), zinc tin oxide (ZTO), indium aluminum zinc oxide (IAZO) or indium gallium zinc oxide (ITZO).

[0052] For example, when the second layer 22 is indium zinc oxide (IZO), zinc tin oxide (ZTO), indium aluminum zinc oxide (IAZO) or indium gallium zinc oxide (ITZO), the first layer 21 can be zinc oxide doped with aluminum.

[0053] In some embodiments, the composite active layer 20 further includes a third layer 23 located on the surface of the second layer 22 away from the first layer 21; the source-drain layer 30 is at least partially located on the side surface of the third layer 23 away from the substrate 10; the thickness of the third layer 23 is 2~5nm.

[0054] The third layer 23 serves as a surface finishing layer, used to passivate the dangling bonds on the surface of the second layer 22.

[0055] For example, the composite active layer 20 includes a first layer 21, a second layer 22, and a third layer 23 that are stacked and contacted in sequence. There are no other layer structures between the first layer 21 and the second layer 22, and there are no other layer structures between the second layer 22 and the third layer 23. The first layer 21 is disposed facing the substrate 10, and the third layer 23 is disposed facing the source and drain layers 30. That is, the composite active layer 20 is a three-layer structure.

[0056] Limiting the thickness of the third layer 23 to 2~5nm ensures a balance between surface passivation and device performance. If the thickness of the third layer 23 is too thin, it will not be able to adequately passivate the surface dangling bonds; if it is too thick, it may hinder carrier transport efficiency.

[0057] In some embodiments, the third layer 23, the second layer 22, and the first layer 21 all comprise the same metal oxide.

[0058] By making the third layer 23, the second layer 22 and the first layer 21 all include the same metal oxide, the chemical matching of the interlayer interface is enhanced, the interface defect density is significantly reduced, the scattering of charge carriers at the interface is reduced, and the carrier transport path is optimized, thereby achieving a significant improvement in the mobility of the thin film transistor.

[0059] In some specific embodiments, the third layer 23 is zinc oxide.

[0060] The third layer 23, the second layer 22, and the first layer 21 all contain zinc oxide.

[0061] The third layer 23 significantly reduces surface defect density by passivating the dangling bonds on the surface of the second layer 22, thereby lowering the scattering probability of charge carriers at the interface. Simultaneously, it improves the contact performance between the source / drain electrodes 32 and the second layer 22 in the source / drain electrode layer, reducing contact resistance and making carrier transport more efficient. Therefore, the device mobility is improved, and the overall performance stability is enhanced, meeting the application requirements of high-performance display devices for high mobility and low defect state density.

[0062] In other embodiments, the third layer 23 may not contain the same metal oxide as the second layer 22, and / or the third layer 23 may not contain the same metal oxide as the first layer 21. For example, the second layer 22 is indium gallium zinc oxide, the first layer 21 is zinc oxide doped with aluminum, and the third layer 23 is SnO2 (tin oxide).

[0063] The oxide thin-film transistor 100 also includes an insulating layer 40 disposed between the substrate 10 and the first layer 21.

[0064] The insulation layer 40 can be a single-layer structure or a multi-layer structure; there are no major restrictions here, and the choice can be made according to actual needs.

[0065] The oxide thin-film transistor 100 can be either a top-gate structure or a bottom-gate structure.

[0066] The specification uses an oxide thin-film transistor 100 as the bottom gate structure.

[0067] For example, such as Figure 1 and Figure 2 As shown, the oxide thin-film transistor 100 also includes a gate 50, which is located between the substrate 10 and the insulating layer 40. In this case, the insulating layer 40 is also called the gate insulating layer (GI layer).

[0068] The gate 50 can be at least one of Mo (molybdenum), Al (aluminum), or Cu (copper).

[0069] The gate 50 can also be made of other materials; there are no major restrictions here, and the choice can be made according to actual needs.

[0070] In some embodiments, such as Figure 3 As shown, the insulating layer 40 includes a first insulating layer 41 and a second insulating layer 42 sequentially stacked on the substrate 10; the thickness of the first insulating layer 41 is 5~10nm; the thickness of the second insulating layer 42 is 3~8nm; the dielectric constant of the first insulating layer 41 is a preset value, which is 18~25; the second insulating layer 42 is located on the surface of the first layer 21 away from the second layer 22.

[0071] The first insulating layer 41 of the insulating layer 40 is disposed facing the substrate 10, and the second insulating layer 42 is disposed facing the first layer 21.

[0072] The dielectric constant of the first insulating layer 41 is a preset value, which is used to enhance the electric field control capability of the gate 50 over the channel.

[0073] For example, the first insulating layer 41 is made of a high dielectric constant material such as hafnium dioxide (HfO2).

[0074] The second insulating layer 42 is used to passivate the interface and reduce the interface state density. The thickness of the second insulating layer 42 is 3~8nm, which optimizes the passivation effect and avoids insufficient passivation due to excessive thinness or the impact of electric field transmission due to excessive thickness.

[0075] For example, the second insulating layer 42 is made of aluminum oxide (Al2O3).

[0076] Through the double insulating layer 40 structure, the high dielectric constant of the first insulating layer 41 enhances the gate 50's control over the channel and reduces interface defect sources. The passivation effect of the second insulating layer 42 reduces the interface state density, thereby significantly reducing carrier scattering at the interface and improving carrier transport efficiency, thus enhancing the mobility of the oxide thin film transistor 100.

[0077] In some embodiments, the oxide thin film transistor 100 includes not only the third layer 23 described above, but also the insulating layer 40, which includes the first insulating layer 41 and the second insulating layer 42 described above. The synergistic effect of the double insulating layer 40 and the third layer 23 reduces the interface state density between the second layer 22 and the insulating layer 40, reduces carrier scattering at the interface, and improves carrier transport efficiency.

[0078] Please see Figures 1 to 5 , Figure 4 This is a schematic flowchart of one embodiment of the method for fabricating an oxide thin-film transistor provided in this application. Figure 5 This is a schematic flowchart of another embodiment of the method for fabricating oxide thin-film transistors provided in this application.

[0079] This application provides a method for fabricating an oxide thin-film transistor 100, wherein the method for fabricating the oxide thin-film transistor 100 includes: S1: Provide a substrate 10.

[0080] Specifically, a substrate 10 is provided and the substrate 10 is pretreated to remove surface impurities and moisture.

[0081] The substrate 10 is made of different materials and the processing methods are different.

[0082] For example, the substrate 10 is a rigid substrate, such as a quartz glass substrate. The pretreatment steps for the substrate 10 are as follows: ultrasonically cleaned with acetone and ethanol for 15-25 minutes in sequence, rinsed with deionized water for 10-15 minutes, and finally dried at 120-150°C for 30-60 minutes.

[0083] For example, the substrate 10 is a flexible substrate, such as a flexible polyimide (PI) substrate. The pretreatment steps for the substrate 10 are as follows: first, wipe the surface with isopropanol, and then bake it in a vacuum environment at 80°C~100°C for 1~2 hours.

[0084] When the substrate 10 is made of other materials, other methods can also be used to pre-treat the substrate 10.

[0085] In one specific embodiment, a quartz glass substrate is selected as the substrate 10, which is then ultrasonically cleaned in acetone and ethanol for 20 minutes, rinsed with deionized water for 12 minutes, and finally dried at 130°C for 40 minutes. S2: Deposit a composite active layer 20 on the substrate 10; the composite active layer 20 includes at least a first layer 21 and a second layer 22 stacked and contacted; there is a difference in lattice constant between the first layer 21 and the second layer 22; the second layer 22 is a metal oxide semiconductor, and the proportion of metal atoms in the second layer 22 decreases monotonically from the side of the substrate 10 to the top surface.

[0086] The first layer 21 and the second layer 22 in the composite active layer 20 are prepared by magnetron sputtering.

[0087] For example, such as Figure 1 and Figure 2 As shown, the composite active layer 20 includes a first layer 21 and a second layer 22 stacked and contacted together. The second layer 22 is indium gallium zinc oxide, and the first layer 21 is zinc oxide doped with aluminum.

[0088] In some embodiments, in a magnetron sputtering apparatus, a ZnO:Al target is used to deposit an AZO layer (i.e., the first layer 21) under conditions of sputtering power of 100W to 150W, sputtering pressure of 0.5Pa to 1.0Pa, and argon flow rate of 20sccm to 30sccm.

[0089] In the same magnetron sputtering equipment, the composite target material of In2O3, Ga2O3 and ZnO was changed, the sputtering power was set to 120W to 180W and the sputtering pressure was set to 0.6Pa to 1.2Pa. The oxygen to argon flow ratio was dynamically adjusted by the gas flow controller from the initial O2 / Ar=1 / 10 to O2 / Ar=1 / 15, so as to achieve a monotonically decreasing distribution of the proportion of metal atoms in the second layer 22, thus obtaining the second layer 22.

[0090] In other implementations, such as Figure 3 As shown, the composite active layer 20 includes a first layer 21, a second layer 22, and a third layer 23 that are stacked and contacted in sequence. The fabrication of the first layer 21 and the second layer 22 is as described above and will not be repeated here.

[0091] For example, the third layer 23 is zinc oxide, the second layer 22 is indium gallium zinc oxide, and the first layer 21 is zinc oxide doped with aluminum.

[0092] The third layer 23 in the composite active layer 20 was prepared by molecular beam epitaxy.

[0093] The sample with the second layer 22 (referring to substrate 10 and the structure on substrate 10) is transferred to a molecular beam epitaxy (MBE) device and subjected to ultra-high vacuum (vacuum level not exceeding 10). -8 In an environment of Pa, a ZnO layer, namely the third layer 23, is grown at 400°C to 500°C using zinc and oxygen as sources.

[0094] In one specific embodiment, the substrate 10 and the structure on the substrate 10 are transferred to a magnetron sputtering apparatus. In the magnetron sputtering apparatus, a ZnO:Al target with an Al doping concentration of 2% is used, and a 15 nm thick AZO layer (i.e., the first layer 21) is deposited under the conditions of sputtering power of 120 W, sputtering pressure of 0.8 Pa, and argon flow rate of 25 sccm.

[0095] In the same magnetron sputtering apparatus, the In₂O₃, Ga₂O₃, and ZnO composite targets were changed. The sputtering power was set to 150W and the sputtering pressure to 1Pa. The oxygen to argon flow ratio was dynamically adjusted using a gas flow controller, gradually increasing from an initial O₂ / Ar = 1 / 10 to O₂ / Ar = 1 / 15 over 30 minutes, depositing a second layer 22 with a thickness of 80nm. The atomic ratio of In:Ga:Zn was 4:1.5:2. The sample with the second layer 22 (referring to substrate 10 and the structure on substrate 10) was then transferred to a molecular beam epitaxy apparatus under a vacuum of 10... -9 A ZnO layer with a thickness of 3 nm, namely the third layer 23, was grown at 450°C using zinc and oxygen as sources under Pa conditions.

[0096] S3: Form source / drain layer 30.

[0097] For example, the source-drain layer 30 is a double-layer metal structure.

[0098] A double-layer metal structure was sequentially deposited using electron beam evaporation technology, followed by annealing at 350°C for 30-60 minutes to form a low-resistance ohmic contact.

[0099] In one specific embodiment, an electron beam evaporation technique is used to first deposit a Ti layer with a thickness of 15 nm, and then deposit an Au layer with a thickness of 100 nm to form a double-layer metal structure.

[0100] In other embodiments, the source and drain layers 30 may be prepared in other ways.

[0101] In other embodiments, the source-drain layer 30 may be a single-layer structure, and no further restrictions are imposed here.

[0102] In some implementations, such as Figure 5 As shown, after step S1 and before step S2, the following is also included: S12: Form an insulating layer 40.

[0103] For example, the insulating layer 40 includes a first insulating layer 41 and a second insulating layer 42.

[0104] The pretreated substrate 10 was placed in an atomic layer deposition apparatus. First, using tetrakis(dimethylamino)hafnium as a precursor and water as an oxidant, an HfO2 layer (i.e., the first insulating layer 41) was cyclically deposited at 200°C to 250°C to the target thickness. Then, using trimethylaluminum as a precursor and water as an oxidant, an Al2O3 layer (i.e., the second insulating layer 42) was cyclically deposited at 150°C to 200°C to the target thickness.

[0105] In one specific embodiment, the pretreated substrate 10 is placed in an atomic layer deposition apparatus. First, using tetrakis(dimethylamino)hafnium as a precursor and water as an oxidant, an HfO2 layer (i.e., the first insulating layer 41) is cyclically deposited at 220°C to a target thickness of 8 nm. Subsequently, using trimethylaluminum as a precursor and water as an oxidant, an Al2O3 layer (i.e., the second insulating layer 42) is cyclically deposited at 180°C to a target thickness of 6 nm.

[0106] In other embodiments, the insulating layer 40 may be prepared in other ways.

[0107] In other embodiments, the insulating layer 40 may be a single-layer or multi-layer structure.

[0108] In some embodiments, the oxide thin-film transistor 100 has a bottom-gate structure. The gate 50 of the oxide thin-film transistor 100 is disposed between the insulating layer 40 and the substrate 10. A metal layer selected from molybdenum, aluminum, or copper is sputtered and deposited on the substrate 10, and the gate 50 is formed by photolithography etching.

[0109] By optimizing the structure of each layer and the fabrication process, defects inside the material were effectively reduced, and the stability of the device was improved.

[0110] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0111] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. An oxide thin-film transistor, comprising: Substrate; The composite active layer includes at least a first layer and a second layer stacked on the substrate and in contact with each other; A source / drain layer is disposed on the substrate and electrically connected to the composite active layer; The first layer and the second layer have a difference in lattice constant; the second layer is a metal oxide semiconductor, and the proportion of metal atoms in the second layer decreases monotonically from the substrate side to the top surface.

2. The oxide thin-film transistor according to claim 1, characterized in that, The first layer comprises a metal oxide doped with an active metal element, and the thickness of the first layer is 10~20 nm; the thickness of the second layer is 60~120 nm; the difference in lattice constant between the first layer and the second layer is 0.94%~1.28%.

3. The oxide thin-film transistor according to claim 2, characterized in that, The second layer is indium gallium zinc oxide, and the first layer is zinc oxide doped with aluminum.

4. The oxide thin-film transistor according to claim 3, characterized in that, In the first layer, aluminum accounts for 1% to 3% of all metal atoms.

5. The oxide thin-film transistor according to claim 3, characterized in that, The atomic ratio of In:Ga:Zn in the second layer is (3~5):(1~2):(1~3).

6. The oxide thin-film transistor according to claim 1, characterized in that, The composite active layer further includes a third layer located on the surface of the second layer away from the first layer; the source and drain layers are at least partially located on the surface of the third layer away from the substrate; the thickness of the third layer is 2~5nm.

7. The oxide thin-film transistor according to claim 6, characterized in that, The third layer, the second layer, and the first layer all comprise the same metal oxide.

8. The oxide thin-film transistor according to claim 7, characterized in that, The third layer is zinc oxide.

9. The thin-film transistor according to claim 1 or 6, characterized in that, The oxide thin-film transistor further includes an insulating layer disposed between the substrate and the first layer; the insulating layer includes a first insulating layer and a second insulating layer sequentially stacked on the substrate; the thickness of the first insulating layer is 5~10nm; the thickness of the second insulating layer is 3~8nm; the dielectric constant of the first insulating layer is a preset value, the preset value being 18~25; The second insulating layer is located on the side surface of the first layer away from the second layer.

10. A method for fabricating an oxide thin-film transistor, used to fabricate the oxide thin-film transistor according to any one of claims 1 to 9, characterized in that, include: Provide a substrate; A composite active layer is deposited on the substrate; The composite active layer includes at least a first layer and a second layer stacked and contacted together; there is a difference in lattice constant between the first layer and the second layer; the second layer is a metal oxide semiconductor, and the proportion of metal atoms in the second layer decreases monotonically from the substrate side to the top surface; Forming source and drain layers.

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