Fully-associative cache management
By employing a fully associative cache management strategy, the wear and tear problem of memory devices during frequent accesses is solved, improving the reliability and performance of the memory system, reducing the number of access operations, and protecting the stability of the memory device.
CN114424173BActive Publication Date: 2026-06-23MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2020-08-20
- Publication Date
- 2026-06-23
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Figure CN114424173B_ABST
Abstract
This application is directed to full-associative cache management. A memory sub-system can receive an access command to store a first data word in a storage component associated with an address space. The memory sub-system can include a full-associative cache to store the data word associated with the storage component. The memory sub-system can determine an address within the cache to store the first data word. For example, the memory sub-system can determine the address of the cache indicated by an address pointer (e.g., based on an order of the address) and determine a number of accesses associated with the data word stored in the cache address. Based on the indicated cache address and the number of accesses, the memory sub-system can store the first data word in the indicated cache address or a second cache address consecutive to the indicated cache address.
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