Single-event flip-flop immune trigger using small-area high-resistivity elements

Abstract

An SEU-immune trigger includes a master-level data latch that is transparent in response to a first clock signal state and locked in response to a second clock signal state; a slave-level data latch; and a scan slave latch having an input coupled to a scan output of the slave-level data latch, the scan slave latch being transparent in response to the second clock signal state and locked in response to the first clock signal state. The slave-level data latch includes a switching inverter that is disabled when the slave latch is in a transparent state and enabled when the slave latch is in a locked state with a time delay longer than the SEU time period.

Description

Technical Field

[0001] This invention relates to digital logic elements. More specifically, this invention relates to single-event flip-flop (SEU) immune triggers that utilize a dense, high-resistivity construction, such as a resistive random access memory (ReRAM) structure as a resistive element. Background Technology

[0002] Triggers exposed to single-event transient (SET) pulses can easily switch states. A trigger switching its own state destabilizes the system using that trigger, necessitating a system reset (once the instability is recognized). Resetting the system results in the loss of system information.

[0003] The SEU immune trigger allows the system to continue operating after the SET pulse. The system recovers and returns to normal operation. This is crucial for mission-critical applications.

[0004] One way to create an SEU-immune trigger is to use a series resistor-capacitor (RC) network to filter out SET particles. The filter must operate with the amplitude of the SET pulse below the trigger's switching point (or the switching point of the inverter inside the trigger).

[0005] One problem that arises with this existing technique is the physical size of the RC network. A 5µ × 5µ capacitor can provide 100fF of capacitance, but it is quite large, with an area of ​​25µm. 2 Furthermore, the typical sheet resistance of a resistor, ρ, is between approximately 600 ohms and 10K ohms. To provide approximately 1ns of SEU / SET immunity, a resistor of at least 100K ohms is required. Therefore, at least 10 squares are needed, which occupies a large area. Given this area, the trigger becomes too large to be implemented using such a network.

[0006] A second approach already used to provide circuits with SEU / SET immunity is to provide three copies of the circuit and use a voting circuit to determine the correct output. This solution consumes more than three times the die area of ​​any one of the individual circuits. Summary of the Invention

[0007] According to one aspect of the present invention, a single-event flip (SEU) immune trigger includes: a clock line configured to supply a clock signal; a master-level data latch having a data input, a data output, and a clock input, the master-level data latch being in a transparent state in response to a first state of the clock signal and in a locked state in response to a second state of the clock signal; a slave-level data latch having a data input, a data output, a scan output, and a slave latch clock input coupled to the data output of the master-level data latch; and a scan slave data latch, wherein... The scan slave data latch has a data input, a data output, and a clock input coupled to the scan output of the slave data latch. The scan slave data latch is in a transparent state in response to a second state of the clock signal and in a locked state in response to a first state of the clock signal. It also includes a slave clock line configured to supply a slave clock signal to the slave clock input of the slave data latch. The slave data latch is in a transparent state in response to a first state of the slave clock signal and in a locked state in response to a second state of the slave clock signal. The slave data latch further includes a switching inverter that is disabled when the slave data latch is in the transparent state and enabled when the slave data latch is in the locked state, the switching inverter being formed by a switching transistor and an inverter transistor; and a time delay regenerative feedback circuit that provides a time delay longer than the time period of the SEU particle when the time delay regenerative feedback circuit is in its locked state.

[0008] According to one aspect of the invention, the SEU immune trigger further includes a set signal line, and the master data latch and the scan slave data latch each include a set input coupled to the set signal line.

[0009] According to one aspect of the invention, the SEU immune trigger further includes a reset signal line, and the master data latch and the scan slave data latch each include a reset input coupled to the reset signal line.

[0010] According to one aspect of the invention, the SEU immune trigger further includes a multiplexer having a first data input coupled to a data signal line, a second data input coupled to a scan input signal line, a data output coupled to the data input of the first-stage data latch, and a selection input coupled to an input selection signal.

[0011] According to one aspect of the invention, the slave data latch has a data output coupled to the output node of the switching inverter.

[0012] According to one aspect of the invention, the time delay is provided by an RC network comprising a vertical resistive element and a capacitive element, the capacitive element comprising the gate capacitance of the inverter transistor in the switching inverter, the vertical resistive element being connected in series with the capacitive element.

[0013] According to one aspect of the invention, the vertical resistive element is formed as an unprogrammed antifuse.

[0014] According to one aspect of the invention, the vertical resistive element is formed as a primitive ReRAM device.

[0015] According to one aspect of the invention, the vertical resistive element is formed as a layer of a high-resistivity metal compound.

[0016] According to one aspect of the invention, the high-resistivity metal compound is one of silicon-rich SiO2, tantalum-rich Ta2O5, titanium-rich TiO2, aluminum-rich Al2O3, and silicon-rich SiN.

[0017] According to one aspect of the invention, the switching inverter includes an inverter input node and an inverter output node, and the switching inverter switching transistor and the inverter transistor include: a p-channel inverter transistor connected in series with a p-channel switching transistor between a first voltage supply node and the inverter output node, the gate of the p-channel inverter transistor being connected to the inverter input node; an n-channel inverter transistor connected in series with an n-channel switching transistor, the inverter output node, and a second voltage supply node, the gate of the n-channel inverter transistor being connected to the inverter input node; and the time delay regenerative feedback circuit, the time delay regenerative feedback circuit including a first inverter, the input of the first inverter being connected to the inverter output node and the output of the first inverter being connected in series with a vertical resistive element to the inverter input node, the provided time delay being a function of the resistance of the vertical resistive element and a capacitor, the capacitor including the capacitance of the gates of the p-channel inverter transistor and the n-channel inverter transistor.

[0018] According to one aspect of the invention, the SEU immune trigger further includes a second inverter connected between the output of the first inverter and the scan output of the slave data latch.

[0019] According to one aspect of the invention, the SEU immune trigger further includes a third inverter connected between the output of the first inverter and the output node of the SEU immune trigger. Attached Figure Description

[0020] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings, in which:

[0021] Figure 1 This is a block diagram of an exemplary SEU immune trigger according to one aspect of the present invention;

[0022] Figure 2 It is possible Figure 1 The schematic diagram of the exemplary latch used in the SEU immune trigger depicted in the figure;

[0023] Figure 3 This is a cross-sectional view of a typical antifuse device structure that can be used as a vertical resistor element in an embodiment of the present invention;

[0024] Figure 4 This is a cross-sectional view of a typical original ReRAM element structure that can be used as a vertical resistor element in an embodiment of the present invention; and

[0025] Figure 5 This is a cross-sectional view of another typical high-resistance structure that can be used as a vertical resistor element in an embodiment of the present invention. Detailed Implementation

[0026] Those skilled in the art will recognize that the following description is merely illustrative and not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0027] Several high-resistance elements are known to be formed as vertical structures that occupy a small area on an integrated circuit (i.e., they can occupy an area the size of the intermetallic or metal-to-substrate contact). These structures will be referred to herein as vertical resistor elements. Examples of vertical resistor elements as used herein are unprogrammed antifuse elements, raw ReRAM elements, i.e., unprogrammed ReRAM elements, and other high-resistance structures. Each of these vertical resistor elements has extremely high resistance while occupying a small area on the integrated circuit. Their extremely high resistance allows for a small capacitance used in the RC network within an SEU immune trigger. The gate capacitance of a field-effect transistor (FET) in the circuit can be used as a small capacitance "C" in the RC network. The name "VRE" is used to designate these vertical resistor elements in the accompanying drawings.

[0028] Now for reference Figure 1The block diagram illustrates an exemplary SEU immune trigger 10 according to one aspect of the invention. The SEU immune trigger 10 includes a three-stage system: a master-level data latch 12, a slave-level data latch 14 containing vertical resistive elements, and a scan slave-level data latch 16 for rapidly transferring data through the SEU immune trigger 10. This scan slave-level data latch is used in a scan chain to provide scan chain data entries and diagnostic tests, such as Automated Test Pattern Generator (ATPG) diagnostics.

[0029] The master-level data latch 12 is a level-clocked latch known in the art, meaning that when the clock input 18 is at a first logic level, the latch is transparent, and data appearing at its data input (D) 20 is passed to its data output (Q) 22. When the clock input 18 is at a second logic level opposite to the first logic level, the data output Q 22 holds the previous data appearing at the data input D 20; that is, changes in the data input D 20 are not passed to the data output Q 22. In some embodiments of the invention, the data latch has a set input (S) 24 that forces the Q output 22 to a one or high logic state when active and a reset input (R) 26 that forces the Q output 22 to a zero or low logic state when active. The set and reset inputs of the latch are well known and commonly used to set or reset the latch to a state desired by the user. The set input (S) 24 is connected to a set line 52, which forces the Q output 22 to a logic state when an assertion active signal is on the set line 52. Reset input (R) 26 is connected to reset line 56, which forces Q output 26 to a zero logic state when an assertion active signal is on reset line 56. Those skilled in the art will understand that the master-level data latch 12 may have one, both, or neither of the set input 24 and reset input 26.

[0030] Slave data latch 14 is also a level-clocked data latch, having a data input 28 connected via line 30 to the Q output 22 of master data latch 12, a slave latch clock input CLK 32 connected to the slave latch clock line CK_S1 shown at reference numeral 34, a Q output 36, and a scan-out (SO) output 38. The Q output 36 forms the output of the SEU immune trigger 10 and can be used, for example, to set the input of a multiplexer or to programmatically connect two interconnecting conductors in a user-programmable integrated circuit. The slave latch clock line CK_S1 is arranged to provide a slave clock signal. Slave data latch 14 is transparent in response to a first state of the slave clock signal and latched in response to a second state of the slave clock signal.

[0031] The scan slave data latch 16 is also a level-clocked latch, which has a data input D 40 connected to the SO output 38 of the slave data latch 14 via line 42, and a clock input 44 and a Q output 46 connected to the SO output 48 of the SEU immune trigger 10. In some embodiments of the invention, the scan slave data latch 16 may have a set input (S) 50 and a reset input (R) 54, which force the Q output 46 to a logic state when an assertion active signal is on the set line 52, and force the Q output 46 to a zero logic state when an assertion active signal is on the reset line 56. Those skilled in the art will understand that the master data latch 12 may have one, both, or neither of the set input 50 and reset input 54.

[0032] The clock inputs 18 and 44 of the master data latch 12 and the scan slave data latch 16 are connected together to clock line 58 (denoted as CK), which is arranged to provide a clock signal. The clock input 18 to the master data latch 12 is inverted, and therefore, when the master data latch 12 is transparent in response to a first state of the clock signal, the scan slave data latch 16 is locked, and when the master data latch 12 is locked in response to a second state of the clock signal, the scan slave data latch 16 is transparent.

[0033] Multiplexer 60 has a first data input (denoted as DATA) connected to data input line 62, a second data input (denoted as SI) connected to scan input line 64, and a data output connected to data input D20 of master data latch 12 at line 66. The multiplexer's select input is connected to select line SE 68. Scan input SI 64 serves as the scan input for SEU immune trigger 10.

[0034] An advantageous use of the SEU-immune trigger 10 of the present invention is in an integrated circuit comprising a series chain of many such SEU-immune triggers 10, wherein a serial stream of data can be computed using the SI and SO inputs / outputs therefrom, for loading data into and reading data from the triggers for circuit diagnostics. Series trigger chains using conventional triggers are known and in use.

[0035] Now for reference Figure 2 The diagram illustrates that it can be used Figure 1The exemplary slave data latch 14 used in the SEU immune trigger depicted herein. The slave data latch 14 includes a switching inverter shown within dashed line 70, which includes a p-channel inverter transistor 72 connected in series with a p-channel switching transistor 74, shown as V at reference numeral 76. DD The switching inverter, shown within dashed line 70, also includes an n-channel inverter transistor 80 connected in series with an n-channel switching transistor 82 between the voltage supply potential (shown as ground at reference numeral 84) and the inverter output node 78. The gates of the p-channel inverter transistor 72 and the n-channel inverter transistor 80 are connected together to form the input node 86 of the switching inverter 70. Switching transistors 74 and 82 are used to selectively enable and disable the switching inverter, as is well known in the art.

[0036] According to embodiments of the present invention, in the process of employing 1V core transistors, p-channel switching transistor 74 and n-channel switching transistor 82 can be fabricated as core transistors. However, transistors of this size can have unacceptably high gate leakage to be used as p-channel inverter transistor 72 and n-channel inverter transistor 80. In cases where the core transistor has unacceptably high gate leakage, special transistors with a thicker gate oxide layer can be designated as inverter transistors 72 and 80. However, replacing high-voltage transistors with thicker gate oxide layers is less costly (e.g., 1.8V transistors are commonly used as I / O transistors in integrated circuits using 1V core transistors), which are already used as inverter transistors 72 and 80 in peripheral device processes.

[0037] Input D 28 is connected to the input of passgate 88, which includes a p-channel passgate 90 connected in parallel with an n-channel passgate transistor 92. The gate of the n-channel passgate 92 is connected to the clock input 32 of the slave data latch 14, which is connected to the CK_S1 clock line as indicated above, and the gate of the p-channel passgate 90 is connected to the complementary sequence of the CK_S1 clock line shown at reference numeral 94 and denoted as CK_S1_B generated by the inverter using the CK_S1 clock line. The gate of the p-channel switching transistor 74 is connected to the CK_S1 clock line, and the gate of the n-channel switching transistor 82 is connected to the CK_S1_B line. The output of passgate 88 is connected to the output node 78 of the switching inverter 70 and to a pair of inverters 96 and 98 connected in series. The output of inverter 96 is also connected at the gates of p-channel inverter transistor 72 and n-channel inverter transistor 80 to the input node 86 of switching inverter 70, this connection being through vertical resistor element 102. The output of inverter 98 on line 100 is connected to the SO output of slave data latch 14 of scan slave data latch 16 at the D input 40. Figure 1 (Ref. 38 shown in the figure).

[0038] A vertical resistor element 102 is connected between the output of inverter 96 and the gate of p-channel inverter transistor 72, and an n-channel inverter transistor 80 forms the input node 86 of the switching inverter 70 to form a time-delay regenerative feedback circuit as a loop around the switching inverter 70. The time delay is determined by the RC network formed by the vertical resistor element 102 and the combined gate capacitance of inverter transistors 72 and 80. This time delay provides SEU immunity for the SEU-immune trigger 10 of the present invention when the slave data latch 14 is in its locked mode. The output of inverter 96 is also connected to the input of inverter 104. The output of inverter 104 forms the Q output of the slave data latch 14, which drives the load of the entire SEU-immune trigger 10, such as the input state of a multiplexer or other configurable circuitry that defines its function or connects interconnects in a programmable circuit.

[0039] If the latch clock line CK_S1 34 is held high, the slave data latch 14 remains in transparent mode because both the p-channel transistor 90 and the n-channel transistor 92 of gate 88 are turned on, and whatever logic signal appears at the D input 28 of the slave data latch 14 is coupled to the output line 100 via gate 88 and inverters 96 and 98, and to the output line 36 via gate 88 and inverters 96 and 104. This data path, enabled by the high level of clock line CK_S1 (and its complementary sequence), reduces the serial data chain path from the SI input 64 of the master latch 12 to the SO output 48 of the scan slave data latch 16 via gate 88, inverter 96, and inverter 98 through the SEU-immune trigger 10. This introduces a small delay through these trigger chains and allows for fast data transfer through the trigger chains, thus allowing for rapid initial setup of all master stages of the SEU-immune trigger 10 in the chain. When slave data latch 14 is held in transparent mode, inverter 70 is disabled because both p-channel switching transistor 74 and n-channel switching transistor 82 are turned off. If slave clock line CK_S1 34 is held low, slave data latch 14 is in its locked mode.

[0040] The complete programming of the SEU immune trigger 10 is accomplished by setting CK 58 to a high logic level and CK_S1 34 to a high logic level, thereby latching the master data latch 12 to the desired state. This provides a low logic level at the clock input 18 of the master data latch 12 to latch its Q output 22, while the slave data latch 14 remains in transparent mode, thereby enabling gate 88 and turning off switching transistors 74 and 82 to disable the switching inverter 70. CK 58 must remain high for a duration sufficient to overcome the RC delay of the slave data latch 14. Once slave data latch 14 is in its final state (i.e., after an RC delay caused by the gate capacitances of vertical resistor element 102 and the p-channel inverter transistor 72 and n-channel inverter transistor 80), the slave latch clock line CK_S1 34 is set to a low logic level to turn on the switching inverter and put slave data latch 14 into regenerative mode, which latches the state of switching inverter 70 through a time-delayed regenerative feedback circuit (i.e., a feedback loop from the output of switching inverter 70, through inverter 96, back to the input of switching inverter 70 via an RC network). Trigger circuit 10 is now SEU-immune.

[0041] Those skilled in the art will readily understand, Figure 2The switching inverter 70 shown can be configured in several different ways. As a non-limiting example, the positions of switching transistors 74 and 82 and inverter transistors 72 and 80 can be reversed, with the common drain of the inverter transistors connected to output node 78, and the sources of switching transistors 78 and 82 connected to voltage supply nodes 76 and 84. Alternatively, switching transistors 78 and 82 can be eliminated, and a gate (and the necessary inverter) can be inserted in series between input node 86 and output node 78 of inverter 70. The gate will be connected to clock lines 34 and 94 of CK_S1 and CK_S1_B, such that it will be enabled when gate 88 is disabled, and disabled when gate 88 is enabled.

[0042] Those skilled in the art will understand that the signals from latch clock line CK_S1 34 and clock line CK_S1_B 94 need to be SEU-immune clock signals. Providing an SEU-immune clock signal is within the scope of those skilled in the art.

[0043] The length of the SET pulse in the SEU-immune trigger 10 of the present invention, which is not subject to SEU immunity, depends on the resistance of the vertical resistor element 102 plus the gate capacitance of the inverter transistors 72 and 80. The vertical resistor element 102 is preferably quite large, i.e., greater than about 1 MΩ. This has several consequences. First, gate leakage of the inverter transistors 72 and 80 becomes critical because the charging rate through the gate capacitance of the vertical resistor element 102 must be greater than the discharging rate of the gate capacitance caused by gate leakage. At vertical resistor resistance values ​​below about 1 GΩ, gate leakage in the core device may allow their use. Designers can easily select based on specific technologies, device geometries, and the processes used.

[0044] The core supply voltage also affects gate leakage. For example, according to one aspect of the invention, at a core supply voltage of 0.8V, a ratio of at least 3:1 between the charging current and the leakage current will ensure that the output of inverter 70 does not switch erroneously. This ratio depends on the core supply voltage (i.e., a ratio of at least 4:1 is sufficient for a core supply voltage of 1V, and a ratio of at least 5:1 is sufficient for a core supply voltage of 1.2V). In integrated circuits, if the gate leakage of the core transistor is too large, high-voltage devices (a term commonly used in integrated circuit design to refer to I / O transistors in integrated circuits employing a gate oxide thicker than that used in the core of the integrated circuit) can be advantageously used as inverter transistors 72 and 80 to provide low gate leakage, as their gate leakage is several orders of magnitude smaller than that of core transistors with thinner gate oxides. Considering the gate capacitance characteristics of inverter transistors 72 and 80, the resistance value of vertical resistor 102 can be selected by choosing the geometry of the vertical resistor or by providing more than one vertical resistor element connected in parallel.

[0045] The SEU-immune trigger 10 has a relatively long settling time, which depends on the value of the RC time constant, determined by the resistance of the vertical resistor element and the gate capacitance of the inverter transistor. This is why the SEU-immune trigger 10 of the present invention is particularly useful for triggers that are rarely programmed, such as those used to configure user-programmable circuits such as FPGAs.

[0046] Now for reference Figure 3 The cross-sectional view illustrates a typical unprogrammed antifuse device structure 110, which can be used as a vertical resistor 102 in an embodiment of the invention. The unprogrammed antifuse 110 is formed over one of a transistor gate, a metal interconnect layer, or a diffusion in a substrate or well (shown as layer 112). Layer 114 is the lower electrode of the antifuse, and layer 116 is an antifuse material layer formed over the lower electrode 114, which can be formed of a material such as doped or undoped amorphous silicon. An upper electrode 118 is formed over the antifuse material 116. Layers 114, 116, and 118 can then be etched as a stack. In some embodiments, layer 112 can be used as an etch stop layer, and in other embodiments, a separate etch stop layer (not shown) can be formed over layer 112. In some embodiments, an additional diffusion barrier layer 120 for the upper metal is also formed on the stack and etched together with the stack.

[0047] Then, a dielectric layer 122 is formed over the stack of layers 114, 116, and 118, and a metal layer is formed and connected to the top layer of the stack (120 or 118). The metal layer is shown as an inlaid copper layer 124 surrounded by a liner 126, as is known in the art. Before forming the liner 126 and the copper metal line 124, vias 128 are formed to connect to the top layer 118 or 120 of the antifuse, as is known in the art.

[0048] Antifuse structures such as those described above are well known. A non-limiting illustrative example of an antifuse device structure 110 is shown in U.S. Patent No. 5,770,885, the entire contents of which are incorporated herein by reference. The antifuse device structure 110 remains in an unprogrammed state and has a resistance in this state on the order of about 1 MΩ to greater than about 1 GΩ.

[0049] Now for reference Figure 4The cross-sectional view illustrates a typical original ReRAM element structure 130, which can be used as another form of a vertical resistor in embodiments of the present invention. The “original” ReRAM element 130 is identical to a conventional ReRAM element in every respect except that it cannot be programmed or erased, and therefore it always remains in a fully erased state at the time of manufacture. This is a high-impedance state, where its resistance depends on the electric field strength but is greater than about 10 MΩ and can exceed about 20 GΩ. This form of the vertical resistor 102 is very useful because it can provide extremely high impedance while taking up almost no layout area on the integrated circuit, as it can be fabricated on existing contacts or inter-metal vias in the integrated circuit structure. The polarity of the ReRAM element 130 is irrelevant. A non-limiting example of a ReRAM element is described in U.S. Patent 8,415,650, published April 9, 2013, the entire contents of which are incorporated herein by reference.

[0050] As we are currently focusing on Figure 4 As shown, a ReRAM element is essentially composed of two metal plates separated by a solid electrolyte layer. A ReRAM element is typically programmed by applying a voltage potential with polarity that drives metal ions from one of the metal plates into the solid electrolyte layer, and erased by applying a voltage potential with polarity that drives metal ions back to the source metal plate.

[0051] Figure 4 Some structures shown in the implementation scheme are similar to Figure 3 Some of the structures shown. Therefore, Figure 4 The existence of in Figure 3 The components in the text will be used in conjunction with the components in the text. Figure 3 The same reference numerals are used to designate them.

[0052] An unprogrammed (“raw”) ReRAM element 130 is formed over one of a transistor gate, a metal interconnect layer, or a substrate or well (shown as layer 112). Layer 132 is a diffusion barrier layer and / or an adhesion layer. Layer 134 is the lower electrode of the raw ReRAM element 130. Layer 136 is a solid electrolyte layer formed over the lower electrode 134. An upper electrode 138 is formed over the solid electrolyte layer 136. In some embodiments, a diffusion barrier layer 120 is also formed on the stack and etched together with the stack. Layers 132, 134, 136, 138, and 120 (if present) can then be etched as a stack. In some embodiments, layer 112 can be used as an etch stop layer, and in other embodiments, a separate etch stop layer (not shown) can be formed over layer 112.

[0053] As in Figure 3In one implementation, a dielectric layer 122 is then formed over the stack of layers 132, 134, 136, 138, and 120, and a metal layer is formed and attached to the top layer of the stack (120 or 138). Figure 4 In this configuration, the metal layer is shown as an inlaid copper layer 124 surrounded by a liner 126, as is known in the art. Prior to forming the liner 126 and the copper metal lines 124, vias 128 are formed to connect to the top layer 138 or 120 of the original ReRAM element structure 130, as is known in the art.

[0054] Now for reference Figure 5 The cross-sectional view shows another typical high-resistance structure 140 that can be used as a vertical resistor in an embodiment of the present invention. Figure 5 Some structures shown in the implementation scheme are similar to Figure 3 and Figure 4 Some of the structures shown. Therefore, Figure 5 The existence of in Figure 3 and Figure 4 The components corresponding to the components in the implementation scheme will be designated using the same reference numerals as those used in the figures.

[0055] A high-resistivity structure 140 is formed over one of the diffusions in the transistor gate, metal interconnect layer, substrate, or well (shown as layer 112). Layer 142 is a diffusion barrier layer and / or adhesion layer. Layer 144 is a high-resistivity material layer formed over layer 142. A second diffusion barrier layer 146 is formed over the high-resistivity material layer 144. In some embodiments, a second diffusion barrier layer 120 is also formed on the stack and etched together with the stack. Layers 142, 144, 146, and 120 (if present) can then be etched as a stack. In some embodiments, layer 112 can be used as an etch stop layer, and in other embodiments, a separate etch stop layer (not shown) can be formed over layer 112.

[0056] As in Figure 3 and Figure 4 In one implementation, a dielectric layer 122 is then formed over the stack of layers 142, 144, 146, and 120, and a metal layer is formed and attached to the top layer of the stack (120 or 146). Figure 5 In this design, the metal layer is shown as an inlaid copper layer 124 surrounded by a liner 126, as is known in the art. Prior to forming the liner 126 and the copper metal lines 124, vias 128 are formed to connect to the top layer 146 or 120 of the original ReRAM element, as is known in the art.

[0057] A variety of materials can be used to form the high-resistivity layer 144. A non-exhaustive list includes silicon-rich SiO2, tantalum-rich Ta2O5, titanium-rich TiO2, aluminum-rich Al2O3, and silicon-rich SiN. Such films can be formed using CVD, PECVD, and other deposition processes. Other process-compatible, stable, high-resistivity materials will be readily apparent to those skilled in the art. The thickness and chemical composition of these materials, as well as the deposition conditions required to deposit them to produce the desired resistance value, can be readily determined experimentally for use in specific embodiments of the invention. These design parameters are readily adjustable by those skilled in the art to achieve resistance values ​​from approximately 1 MΩ to greater than 1 GΩ.

[0058] Those skilled in the art will understand that, although in Figures 3 to 5 The diagram illustrates an inlaid copper metallization structure 124, but other types of metallization layers can be used alternatively. Those skilled in the art will readily understand how such other metallization schemes can be integrated into the present invention.

[0059] Those skilled in the art will understand that the accompanying drawings show all vertical resistors oriented with the same polarity. Such a person will also understand that, since these devices will never be programmed, the orientation of the ReRAM elements is irrelevant in any circuit disclosed herein, and they can be oriented in whatever manner best suits the layout and design.

[0060] A key advantage of the SEU immune trigger of this invention is its size. For a given resistance, the vertical resistor element is very small, allowing for a simple gate capacitance for the RC network.

[0061] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A single-event flip (SEU) immune trigger, comprising: A clock line, configured to supply a clock signal; A master-level data latch has a data input, a data output, and a clock input. The master-level data latch is in a transparent state in response to a first state of the clock signal and in a locked state in response to a second state of the clock signal. A slave data latch, the slave data latch having a data input, a data output, a scan output and a slave clock input coupled to the data output of the master data latch; A scan slave data latch has a data input, a data output, and a clock input coupled to the scan output of the slave data latch. The scan slave data latch is in a transparent state in response to a second state of the clock signal and in a locked state in response to a first state of the clock signal. as well as The slave clock line is configured to supply a slave clock signal to the slave clock input of the slave data latch, the slave data latch having a transparent state in response to a first state of the slave clock signal and a locked state in response to a second state of the slave clock signal. The slave-level data latch includes: A switching inverter is disabled when the slave data latch is in the transparent state and enabled when the slave data latch is in the locked state. The switching inverter is formed by a switching transistor and an inverter transistor. as well as A time delay regeneration feedback circuit, when in its locked state, provides a time delay longer than the time period of the SEU particles.

2. The SEU immune trigger according to claim 1, further comprising: Set signal line; and The master data latch and the scan slave data latch each include a set input coupled to the set signal line.

3. The SEU immune trigger according to claim 1, further comprising: Reset signal line; and The master-level data latch and the scan slave data latch each include a reset input coupled to the reset signal line.

4. The SEU immune trigger according to claim 1, further comprising: A multiplexer having a first data input coupled to a data signal line, a second data input coupled to a scan input signal line, a data output coupled to the data input of the master data latch, and a selection input coupled to an input selection signal.

5. The SEU immune trigger according to claim 1, wherein the slave data latch has a data output coupled to the output node of the switch inverter.

6. The SEU immune trigger of claim 1, wherein the time delay is provided by an RC network, the RC network comprising a vertical resistive element and a capacitive element, the capacitive element comprising the gate capacitance of the inverter transistor in the switching inverter, the vertical resistive element being connected in series with the capacitive element.

7. The SEU immune trigger of claim 6, wherein the vertical resistive element is formed as an unprogrammed antifuse.

8. The SEU immune trigger according to claim 6, wherein the vertical resistive element is formed as a primitive ReRAM device.

9. The SEU immune trigger according to claim 6, wherein the vertical resistive element is formed as a layer of a high-resistivity metal compound.

10. The SEU immune trigger according to claim 9, wherein the high-resistance metal compound is one of silicon-rich SiO2, tantalum-rich Ta2O5, titanium-rich TiO2, aluminum-rich Al2O3, and silicon-rich SiN.

11. The SEU immune trigger according to claim 1, wherein the switching inverter comprises: Inverter input node; as well as Inverter output node, and The switching inverter switching transistor and the inverter transistor include: A p-channel inverter transistor is connected in series with a p-channel switching transistor between a first voltage supply node and the inverter output node, and the gate of the p-channel inverter transistor is connected to the inverter input node. An n-channel inverter transistor, wherein the n-channel inverter transistor and an n-channel switching transistor are connected in series between the inverter output node and the second voltage supply node, and the gate of the n-channel inverter transistor is connected to the inverter input node, and The time delay regenerative feedback circuit includes a first inverter, the input of which is connected to the inverter output node, and the output of which is connected in series with a vertical resistor element to the inverter input node. The provided time delay is a function of the resistance of the vertical resistor element and a capacitor, the capacitor including the capacitance of the gate of the p-channel inverter transistor and the n-channel inverter transistor.

12. The SEU immune trigger of claim 11, further comprising a second inverter connected between the output of the first inverter and the scan output of the slave data latch.

13. The SEU immune trigger according to claim 12, further comprising a third inverter connected between the output of the first inverter and the output node of the SEU immune trigger.

14. A single-event flip (SEU) immune trigger, comprising: A clock line, configured to supply a clock signal; A master-level data latch having a data input, a data output, and a clock input coupled to the clock line, the master-level data latch being in a transparent state in response to a first state of the clock signal and in a locked state in response to a second state of the clock signal; A slave data latch, the slave data latch having a data input, a data output, a scan output and a slave clock input coupled to the data output of the master data latch; A scan slave data latch has a data input coupled to the scan output of the slave data latch, a data output and a clock input coupled to the clock line, the scan slave data latch being in a transparent state in response to a second state of the clock signal and in a locked state in response to a first state of the clock signal; as well as The slave clock line is configured to supply a slave clock signal to the slave clock input of the slave data latch, the slave data latch having a transparent state in response to a first state of the slave clock signal and a locked state in response to a second state of the slave clock signal. The slave-level data latch includes: A switching inverter having an input node and an output node, wherein the switching inverter is disabled when the slave data latch is in the transparent state and enabled when the slave data latch is in the locked state, the switching inverter being formed by a switching transistor and an inverter transistor; as well as A time-delay regenerative feedback circuit is coupled between the input node and the output node of the switching inverter, and the time-delay regenerative feedback circuit includes a vertical resistive element. When the inverter is in its enabled state, the vertical resistor element forms an RC network, which includes a capacitor element connected in series with the vertical resistor element, and the capacitor element includes the gate capacitance of the inverter transistor.

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