Memory cell access technology for memory systems

Abstract

This application relates to memory cell access technology for a memory system. The memory system can receive a set of commands from a host system to write data into the memory system. The memory system can analyze a set of parameters associated with the received command set. Based on the analysis of the parameters, the memory system can determine whether to use a first mode or a second mode to write the data of the command set into the memory system. The memory system can then use either the first mode or the second mode to write the data based on this determination.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 091,980, filed November 6, 2020, entitled “Memory Cell Access Technologies for Memory Systems”, by Soberanes et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to memory cell access techniques for memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of these more than two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe a device. The device may include: a memory array; and a controller coupled to the memory array and configured such that the device: receives from a host system a set of commands for writing data to the memory array; analyzes a set of parameters associated with the received command set at least in part based on the received command set; determines, at least in part based on the analyzed parameter set, whether to use a first mode to write the data of the command set to the memory array or to use a second mode to write the data to the memory array; and at least in part based on the determination, uses the first mode to write the data to the memory array.

[0007] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive from a host system a set of commands for writing data to a memory system; analyze a set of parameters associated with the command set based at least in part on the received command set; determine, at least in part on the analysis of the parameter set, whether to use a first mode or a second mode to write the data of the command set to the memory system; and at least in part on the determination to use the first mode to write the data to the memory system.

[0008] A method performed by a memory system is described. The method performed by the memory system may include: receiving a set of commands from a host system for writing data to the memory system; analyzing a set of parameters associated with the command set based at least in part on the received command set; determining, based at least in part on the analysis of the parameter set, whether to use a first mode or a second mode to write the data to the memory system; and using the first mode to write the data to the memory system based at least in part on the determination. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support memory cell access techniques for memory systems, as illustrated in the examples disclosed herein.

[0010] Figure 2 This document describes examples of systems that support memory cell access techniques for memory systems, as illustrated in the examples disclosed herein.

[0011] Figure 3-5 This describes an example of a memory system that supports memory cell access technology for memory systems, as illustrated in the examples disclosed herein.

[0012] Figure 6 A block diagram of a memory system is shown, which supports memory cell access techniques for memory systems based on examples disclosed herein.

[0013] Figure 7The flowchart illustrates one or more methods for supporting memory cell access techniques for memory systems, based on examples disclosed herein. Detailed Implementation

[0014] Some memory systems support multiple access modes, such as single-level cell (SLC) access mode, multi-level cell (MLC) access mode (e.g., two levels), three-level cell (TLC) access mode, four-level cell (QLC) access mode, or other numbers of levels. For example, a system may include a host system and a memory system coupled to the host system. The memory system may include one or more memory arrays for storing data. The one or more memory arrays may contain NAND cells for such storage. In some instances, the memory system may use SLC access mode to write data to the memory array. For example, the memory system may write a single bit of information to the corresponding memory cell, which can result in relatively high data throughput (e.g., relatively high performance in data storage), and other advantages. In some instances, the memory system may write data to the memory array according to MLC access mode. For example, a memory system can write two, three, four or more bits of information to corresponding memory cells of a memory array when operating in different access modes, and other instances, which can result in increased storage density and improved memory utilization, as well as other advantages.

[0015] However, in some cases, memory systems can operate relatively inefficiently in such access modes. For example, a memory system may experience relatively high latency and / or high error rates (e.g., due to operation in MLC access modes used for one or more relatively high-performance applications). Alternatively, a memory system may experience relatively high write amplification, for example, due to operation in SLC access modes used for relatively low-performance applications (e.g., information may be written between the SLC cache and the MLC cache a relatively high number of times), which can reduce the lifetime of the memory system (e.g., due to wear and tear from write amplification).

[0016] According to the techniques described herein, a memory system may implement one or more memory cell access techniques to write data using a first mode (e.g., SLC access mode) or a second mode (e.g., MLC access mode or other multi-bit access modes). For example, the memory system may receive a set of commands from a host system to write data to the memory system. The memory system may analyze a set of parameters associated with the command set. Based on the analysis, the memory system may determine whether to use the first mode or the second mode to write data.

[0017] For example, a memory system may include pattern tools (e.g., pattern recognition or learning tools using artificial intelligence, and other instances). The memory system may determine the pattern (e.g., usage pattern) of a command set via these pattern tools. In some instances, the memory system may determine that the pattern corresponds to a high-performance pattern. In such instances, the memory system may operate in a first mode (e.g., SLC mode) based on the pattern corresponding to the high-performance pattern. In some other instances, the memory system may determine that the pattern corresponds to a low-performance pattern. In such instances, the memory system may operate in a second mode (e.g., MLC mode or other multi-bit access mode) based on the pattern corresponding to the low-performance pattern. In some instances, the memory system may tune (e.g., train) the pattern tools. For example, the memory system may identify training events based on a set of parameters (e.g., parameters associated with a command set) that satisfy one or more thresholds. The memory system may use these training events to tune the pattern tools. Such techniques enable memory systems to identify applications associated with relatively high-performance or low-performance commands, resulting in efficient operation and improved lifespan of the memory system while ensuring relatively high performance, among other advantages. Furthermore, type identification of the memory system can also lead to efficient operation and improved lifespan of the memory system, while ensuring relatively high performance, among other advantages.

[0018] First, as referenced Figure 1-5 The features of this disclosure are described in the context of the systems and memory systems described herein. These and other features of this disclosure are illustrated by and referenced to, as shown in, references to, etc. Figure 6 and 7 The block diagrams and flowcharts related to the memory cell access technology for memory systems are further illustrated and described.

[0019] Figure 1 This is an example of a system 100 that supports memory cell access techniques for a memory system, based on examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any computing device that includes memory and processing devices.

[0022] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations as described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but it should be understood that the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, USB interfaces, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR), Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR). In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 or memory device 140 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Although in Figure 1 The example shows a memory device 130 and a memory device 140, but it should be understood that the memory system 110 may contain any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may lack either memory device 130 or memory device 140.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with memory device 130 or memory device 140 to perform operations such as reading data, writing data, erasing data, or refreshing data at memory device 130 or memory device 140, and other such operations that may generally be referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or memory device 140 to execute such commands (e.g., at a memory array within one or more memory devices 130 or memory device 140). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate the commands or operations into instructions or appropriate commands to implement the desired access to memory device 130 or memory device 140. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 or 140 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with memory devices 130 or 140 into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with memory device 130 or memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 130 or memory device 140.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic for performing the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, when reading from or writing to memory device 130 or memory device 140, data may be stored in local memory 120 and may be available in local memory 120 for subsequent retrieval or manipulation (e.g., updating) by host system 105 according to a caching strategy (e.g., in the case of reduced latency relative to memory device 130 or memory device 140).

[0029] although Figure 1 The example of memory system 110 has been described as including memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or may perform the functions attributed herein to memory system controller 115, which may be located within memory device 130 or memory device 140, respectively. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or local controller 145, or any combination thereof.

[0030] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells. In some instances, memory device 140 may (e.g., by host system 105) support random access operations with reduced latency relative to memory device 130, or may provide one or more other performance differences relative to memory device 130.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0032] In some instances, memory device 130 or memory device 140 may each include (e.g., on the same die or within the same package) a local controller 135 or local controller 145, which can perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device and may include a memory array and associated circuitry combined with a local (e.g., on-die or within-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are in different planes 165. In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data retained in the old block 170 as invalid or obsolete, and update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, such copying and remapping may be used instead of erasing and rewriting the entire old block 170, for example, due to latency or wear and tear considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0039] In some cases, an L2P table can be maintained and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data because the latest version or an updated version of the data is stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by host system 105. Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has not yet been written to or has been erased.

[0040] In some cases, the memory system controller 115, local controller 135, or local controller 145 may perform operations on memory device 130 or memory device 140 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for some or all of the pages 175 in block 170 to contain invalid data for erasure and to reuse block 170, an algorithm called "garbage collection" may be invoked to allow block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations that include, for example, selecting blocks 170 containing valid and invalid data, selecting pages 175 within the blocks containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected blocks 170. As a result, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0041] System 100 may include any number of non-transitory computer-readable media that support memory cell access technologies for memory devices. For example, host system 105, memory system controller 115, memory device 130, or memory device 140 may include or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, memory device 130, or memory device 140. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, memory device 130 (e.g., by local controller 135), or memory device 140 (e.g., by local controller 145), may cause host system 105, memory system controller 115, memory device 130, or memory device 140 to perform one or more associated functions as described herein.

[0042] System 100 may implement one or more memory cell access techniques to write data using a first mode (e.g., SLC access mode) or a second mode (e.g., MLC access mode or other multi-bit access modes). For example, memory system 110 may receive a set of commands from host system 105 to write data to memory device 130 or 140. Memory system 110 or host system 105 may analyze a set of parameters associated with the command set. System 100 (e.g., host system 105 or memory system 110) may determine whether to use the first mode or the second mode to write data based on the analysis.

[0043] System 100 may include pattern tools (e.g., pattern recognition or learning tools using artificial intelligence, and other instances). For example, pattern tools may be included in memory system 110 (e.g., memory system controller 115, memory device 130, local controller 135, etc.). System 100 may determine the pattern (e.g., usage pattern) of a command set via the pattern tools. In some instances, system 100 may determine that the pattern corresponds to a high-performance pattern. In such instances, system 100 may operate in a first mode (e.g., SLC mode) based on the pattern corresponding to the high-performance pattern. In some other instances, system 100 may determine that the pattern corresponds to a low-performance pattern. In such instances, system 100 may operate in a second mode (e.g., MLC mode) based on the pattern corresponding to the low-performance pattern. In some instances, system 100 may tune (e.g., train) the pattern tools. For example, system 100 may identify training events based on a set of parameters (e.g., parameters associated with a command set) that satisfy one or more thresholds. System 100 can use training events to tune type tools. This technique enables System 100 to identify applications associated with relatively high-performance or low-performance commands, resulting in efficient operation and improved lifespan of System 100 while ensuring relatively high performance, among other advantages.

[0044] Figure 2 This document describes an example of a system 200 that supports memory cell access techniques for memory systems, as disclosed herein. In some instances, system 200 may implement aspects of system 100. For example, system 200 may include a host system 205 and a memory system 210, which may be as described in the references... Figure 1 Examples of or including aspects of the described host system 105 or memory system 110. Memory system 210 may include firmware 215 and type tool 220. Generally, system 200 may describe an example system for implementing type tool 220 for operation in access mode 225-a or access mode 225-b, but any number or type of access mode may be used.

[0045] Although the various components of system 200 are shown as individual components for clarity, components of system 200 can be combined or additional components can be added (e.g., a type tool may be contained in firmware 215, or in the hardware of memory system 210, or in host system 205, etc.). Furthermore, components may be located differently from those shown (e.g., host system 205 may contain type tool 220, and other examples). In some instances, an operation described as being performed by one component may, alternatively, be performed by different components.

[0046] System 200 may support multiple access modes 225, such as SLC access mode, MLC access mode, TLC access mode, or QLC access mode, as well as other instances of access modes. As an illustrative example, memory system 210 may be configured to perform access operations (e.g., write operations, read operations, etc.) in access mode 225-a or access mode 225-b.

[0047] In some instances, memory system 210 may use access mode 225-a to store data in memory cells (e.g., NAND cells). As an illustrative example, access mode 225-a may be an example of SLC access mode, and memory system 210 may store a single bit of information in a memory cell within the SLC cache (e.g., a portion of the memory array associated with an operation in access mode 225-a). Alternatively, memory system 210 may use access mode 225-b to store data in memory cells. As another illustrative example, when operating in MLC access mode, the memory system may write two bits of information to the corresponding memory cell of the memory array; when operating in TLC access mode, the memory system may write three bits of information to the corresponding memory cell of the memory array; and when operating in QLC access mode, four bits of information may be written to the memory cell, and so on. In some instances, the term multilevel cell can refer to any access mode that stores two or more information bits in a single memory cell, or the term multilevel cell can refer to an access mode for storing exactly two information bits in a memory cell. When operating in access mode 225-a, memory system 210 can achieve relatively high performance (e.g., relatively high speed or throughput of access operations). Alternatively, when operating in access mode 225-b, memory system 210 can achieve relatively improved storage density.

[0048] In some instances, system 200 may be configured to have a default access mode 225-a. For example, if there is space in the SLC cache (e.g., if a portion of the memory array used for SLC operations has available memory cells), memory system 210 can operate in access mode 225-a, which can result in relatively high performance for processing operations. However, in some cases, such implementations can result in relatively high write amplification. For example, memory system 210 may store data for access operations in the SLC portion of the device and then rewrite the data to the TLC portion of the device for long-term storage to free up space in the SLC portion for subsequent access operations. Such additional procedures or erase cycles can lead to wear and tear on memory system 210, which may reduce the reliability or lifespan of memory system 210.

[0049] In some instances, host system 205 may indicate access mode 225 to memory system 210. For example, host system 205 may include a write boost component. Host system 205 may transmit one or more commands for one or more operations to memory system 210 via a data bus. Alternatively, host system 205 may transmit a write boost signal to memory system 210. The write boost signal may indicate whether memory system 210 will use access mode 225-a or access mode 225-b for access operations. As an illustrative example, if the write boost is enabled (e.g., the host device transmits a signal indicating that the write boost is enabled), memory system 210 may use access mode 225-a (e.g., if the SLC cache is available). As another example, if the write boost is disabled (e.g., the host device transmits a signal indicating that the write boost is disabled), memory system 210 may use access mode 225-b for one or more operations based on commands received from host system 205. In some instances, host system 205 can activate or deactivate the write booster based on one or more thresholds. For example, host system 205 can determine that the amount of data in the command queue meets a threshold (e.g., if it is greater than 20 megabytes (MB) in the command queue), and host system 205 can activate the write booster. As another example, host system 205 can determine that the amount of data in the command queue meets a different threshold (e.g., if it is less than 4 kilobytes (KB) in the command queue), and host system 205 can deactivate the write booster. Some write boosting techniques are activated or deactivated and can be controlled by the host system. Techniques for more dynamic access mode selectors and access mode selectors controlled by the memory system can benefit the efficiency of the memory system.

[0050] System 200 may implement one or more memory cell access techniques to efficiently determine the access mode 225 for operation. For example, memory system 210 may receive a set of commands to perform one or more access operations (e.g., host system 205 may send data for writing, and other instances of access operations). Memory system 210 may identify a set of parameters associated with the set of commands. For example, firmware 215 may determine the queue depth of the command set (e.g., the number of commands in the queue awaiting processing by the controller of memory system 210). In some instances, memory system 210 may be configured to have a threshold queue depth (e.g., an upper limit of 32 commands for the queue depth). In such instances, memory system 210 may indicate that the queue depth meets the threshold queue depth, and host system 205 may avoid transmitting additional commands based on said indication.

[0051] The parameter set may contain one or more opcodes from the command set. For example, firmware 215 may determine the opcode for each command in the command set (e.g., command type, such as write command, read command, and other instances of command type). In some instances, firmware 215 may determine the number of command types received, the frequency of command types received, etc. The parameter set may contain one or more block sizes. For example, firmware 215 may determine the size of the data associated with a command in the command set. The parameter set may contain command timestamps. For example, firmware 215 may determine the time for receiving and / or processing each command (e.g., the delay between receiving each command). The parameter set may contain LBA parameters. For example, firmware 215 may determine the LBA range of commands in the command set (e.g., the LBA range of each command).

[0052] Memory system 210 can analyze parameters associated with the received command set. For example, firmware 215 can input parameters into type tool 220 for analysis. Type tool 220 can use machine learning algorithms (e.g., AI) to analyze the input parameters. For example, type tool 220 can determine the type of the command set based on the analyzed parameters. As an illustrative example, type tool 220 can classify the command set into a high-performance case (e.g., the application of host system 205 can use low-latency operation) or a low-performance case (e.g., high-latency operation) based on the algorithm's output. In some instances, memory system 210 can determine to operate in access mode 225-a based on the analyzed parameters (e.g., type tool 220 can determine to use access mode 225 for high-performance cases). In some instances, memory system 210 can determine to operate in access mode 225-b based on the analyzed parameters (e.g., type tool 220 can determine to use access mode 225 for low-performance cases). By determining to operate in access mode 225-b, memory system 210 can avoid transferring information from being stored as part of SLC access mode to being stored as part of MLC access mode (or higher), thereby increasing the density of storage devices for long-term storage and reducing write amplification of memory system 210.

[0053] As an illustrative example, memory system 210 may determine whether to use access mode 225-a (e.g., SLC access) or access mode 225-b based on the queue depth of the command set. For example, if the queue depth meets a threshold (e.g., a relatively high queue depth) for a certain number of durations, memory system 210 may use access mode 225-a, which can improve the performance of memory system 210. Alternatively, if the queue depth fails to meet a threshold (e.g., a relatively low queue depth) for a certain number of durations, memory system 210 may determine to use access mode 225-b (e.g., TLC access), which can reduce write amplification of memory system 210. Additionally or alternatively, other thresholds may be used to determine whether to use access mode 225-a or access mode 225-b. For example, if a threshold number of events (e.g., the number of received command sets for one or more applications) is associated with a queue depth that meets the threshold (e.g., if the queue depth is greater than the threshold duration for a certain number of durations), memory system 210 may use access mode 225-a. As another example, if the command set corresponds to a relatively small LBA range, or if the information block size of the command set is relatively large, the memory system 210 may determine to use access mode 225-a (e.g., profiling tool 220 may identify high-performance applications). In some cases, such thresholds may be determined by machine algorithms of profiling tool 220. In some instances, profiling tool 220 may weight the importance of multiple parameters and determine whether the profiling is high-performance or low-performance based on the sum of weighted parameters that satisfy one or more thresholds.

[0054] In some instances, memory system 210 can tune type tool 220. For example, type tool 220 can be trained with machine learning algorithms (e.g., artificial intelligence (AI) of type tool 220) to identify high-performance types from received commands. In some instances, type tool 220 (e.g., the algorithm) can be implemented in hardware, firmware, software, or a combination thereof. In some instances, type tool 220 can be implemented by memory system 210, host system 205, or a combination thereof.

[0055] As an example, the prototyping tool 220 can identify training events based on a set of analytical parameters (e.g., parameters associated with a set of commands). For instance, the prototyping tool 220 can determine that one or more values ​​of the parameters satisfy one or more thresholds, and the prototyping tool 220 can select the set of commands associated with the satisfied thresholds as training events. The prototyping tool 220 can use training events used to train algorithms to identify performance conditions, as referenced in [reference missing]. Figure 3-5 As described. This type of technology enables system 200 to identify applications associated with relatively high-performance or low-performance commands, which can result in efficient operation and improved lifespan of the memory system, while ensuring relatively high performance, and other advantages.

[0056] Figure 3 This document describes an example of a memory system 300 that supports memory cell access techniques for memory systems, based on examples disclosed herein. In some examples, the memory system 300 may implement aspects of system 100 or system 200. For example, the memory system 300 may include firmware 315 and type tool 320, which may be as described in the references... Figure 1 and 2 Examples of the corresponding devices described or aspects including the corresponding devices. Memory system 300 may illustrate an example process for training the type tool 320 or determining whether to use one or more access modes.

[0057] The memory system 300 can receive data 305 from the host system via a data bus. For example, the memory system 300 can receive a set of commands associated with an application on the host system. The set of commands may correspond to one or more parameters. The firmware 315 can identify the set of parameters corresponding to the set of commands. For example, the firmware can determine the queue depth associated with the set of commands, one or more opcodes of the set of commands, one or more block sizes of the set of commands, one or more timestamps of the set of commands (e.g., the frequency of receiving commands), the LBA range associated with the set of commands, or any combination thereof.

[0058] The firmware can input one or more parameters to the prototyping tool 320. The prototyping tool 320 may be an instance of an algorithm for determining whether to use a first access mode or a second access mode as described herein. The prototyping tool 320 may contain one or more components or modules for training and / or for determining whether to use a first access mode (e.g., SLC access) or a second access mode (e.g., MLC, TLC, or QLC access). For example, the prototyping tool 320 may contain a clock 325 that can track timing associated with a command set (e.g., clock 325 can be used to determine whether one or more parameters satisfy a threshold duration of clock 325). The prototyping tool 320 may contain a command counter 330, an opcode tracker 335, an information block component 340, a delay component 345, or any combination thereof, and other instances of components and modules.

[0059] In some instances, memory system 300 may illustrate instances of identifying training events for tuning pattern tool 320. For example, pattern tool 320 may receive one or more parameters associated with a command set and determine whether the parameters satisfy one or more thresholds. Command counter 330 may determine whether the queue depth (QD) satisfies a threshold (e.g., equal to or greater than threshold QD) for a duration of the threshold. Opcode tracker 335 may determine whether the number of types (or the frequency of types) in the queue satisfies a threshold (e.g., the threshold "z" quantity of types or the threshold "z" frequency of types). Block component 340 may determine whether one or more block sizes satisfy a threshold (e.g., written data larger than the threshold size) or the number of block sizes of commands satisfies a threshold quantity. Latency component 345 may determine whether command latency satisfies a threshold (e.g., the difference in timestamps between each command indicates that the frequency of received commands satisfies a threshold).

[0060] In some instances, one or more components of the pattern tool 320 may be determined to satisfy one or more thresholds. The pattern tool 320 may be determined to use a command set (and associated parameters) to tune the pattern tool 320. Alternatively, one or more components may be determined to have parameters of the command set that fail to satisfy one or more thresholds, and the pattern tool 320 may avoid using the command set to train the algorithm of the pattern tool 320.

[0061] In some instances, the modeling tool 320 may determine the command set to be used for tuning, for example, based on one or more satisfied thresholds. In such instances, the modeling tool 320 may select parameters associated with the command set to be included in the training set of a machine learning algorithm. The result of the parameters may be defined as the high-performance case. As an illustrative example, the modeling tool 320 may iteratively tune one or more parameters of the algorithm and process the training set (e.g., a training set containing one or more of the selected parameter sets) until the algorithm successfully used to identify high-performance and low-performance cases satisfies the thresholds.

[0062] Such tuning can yield one or more potential benefits. For example, the modeling tool 320 can be enabled to dynamically adjust the algorithm to more efficiently activate a first access mode for high-performance applications or a second access mode for relatively low-performance applications. Alternatively, the adjusted parameters of the algorithm can be customized for different users. For example, a first user may use a first type of application with a relatively low performance threshold (e.g., streaming, email, etc.). The algorithm can be adjusted so that the first user implements a second access mode for such applications, which can extend the lifetime of the memory system 300, and other benefits. As another example, a second user may use a second type of application with a relatively high performance threshold (e.g., drawing software, games, etc.). The algorithm for the second user can be adjusted in a different manner than for the first user. For example, the algorithm can be adjusted so that the second user implements the first access mode relatively more frequently, which can improve the performance of the memory system 300, and other benefits. Therefore, the modeling tool 320 can dynamically adjust in different ways for different users throughout the lifespan of the device, which can improve the user experience.

[0063] In some instances, memory system 300 may illustrate instance procedures for determining whether to operate in a first access mode or a second access mode. For example, type tool 320 may be tuned as described herein. Type tool 320 may receive a subsequent set of commands and input them into a tuned algorithm (e.g., an algorithm with user-customized parameters). Type tool 320 may identify a high-performance mode based on the received set of commands (e.g., based on parameters associated with the commands through algorithmic execution), and memory system 300 may process the commands using a first mode based on the identified high-performance mode. Alternatively, type tool 320 may identify a low-performance mode based on the received set of commands (e.g., based on parameters associated with the commands through algorithmic execution), and memory system 300 may process the commands using a second mode based on the identified low-performance mode.

[0064] Figure 4 This document describes an example of a memory system 400 that supports memory cell access technologies for memory systems, based on examples disclosed herein. In some examples, the memory system 400 may implement aspects of system 100 or systems 200 and 300. For example, the memory system 400 may include firmware 415 and typesetting tools 420, which may be as described in reference... Figure 1-3 The described corresponding device is an example or aspect including the corresponding device. Memory system 400 may illustrate an example process for training type tool 420 or determining whether to use one or more access modes. In some instances, the operation of memory system 400 may be combined with other operations described herein, for example, with reference to... Figure 3 Or, it can be removed.

[0065] The memory system 400 can receive data 405 from the host system via a data bus. For example, the memory system 400 can receive a set of commands associated with an application on the host system. The set of commands may correspond to one or more parameters. The firmware 415 can identify the set of parameters corresponding to the set of commands. For example, the firmware can determine the queue depth associated with the set of commands, one or more opcodes of the set of commands, one or more block sizes of the set of commands, one or more timestamps of the set of commands (e.g., the frequency of receiving commands), the LBA range associated with the set of commands, or any combination thereof.

[0066] The firmware can input one or more parameters to the prototyping tool 420. The prototyping tool 420 may be an instance of an algorithm for determining whether to use a first access mode or a second access mode as described herein. The prototyping tool 420 may contain one or more components or modules for training and / or for determining whether to use a first access mode (e.g., SLC access) or a second access mode (e.g., MLC, TLC, or QLC access). For example, the prototyping tool 420 may contain a QD tracker 425, a block information component 430, an LBA range component 435, or any combination thereof, as well as other instances of components and modules.

[0067] In some instances, memory system 400 may illustrate instances of identifying training events for tuning pattern tool 420. For example, pattern tool 420 may receive one or more parameters associated with a command set and determine whether the parameters satisfy one or more thresholds. QD tracker 425 may determine whether a QD satisfies a threshold for a certain duration. In some cases, QD tracker 425 may include a command counter (e.g., a counter incremented by received commands, enabling QD tracker 425 to track the number of commands received in the command set), a QD counter (e.g., the value of a QD that can be monitored by QD tracker 425), or both. Block component 430 may determine whether the amount of data for a command satisfies a threshold (e.g., whether the number of writes with a block size of 'y' satisfies threshold 'x'). In some instances, block component 430 may include a command block size component for determining the block size of a command, a block size counter for tracking the number of times a block size is received in the command set, or a combination thereof. LBA range component 435 may be an instance of an LBA range calculator. LBA range component 435 can determine whether the range of the LBA associated with the received command meets a threshold (e.g., a relatively small LBA range may indicate relatively high performance usage).

[0068] In some instances, one or more components of the pattern tool 420 may be determined to satisfy one or more thresholds (e.g., the satisfied thresholds of one or more components may indicate high performance). The pattern tool 420 may be determined to be tuned using a set of commands (and associated parameters). Alternatively, one or more components may be determined to have parameters of the command set that fail to satisfy one or more thresholds, and the pattern tool 420 may avoid using the command set to train its algorithm.

[0069] In some instances, the modeling tool 420 may determine the command set to be used for tuning, for example, based on one or more satisfied thresholds. In such instances, the modeling tool 420 may select parameters associated with the command set to be included in the training set of a machine learning algorithm. The result of the parameters may be defined as the high-performance case. As an illustrative example, the modeling tool 420 may iteratively tune one or more parameters of the algorithm and process the training set (e.g., a training set containing one or more of the selected parameter sets) until the algorithm successfully used to identify high-performance and low-performance cases satisfies the thresholds.

[0070] Such tuning can yield one or more potential benefits. For example, the modeling tool 420 can be enabled to dynamically adjust the algorithm to more efficiently activate a first access mode for high-performance applications or a second access mode for relatively low-performance applications. Alternatively, the adjusted parameters of the algorithm can be customized for different users. For example, a first user may use a first type of application with a relatively low performance threshold (e.g., streaming, email, etc.). The algorithm can be adjusted so that the first user implements the second access mode for such applications, which can extend the lifetime of the memory system 400, and other benefits. As another example, a second user may use a second type of application with a relatively high performance threshold (e.g., drawing software, games, etc.). The algorithm for the second user can be adjusted in a different manner than for the first user. For example, the algorithm can be adjusted so that the second user implements the first access mode relatively more frequently, which can improve the performance of the memory system 400, and other benefits. Therefore, the modeling tool 420 can dynamically adjust in different ways for different users throughout the lifetime of the device, which can improve the user experience.

[0071] In some instances, memory system 400 may illustrate instance procedures for determining whether to operate in a first access mode or a second access mode. For example, type tool 420 may be tuned as described herein. Type tool 420 may receive a subsequent set of commands and input them into a tuned algorithm (e.g., an algorithm with user-customized parameters). Type tool 420 may identify a high-performance type based on the received set of commands (e.g., based on parameters associated with the commands through algorithmic execution), and memory system 400 may process the commands using a first mode based on the identified high-performance type. Alternatively, type tool 420 may identify a low-performance type based on the received set of commands (e.g., based on parameters associated with the commands through algorithmic execution), and memory system 400 may process the commands using a second mode based on the identified low-performance type.

[0072] Figure 5 This document describes an example of a memory system 500 that supports memory cell access techniques for memory systems, based on examples disclosed herein. In some examples, the memory system 500 may implement aspects of system 100 or systems 200-400. For example, the memory system 500 may include firmware 515 and typesetting tools 520, which may be as described in the references... Figure 1-3 The described corresponding device is an example or aspect comprising the corresponding device. The memory system 500 may illustrate an example process for training the type tool 520 or determining whether to use one or more access modes 525. In some instances, the operation of the memory system 500 may be combined with other operations described herein, for example, with reference to... Figure 1-4 .

[0073] The memory system 500 can receive data 505 from the host system via a data bus. For example, the memory system 500 can receive a set of commands associated with an application on the host system. The set of commands may correspond to one or more parameters. The firmware 515 can identify the set of parameters corresponding to the set of commands. For example, the firmware can determine the queue depth associated with the set of commands, one or more opcodes of the set of commands, one or more block sizes of the set of commands, one or more timestamps of the set of commands (e.g., the frequency of receiving commands), the LBA range associated with the set of commands, or any combination thereof, and other instances of parameters.

[0074] Firmware 515 can input one or more parameters to type tool 520. Type tool 520 may be an instance of an algorithm for determining whether to use a first access mode or a second access mode as described herein. For example, type tool 520 may include one or more components or modules for training and / or for determining whether to use a first access mode 525-a (e.g., SLC access) or a second access mode 525-b (e.g., MLC, TLC, or QLC access), such as those referenced herein. Figure 1-4 The components described.

[0075] The model tool 520 can determine whether it has been trained (e.g., whether the algorithm has been tuned). In some instances, the model tool 520 can determine that it has not been trained. In such instances, the model tool 520 can determine whether the parameter set contains training events (e.g., as referenced). Figure 3 and 4 (As described). Alternatively or concurrently, the type tool 520 may avoid using an algorithm to determine whether to use access mode 525-a or 525-b. For example, the type tool 520 may use a write boost (WB) flag or signal to determine whether to use access mode 525-a or 525-b, or the memory system 500 may be configured to have a default access mode 525 (e.g., default SLC cache), and other instances.

[0076] In some instances, the model tool 520 can determine that it has been trained (e.g., the machine algorithm has been trained on a high-performance scenario as described herein). In such instances, the model tool 520 can analyze parameters. The model tool 520 can classify commands (e.g., data 505) into high-performance or low-performance scenarios. In some instances, the model tool 520 can determine that the command set corresponds to a high-performance scenario. In such instances, the memory device can use access mode 525-a (e.g., SLC access mode) based on determination. In some other instances, the model tool 520 can determine that the command set does not correspond to a high-performance scenario (e.g., the algorithm's output can classify the command set as a low-performance scenario). In such instances, the memory system 500 can use access mode 525-b (e.g., MLC, TLC, or QLC access mode) based on determination.

[0077] Various operations displayed in the memory system 500 can be added, removed, or modified. For example, in addition to determining whether a command contains high-performance conditions (e.g., based on analysis parameters), the pattern tool 520 can also train the command set. The memory system 500 may contain references. Figure 1-4 The described aspects of the memory system, and vice versa.

[0078] Figure 6A block diagram 600 illustrates a memory system 605 that supports memory cell access techniques for memory systems, based on examples disclosed herein. The memory system 605 may be as described in the references... Figure 1-5 Examples of aspects of the described memory system. Memory system 605 may include command component 610, parameter component 615, mode component 620, write component 625, pattern component 630, tuning component 635, and threshold component 640. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0079] Command component 610 may receive a set of commands from the host system for writing data to the memory system. In some instances, command component 610 may receive a second set of commands for writing second data to the memory system.

[0080] Parameter component 615 can analyze the parameter set associated with the received command set. In some instances, parameter component 615 can analyze a second parameter set associated with a second command set based on a machine learning algorithm that meets a quality threshold.

[0081] The mode component 620 can determine, based on the analysis of a set of parameters, whether to use a first mode or a second mode to write the data of the command set to the memory system. In some instances, the mode component 620 can determine, based on the analysis of a second set of parameters, whether to use the first mode or the second mode to write the second data of the second command set to the memory system.

[0082] In some cases, the first mode includes an SLC mode associated with memory cells of the memory array. In some cases, the second mode includes an MLC mode, TLC mode, or QLC mode associated with memory cells of the memory array.

[0083] The write component 625 may write data to the memory system using a first mode based on determination. In some instances, the write component 625 may write second data to the memory system using either a first mode or a second mode based on determination. In some instances, the write component 625 may write second data to the memory array based on the value of a signal, a default mode, or a combination thereof.

[0084] In some instances, when using the first mode, the write component 625 can write a single data bit to a memory cell of the memory array. In some instances, when using the second mode, the write component 625 can write a set of data bits to a memory cell of the memory array.

[0085] The type component 630 can determine the type of the command set at least in part based on the set of analysis parameters, wherein determining whether to use a first mode or a second mode to write data further includes determining that the type of the command set corresponds to the first mode, wherein using the first mode to write data to the memory system is based on determining that the type of the command set corresponds to the first mode.

[0086] Tuning component 635 can determine whether the machine learning algorithm of the memory system, and is used to determine whether to use a first mode or a second mode, is tuned. In some instances, tuning component 635 can use a second set of commands to tune the machine learning algorithm, thereby using either the first mode or the second mode, or both, to write second data to the memory system based on whether the machine learning algorithm of the memory system is tuned. In some instances, tuning component 635 can use a second set of commands to tune the machine learning algorithm based on whether the machine learning algorithm fails to meet a quality threshold.

[0087] Thresholding component 640 can determine whether a machine learning algorithm in the memory system meets a quality threshold. In some instances, thresholding component 640 can determine whether a machine learning algorithm used to determine whether a first mode or a second mode fails to meet a quality threshold. In some instances, thresholding component 640 can determine whether a second set of parameters associated with a second set of commands meets one or more thresholds, wherein the machine learning algorithm is tuned based on a second set of parameters that meets one or more thresholds.

[0088] Figure 7 The illustrations depict flowcharts of one or more methods 700 supporting memory cell access techniques for memory systems, based on examples disclosed herein. Operation of method 700 can be implemented by a memory system or its components as described herein. For example, operation of method 700 can be performed as described in the references... Figure 6 The described memory system performs the functions described. In some instances, the memory system can execute a set of instructions to control the functional elements of the memory system to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0089] At 705, the memory system can receive a set of commands from the host system for writing data to the memory system. The operation of 705 can be performed according to the methods described herein. In some instances, aspects of the operation of 705 can be as described in the references... Figure 6 The command component described is used.

[0090] At 710, the memory system can analyze the parameter set associated with the received command set. The operation of 710 can be performed according to the methods described herein. In some instances, aspects of the operation of 710 can be derived from, as referenced... Figure 6 The described parameter components are used.

[0091] At point 715, the memory system can determine, based on the analysis parameter set, whether to use the first mode or the second mode to write the command set data to the memory system. The operation of point 715 can be performed according to the methods described herein. In some instances, aspects of the operation of point 715 can be derived from, as referenced... Figure 6 The described pattern components are used.

[0092] At 720, the memory system can write data to the memory system using a first mode based on a determination. The operation of 720 can be performed according to the methods described herein. In some instances, aspects of the operation of 720 can be as described in the references... Figure 6 The described writing component is used.

[0093] In some instances, the apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a set of commands from a host system to write data to a memory system; analyzing a set of parameters associated with the received command set; determining, based on the analyzed parameter set, whether to use a first mode or a second mode to write the data to the memory system; and, based on the determination, using the first mode to write the data to the memory system.

[0094] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for determining the type of a command set based on an analysis parameter set, wherein determining whether to use a first mode or a second mode to write data further includes determining that the type of the command set corresponds to the first mode, wherein using the first mode to write data to the memory system is at least partially based on determining that the type of the command set corresponds to the first mode.

[0095] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for: receiving a second set of commands for writing second data into a memory system; determining whether a machine learning algorithm of the memory system, and for determining whether to use a first mode or a second mode, is tunable; and using the second set of commands to tune the machine learning algorithm, thereby using either the first mode or the second mode, or both, to write the second data into the memory system based on determining whether the machine learning algorithm of the memory system is tunable.

[0096] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for: determining that a machine learning algorithm of the memory system meets a quality threshold; analyzing a second set of parameters associated with a second command set based on the machine learning algorithm that meets the quality threshold; determining, based on the analysis of the second set of parameters, whether to use a first mode or a second mode to write the second data of the second command set to the memory system; and using the first mode or the second mode to write the second data to the memory system based on the determination.

[0097] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for: determining whether a machine learning algorithm, using a first mode or a second mode, fails to meet a quality threshold; and using a second set of commands to tune the machine learning algorithm based on the determination that the machine learning algorithm fails to meet the quality threshold.

[0098] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for determining that a second set of parameters associated with a second set of commands satisfies one or more thresholds, wherein a machine learning algorithm may be tuned based on the second set of parameters that satisfies one or more thresholds.

[0099] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for writing second data to a memory array based on the value of a signal, a default mode, or a combination thereof.

[0100] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for writing a single data bit to a memory cell of a memory array when using a first mode.

[0101] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for writing a set of data bits to memory cells of a memory array when using the second mode.

[0102] In some instances of method 700 and the devices described herein, the parameter set includes queue depth, information block size, logical block address range, timestamp, or command type, or any combination thereof.

[0103] In some instances of method 700 and the device described herein, the first mode includes an SLC mode associated with memory cells of the memory array, and the second mode includes an MLC mode, a TLC mode, or a QLC mode associated with memory cells of the memory array.

[0104] In method 700 and some instances of the devices described herein, determining whether to use a first mode or a second mode to write data employs a machine learning algorithm implemented by a controller associated with the non-transitory computer-readable medium of the stored code storage system.

[0105] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0106] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0107] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between components via a conductive path, and in which a signal can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0109] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0110] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0111] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET accordingly can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "turned off" or "deactivated".

[0112] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "illustrative" as used herein means "serving as an example, example, or illustration" and is not "preferred" or "superior to" other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0113] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0114] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the software nature of the functions, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0115] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0116] Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0117] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these also fall under the category of computer-readable media.

[0118] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory array; as well as A controller, coupled to the memory array and configured such that the device: Receive a set of commands from the host system to write data into the memory array; The parameter set associated with the command set is analyzed, at least in part, based on the received command set; The determination of whether to use a first mode to write the data of the command set to the memory array or to use a second mode is based at least in part on the analysis of the parameter set. The first mode is used to write the data into the memory array, at least in part based on the determination; Receive a second set of commands for writing second data into the memory array; Determine whether the machine learning algorithm used to determine whether to use the first mode or the second mode has been tuned; as well as The second command set is used to tune the machine learning algorithm, thereby writing the second data into the memory array using either the first mode or the second mode, or both, based at least in part on determining whether the machine learning algorithm is tuned.

2. The device of claim 1, wherein the controller is further configured to cause the device to: The machine learning algorithm used to determine whether to use the first mode or the second mode satisfies the quality threshold; The machine learning algorithm is used to analyze the second parameter set associated with the second command set, at least in part based on the machine learning algorithm meeting the quality threshold. The determination of whether to use the first mode or the second mode to write the second data of the second command set to the memory array is based at least in part on the analysis of the second parameter set; as well as The second data is written to the memory array using either the first mode or the second mode, at least in part, based on the determination.

3. The device of claim 1, wherein the controller is further configured such that the device: Determining whether the machine learning algorithm used to determine whether the first mode or the second mode failed to meet the quality threshold; and The second command set is used to tune the machine learning algorithm, at least in part, based on the machine learning algorithm's failure to meet the quality threshold.

4. The device of claim 3, wherein the controller is further configured such that the device: A second set of parameters associated with the second command set is determined to satisfy one or more thresholds, wherein the machine learning algorithm is tuned at least in part based on the second set of parameters satisfying the one or more thresholds.

5. The device of claim 3, wherein the controller is further configured such that the device: The second data is written to the memory array based at least in part on the value of the signal, the default mode, or a combination thereof.

6. The device of claim 1, wherein the controller is further configured such that the device: When using the first mode, a single bit of the data is written to a memory cell of the memory array.

7. The device of claim 1, wherein the controller is further configured such that the device: When using the second mode, multiple bits of the data are written to memory cells of the memory array.

8. The device according to claim 1, wherein the parameter set includes queue depth, information block size, logical block address range, timestamp, or command type, or any combination thereof.

9. The device according to claim 1, wherein: The first mode includes a single-level cell (SLC) mode associated with memory cells of the memory array; and The second mode includes a multi-level cell (MLC) mode, a three-level cell (TLC) mode, or a four-level cell (QLC) mode associated with the memory cells of the memory array.

10. The device according to claim 1, wherein: Determining whether to use the first mode or the second mode to write the data employs a machine learning algorithm implemented by the controller associated with the non-transitory computer-readable medium of the code storage storage system.

11. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive a set of commands from the host system to write data into the memory system; The parameter set associated with the command set is analyzed, at least in part, based on the received command set; The determination of whether to use a first mode to write the data of the command set to the memory system or to use a second mode is based at least in part on the analysis of the parameter set. The first mode is used to write the data into the memory system, at least in part based on the determination; Receive a second set of commands for writing second data into the memory system; Determine whether the machine learning algorithm implemented by the memory system and used to determine whether to use the first mode or the second mode is tuned; as well as The second command set is used to tune the machine learning algorithm, thereby writing the second data into the memory system based at least in part on determining whether the machine learning algorithm of the memory system is tuned to use the first mode or the second mode or both.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The type of the command set is determined at least in part based on the analysis of the parameter set, wherein determining whether to use the first mode to write the data or to use the second mode to write the data further includes determining that the type of the command set corresponds to the first mode, wherein using the first mode to write the data to the memory system is at least in part based on determining that the type of the command set corresponds to the first mode.

13. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The machine learning algorithm of the memory system is determined to meet a quality threshold. The machine learning algorithm is used to analyze the second parameter set associated with the second command set, at least in part based on the machine learning algorithm meeting the quality threshold. The determination of whether to use the first mode or the second mode to write the second data of the second command set to the memory system is based at least in part on the analysis of the second parameter set; as well as The second data is written to the memory system using either the first mode or the second mode, at least in part, based on the determination.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Determining whether the machine learning algorithm used to determine whether the first mode or the second mode failed to meet the quality threshold; and The second command set is used to tune the machine learning algorithm, at least in part, based on the machine learning algorithm's failure to meet the quality threshold.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A second set of parameters associated with the second command set is determined to satisfy one or more thresholds, wherein the machine learning algorithm is tuned at least in part based on the second set of parameters satisfying the one or more thresholds.

16. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The second data is written to the memory system based at least in part on the value of the signal, the default mode, or a combination thereof.

17. A method performed by a memory system, the method comprising: Receive a set of commands from the host system to write data into the memory system; The parameter set associated with the command set is analyzed, at least in part, based on the received command set; The determination of whether to use a first mode to write the data of the command set to the memory system or to use a second mode is based at least in part on the analysis of the parameter set. The first mode is used to write the data into the memory system, at least in part based on the determination; Receive a second set of commands for writing second data into the memory system; Whether the machine learning algorithm used to determine whether to use the first mode or the second mode of the memory system is tuned; as well as The second command set is used to tune the machine learning algorithm, thereby writing the second data into the memory system based at least in part on determining whether the machine learning algorithm of the memory system is tuned to use the first mode or the second mode or both.

18. The method of claim 17, further comprising: The machine learning algorithm of the memory system is determined to meet a quality threshold. The second parameter set associated with the second command set is analyzed, at least in part, based on the machine learning algorithm satisfying the quality threshold. The determination of whether to use the first mode or the second mode to write the second data of the second command set to the memory system is based at least in part on the analysis of the second parameter set; as well as The second data is written to the memory system using either the first mode or the second mode, at least in part, based on the determination.

19. The method of claim 17, further comprising: The machine learning algorithm used to determine whether the first mode or the second mode failed to meet the quality threshold; as well as The second command set is used to train the machine learning algorithm, at least in part, based on the fact that the machine learning algorithm fails to meet the quality threshold.

Images