Display device

Abstract

A display device includes: a display panel for displaying an image during a plurality of driving frames; a panel driver for driving the display panel; and a drive controller for controlling the driving operation of the panel driver. The drive controller divides the display panel into a first display area and a second display area based on an image signal. Each of the plurality of driving frames includes a full frame driving both the first and second display areas, and a plurality of partial frames driving only the first display area. The number of the plurality of partial frames included in each of the plurality of driving frames is varied.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to display devices, and more specifically, to display devices capable of being driven at high speeds or high frequencies. Background Technology

[0002] Among various types of display devices, organic light-emitting diodes (OLEDs) display images by using organic light-emitting diodes (OLEDs) that generate light through the recombination of electrons and holes. Such OLEDs can have fast response times and are driven with low power consumption.

[0003] Organic light-emitting display devices may include pixels connected to data lines and scan lines. Typically, each pixel includes an organic light-emitting diode (OLED) and a circuit unit that controls the amount of current flowing through the OLED. The circuit unit controls the amount of current flowing from a first driving voltage (e.g., a first driving voltage source) through the OLED to a second driving voltage (e.g., a second driving voltage source) in response to a data signal, such that light with a predetermined brightness corresponding to the amount of current flowing through the OLED is emitted from the OLED.

[0004] When video is displayed on a display device, the display quality can improve with increasing operation frequency. Summary of the Invention

[0005] Embodiments of this disclosure provide a display device that can improve display quality when the display device operates at high speed or high frequency.

[0006] According to an embodiment, a display device includes: a display panel for displaying an image during a plurality of driving frames; a panel driver for driving the display panel; and a drive controller for controlling the driving operation of the panel driver.

[0007] In such an embodiment, the drive controller divides the display panel into a first display area and a second display area based on an image signal. In such an embodiment, each of the plurality of drive frames includes a full frame driving both the first and second display areas, and a plurality of partial frames driving only the first display area. In such an embodiment, the number of the plurality of partial frames included in each of the plurality of drive frames is varied.

[0008] According to an embodiment, a display device includes: a display panel for displaying an image; a panel driver for driving the display panel; and a drive controller for controlling the driving operation of the panel driver.

[0009] In such an embodiment, the drive controller divides the display panel into a first display area and a second display area based on the image signal. In such an embodiment, the drive controller provides the panel driver with full data signals corresponding to the first and second display areas during a full frame, and provides the panel driver with partial data signals corresponding to the first display area during each of a plurality of partial frames following the full frame. In such an embodiment, the number of the plurality of partial frames between two adjacent full frames is varied. Attached Figure Description

[0010] The above and other features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1A This is a perspective view of a display device according to an embodiment of the present disclosure;

[0012] Figure 1B This is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0013] Figure 1C and Figure 1D It is along Figure 1B The cross-sectional view of the display device shown is taken by line I-I'.

[0014] Figure 2A This is a plan view of the screen of a display device operating in a conventional frequency mode according to an embodiment of the present disclosure;

[0015] Figure 2B This is a plan view of the screen of a display device operating in multi-frequency mode according to an embodiment of the present disclosure;

[0016] Figure 3A This is a diagram illustrating the operation of a display device in a conventional frequency mode according to an embodiment of the present disclosure;

[0017] Figure 3B and Figure 3C This is a diagram illustrating the operation of a display device in multi-frequency mode according to an embodiment of the present disclosure;

[0018] Figure 4A This is a diagram illustrating frame data input to a display device in a conventional frequency mode according to an embodiment of the present disclosure;

[0019] Figure 4B Is showing Figure 4A A diagram of the frames of the frame data shown;

[0020] Figure 5AThis is a diagram illustrating full-frame data and partial-frame data input to a display device in multi-frequency mode according to an embodiment of the present disclosure;

[0021] Figure 5B It is shown as follows Figure 5A The diagram shown displays the full frame data and the partial frames in each of them, as well as the partial frame data.

[0022] Figure 6 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0023] Figure 7 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure;

[0024] Figure 8 This is a block diagram of a scan driver according to an embodiment of the present disclosure;

[0025] Figure 9 yes Figure 8 The circuit diagram of the j-th driver stage in the driver stage shown;

[0026] Figure 10 This is a waveform diagram showing the start signal, the first masking signal, and the second masking signal in multi-frequency mode;

[0027] Figure 11 This is a block diagram of a scan driver according to embodiments of the present disclosure; and

[0028] Figure 12A and Figure 12B This is a perspective view of a display device according to an embodiment of the present disclosure. Detailed Implementation

[0029] In the following description, the invention will be described more fully with reference to the accompanying drawings, which illustrate various embodiments. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0030] In this specification, when a component (or region, layer, or portion, etc.) is described as "on" another component, "connected to" or "coupled to" another component, this means that the component may be directly located on / directly connected to / directly coupled to the other component, or that an intermediary element may exist between the component and the other component.

[0031] The same reference numerals refer to the same components. Moreover, in order to effectively describe the technical features, the thickness, proportions, and dimensions of the components may be exaggerated in the accompanying drawings.

[0032] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of this document, the “first element,” “component,” “region,” “layer,” or “part” discussed below may be referred to as a second element, component, region, layer, or part.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” is not to be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0034] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0035] It will also be understood that, when used herein, the terms “comprising,” “including,” “containing,” and / or “having” indicate the presence of the stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0036] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "approximately" or "about" as used herein include the stated values ​​and are intended to refer to an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0037] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless interpreted in an idealized or overly formal sense, terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and are expressly defined herein.

[0038] This document describes embodiments with reference to cross-sectional views of schematic diagrams as idealized embodiments. Thus, variations in the shape of the diagrams are anticipated, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include deviations in shape, for example, due to manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of this claim.

[0039] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1A This is a perspective view of a display device according to an embodiment of the present disclosure. Figure 1B This is an exploded perspective view of a display device according to an embodiment of the present disclosure. Figure 1C and Figure 1D It is along Figure 1B The cross-sectional view of the display device is shown by line I-I'.

[0041] Reference Figure 1A and Figure 1B The display device DD can be a device activated by an electrical signal. The display device DD can be applied to electronic devices such as smartwatches, tablet PCs, laptops, personal computers (“PCs”), or smart TVs.

[0042] In an embodiment, the display device DD can display an image IM on a display surface IS in a third direction DR3, the display surface IS being parallel to each of the first direction DR1 and the second direction DR2. The display surface IS on which the image IM is displayed may correspond to the front surface of the display device DD. The image IM may include not only static images but also moving images or videos.

[0043] In this embodiment, the front (or upper) and rear (or lower) surfaces of each component are defined relative to the orientation of the displayed image IM. The front and rear surfaces may be opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3.

[0044] The spacing between the front and rear surfaces in the third direction DR3 can correspond to the thickness of the display device DD in the third direction DR3. Here, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative and can be changed to different directions.

[0045] In an embodiment, the display device DD can detect external input applied from the outside. External input can include various types of input provided from outside the display device DD. In one embodiment, for example, external input can include external input applied when a part of the user's body, such as a hand, is close to or spaced from the display device at a predetermined distance (e.g., hovering), and contact with a body part. In an embodiment, external input can take various forms, such as force, pressure, temperature, and light.

[0046] The display surface IS of the display device DD can be divided into a transparent area TA and a border area BZA. The image IM can be displayed in the transparent area TA. The user visually perceives the image IM through the transparent area TA. In an embodiment, as... Figure 1A As shown, the transparent area TA can be a rectangular shape with rounded corners. However, the transparent area TA according to this disclosure is not limited to this. In one embodiment, for example, the transparent area TA can have one of a variety of other shapes, but is not specifically limited thereto.

[0047] The border region BZA is adjacent to the transparent region TA. The border region BZA may have a predetermined color. The border region BZA may surround the transparent region TA. Therefore, the shape of the transparent region TA may be substantially defined by the border region BZA. However, the border region BZA is not limited thereto. Alternatively, the border region BZA may be configured to be adjacent to only one side of the transparent region TA, or it may be omitted. Various modifications can be made to the display device DD according to embodiments of the present disclosure, and it is not limited to any one embodiment.

[0048] In an embodiment, such as Figure 1B As shown, the display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM may include a display panel DP and an input sensor ISP.

[0049] The display panel DP according to this disclosure can be a light-emitting display panel, but is not specifically limited thereto. In one embodiment, for example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, for ease of description, embodiments of the display panel DP being an organic light-emitting display panel will be described in detail.

[0050] Reference Figure 1C In one embodiment, the input sensor ISP can be directly disposed on the display panel DP. According to embodiments of this disclosure, the input sensor ISP can be provided or formed on the display panel DP through a continuous process. In such an embodiment, where the input sensor ISP is directly disposed on the display panel DP, the adhesive film is not located between the input sensor ISP and the display panel DP. In alternative embodiments, such as... Figure 1D As shown, the internal adhesive film I_AF can be located between the input sensor ISP and the display panel DP. In such an embodiment, the input sensor ISP is not manufactured together with the display panel DP through a continuous process. In such an embodiment, the input sensor ISP can be manufactured through a different process than the process used to manufacture the display panel DP, and can then be attached or fixed to the upper surface of the display panel DP via the internal adhesive film I_AF.

[0051] The display panel (DP) generates an image, and the input sensor (ISP) obtains external coordinate information.

[0052] The window WM may include or be formed of a transparent material capable of projecting images. In one embodiment, for example, the window WM may include, or be formed of, glass, sapphire, or plastic, etc. In embodiments, such as... Figure 1C and Figure 1D As shown, the window WM can have a single-layer structure, but is not limited to this. In an alternative embodiment, for example, the window WM can have a multi-layer structure including multiple layers. In the embodiment, although in Figure 1C and Figure 1D Not shown in the diagram, but the bezel area BZA of the aforementioned display device DD (see...) Figure 1BThis can essentially be provided as an area for printing material comprising a predetermined color in one region of the window WM. According to embodiments of this disclosure, the window WM may include a light-shielding pattern WBM to define a border area BZA (see...). Figure 1B In one embodiment, for example, the light-shielding pattern WBM can be formed as a colored organic film by a coating method.

[0053] The window WM can be coupled to the display module DM via an adhesive film AF. According to embodiments of this disclosure, the adhesive film AF may include an optically clear adhesive film (“OCA”). However, the adhesive film AF is not limited thereto. Alternatively, the adhesive film AF may include a common adhesive or a pressure-sensitive adhesive. In one embodiment, for example, the adhesive film AF may include an optically clear resin (“OCR”) film or a pressure-sensitive adhesive (“PSA”) film.

[0054] An anti-reflective layer (not shown) may be further disposed between the window WM and the display module DM. The anti-reflective layer reduces the reflectivity of external light incident from the upper surface of the window WM. In embodiments, the anti-reflective layer may include a retarder and a polarizer. The retarder may be of film type or liquid crystal coated type, and may include λ / 2 retarder and / or λ / 4 retarder. The polarizer may also be of film type or liquid crystal coated type. The film type may include a stretched synthetic resin film, and the liquid crystal coated type may include liquid crystals arranged in a predetermined array. The retarder and polarizer may be implemented as a single polarizing film or together define a single polarizing film.

[0055] The display module DM can display images based on electrical signals and can send / receive information about external inputs. The display module DM can be defined as a display area DA and a non-display area NDA. The display area DA can be defined as the area projecting the image provided from the display module DM.

[0056] The non-display area NDA is adjacent to the display area DA. In one embodiment, for example, the non-display area NDA may surround the display area DA. However, the non-display area NDA is not limited thereto. In an alternative embodiment, for example, the non-display area NDA may have one of a variety of other shapes, without being specifically limited. According to an embodiment, the display area DA of the display module DM may correspond to at least a portion of the transparent area TA.

[0057] The display module DM may also include a main circuit board MCB, a flexible circuit film FCB, and a driver chip DIC. The main circuit board MCB is connected to the flexible circuit film FCB and can be electrically connected to the display panel DP. The main circuit board MCB may include multiple driving elements. The multiple driving elements may include circuit units that drive the display panel DP. The flexible circuit film FCB is connected to the display panel DP to electrically connect the display panel DP to the main circuit board MCB. The driver chip DIC may be disposed on or mounted on the flexible circuit film FCB.

[0058] The driver chip (DIC) may include driving elements for driving the pixels of the display panel (DP), such as data driving circuitry. In an embodiment, such as... Figure 1B As shown, a single flexible circuit film (FCB) may be included in the display device (DD), but is not limited thereto. In an alternative embodiment, for example, multiple flexible circuit films (FCBs) may be connected to the display panel (DP). Figure 1B An embodiment is shown in which the driver chip DIC is mounted on a flexible circuit film FCB, but this disclosure is not limited thereto. In an alternative embodiment, for example, the driver chip DIC may be mounted directly on the display panel DP. In such an embodiment, a portion of the driver chip DIC on which the display panel DP is mounted may be bent to be disposed on the rear surface of the display module DM.

[0059] The input sensor ISP can be electrically connected to the main circuit board MCB via a flexible circuit film FCB. However, embodiments of this disclosure are not limited thereto. Alternatively, the display module DM may also include a separate flexible circuit film for electrically connecting the input sensor ISP to the main circuit board MCB.

[0060] The display device DD also includes a housing EDC for housing the display module DM. The housing EDC may be coupled to the window WM to define the appearance of the display device DD. The housing EDC protects the components included in the housing EDC by absorbing impacts applied from the outside and preventing foreign objects / moisture from penetrating into the display module DM through the housing EDC. In embodiments of this disclosure, the housing EDC may be provided in an assembled form or in a form in which multiple storage components or parts are coupled to each other.

[0061] In an embodiment, the display device DD may further include: an electronic module including various functional modules for operating the display module DM; a power module for supplying the power required for the overall operation of the display device DD; a bracket coupled to the display module DM and / or the housing EDC and for dividing the internal space of the display device DD; and so on.

[0062] Figure 2A This is a plan view showing the screen of a display device operating in normal frequency mode. Figure 2BThis is a plan view showing the screen of a display device operating in multi-frequency mode. Figure 3A This is a diagram illustrating the operation of a display device in normal frequency mode. Figure 3B and Figure 3C This is a diagram illustrating the operation of the display device in multi-frequency mode.

[0063] Reference Figures 2A to 3C Embodiments of the display device DD can display images in either a regular frequency mode NFM or a multi-frequency mode MFM. In regular frequency mode NFM, the display area DA of the display device DD is not divided into multiple display areas with different operating frequencies. In such an embodiment, the display area DA in regular frequency mode NFM can operate at a single operating frequency; the operating frequency of the display area DA in regular frequency mode NFM can be defined as the regular frequency. In one embodiment, for example, the regular frequency can be 60 Hz. In regular frequency mode NFM, 60 images corresponding to frames F1 to F60 (e.g., frame F1, frame F2, frame F3, ..., frame F58, frame F59, and frame F60) can be displayed in the display area DA of the display device DD for 1 second (sec).

[0064] In Multi-Frequency Mode (MFM), the display area DA of the display device DD is divided into multiple display areas with different operating frequencies. According to embodiments of this disclosure, the display area DA in MFM may include a first display area DA1 and a second display area DA2. The first display area DA1 and the second display area DA2 are positioned adjacent to each other in a first direction DR1. The operating frequency of the first display area DA1 may be higher than the conventional frequency, and the operating frequency of the second display area DA2 may be lower than the conventional frequency. In one embodiment, for example, when the conventional frequency is 60Hz, the operating frequency of the first display area DA1 may be 80Hz, 90Hz, 100Hz, or 120Hz, etc., and the operating frequency of the second display area DA2 may be 1Hz, 20Hz, 30Hz, or 40Hz, etc.

[0065] According to embodiments of this disclosure, the first display area DA1 may be an area that displays video at high speed or high frequency (hereinafter referred to as "first image IM1"), and the second display area DA2 may be an area that displays a still image or text image with a long variation period at low speed or low frequency (hereinafter referred to as "second image IM2"). Therefore, when still images and video are simultaneously displayed on the screen of the display device DD, the display device DD can be controlled to operate in multi-frequency mode (MFM), and thus, overall power consumption can be reduced while improving the display quality of the video.

[0066] Reference Figures 3A to 3C In Multi-Frequency Mode (MFM), an image can be displayed in the display area DA of the display device DD during multiple drive frames. Each drive frame may include a full frame (FF) and partial frames. The full frame (FF) drives a first display area DA1 and a second display area DA2, while each of the partial frames drives only the first display area DA1. Each of the partial frames may have a shorter duration than the full frame. In embodiments, the number of partial frames included in each drive frame can be varied. Here, each drive frame can be defined as the interval from the start time of the current full frame to the start time of the next full frame.

[0067] In Multi-Frequency Mode (MFM), the nth drive frame (DFn) in the drive frame consists of a full frame (FF) and k partial frames. The (n+1)th drive frame (DFn+1) in the drive frame consists of a full frame (FF) and j partial frames. Here, n, k, and j are integers greater than or equal to 1, and k can have a value different from j.

[0068] According to embodiments of this disclosure, during the nth driving frame DFn, the first display area DA1 can operate at 100Hz, and the second display area DA2 can operate at 1Hz. In such an embodiment, the nth driving frame DFn can have a duration corresponding to 1 second and can include a full frame FF and 99 partial frames HF1 to HF99 (e.g., first partial frame HF1, second partial frame HF2, third partial frame HF3, ..., 97th partial frame HF97, 98th partial frame HF98, and 99th partial frame HF99). During the nth driving frame DFn, 100 first images IM1 corresponding to a full frame FF and 99 partial frames HF1 to HF99 are displayed in the first display area DA1 of the display device DD, and a second image IM2 corresponding to a full frame FF can be displayed in the second display area DA2.

[0069] During the (n+1)th driving frame DFn+1, the first display area DA1 can operate at 90Hz, and the second display area DA2 can operate at 1Hz. In such an embodiment, the (n+1)th driving frame DFn+1 can have a duration corresponding to 1 second and can include a full frame FF and 89 partial frames HF1 to HF89 (e.g., first partial frame HF1, second partial frame HF2, third partial frame HF3, ..., 87th partial frame HF87, 88th partial frame HF88, and 89th partial frame HF89). During the (n+1)th driving frame DFn+1, 90 first images IM1 corresponding to a full frame FF and 89 partial frames HF1 to HF89 are displayed in the first display area DA1 of the display device DD, and a second image IM2 corresponding to a full frame FF can be displayed in the second display area DA2.

[0070] For ease of description, a detailed description will be provided as follows: Figure 3B and Figure 3C The embodiment shown in the multi-frequency mode (MFM) has the operating frequency of the second display area DA2 fixed at 1Hz. However, the operating frequency of the second display area DA2 can be changed instead of being fixed. In one embodiment, for example, if the operating frequency of the first display area DA1 is changed to 100Hz or 90Hz, the operating frequency of the second display area DA2 can also be changed to 20Hz or 30Hz.

[0071] Figure 4A This is a diagram illustrating frame data input to a display device in a normal frequency mode according to an embodiment of the present disclosure. Figure 4B Is showing Figure 4A The diagram shows a frame of frame data. Figure 5A This is a diagram illustrating full-frame data and partial-frame data input to a display device in multi-frequency mode according to an embodiment of the present disclosure. Figure 5B It is shown as follows Figure 5A The diagram shown displays the full frame data and the partial frames in each of them, as well as the partial frame data.

[0072] Reference Figure 4A and Figure 4B In this context, the display device (DD) refers to a device for displaying images, and the main processor (HP) controls the operation of the display device (DD). According to embodiments of this disclosure, the main processor (HP) may be a graphics processing unit (“GPU”). The main processor (HP) can render frame data and provide the rendered frame data to the display device (DD). The frame data sequentially provided from the main processor (HP) can be stored in the frame memory (FM) of the display device (DD).

[0073] The frame memory FM may include a first library BK1 and a second library BK2. Each of the first library BK1 and the second library BK2 may have a size capable of storing frame data corresponding to a single frame. When the first frame data FD1 in the frame data is stored in the first library BK1, the second frame data FD2 following the first frame data FD1 may be stored in the second library BK2.

[0074] In the normal frequency mode NFM, the display device DD can read the first frame data FD1 stored in the first library BK1, and can display the image corresponding to the first frame data FD1 in the display area DA during the first frame F1. During the first frame F1, the second frame data FD2 can be written into the second library BK2 of the display device DD.

[0075] The display device DD can read the second frame data FD2 stored in the second library BK2, and can display the image corresponding to the second frame data FD2 in the display area DA during the second frame F2. During the second frame F2, the third frame data FD3 can be written into the first library BK1 of the display device DD.

[0076] The display device DD can read the third frame data FD3 stored in the first library BK1, and can display the image corresponding to the third frame data FD3 in the display area DA during the third frame F3. During the third frame F3, the fourth frame data FD4 can be written to the second library BK2 of the display device DD. In such an embodiment, the display device DD can read the fourth frame data FD4 stored in the second library BK2 during the fourth frame F4. During the fourth frame F4, the fifth frame data FD5 can be written to the first library BK1. Furthermore, the display device DD can read the fifth frame data FD5 stored in the first library BK1 during the fifth frame F5. During the fifth frame F5, the sixth frame data FD6 can be written to the second library BK2.

[0077] In the normal frequency mode NFM, through the above process, the display device DD can display an image at a normal frequency in the display area DA. According to an embodiment of this disclosure, when the normal frequency is 60Hz, each of the first frame F1 to the sixth frame F6 can have a duration corresponding to approximately 16.7 milliseconds (ms).

[0078] Reference Figure 5A and Figure 5BIn Multi-Frequency Mode (MFM), the speed at which the main processor HP renders partial frame data HD1 to HD6 (i.e., its internal processing speed) can be inconsistent. In an embodiment, the internal processing speed of the main processor HP can vary depending on the partial frame data HD1 to HD6. In such an embodiment, if the internal processing speed of the main processor HP is slower than the operating speed of the display device DD when driving the display device DD at high speed, the image may be truncated.

[0079] According to embodiments of this disclosure, in Multi-Frequency Mode (MFM), the display device DD can control the operating frequencies of the first display area DA1 and the second display area DA2 based on the internal processing speed of the main processor HP. In Multi-Frequency Mode (MFM), the operating frequencies of the first display area DA1 and the second display area DA2 can be changed according to the internal processing speed of the main processor HP.

[0080] In Multi-Frequency Mode (MFM), the full frame data FFD1 to FFD3 and partial frame data HD1 to HD6 provided by the main processor HP can be stored in the frame memory FM of the display device DD.

[0081] The frame memory FM may include a first library BK1 and a second library BK2. Each of the first library BK1 and the second library BK2 may have a size capable of storing full-frame data corresponding to a full frame. A first full-frame data FFD1 is stored in the first library BK1. The first full-frame data FFD1 is defined as data corresponding to a first display area DA1 and a second display area DA2. Subsequently, a first partial frame data HD1 and a second partial frame data HD2 following the first full-frame data FFD1 may be stored in the second library BK2. Each of the first partial frame data HD1 and the second partial frame data HD2 is defined as data corresponding to the first display area DA1.

[0082] When the nth driving frame DFn begins, the display device DD can read the first full-frame data FFD1 stored in the first library BK1, and can display the image corresponding to the first full-frame data FFD1 in the first display area DA1 and the second display area DA2 during the first full-frame FF1. During the first full-frame FF1, the first partial frame data HD1 and the second partial frame data HD2 can be written into the second library BK2 of the display device DD.

[0083] The display device DD can read the first portion of frame data HD1 and the second portion of frame data HD2 stored in the second library BK2, and can display the image corresponding to the first portion of frame data HD1 and the image corresponding to the second portion of frame data HD2 in the first display area DA1 during the first portion of frame data HF1 and the second portion of frame data HF2, respectively. During the first portion of frame data HF1 and the second portion of frame data HF2, the third portion of frame data HD3 and the fourth portion of frame data HD4 can be written into the first library BK1 of the display device DD.

[0084] The display device DD can read the third frame data HD3 and the fourth frame data HD4 stored in the first library BK1, and can display the image corresponding to the third frame data HD3 and the image corresponding to the fourth frame data HD4 in the first display area DA1 during the third frame HF3 and the fourth frame HF4, respectively. During the third frame HF3 and the fourth frame HF4, the second full frame data FFD2 can be written into the second library BK2 of the display device DD.

[0085] In Multi-Frequency Mode (MFM), through the above process, during the nth driving frame DFn, the display device DD can display the first image IM1 in the first display area DA1 at a first operating frequency and can display the second image IM2 in the second display area DA2 at a second operating frequency. According to embodiments of this disclosure, the first operating frequency can be 100Hz and the second operating frequency can be 20Hz.

[0086] When the (n+1)th driving frame DFn+1 begins, the display device DD can read the second full-frame data FFD2 stored in the second library BK2, and can display the image corresponding to the second full-frame data FFD2 in the first display area DA1 and the second display area DA2 during the second full-frame FF2. During the second full-frame FF2, the fifth part of frame data HD5 and the sixth part of frame data HD6 can be written into the first library BK1 of the display device DD.

[0087] The display device DD can read the fifth frame data HD5 and the sixth frame data HD6 stored in the first library BK1, and can display the image corresponding to the fifth frame data HD5 and the image corresponding to the sixth frame data HD6 in the first display area DA1 during the fifth frame HF5 and the sixth frame HF6, respectively. During the fifth frame HF5 and the sixth frame HF6, the third full frame data FFD3 can be written into the second library BK2 of the display device DD.

[0088] In Multi-Frequency Mode (MFM), during the (n+1)th driving frame DFn+1, the display device DD can display the first image IM1 in the first display area DA1 at a third operating frequency and can display the second image IM2 in the second display area DA2 at a fourth operating frequency. Here, the third operating frequency may be different from the first operating frequency, and the fourth operating frequency may be different from the second operating frequency. According to embodiments of this disclosure, the first operating frequency may be 100Hz, the second operating frequency may be 20Hz, the third operating frequency may be 90Hz, and the fourth operating frequency may be 30Hz. The first to fourth operating frequencies may vary, but are not limited thereto.

[0089] In Multi-Frequency Mode (MFM), the operating frequency of the first display area DA1 can be changed in units of at least one driving frame, or the operating frequency of the first display area DA1 can be determined periodically within each unit cycle corresponding to at least one driving frame. In an embodiment, the operating frequency of the first display area DA1 can be changed in real time according to the internal processing speed of the main processor HP. Therefore, even when the first display area DA1 of the display device DD is driven at high speed, image truncation in the first display area DA1 due to the reduction in the internal processing speed of the main processor HP can be effectively prevented.

[0090] In this embodiment, as the operating frequency of the first display area DA1 changes, the nth driving frame DFn and the (n+1)th driving frame DFn+1 can have different durations. In such an embodiment, the nth driving frame DFn has a first duration, and the (n+1)th driving frame DFn+1 has a second duration. Here, the first duration can be different from the second duration.

[0091] When the first operating frequency is 100Hz and the second operating frequency is 20Hz, the nth driving frame DFn may include a first full frame FF1 and four partial frames (i.e., first partial frames HF1 to fourth partial frames HF4). When the third operating frequency is 90Hz and the fourth operating frequency is 30Hz, the (n+1)th driving frame DFn+1 may include a second full frame FF2 and two partial frames (i.e., fifth partial frame HF5 and sixth partial frame HF6). The duration of each of the first partial frames HF1 to fourth partial frames HF4 may differ in magnitude from the duration of each of the fifth partial frames HF5 and sixth partial frames HF6. In one embodiment, for example, the duration of each of the first partial frames HF1 to fourth partial frames HF4 may be approximately 10ms, and the duration of each of the fifth partial frames HF5 and sixth partial frames HF6 may be approximately 11.12ms.

[0092] The duration of each of the partial frames HF1 to HF6 may be shorter than the duration of each of the first full frame FF1 and the second full frame FF2. In one embodiment, for example, the duration of each of the first full frame FF1 and the second full frame FF2 may be approximately 16.7 ms longer than the duration of each of the first partial frames HF1 to the sixth partial frames HF6.

[0093] In Multi-Frequency Mode (MFM), as the operating frequency of the first display area DA1 changes, the number of partial frames HF1 to HF4 included in the nth driving frame DFn can differ from the number of partial frames HF5 and HF6 included in the (n+1)th driving frame DFn+1. In an embodiment, for example, the nth driving frame DFn may include four partial frames HF1 to HF4, and the (n+1)th driving frame DFn+1 may include two partial frames HF5 and HF6.

[0094] According to embodiments of this disclosure, the size of the first display area DA1 may be the same as or different from the size of the second display area DA2. The size ratio of the first display area DA1 to the second display area DA2 can be used to set a first operating frequency and a second operating frequency, and to set a third operating frequency and a fourth operating frequency. In such embodiments, the size ratio of the first display area DA1 to the second display area DA2 can be changed differently depending on the usage mode of the display device DD.

[0095] Figure 6 This is a block diagram of a display device according to an embodiment of the present disclosure. Figure 7 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0096] Reference Figure 6 and Figure 7 An embodiment of the display device DD includes a display panel DP, a panel driver, and a drive controller 100. According to an embodiment of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, a light-emitting driver 350, and a voltage generator 400.

[0097] The drive controller 100 receives an image signal RGB and a control signal CTRL. The drive controller 100 generates an image data signal DATA by converting the data format of the image signal RGB into an interface specification suitable for the data driver 200. The drive controller 100 outputs a scan control signal SCS and a data control signal DCS. For example, in an embodiment, the drive controller 100 can divide the display panel DP into a first display area DA1 based on the image signal RGB (see...). Figure 2B ) and the second display area DA2 (see Figure 2BFor example, in an embodiment, when the display panel DP is in multi-frequency mode MFM (also known as "first mode") (see... Figure 3B During operation, the drive controller 100 can divide the display panel DP into a first display area DA1 based on the image signal RGB (see below). Figure 2B ) and the second display area DA2 (see Figure 2B When the display panel DP is in the normal frequency mode NFM (also known as "second mode") (see...) Figure 3A During operation, the drive controller 100 may not divide the display panel DP into the first display area DA1 (see below). Figure 2B ) and the second display area DA2 (see Figure 2B ).

[0098] The data driver 200 receives a data control signal DCS and an image data signal DATA from the drive controller 100. The data driver 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm (e.g., data lines DL1, DL2, ..., DLm), which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0099] The scan driver 300 receives a scan control signal SCS from the drive controller 100. The scan driver 300 can output a scan signal to the scan line in response to the scan control signal SCS.

[0100] Voltage generator 400 generates voltages for operating the display panel DP. In this embodiment, voltage generator 400 generates a first drive voltage ELVDD, a second drive voltage ELVSS, and an initialization voltage VINT.

[0101] The display panel DP includes initialization scan lines SIL1 to SILn (e.g., initialization scan lines SIL1, SIL2, SIL3, ..., SILn), compensation scan lines SCL1 to SCLn (e.g., compensation scan lines SCL1, SCL2, SCL3, ..., SCLn), black scan lines SWL1 to SWLn (e.g., black scan lines SWL1, SWL2, SWL3, ..., SWLn), emissivity control lines EML1 to EMLn (e.g., emissivity control lines EML1, EML2, EML3, ..., EMLn), data lines DL1 to DLm (e.g., data lines DL1, DL2, ..., DLm), and pixels PX. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, black scan lines SWL1 to SWLn, emissivity control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX can overlap with the display area DA. Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, black scan lines SWL1 to SWLn, and light emission control lines EML1 to EMLn extend in the second direction DR2. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, black scan lines SWL1 to SWLn, and light emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the first direction DR1. Data lines DL1 to DLm extend in the first direction DR1 and are arranged to be spaced apart from each other in the second direction DR2.

[0102] Multiple pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, black scan lines SWL1 to SWLn, light emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. Each of the multiple pixels PX can be electrically connected to three scan lines. In one embodiment, for example, as shown... Figure 6 As shown, the pixels in the first row can be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, and the first black scan line SWL1. In such an embodiment, the pixels in the second row can be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, and the second black scan line SWL2.

[0103] The scan driver 300 can be located in the non-display area NDA of the display panel DP. The scan driver 300 receives a scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan driver 300 can output an initialization scan signal to the initialization scan lines SIL1 to SILn, an compensation scan signal to the compensation scan lines SCL1 to SCLn, and a black scan signal to the black scan lines SWL1 to SWLn. The circuit configuration and operation of the scan driver 300 will be described in detail later.

[0104] In one embodiment, the light-emitting driver 350 can output light-emitting control signals to light-emitting control lines EML1 to EMLn. In an alternative embodiment, the scan driver 300 can be connected to the light-emitting control lines EML1 to EMLn. In such an embodiment, the scan driver 300 can output light-emitting control signals to the light-emitting control lines EML1 to EMLn.

[0105] Each of the plurality of pixels PX includes a light-emitting diode ED and a pixel circuit unit PXC for controlling the light emission of the light-emitting diode ED. The pixel circuit unit PXC may include a plurality of transistors and capacitors. The scan driver 300 may include transistors formed using the same process as the pixel circuit unit PXC.

[0106] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0107] Figure 7 It shows Figure 6 The equivalent circuit diagram of pixel PXij among the multiple pixels shown is illustrated. Each of the multiple pixels has the same circuit structure as the others. In the following description, reference will be made to… Figure 7 Provide a detailed description of pixel PXij connected to the i-th data line DLi, the j-th compensation scan line SCLj, the j-th initialization scan line SILj, and the j-th black scan line SWLj, omitting any repetitive detailed descriptions of the remaining pixels. Figure 6 and Figure 7As shown, pixel PXij is connected to the i-th data line DL1 to DLm (hereinafter referred to as "data line"), the j-th initialization scan line SILj (hereinafter referred to as "initialization scan line") among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj (hereinafter referred to as "compensation scan line") among the compensation scan lines SCL1 to SCLn, the j-th black scan line SWLj (hereinafter referred to as "black scan line") among the black scan lines SWL1 to SWLn, and the j-th light emission control line EMLj (hereinafter referred to as "light emission control line") among the light emission control lines EML1 to EMLn.

[0108] Pixel PXij includes a light-emitting diode ED and a pixel circuit unit PXC. The pixel circuit unit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a single capacitor Cst. In an embodiment, each of the first transistors T1 to T7 may be a P-type transistor having a low-temperature polycrystalline silicon (“LTPS”) semiconductor layer. However, this disclosure is not limited thereto. In an alternative embodiment, for example, the first transistors T1 to T7 may be N-type transistors using oxide semiconductor as the semiconductor layer. In another alternative embodiment, at least one of the first transistors T1 to T7 may be an N-type transistor, and the remaining transistors of the first transistors T1 to T7 may be P-type transistors. The configuration of the pixel circuit unit PXC according to this disclosure is not limited to... Figure 7 The embodiments shown are not intended to limit this disclosure. Alternatively, the configuration of the pixel circuit unit (PXC) can be modified and implemented differently.

[0109] The j-th initialization scan signal SIj, the j-th compensation scan signal SCj, the j-th black scan signal SWj, and the j-th illumination control signal EMj can be applied to pixel PXij through the initialization scan line SILj, the compensation scan line SCLj, the black scan line SWLj, and the illumination control line EMLj, respectively. The data signal Di is applied to pixel PXij through the data line DL1. The data signal Di can have the same characteristics as the input to the display device DD (see...). Figure 6 The voltage levels corresponding to the RGB values ​​of the image signal. The first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT can be applied to the pixel PXij through the first driving voltage line VL1, the second driving voltage line VL2, and the third driving voltage line VL3, respectively.

[0110] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted by the data line DLi based on the switching operation of the second transistor T2, and can then supply the drive current Id to the light-emitting diode ED.

[0111] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The second transistor T2 can be turned on according to the j-th compensation scan signal SCj received through the compensation scan line SCLj, and the data signal Di transmitted from the data line DLi can be applied to the first electrode of the first transistor T1.

[0112] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The third transistor T3 can be turned on based on the j-th compensation scan signal SCj received through the compensation scan line SCLj, and therefore, the gate electrode and the second electrode of the first transistor T1 can be connected, that is, the first transistor T1 can be connected in a diode manner.

[0113] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3, and a gate electrode connected to the initialization scan line SILj. An initialization voltage VINT is applied through the third drive voltage line VL3. The fourth transistor T4 can be turned on according to the initialization scan signal SIj received through the initialization scan line SILj, thereby applying the initialization voltage VINT to the gate electrode of the first transistor T1. Therefore, an initialization operation can be performed to initialize the voltage of the gate electrode of the first transistor T1.

[0114] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light-emitting control line EMLj.

[0115] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the light-emitting control line EMLj.

[0116] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on based on the j-th light emission control signal EMj received via the light emission control line EMLj. The first drive voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the first transistor T1 connected in a diode manner, and can then be applied to the light emission diode ED.

[0117] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the black scan line SWLj.

[0118] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first drive voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second drive voltage line VL2, which transmits the second drive voltage ELVSS.

[0119] When the j-th initialization scan signal SIj with a low level is provided through the initialization scan line SILj, the fourth transistor T4 turns on in response to the j-th initialization scan signal SIj with a low level. The initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first transistor T1 is initialized by the initialization voltage VINT.

[0120] Next, when a low-level j-th compensation scan signal SCj is supplied through the compensation scan line SCLj, the third transistor T3 is turned on. The third transistor T3, with the first transistor T1 turned on, is connected in a diode configuration and can be forward biased. Furthermore, the second transistor T2 is turned on by the low-level j-th compensation scan signal SCj. Then, a compensation voltage “Di-Vth” obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the voltage of the data signal Di supplied from the data line DL1 is applied to the gate electrode of the first transistor T1. That is, the potential of the gate electrode of the first transistor T1 can be the compensation voltage, which is obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the voltage of the data signal Di, i.e., “Di-Vth”.

[0121] A first driving voltage ELVDD and a compensation voltage (Di-Vth) can be applied to both ends of a capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in the capacitor Cst.

[0122] When a low-level black scan signal SWj is applied through the black scan line SWLj, the seventh transistor T7 is turned on. A portion of the drive current Id can flow through the seventh transistor T7 as a bypass current Ibp.

[0123] When the light-emitting diode (ED) emits light, even if the minimum current of the first transistor T1 used to display a black image flows as the drive current, the black image cannot be properly displayed. Therefore, in this embodiment, the seventh transistor T7 in pixel PXij can allocate a portion of the minimum current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the ED. Here, the minimum current of the first transistor T1 refers to the current under the condition that the first transistor T1 is turned off because its gate-source voltage (Vgs) is less than its threshold voltage (Vth). Thus, the minimum drive current (e.g., approximately 10 picoamperes (pA) or less) under the condition that the first transistor T1 is turned off is applied to the ED, and thus represents the image with black brightness. When the minimum drive current for displaying a black image flows, the bypass current Ibp is greatly affected. On the other hand, when a large drive current flows to display an image such as a regular image or a white image, the bypass current Ibp is hardly affected. Therefore, when the drive current for displaying a black image flows, the luminous current Ied of the light-emitting diode ED, obtained by subtracting the bypass current Ibp flowing through the seventh transistor T7 from the drive current Id, has the minimum current required to achieve a level capable of accurately rendering a black image. Thus, contrast can be improved by using the seventh transistor T7 to achieve an image with accurate black brightness.

[0124] Next, the j-th light-emitting control signal EMj supplied from the light-emitting control line EMLj changes from high to low. The fifth transistor T5 and the sixth transistor T6 are turned on by the low-level light-emitting control signal EMj. Then, a drive current Id appears, corresponding to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Id is supplied to the light-emitting diode ED through the sixth transistor T6, and the light-emitting current Ied flows into the light-emitting diode ED.

[0125] Figure 8 This is a block diagram of a scan driver according to an embodiment of the present disclosure. Figure 9 yes Figure 8 The circuit diagram of the j-th driver stage is shown. Figure 10 This is a waveform diagram showing the start signal, the first masking signal, and the second masking signal in multi-frequency mode.

[0126] Reference Figure 8 An embodiment of the scan driver 300 includes driver levels ST0 to STn (e.g., driver levels ST0, ST1, ST2, ..., STk, STk+1, STk+2, ..., STn). Each of the driver levels ST0 to STn is connected from... Figure 6The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a masking signal. The masking signal may include a first masking signal MS1 and a second masking signal MS2. Each of the drive stages ST0 to STn also receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 6 The voltage generator 400 shown is provided.

[0127] Also refer to Figure 10 In multi-frequency mode (MFM), a first masking signal MS1 and a second masking signal MS2 are provided to some of the drive levels STk to STn among the drive levels ST0 to STn, and the first masking signal MS1 and the second masking signal MS2 are used to mask the scan signal supplied to the second display area DA2 at a predetermined level.

[0128] In an embodiment, driver stages ST0 to STn output compensation scan signals SC0 to SCn (e.g., compensation scan signals SC0, SC1, SC2, ..., SCk-1, SCk, SCk+1, SCk+2, ..., SCn), respectively. Each of driver stages ST0 to STn may include a first output terminal for outputting the corresponding compensation scan signal. A corresponding compensation scan line is connected to the first output terminal of each of driver stages ST1 to STn. Compensation scan signals SC1 to SCn are provided via compensation scan lines SCL1 to SCLn, respectively. In an embodiment, the first output terminal of the first driver stage ST1 of driver stages ST1 to STn is connected to the corresponding first compensation scan line SCL1, and the first compensation scan signal SC1 is supplied to the first compensation scan line SCL1.

[0129] The corresponding initialization scan line can be connected to the first output terminal of each of the driver stages ST0 to STk-1 in the driver stages ST0 to STn. The compensation scan signals SC0 to SCk-1 output from the first output terminals of the driver stages ST0 to STk-1 are respectively provided to the initialization scan lines SIL1 to SILk. In an embodiment, the first output terminal of the first driver stage ST1 in the driver stages ST0 to STk-1 is connected to the corresponding second initialization scan line SIL2, and the first compensation scan signal SC1 is supplied to the second initialization scan line SIL2. According to an embodiment of this disclosure, the first compensation scan signal SC1 can be supplied as a second initialization scan signal to the second initialization scan line SIL2.

[0130] The driver stages STk to STn in the driver stages ST0 to STn also include a second output terminal. The corresponding initialization scan lines can be connected to the second output terminals of the driver stages STk to STn. The initialization scan signals SIk to SIn-1 (e.g., initialization scan signals SIk, SIk+1, ..., SIn-1) output from the second output terminals of the driver stages STk to STn are respectively provided to the initialization scan lines SILk+1 to SILn (e.g., initialization scan lines SILk+1, SILk+2, ..., SILn). In an embodiment, the second output terminal of the kth driver stage STk in the driver stages STk to STn is connected to the corresponding (k+1)th initialization scan line SILk+1, and the kth initialization scan signal is supplied to the (k+1)th initialization scan line SILk+1. In such an embodiment, according to an embodiment of this disclosure, the kth initialization scan signal SIk can be supplied to the (k+1)th initialization scan line SILk+1 as the (k+1)th initialization scan signal.

[0131] Here, the first initialization scan line SIL1 to the kth initialization scan line SILk among the n initialization scan lines SIL1 to SILn are arranged in the first display area DA1 (see [reference]). Figure 2B In the n initialization scan lines SIL1 to SILn, the (k+1)th initialization scan line SILk+1 to the nth initialization scan line SILn is arranged in the second display area DA2 (see...). Figure 2B In the n compensation scan lines SCL1 to SCLn, the first compensation scan line SCL1 to the kth compensation scan line SCLk are arranged in the first display area DA1 (see...). Figure 2B In the second display area DA2, the (k+1)th compensation scan line SCLk+1 to the nth compensation scan line SCLn of the n compensation scan lines SCL1 to SCLn are arranged (see...). Figure 2B )middle.

[0132] exist Figure 8 In the middle, not shown Figure 6 The black scan lines SWL1 to SWLn are shown in the diagram. In an embodiment, each of the drive stages ST1 to STn of the scan driver 300 may be connected to the corresponding black scan line, but this disclosure is not limited thereto. Alternatively, in addition to the drive stages ST1 to STn, the scan driver 300 may also include drive stages for providing black scan signals to the black scan lines SWL1 to SWLn respectively.

[0133] Driver stage ST0 may receive a start signal FLM as a carry signal. Each of driver stages ST1 to STn receives a carry signal from the preceding driver stage. In one embodiment, for example, driver stage ST1 receives a carry signal from the preceding driver stage ST0, and driver stage ST2 receives a carry signal from the preceding driver stage ST1. According to embodiments of this disclosure, the carry signal may be the same signal as the compensation scan signal output from the preceding driver stage ST1. The compensation scan signal output from the immediately preceding driver stage may be provided as a carry signal to the first driver stage ST1 to the kth driver stage STk among driver stages ST1 to STn. Alternatively, the initialization scan signal output from the immediately preceding driver stage may be provided as a carry signal to the (k+1)th driver stage STk+1 to the nth driver stage STn among driver stages ST1 to STn. However, this disclosure is not limited thereto. In embodiments, a carry signal output from one of the previous driver stages may be provided to each of driver stages ST1 to STn.

[0134] In Multi-Frequency Mode (MFM), a first masking signal MS1 and a second masking signal MS2 are provided to some of the driver levels STk to STn among the driver levels ST0 to STn, and the first masking signal MS1 and the second masking signal MS2 are used to mask the scan signal supplied to the second display area DA2 at a predetermined level. According to embodiments of this disclosure, the first masking signal MS1 and the second masking signal MS2 may not be provided to some of the driver levels ST0 to STk-1 among the driver levels ST0 to STn. Figure 9 The diagram schematically illustrates drive stage STj (i.e., the j-th drive stage) among drive stages STk to STn, with a first masking signal MS1 and a second masking signal MS2 provided to drive stage STj.

[0135] Figure 8 Each of the driver levels STk to STn shown may include the same circuit configuration as the j-th driver level STj. In the following text, the j-th driver level STj will be referred to as "driver level STj".

[0136] Reference Figure 9 An embodiment of the driver stage STj includes a driver circuit DC, a masking circuit, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, and a fifth input terminal IN5, a first voltage terminal V1 and a second voltage terminal V2, and a first output terminal OUT1 and a second output terminal OUT2. The masking circuit may include a first masking circuit MSC1 and a second masking circuit MSC2.

[0137] The driving circuit DC includes driving transistors PT1 to PT7 and driving capacitors PC1 and PC2. The driving circuit DC receives a first clock signal CLK1, a second clock signal CLK2, and a carry signal CRj-1 through the first input terminal IN1, the second input terminal IN2, and the third input terminal IN3, respectively. The driving circuit DC receives a first voltage VGL and a second voltage VGH through the first voltage terminal V1 and the second voltage terminal V2, respectively. The driving circuit DC outputs the j-th compensation scan signal SCj and the j-th initialization scan signal SIj through the first output terminal OUT1 and the second output terminal OUT2, respectively. The carry signal CRj-1 received through the third input terminal IN3 can be the (j-1)-th compensation scan signal output from the previous driving stage.

[0138] In an embodiment, Figure 8 The first input terminal IN1 of each of the drive stages ST0 to STn (e.g., odd-numbered drive stages) shown receives the first clock signal CLK1, and Figure 8 In the illustrated drive stages ST0 to STn, the second input terminal IN2 of each of the drive stages (e.g., odd-numbered drive stages) receives the second clock signal CLK2. In such an embodiment, the first input terminal IN1 of each of the remaining drive stages ST0 to STn (e.g., even-numbered drive stages) receives the second clock signal CLK2, and the second input terminal IN2 of each of the remaining drive stages ST0 to STn (e.g., even-numbered drive stages) receives the first clock signal CLK1.

[0139] The first driving transistor PT1 is connected between the third input terminal IN3 and the first node N1, and includes a gate electrode connected to the first input terminal IN1. The second driving transistor PT2 is connected between the second voltage terminal V2 and the third node N3, and includes a gate electrode connected to the second node N2. The third driving transistor PT3 is connected between the third node N3 and the first node N1, and includes a gate electrode connected to the second input terminal IN2.

[0140] The fourth driving transistor PT4 is connected between the second node N2 and the first input terminal IN1, and includes a gate electrode connected to the first node N1. The fifth driving transistor PT5 is connected between the second node N2 and the first voltage terminal V1, and includes a gate electrode connected to the first input terminal IN1. The sixth driving transistor PT6 is connected between the second voltage terminal V2 and the first output terminal OUT1, and includes a gate electrode connected to the second node N2. The seventh driving transistor PT7 is connected between the first output terminal OUT1 and the second input terminal IN2, and includes a gate electrode connected to the first node N1.

[0141] The first driving capacitor PC1 is connected between the first node N1 and the first output terminal OUT1. The second driving capacitor PC2 is connected between the second voltage terminal V2 and the second node N2.

[0142] The first masking circuit MSC1 includes a first masking transistor MT1. The first masking transistor MT1 is connected between a second voltage terminal V2 and a second output terminal OUT2, and includes a gate electrode connected to a fourth input terminal IN4. The second masking circuit MSC2 includes a second masking transistor MT2. The second masking transistor MT2 is connected between a first output terminal OUT1 and a second output terminal OUT2, and includes a gate electrode connected to a fifth input terminal IN5.

[0143] The first masking circuit MSC1 stops (or masks) the output of the j-th initialization scan signal SIj in response to the first masking signal MS1 received via the fourth input terminal IN4. The second masking circuit MSC2 stops (or masks) the output of the j-th compensation scan signal SCj in response to the second masking signal MS2 received via the fifth input terminal IN5.

[0144] Reference Figure 8 , Figure 9 and Figure 10 The start signal FLM supplied to the scan driver 300 is activated at the start point of each of the full frames FF1 to FF3 and at the start point of each of the partial frames HF1 to HF6. During each of the full frames FF1 to FF3, the start signal FLM is generated with a first period corresponding to the duration of each of the full frames FF1 to FF3; during each of the partial frames HF1 to HF6, the start signal FLM is generated with a second period corresponding to the duration of each of the partial frames HF1 to HF6. The second period may differ in size from the first period. According to embodiments of this disclosure, the first period may be larger than the second period.

[0145] In an embodiment, the first masking signal MS1 and the second masking signal MS2 may have opposite phases. In such an embodiment, the inactive section of the first masking signal MS1 corresponds to the active section of the second masking signal MS2, and the active section of the first masking signal MS1 corresponds to the inactive section of the second masking signal MS2. Therefore, the first masking transistor MT1 and the second masking transistor MT2 can be alternately turned on by the first masking signal MS1 and the second masking signal MS2. According to an embodiment of this disclosure, the first masking signal MS1 is disabled during full frames FF1, FF2, and FF3, and activated during the first partial frame HF1 to the sixth partial frame HF6. In such an embodiment, the second masking signal MS2 is activated during full frames FF1, FF2, and FF3, and disabled during the first partial frame HF1 to the sixth partial frame HF6.

[0146] In this embodiment, during full frames FF1, FF2, and FF3, the first masking signal MS1 has a first level (e.g., a high level), and the first masking transistor MT1 is turned off in response to the first masking signal MS1. The second voltage terminal V2 and the second output terminal OUT2 are electrically isolated from each other via the turned-off first masking transistor MT1.

[0147] During full frames FF1, FF2, and FF3, the second masking signal MS2 has a second level (e.g., low level), and the second masking transistor MT2 is turned on in response to the second masking signal MS2. The first output terminal OUT1 and the second output terminal OUT2 are electrically connected to each other via the turned-on second masking transistor MT2. When the first output terminal OUT1 and the second output terminal OUT2 are electrically connected to each other, the j-th compensation scan signal SCj output through the first output terminal OUT1 can be provided to the second output terminal OUT2 through the turned-on second masking transistor MT2. Therefore, during full frames FF1 and FF2, the j-th driver stage STj can output the j-th compensation scan signal SCj and the j-th initialization scan signal SIj through the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0148] In this embodiment, during the period from the first partial frame HF1 to the sixth partial frame HF6, the first masking signal MS1 is at a low level, and the first masking transistor MT1 is turned on in response to the first masking signal MS1. The second voltage terminal V2 and the second output terminal OUT2 are electrically connected to each other through the turned-on first masking transistor MT1. Therefore, during the period from the first partial frame HF1 to the sixth partial frame HF6, the j-th initialization scan signal SIj output from the second output terminal OUT2 is disabled.

[0149] During the first partial frame HF1 to the sixth partial frame HF6, the second masking signal MS2 is high, and the second masking transistor MT2 is turned off in response to the second masking signal MS2. The first output terminal OUT1 and the second output terminal OUT2 are electrically isolated from each other via the turned-off second masking transistor MT2.

[0150] Even when the k-th compensation scan signal SCk is output through the first output terminal OUT1 of the k-th driver stage STk, the k-th compensation scan signal SCk may not be provided to the second output terminal OUT2. Furthermore, the k-th initialization scan signal SIk can be disabled by the second voltage VGH supplied to the second output terminal OUT2 of the k-th driver stage STk through the conducting first masking transistor MT1. Therefore, during the first partial frame HF1 to the sixth partial frame HF6, the driver stages from the (k+1)-th driver stage STk+1 to the n-th driver stage STn, which receive the k-th initialization scan signal SIk as a carry signal, are not activated. Therefore, during the first partial frame HF1 to the sixth partial frame HF6, scan signals are not supplied to the second display area DA2 (see...). Figure 2B ), so that in the second display area DA2 (see Figure 2B The image is not displayed in the text.

[0151] Figure 11 This is a block diagram of a scan driver according to an embodiment of the present disclosure.

[0152] Figures 8 to 10 The second display area DA2 is shown (see [reference]). Figure 2B The position and size of the display device DD (see Figure 2B An embodiment of the scan driver 300 with a fixed structure in the second display area DA2 (see [reference]) is described, and a first masking signal MS1 and a second masking signal MS2 are provided to the scan driver 300. However, this disclosure is not limited thereto. In an embodiment, in the second display area DA2 (see [reference])... Figure 2B When the position and size of ) change, Figure 11 The example shown is applied to the display device DD (see...) Figure 2B The scan driver 301 can be structurally different from... Figure 8 The scan driver 300 shown is shown.

[0153] Reference Figure 11 An embodiment of scan driver 301 includes drive levels ST0 to STn (e.g., drive levels ST0, ST1, ST2, ..., STk, STk+1, STk+2, ..., STn). Each of drive levels ST0 to STn is connected from... Figure 6The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a first masking signal MS1, and a second masking signal MS2.

[0154] In the embodiments, reference is also made to Figure 10 In multi-frequency mode (MFM), a first masking signal MS1 and a second masking signal MS2 can be provided to driver stages ST0 to STn. The first masking signal MS1 and the second masking signal MS2 are signals that mask the scan signal supplied to the second display area DA2 at a predetermined level. In such an embodiment, each of the driver stages ST0 to STn may include a driver circuit DC (… Figure 9 (as shown) and the first masking circuit MSC1 and the second masking circuit MSC2 ( Figure 9 (As shown in the diagram). Therefore, when the position and size of the second display area DA2 change in the display device DD, the scan signal can be masked based on the changed position and size of the second display area DA2.

[0155] In an embodiment, each of the drive stages ST0 to STn may include a first output terminal for outputting a corresponding compensation scan signal and a second output terminal for outputting a corresponding initialization scan signal. Figure 11 The circuit configuration of each of the drive stages ST0 to STn shown is... Figure 9 The circuit configuration of the j-th drive stage STj shown is similar, and therefore any repeated detailed descriptions of it will be omitted.

[0156] Figure 12A This is a perspective view showing a display device in an unfolded state according to an embodiment of the present disclosure. Figure 12B It is shown Figure 12A The image shows a perspective view of the display device in a folded state.

[0157] Figure 12A and Figure 12B The illustration shows an embodiment of the display device F_DD as a mobile phone. However, this disclosure is not limited thereto. Alternatively, the display device F_DD can be a tablet PC, smartphone, personal digital assistant (“PDA”), portable multimedia player (“PMP”), game console, or watch-type electronic device, etc. For example, embodiments of this disclosure can also be applied to small and medium-sized electronic devices such as personal computers (“PCs”), notebook computers, kiosks, car navigation units, and cameras, but are not limited thereto, in addition to large electronic devices such as televisions or outdoor billboards. Alternatively, these embodiments can be applied to other electronic devices as long as they do not depart from the concept of this disclosure.

[0158] The display device F_DD includes a display area DA and a non-display area NDA. The display device F_DD can display images IM1 and IM2 through the display area DA. In the unfolded state of the display device F_DD, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The non-display area NDA surrounds the display area DA.

[0159] The display area DA may include a first non-folded area NFA1, a folded area FA, and a second non-folded area NFA2. The folded area FA may be bent around a folding axis FX extending in the second direction DR2.

[0160] When the display device F_DD is folded, the first non-folded region NFA1 and the second non-folded region NFA2 can face each other. In this folded state, the display area DA is not exposed to the outside; this can be referred to as the "inward folded state." When the display device F_DD is folded, the first non-folded region NFA1 and the second non-folded region NFA2 can be opposite each other. In this folded state, the display area DA is exposed to the outside; this can be referred to as the "outward folded state."

[0161] In one embodiment, the display device F_DD may perform only one of the inward folding operation and the outward folding operation. Alternatively, the display device F_DD may perform both the inward folding operation and the outward folding operation. In such an embodiment, the folding region FA of the display device F_DD may be folded inward and outward. Alternatively, a portion of the display device F_DD may be folded inward, and another portion may be folded outward.

[0162] Figure 12A and Figure 12B An embodiment is shown that includes a single folded region FA and two non-folded regions NFA1 and NFA2. However, the number of folded regions and non-folded regions is not limited thereto. In one embodiment, for example, the display device F_DD may include a plurality of non-folded regions and a plurality of folded regions, wherein the number of the plurality of non-folded regions is greater than two, and each of the plurality of folded regions is situated between adjacent non-folded regions.

[0163] Figure 12A and Figure 12B An embodiment is shown in which the folding axis FX is parallel to the short edge of the display device F_DD. However, this disclosure is not limited thereto. In an alternative embodiment, for example, the folding axis FX may extend in a direction parallel to the long edge of the display device F_DD (e.g., a first direction DR1). In such an embodiment, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 may be arranged sequentially in a second direction DR2.

[0164] The display area DA of the display device F_DD may include multiple display areas DA1 and DA2. In an embodiment, such as Figure 12A As shown, for example, the display area DA of the display device F_DD may include two display areas DA1 and DA2. However, in embodiments, the number of display areas included in the display area DA is not limited to this.

[0165] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. In one embodiment, for example, the first display area DA1 may be the area displaying a first image IM1. The second display area DA2 may be the area displaying a second image IM2. In one embodiment, for example, the first image IM1 may be a video, and the second image IM2 may be a text image or a still image with a long change period.

[0166] In normal frequency mode, embodiments of the display device F_DD can drive both the first display area DA1 and the second display area DA2 at a normal frequency. In multi-frequency mode, such embodiments of the display device F_DD can drive the first display area DA1, which displays the first image IM1, at an operating frequency higher than the normal frequency, and can drive the second display area DA2, which displays the second image IM2, at an operating frequency lower than the normal frequency. The display device F_DD can increase the operating frequency of the first display area DA1, thereby improving the video display quality. The display device DD can reduce power consumption by decreasing the operating frequency of the second display area DA2.

[0167] In one embodiment, the size of each of the first display area DA1 and the second display area DA2 can be a preset size and can be changed by an application. In another embodiment, the first display area DA1 may correspond to a first non-folding area NFA1, and the second display area DA2 may correspond to a second non-folding area NFA2. In such an embodiment, a portion of the folded area FA may correspond to the first display area DA1, and the remaining portion of the folded area FA may correspond to the second display area DA2.

[0168] In one embodiment, the first display area DA1 may correspond to a portion of the first non-folding area NFA1, and the second display area DA2 may correspond to the remainder of the first non-folding area NFA1, the folding area FA, and the second non-folding area NFA2. In such an embodiment, the size of the first display area DA1 may be smaller than the size of the second display area DA2.

[0169] In one embodiment, the first display area DA1 may correspond to a portion of the first non-folding area NFA1, the folding area FA, and the second non-folding area NFA2, and the second display area DA2 may be the remaining portion of the second non-folding area NFA2. In such an embodiment, the size of the second display area DA2 may be smaller than the size of the first display area DA1.

[0170] In an embodiment, such as Figure 12B As shown, when the folded area FA is folded, the first display area DA1 can correspond to the first non-folded area NFA1, and the second display area DA2 can correspond to the folded area FA and the second non-folded area NFA2.

[0171] Figure 12A and Figure 12B An embodiment of a foldable display device F_DD is shown. However, this disclosure is not limited thereto. In one embodiment, for example, the display device may be a rollable display device.

[0172] In embodiments of the present invention, as described therein, the display device can drive a first display area for displaying video and a second display area for displaying still images at different operating frequencies. In such embodiments, by increasing the operating frequency of the first display area for displaying video to a higher frequency than usual, the display quality of the first display area can be improved. In such embodiments, by changing the operating frequency of the first display area, degradation of display quality due to differences in the data processing speed of the main processor for each frame can be prevented.

[0173] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0174] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes and modifications in form and detail may be made to the invention without departing from the spirit and scope of the invention as defined by the claims.

Claims

1. A display device, wherein, The display device includes: The display panel shows the image during multiple driving frames; Panel driver, driving the display panel; and The drive controller controls the drive operation of the panel driver. The drive controller divides the display panel into a first display area and a second display area based on the image signal. Each of the plurality of driving frames includes a full frame that drives both the first display area and the second display area, as well as a plurality of partial frames that drive only the first display area and not the second display area. The number of the plurality of partial frames included in each of the plurality of driving frames is changed. Wherein, the nth driving frame among the plurality of driving frames comprises k partial frames, and the (n+1)th driving frame among the plurality of driving frames comprises j partial frames. Where k and j are integers greater than or equal to 1, and k and j have different values ​​from each other.

2. The display device according to claim 1, wherein, The nth driving frame has a first duration, and The (n+1)th driving frame has a second duration. The first duration is different from the second duration.

3. The display device according to claim 2, wherein, The duration of each of the k partial frames is different from the duration of each of the j partial frames.

4. The display device according to claim 1, wherein, The duration of each of the plurality of partial frames is shorter than the duration of the entire frame.

5. The display device according to claim 1, wherein, The display panel includes: Multiple pixels, connected to multiple data lines and multiple scan lines, and The panel driver includes: Data driver, driving the multiple data lines; and The scan driver drives the multiple scan lines.

6. The display device according to claim 5, wherein, The scan driver sequentially drives the plurality of scan lines during the entire frame, and The scan driver sequentially drives only the scan line corresponding to the first display area among the plurality of scan lines during each of the plurality of partial frames, and stops driving the scan line corresponding to the second display area among the plurality of scan lines.

7. The display device according to claim 6, wherein, The drive controller provides a masking signal to the scan driver, and The scan driver stops driving the scan line corresponding to the second display area in response to the masking signal.

8. The display device according to claim 7, wherein, The scan driver includes multiple drive stages respectively connected to the multiple scan lines, and The first of the plurality of driver stages receives the start signal.

9. The display device according to claim 8, wherein, Each of the plurality of drive levels includes: The driving circuit outputs the first scan signal to the first output terminal; and A masking circuit that controls the output of the first scan signal to the second output terminal in response to the masking signal.

10. The display device according to claim 9, wherein, The first output terminal of the j-th driver stage of the plurality of driver stages is connected to one of the scan lines corresponding to the pixels arranged in the j-th row of the plurality of pixels, and The second output terminal of the j-th driving stage is connected to one of the scan lines corresponding to the pixel in the (j+1)-th row among the plurality of pixels.

11. The display device according to claim 8, wherein, One of the plurality of driver levels connected to the first driver level of the first display area includes: The first driving circuit outputs the first scan signal to the output terminal, and Each of the plurality of driving levels connected to the second driving level of the second display area includes: The second driving circuit outputs the second scan signal to the first output terminal; and A masking circuit that controls the output of the second scan signal to the second output terminal in response to the masking signal.

12. The display device according to claim 8, wherein, The start signal has a first period during the entire frame and a second period during each of the plurality of partial frames, and The second period has a different size than the first period.

13. The display device according to claim 12, wherein, The first period is longer than the second period.

14. The display device according to any one of claims 1 to 13, wherein, The display panel operates in either the first mode or the second mode. When the display panel operates in the first mode, the drive controller divides the display panel into a first display area and a second display area based on the image signal, and When the display panel is operating in the second mode, the drive controller does not divide the display panel into the first display area and the second display area.

15. The display device according to claim 14, wherein, In the first mode, the first display area displays a first image at a first operating frequency higher than the normal frequency of the second mode, and the second display area displays a second image at a second operating frequency lower than the normal frequency of the second mode.

Images