A memory device operation method and a memory device

Abstract

The application provides a storage device operation method and a storage device, relates to the technical field of neural networks, and is used for avoiding the case that the conductance of a storage unit in the storage device changes slowly. The storage device comprises a storage unit array composed of a plurality of storage strings, the storage string comprises a plurality of storage units, and the conductance of at least one storage unit in the plurality of storage units is a synaptic weight between a first neuron and a second neuron. The method comprises the following steps: applying a first pulse voltage to a target storage unit to perform a first operation on the target storage unit, wherein the target storage unit comprises the at least one storage unit; and applying a second pulse voltage to the target storage unit to perform a second operation on the target storage unit, wherein the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

Description

Technical Field

[0001] This application relates to the field of neural network technology, and in particular to a storage device operation method and a storage device. Background Technology

[0002] A neural network consists of multiple neurons and multiple synapses. Each synapse can connect a front-end neuron to a back-end neuron, transmitting electrical or chemical signals from the front-end neuron to the back-end neuron. Three-dimensional (3D) NAND flash memory is a storage device composed of multiple stacked storage cells. It has advantages such as non-volatility, large storage capacity, high process maturity, and low cost, and therefore can be applied in neural networks as a biomimetic synaptic device.

[0003] When applying 3D NAND flash memory to neural networks, the electrical conductance of the storage cells in the 3D NAND flash memory is usually used as synaptic weights. Synaptic weights can be used to represent the connection strength between two neurons in a neural network. Summary of the Invention

[0004] This application provides a storage device operation method and a storage device to avoid the slow change in the conductivity of the storage cells in the storage device.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, a method for operating a storage device is provided. The storage device includes: an array of storage cells consisting of multiple storage strings, each storage string comprising multiple storage cells, wherein the conductance of at least one of the storage cells serves as the synaptic weight between a first neuron and a second neuron. The method includes: applying a first pulse voltage to a target storage cell, the first pulse voltage being either a positive or negative pulse voltage, to perform a first operation on the target storage cell, the first operation being either a programming operation or an erasing operation, wherein the target storage cell includes the at least one storage cell; applying a second pulse voltage to the target storage cell, the second pulse voltage being either a positive or negative pulse voltage, to perform a second operation on the target storage cell, the first operation and the second operation being two consecutive operations, for example, when the first operation is a programming operation, the second operation is also a programming operation, and the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

[0007] In the above technical solution, a first pulse voltage is applied to the target storage cell to perform a first operation on the target storage cell, and a second pulse voltage is applied to the target storage cell to perform a second operation on the target storage cell. The first operation and the second operation are two consecutive operations. The absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage. The pulse voltage gradually increases, thereby enabling continuous programming or erasing operations on the target storage cell. This allows the conductance in the target storage cell to continuously increase or decrease by the same amount. Compared with the slow change in the conductance of the storage cell due to the increase of the threshold voltage and the use of a pulse voltage of the same amplitude, this avoids the phenomenon of programming saturation and erasing saturation.

[0008] In one possible implementation of the first aspect, the method includes: applying a third pulse voltage to the target memory cell to perform a third operation on the target memory cell, wherein the time interval between the first pulse voltage and the second pulse voltage and the time interval between the second pulse voltage and the third pulse voltage are equal, and the absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage. In the above possible implementation, the target storage cell is subjected to three consecutive operations. After the first operation, the conductivity of the target storage cell is a first conductivity value; after the second operation, the conductivity of the target storage cell is a second conductivity value; and after the third operation, the conductivity of the target storage cell is a third conductivity value. The difference between the first conductivity value and the second conductivity value is a first value, and the difference between the second conductivity value and the third conductivity value is a second value. Since the absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, and the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage are all within a preset voltage range, the first pulse voltage, the second pulse voltage, and the third pulse voltage can be approximately considered to increase proportionally, and the first conductivity value, the second conductivity value, and the third conductivity value can be approximately considered to decrease proportionally or increase proportionally. The changing trends of the first conductivity value, the second conductivity value, and the third conductivity value can be approximately a straight line, thereby improving the linearity of the conductivity of the target storage cell and further improving the accuracy of the neural network.

[0009] In one possible implementation of the first aspect, after the first operation, the conductivity of the target storage cell is a first conductivity value; after the second operation, the conductivity of the target storage cell is a second conductivity value; and after the third operation, the conductivity of the target storage cell is a third conductivity value; wherein the first conductivity value, the second conductivity value, and the third conductivity value are linearly related. In the above possible implementation, the linear relationship between the first conductivity value, the second conductivity value, and the third conductivity value improves the linearity of the conductivity of the target storage cell, further improving the accuracy of the neural network when the storage device is applied.

[0010] In one possible implementation of the first aspect, the storage device further includes a word line connected to the target storage cell, the pulse voltage being a positive pulse voltage applied to the word line, and the operation being a programming operation. In the above possible implementation, the pulse voltage is a positive pulse applied to the word line of the target storage cell to perform a programming operation on the target storage cell, thereby reducing the conductance value of the target storage cell and achieving the purpose of adjusting the conductance value of the target storage cell.

[0011] In one possible implementation of the first aspect, the storage device further includes a word line connected to the target storage cell, the pulse voltage being a negative pulse voltage applied to the word line, and the operation being an erase operation. In the above possible implementation, the pulse voltage is a negative pulse applied to the word line of the target storage cell to perform an erase operation on the target storage cell, thereby increasing the conductivity value of the target storage cell and achieving the purpose of adjusting the conductivity value of the target storage cell.

[0012] In one possible implementation of the first aspect, the storage device further includes a bit line connected to the target storage cell, and the pulse voltage is a positive pulse voltage applied to the bit line, the operation being an erase operation. In the above possible implementation, the pulse voltage is a positive pulse voltage applied to the bit line of the target storage cell to perform an erase operation on the target storage cell, thereby increasing the conductance of the target storage cell and achieving the purpose of adjusting the conductance of the target storage cell.

[0013] In one possible implementation of the first aspect, before applying each of a plurality of pulse voltages to the target memory cell, the method further includes: acquiring the current conductance value of the target memory cell; and adjusting the pulse voltage according to the current conductance value and a preset conductance value corresponding to the current conductance value. In the above possible implementation, adjusting the pulse voltage according to the current conductance value and the preset conductance value corresponding to the current conductance value makes the conductance value of the target memory cell closer to the preset conductance value, improving the linearity of the change in the conductance value of the target memory cell. Furthermore, when the memory device is applied to a neural network, this further improves the accuracy of the neural network.

[0014] In one possible implementation of the first aspect, when the operation is an erase operation, the pulse voltage is adjusted according to the current conductance value and a preset conductance value corresponding to the current conductance value. This includes: if the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is decreased, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the decreased pulse voltage; if the current conductance value is less than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the increased pulse voltage. In the above possible implementation, the conductance value of the target memory cell is made closer to the preset conductance value, improving the linearity of the change in the conductance value of the target memory cell. When the memory device is applied to a neural network, this further improves the accuracy of the neural network.

[0015] In one possible implementation of the first aspect, when the operation is a programming operation, adjusting the pulse voltage according to the current conductance value and a preset conductance value corresponding to the current conductance value includes: if the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then increasing the absolute value of the pulse voltage, wherein the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the increased absolute value of the pulse voltage; if the current conductance value is less than the preset conductance value corresponding to the current conductance value, then decreasing the absolute value of the pulse voltage, wherein the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the decreased absolute value of the pulse voltage. In the above possible implementation, the conductance value of the target memory cell is made closer to the preset conductance value, improving the linearity of the change in the conductance value of the target memory cell. When the memory device is applied to a neural network, the accuracy of the neural network is further improved.

[0016] In a second aspect, a storage device is provided, comprising: a storage cell array consisting of multiple storage strings and peripheral circuitry, wherein the storage strings include multiple storage cells, and the conductance of at least one of the multiple storage cells serves as the synaptic weight between a first neuron and a second neuron; the peripheral circuitry is configured to apply a first pulse voltage to a target storage cell to perform a first operation on the target storage cell, wherein the target storage cell includes the at least one storage cell; the peripheral circuitry is further configured to apply a second pulse voltage to the target storage cell to perform a second operation on the target storage cell, wherein the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

[0017] In one possible implementation of the second aspect, the peripheral circuit is further configured to: apply a third pulse voltage to the target memory cell to perform a third operation on the target memory cell, wherein the time interval between the first pulse voltage and the second pulse voltage and the time interval between the second pulse voltage and the third pulse voltage are equal, and the absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage.

[0018] In one possible implementation of the second aspect, after the first operation, the conductivity of the target memory cell is a first conductivity value; after the second operation, the conductivity of the target memory cell is a second conductivity value; and after the third operation, the conductivity of the target memory cell is a third conductivity value, wherein the first conductivity value, the second conductivity value, and the third conductivity value are linearly related.

[0019] In one possible implementation of the second aspect, before applying each of the plurality of pulse voltages to the target memory cell, the peripheral circuit is further configured to: obtain the current conductance value of the target memory cell; and adjust the pulse voltage according to the current conductance value and a preset conductance value corresponding to the current conductance value.

[0020] In one possible implementation of the second aspect, when the operation is an erase operation, the peripheral circuit is further configured to: if the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then decrease the absolute value of the pulse voltage, wherein the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the decreased pulse voltage; if the current conductance value is less than the preset conductance value corresponding to the current conductance value, then increase the absolute value of the pulse voltage, wherein the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the increased pulse voltage.

[0021] In one possible implementation of the second aspect, when the operation is a programming operation, the peripheral circuit is further configured to: if the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then increase the absolute value of the pulse voltage, wherein the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the increased pulse voltage; if the current conductance value is less than the preset conductance value corresponding to the current conductance value, then decrease the absolute value of the pulse voltage, wherein the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the decreased pulse voltage.

[0022] In another aspect of this application, a computer-readable storage medium is provided, the computer-readable storage medium including computer instructions that, when executed, perform a storage device operation method as provided in the first aspect or any possible implementation thereof.

[0023] In another aspect of this application, a computer program product containing instructions is provided, which, when run on a computer, causes a storage device to perform the storage device operation method provided by the first aspect or any possible implementation thereof.

[0024] It is understood that any of the storage devices, computer-readable storage media and computer program products provided above can be used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a neural network structure;

[0026] Figure 2 This is a schematic diagram of a fixed amplitude pulse;

[0027] Figure 3 This is a schematic diagram illustrating how the conductivity of a 3D NAND flash memory varies with the number of pulses.

[0028] Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of another storage device provided in an embodiment of this application;

[0031] Figure 7 A schematic flowchart illustrating a storage device operation method provided in an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of the absolute value of a pulse voltage provided in an embodiment of this application;

[0033] Figure 9 A schematic diagram illustrating the accuracy and conductivity of a neural network as provided in this application embodiment;

[0034] Figure 10 A bar chart illustrating a storage device operation method provided in an embodiment of this application;

[0035] Figure 11 This is a schematic diagram of a storage device structure provided in an embodiment of this application. Detailed Implementation

[0036] In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, embodiments of this application use terms such as "first" and "second" to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order.

[0037] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] Before introducing the embodiments of this application, the background technology related to neural networks will be introduced first.

[0039] A neural network consists of multiple neurons and multiple synapses. Each synapse can be used to connect the front and back neurons of the multiple neurons and transmit the electrical or chemical signals of the front neurons to the back neurons.

[0040] Figure 1This is a schematic diagram of a neural network structure, comprising at least two layers of neurons and multiple synapses. Each of the at least two layers of neurons may include multiple neurons. For example, the at least two layers of neurons may include three layers of neurons, comprising a first layer of neurons, a second layer of neurons, and a third layer of neurons that are sequentially adjacent. The first layer of neurons may include multiple neurons and can be represented as X1 to Xn, the second layer of neurons may include multiple neurons and can be represented as Y1 to Yn, and the third layer of neurons may include multiple neurons and can be represented as Z1 to Zn, where n is greater than 1. Each of the multiple synapses can be used to connect two neurons in two adjacent layers of neurons and can be represented as Sxy, where x and y are greater than or equal to 1. For example, synapse S11 can be used to connect neuron X1 and neuron Y1, and synapse S21 can be used to connect neuron X2 and neuron Y1. Figure 1 Taking at least two layers of neurons, including three layers of neurons, as an example, and Figure 1 Only a portion of neurons and synapses are shown in the image.

[0041] Optionally, relative to two adjacent layers of neurons, each neuron in the preceding layer can be called a front-end neuron, and each neuron in the following layer can be called a back-end neuron. Taking the above three layers of neurons as an example, for the first and second layers of neurons, each neuron in the first layer can be a front-end neuron, and each neuron in the second layer can be a back-end neuron; for the second and third layers of neurons, each neuron in the second layer can be a front-end neuron, and each neuron in the third layer can be a back-end neuron.

[0042] Three-dimensional (3D) NAND flash memory comprises an array of memory cells. NAND flash memory possesses advantages such as non-volatility, large storage capacity, mature manufacturing process, and low cost, making it suitable for application as a biomimetic synaptic device in neural networks. When applying 3D NAND flash memory to neural networks, the conductance of the memory cells in the array is typically used as synaptic weights, which represent the connection strength between two neurons in the neural network. 3D NAND flash memory also includes peripheral circuitry used to provide voltage to the memory cells in the array.

[0043] Currently, memory cells in 3D NAND flash memory are programmed or erased using continuous pulses of fixed amplitude (including programming and erasing pulses). The conductance of the memory cell is adjusted by changing its threshold voltage, where conductance represents the cell's electrical conductivity. For example, ... Figure 2As shown, the horizontal axis represents time (T), and the vertical axis represents voltage (V). The pulse voltage amplitudes at times T1, T2, and T3 are all the same and equal to V1. Specifically, by using continuous programming pulses with fixed amplitudes, the memory cells in the 3D NAND flash memory are programmed, causing negative charges to be stored in the storage layer of the memory cells. This increases the amount of negative charges in the storage layer of the memory cells, thus raising the threshold voltage of the memory cells. Since the threshold voltage of a memory cell is inversely correlated with its conductance (i.e., a higher threshold voltage leads to a lower conductance), the conductance of the memory cells is reduced. Similarly, by using continuous erase pulses with fixed amplitudes, the memory cells in the 3D NAND flash memory are erased, reducing the amount of negative charges in the storage layer of the memory cells. This lowers the threshold voltage of the memory cells. Again, since the threshold voltage of a memory cell is inversely correlated with its conductance (i.e., a lower threshold voltage leads to a higher conductance), the conductance of the memory cells is increased.

[0044] However, since the threshold voltage of the storage cell in 3D NAND flash memory increases with the increase of negative charge in the storage layer, when there are many pulses, the change in threshold voltage and conductance generated by programming or erasing pulses of the same amplitude will be slow, resulting in programming saturation or erasing saturation.

[0045] Figure 3 This diagram illustrates the change in conductivity of 3D NAND flash memory with the number of pulses. The horizontal axis represents the number of pulses, and the vertical axis represents conductivity. Curve S1 shows the trend of conductivity with the number of erase pulses; as the number of erase pulses increases, the conductivity gradually increases, and the change in conductivity gradually slows down, indicating erase saturation. Curve S2 shows the trend of conductivity with the number of programming pulses; as the number of programming pulses increases, the conductivity gradually decreases, and the change in conductivity gradually slows down, indicating programming saturation. Line S3 shows the trend of conductivity with the number of erase pulses under ideal conditions; as the number of erase pulses increases, the conductivity gradually increases and changes linearly. Line S4 shows the trend of conductivity with the number of programming pulses under ideal conditions; as the number of programming pulses increases, the conductivity gradually decreases and changes linearly.

[0046] Based on this, this application provides a storage device operation method. This operation method is applied to a storage device and can continuously program or erase the storage cell array in the storage device, so that the change in the conductivity of the storage device is linear, thereby avoiding the phenomenon of programming saturation or erasure saturation.

[0047] The structure of the storage device will be described below.

[0048] Figure 4 This is a schematic diagram of a possible structure of a storage device provided in an embodiment of this application, such as... Figure 4 As shown, the storage device may include: peripheral circuitry 01 and a storage cell array 02. The storage cell array 02 includes bit lines and word lines.

[0049] The peripheral circuit 01 can be used to provide voltage to the memory cell array 02. For example, the peripheral circuit 01 may include a power supply module, which provides turn-on voltage and pulse voltage to the memory cell array 02. For example, the power supply module can provide programming pulse voltage and erase pulse voltage to the memory cell array 02, wherein the programming pulse voltage is a positive pulse voltage applied to the word line of the memory cell array 02, and the erase pulse voltage is a negative pulse voltage applied to the word line of the memory cell array 02. The power supply module can also provide a positive erase pulse voltage to the bit line of the memory cell array 02. The power supply module can also provide turn-on voltage to the word line of the memory cell array 02. For example, the peripheral circuit 01 provides a 1.7V turn-on voltage to the memory cell in the memory cell array 02. Optionally, the peripheral circuit 01 may also include a read module and a calculation module. The read module is used to read the conductance value of the memory cell in the memory cell array 02, and the calculation module is used to calculate the difference in conductance between two memory cells. The peripheral circuit 01 may also include an address selection module, which includes multiple switches and is used to select the memory cell that needs to be operated. Optionally, the peripheral circuit 01 can be a complementary metal-oxide-semiconductor (CMOS) circuit, which may include multiple metal-oxide-semiconductor field-effect transistors (MOS-FETs). For detailed information on the structure of a CMOS circuit, please refer to existing technologies; this embodiment will not elaborate further.

[0050] In the memory cell array 02, multiple memory cells located in the same row are connected by a word line, and memory cells located in the same column are connected by a bit line. The word line can be used to receive pulse voltages provided by the peripheral circuit 01 and to perform programming or erasing operations based on these pulse voltages. For example, the word line can be used to receive positive pulse voltages provided by the peripheral circuit 01 and to program the memory cells in the memory cell array based on these positive pulse voltages; the word line can also be used to receive negative pulse voltages provided by the peripheral circuit 01 and to erase the memory cell array based on these negative pulse voltages. The word line can also receive a conduction voltage provided by the peripheral circuit 01 and to activate the corresponding memory cells in the memory cell array based on this conduction voltage.

[0051] Figure 5 This is a schematic diagram of a cross-sectional structure of a storage device in the vertical direction, provided as an embodiment of this application. Figure 5The following description uses a storage device comprising five layers of storage units as an example. Each layer of storage units includes multiple storage units. Multiple storage units located in the same column within each layer are connected via bit lines, and multiple storage units located in the same row are connected via word lines. At least one storage unit Gxy in each layer can serve as a synapse connecting multiple first neurons and one second neuron. For example, the multiple first neurons can be represented as X1 to Xn, and the multiple second neurons can be represented as Y1 to Ym. The multiple first neurons and multiple second neurons can be... Figure 1 The neural network shown represents any two adjacent layers of neurons. For example, multiple first neurons can be neurons in a second layer, and multiple second neurons can be neurons in a third layer. At least one storage unit in the first layer can serve as a synapse between multiple first neurons X1 to Xn and a second neuron Y1. For example, storage unit G11 in the first layer can serve as a synapse between first neuron X1 and second neuron Y1, storage unit G21 in the first layer can serve as a synapse between first neuron X2 and second neuron Y1, and storage unit Gn1 in the first layer can serve as a synapse between first neuron Xn and second neuron Y1. At least one storage unit in the second layer can serve as a synapse between multiple first neurons X1 to Xn and second neuron Y2. For example, storage unit G12 in the second layer can serve as a synapse between first neuron X1 and second neuron Y2, and storage unit G22 in the second layer can serve as a synapse between first neuron X2 and second neuron Y2.

[0052] It should be noted that when applying a storage device to a neural network, the conductance of at least one storage cell in the storage device can be used as the synaptic weight between the first neuron X1 and the second neuron Y1. Figure 5 The example described uses at least one storage unit as an example. For instance, the conductance of storage unit G11 can be the synaptic weight between the first neuron X1 and the second neuron Y1. Optionally, when reading the conductance in the storage unit, a read voltage can be applied to the word line of the storage unit through external circuitry to read the conductance value in the storage unit.

[0053] Optionally, when at least one storage unit comprises two storage units, the structure of the neural network is as follows: Figure 6 As shown, in this case, the difference in conductance between the two memory cells is used as the synaptic weight. For example, memory cell G11 + The difference between the conductance of the first neuron X1 and the conductance of the storage unit G11 is used as the synaptic weight between the first neuron X1 and the second neuron Y1. Here, positive and negative signs simply indicate two different storage units. Optionally, a read module in the peripheral circuit can be used to read the storage unit G11.+ The conductivity value and storage unit G11 - The conductivity value is used by the calculation module in the peripheral circuit based on the storage unit G11. + The difference in conductance is calculated by comparing the conductance value of the storage cell G11 with that of the storage cell G11-. For ease of understanding, the following embodiments will be described using the example of at least one storage cell.

[0054] The following is combined Figure 4 The storage device shown and Figure 5 The storage device shown illustrates the operation method of the storage device provided in this application.

[0055] Figure 7 This is a flowchart illustrating a storage device operation method provided in an embodiment of this application, such as... Figure 7 As shown, the method of operating the storage device includes the following steps.

[0056] S701: Apply a first pulse voltage to the target memory cell to perform a first operation on the target memory cell, wherein the target memory cell includes at least one memory cell.

[0057] Optionally, after the first operation, the conductivity value of the target memory cell can be a first conductivity value.

[0058] The target memory cell may include one or more memory cells. For example, the target memory cell may include memory cell G11 in the first layer of memory cells. In this case, the peripheral circuit applies a programming voltage to the word line of memory cell G11 and applies the same programming voltage to the bit lines of other memory cells in the first layer of memory cells besides memory cell G11. The target memory cell may also be a memory cell array. In this case, the peripheral circuit applies an erase voltage to the word line of each memory cell in the memory cell array.

[0059] Optionally, the first pulse voltage can be a positive pulse or a negative pulse. The first operation can include a programming operation or an erasing operation. When the first pulse voltage is a positive pulse voltage, the first operation can be either a programming operation or an erasing operation. For example, if the first pulse voltage is a positive pulse voltage applied to the word line of the target memory cell, the first operation is a programming operation; if the first pulse voltage is a positive pulse voltage applied to the bit line of the target memory cell, the first operation is an erasing operation. When the first pulse voltage is a negative pulse voltage, the first operation is an erasing operation, for example, if the first pulse voltage is a negative pulse voltage applied to the word line of the target memory cell, the first operation is an erasing operation.

[0060] It should be noted that in practical applications, the erase operation of the target memory cell is usually performed by applying a positive pulse voltage to the bit line of the target memory cell. In the following embodiments, for ease of understanding, the first operation is a programming operation when the first pulse voltage is a positive pulse voltage, and an erase operation when the first pulse voltage is a negative pulse voltage.

[0061] Optionally, during the erase and programming operations, the target storage unit may include one storage unit or multiple storage units. In the following embodiment, the target storage unit includes one storage unit during the programming operation and multiple storage units during the erase operation, as an example for illustration.

[0062] The following sections describe the programming and erasing processes for the target storage unit.

[0063] In one possible embodiment, the target storage unit includes a storage unit representing a corresponding connection between a first neuron and a second neuron. The first pulse voltage is a positive pulse voltage, and the first operation is a programming operation. For example, the target storage unit includes a storage unit G11 representing a corresponding connection between a first neuron X1 and a second storage unit Y1. A positive pulse voltage is applied to storage unit G11 to perform a programming operation on storage unit G11. The programming operation refers to the process of storing negative charges in the storage layer of storage unit G11 using a positive pulse voltage. In this embodiment, by programming the target memory cell, the number of negative charges in the storage layer of the target memory cell is increased. The number of negative charges in the target memory cell is positively correlated with the threshold voltage (the voltage when the target memory cell is turned on). That is, the more negative charges in the storage layer of the target memory cell, the higher the threshold voltage, which is equivalent to increasing the threshold voltage of the target memory cell. Since the threshold voltage of the target memory cell is inversely correlated with the conductance, that is, the higher the threshold voltage of the target memory cell, the lower the conductance, which is equivalent to reducing the conductance of the target memory cell, thereby achieving the purpose of adjusting the conductance of the target memory cell, that is, achieving the purpose of adjusting the synaptic weight.

[0064] In practical applications, when the first pulse voltage is a positive pulse voltage, the first pulse voltage is greater than the turn-on voltage of the target memory cell. For example, the first pulse voltage can be 10V and the turn-on voltage can be 1.7V.

[0065] In another possible embodiment, the target storage unit includes multiple storage units corresponding to the connections between the plurality of first neurons and the plurality of second neurons. The first pulse voltage is a negative pulse voltage, and the first operation is an erasure operation. For example, the target storage unit includes multiple storage units corresponding to the connections between six first neurons X1 to X6 and four second neurons Y1 to Y4. These multiple storage units include 24 storage units. A negative pulse voltage is simultaneously applied to the multiple storage units to perform an erasure operation simultaneously. The erasure operation refers to the process of erasing the negative charge stored in the storage layer of each storage unit in the plurality of storage units using a negative pulse voltage. In this embodiment, by performing an erase operation on the target storage cell, the number of negative charges in the storage layer of the target storage cell is reduced. The number of negative charges in the target storage cell is positively correlated with the threshold voltage, that is, the fewer the negative charges in the storage layer of the target storage cell, the lower the threshold voltage, which is equivalent to reducing the threshold voltage of the target storage cell. Since the threshold voltage of the target storage cell is inversely correlated with the conductance, that is, the smaller the threshold voltage of the target storage cell, the larger the conductance, which is equivalent to increasing the conductance of the target storage cell, thereby achieving the purpose of adjusting the conductance of the target storage cell, that is, achieving the purpose of adjusting the synaptic weight.

[0066] In practical applications, when the first pulse voltage is a negative pulse voltage, the absolute value of the first pulse voltage is greater than the turn-on voltage of the target memory cell, but the numerical value of the first pulse voltage is less than the turn-on voltage of the target memory cell. For example, the first pulse voltage can be -10V, and the turn-on voltage can be 1.7V.

[0067] S702: Apply a second pulse voltage to the target memory cell to perform a second operation on the target memory cell, wherein the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

[0068] The second pulse voltage can be either a positive or negative pulse voltage. The second operation can be either a programming or erasing operation. Specifically, when the second pulse voltage is positive, the second operation is a programming operation, which reduces the conductance of the target memory cell, resulting in a second conductance value that is less than the first conductance value. When the second pulse voltage is negative, the second operation is an erasing operation, which increases the conductance of the target memory cell, resulting in a second conductance value that is greater than the first conductance value.

[0069] The following sections will explain the two scenarios for performing the second operation on the target storage unit.

[0070] In one possible embodiment, when the first operation is a programming operation, the second pulse voltage is a positive pulse voltage. The second operation is a programming operation, and the first and second operations are two consecutive programming operations. The absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage. In this embodiment, the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage. Through two consecutive programming operations, negative charges can be continuously stored in the storage layer of the target memory cell, thereby continuously reducing the conductance of the target memory cell. This avoids the threshold voltage of the target memory cell increasing due to the increase in the number of negative charges in the storage layer, which would prevent the negative charges from being continuously stored in the storage layer of the target memory cell. In other words, it avoids programming saturation, which would prevent the conductance of the target memory cell from changing.

[0071] In practical applications, when the second pulse voltage is a positive pulse voltage, the second pulse voltage is greater than the turn-on voltage of the target memory cell. For example, the second pulse voltage can be 14V and the turn-on voltage can be 2V.

[0072] In another possible embodiment, when the first operation is an erase operation, the second pulse voltage is a negative pulse voltage, and the second operation is also an erase operation. The first and second operations are two consecutive erase operations of the same type, and the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage. In this embodiment, the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage. Through two consecutive erase operations, negative charges stored in the target memory cell's storage layer can be continuously erased, thus continuously increasing the conductivity of the target memory cell. This avoids the phenomenon that negative charges in the target memory cell's storage layer cannot be erased, and prevents the slow change in the target memory cell's conductivity.

[0073] In practical applications, when the second pulse voltage is a negative pulse voltage, the absolute value of the second pulse voltage is greater than the turn-on voltage of the target memory cell, but the numerical value of the second pulse voltage is less than the turn-on voltage of the target memory cell. For example, the second pulse voltage can be -14V, and the turn-on voltage can be 1.5V.

[0074] In one possible embodiment, a third pulse voltage is applied to the target memory cell to perform a third operation on the target memory cell. The second operation and the third operation are two consecutive operations. The time interval between the first pulse voltage and the second pulse voltage and the time interval between the second pulse voltage and the third pulse voltage are equal. The absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage. The absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, and the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage are both within a preset voltage range.

[0075] For example, such as Figure 8 As shown, the horizontal axis represents time, and the vertical axis represents the absolute value of the pulse voltage. The absolute value of the first pulse voltage is 10V, the absolute value of the second pulse voltage is 14.9V, and the absolute value of the third pulse voltage is 20V. The absolute value of the difference between the second pulse voltage and the first pulse voltage is 4.9V, and the absolute value of the difference between the third pulse voltage and the second pulse voltage is 5.1V. Assuming that the preset voltage range can be (4.5~5.5V), the absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, as well as the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage, are all within the preset voltage range.

[0076] The preset voltage range can be set according to actual needs and the experience of relevant technical personnel. This application embodiment does not impose specific limitations on this.

[0077] Furthermore, the third pulse voltage can be either a positive or negative pulse voltage. This third operation can be either a programming operation or an erasing operation. When the third pulse voltage is a positive pulse voltage, the third operation is a programming operation, which reduces the conductance of the target memory cell. After this third operation, the conductance of the target memory cell can be the third conductance value, which is less than the second conductance value. When the third pulse voltage is a negative pulse voltage, the third operation is an erasing operation, which increases the conductance of the target memory cell. In this case, the third conductance value is greater than the second conductance value.

[0078] The following sections will explain the two scenarios for performing the third operation on the target storage unit.

[0079] In one possible embodiment, when the second operation is a programming operation, the third pulse voltage is a positive pulse voltage. The third operation is a programming operation, and the first operation, the second operation, and the third operation are three consecutive programming operations. The target memory cell is programmed three times consecutively, and the conductance value of the target memory cell gradually decreases. The second conductance value is less than the first conductance value, and the third conductance value is less than the second conductance value. The difference between the first conductance value and the second conductance value is a first value, and the difference between the second conductance value and the third conductance value is a second value. The absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage. The absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, and the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage are both within a preset voltage range. In this embodiment, since the absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, and the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage are both within a preset voltage range, the difference between the first value and the second value is less than the preset value. That is, the first pulse voltage, the second pulse voltage, and the third pulse voltage can be approximately considered to increase proportionally, and the first conductance value, the second conductance value, and the third conductance value can be approximately considered to decrease proportionally. The changing trends of the first conductance value, the second conductance value, and the third conductance value can be approximately a straight line, thereby improving the linearity of the conductance of the target memory cell and further improving the accuracy of the neural network.

[0080] It should be noted that the preset value can be determined based on actual needs or the experience of relevant technical personnel, and this application embodiment does not impose specific limitations on it.

[0081] In practical applications, when the third pulse voltage is a positive pulse voltage, the third pulse voltage is greater than the turn-on voltage of the target memory cell. For example, the third pulse voltage can be 21V and the turn-on voltage can be 2.5V.

[0082] In another possible embodiment, when the second operation is an erase operation, the third pulse voltage is a negative pulse voltage. The third operation is an erase operation, and the first operation, the second operation, and the third operation are three consecutive erase operations. The target memory cell is subjected to three consecutive erase operations, and the conductivity value of the target memory cell gradually increases. The second conductivity value is greater than the first conductivity value, and the third conductivity value is greater than the second conductivity value. The difference between the first conductivity value and the second conductivity value is a first value, and the difference between the second conductivity value and the third conductivity value is a second value. The absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage. The absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, and the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage are both within a preset voltage range. In this embodiment, since the absolute values ​​of the difference between the second pulse voltage and the first pulse voltage, and the absolute values ​​of the difference between the third pulse voltage and the second pulse voltage are both within a preset voltage range, the difference between the first value and the second value is less than the preset value. That is, the first pulse voltage, the second pulse voltage, and the third pulse voltage can be approximately considered to decrease proportionally, and the first conductance value, the second conductance value, and the third conductance value can be approximately considered to increase proportionally. The changing trends of the first conductance value, the second conductance value, and the third conductance value can be approximately a straight line, thereby improving the linearity of the conductance of the target memory cell and further improving the accuracy of the neural network.

[0083] For example, such as Figure 9 As shown, the linearity of the target memory cell under the same amplitude pulse is A1, and the linearity of the target memory cell under the step pulse is A2. A1 is less than A2, that is, the linearity of the target memory cell under the step pulse is higher than that under the same amplitude pulse. When the linearity is A1, the accuracy of the corresponding neural network is B1. When the linearity is A2, the accuracy of the corresponding neural network is B2. B2 is greater than B1, that is, the higher the linearity of the target memory cell, the higher the accuracy of the neural network.

[0084] In practical applications, when the third pulse voltage is a negative pulse voltage, the absolute value of the third pulse voltage is greater than the turn-on voltage of the target memory cell. For example, the third pulse voltage can be -21V and the turn-on voltage can be 1V.

[0085] Furthermore, the positive pulse voltage may include an incremental step pulse program (ISPP) voltage, and the negative pulse voltage may include an incremental step pulse erase (ISPE) voltage. The positive pulse voltage and the negative pulse voltage may also be referred to as programming voltage or step voltage.

[0086] In one possible embodiment, multiple pulse voltages with the same time interval can be applied to the target memory cell, including the first pulse voltage, second pulse voltage, and third pulse voltage. Before applying each of the multiple pulse voltages to the target memory cell, a read verification is performed on the target memory cell. The method further includes: obtaining the current conductance value of the target memory cell; adjusting the pulse voltage according to the current conductance value and a preset conductance value corresponding to the current conductance value, so that the adjusted pulse voltage can be applied when applying voltage to the target memory cell.

[0087] The erase operation and the programming operation are explained below.

[0088] During the erase operation, if the current conductance value is greater than the preset conductance value corresponding to the current conductance value, the absolute value of the pulse voltage is decreased, and the absolute value of the next pulse voltage among the multiple pulse voltages is greater than the absolute value of the decreased pulse voltage; if the current conductance value is less than the preset conductance value corresponding to the current conductance value, the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the multiple pulse voltages is greater than the absolute value of the decreased pulse voltage. The preset conductance value is the conductance value under ideal conditions, that is, the conductance value when the conductance is linear with the number of pulse voltages.

[0089] For example, assuming the required conductance range is (40-360), and the applied pulse voltage increases by 5V and the conductance decreases by 40 in each adjustment, before applying the first pulse voltage to the target memory cell, the current conductance of the target memory cell is 356. At this time, the preset conductance corresponding to the current conductance is 360. Since the current conductance is less than the preset conductance, the first pulse voltage is increased, and a first pulse voltage of 21V is applied to the target memory cell (following a linear change, a pulse voltage of 20V can reduce the conductance by 40). A first operation is performed on the target memory cell. After the first operation, the current conductivity value of the target memory cell is a first conductivity value. The first conductivity value is 324, and the preset conductivity value corresponding to the first conductivity value is 320. If the first conductivity value is greater than the preset conductivity value corresponding to the first conductivity value, the second pulse voltage is reduced. Then, a second pulse voltage of 24.9V is applied to the target memory cell. The absolute value of the second pulse voltage is greater than the absolute value of the increased first pulse voltage. A second operation is performed on the target memory cell. After the second operation, the current conductivity value of the target memory cell is the second conductivity value.

[0090] During programming, if the current conductance value is greater than the preset conductance value corresponding to the current conductance value, the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the multiple pulse voltages is greater than the increased absolute value of the pulse voltage; if the current conductance value is less than the preset conductance value corresponding to the current conductance value, the absolute value of the pulse voltage is decreased, and the absolute value of the next pulse voltage among the multiple pulse voltages is greater than the decreased absolute value of the pulse voltage. The specific adjustment process is similar to that of the erase operation and will not be described in detail here.

[0091] For ease of understanding, the following will use... Figure 10 The bar chart shown is used as an example to illustrate the technical solution provided in this application.

[0092] like Figure 10 As shown, before applying the first pulse voltage V1 to the target storage cell, i.e. before time T1, a read verification is performed on the target storage cell, and the first pulse voltage V1 is provided based on the result of the read verification. Before applying the second pulse voltage V2 to the target storage cell, i.e. before time T2, a read verification is performed on the target storage cell, and the second pulse voltage V2 is provided based on the result of the read verification. The absolute value of the second pulse voltage V2 is greater than the absolute value of the first pulse voltage V1. Before applying the third pulse voltage V3 to the target storage cell, i.e. before time T3, a read verification is performed on the target storage cell, and the third pulse voltage V3 is provided based on the result of the read verification. The absolute value of the third pulse voltage V3 is greater than the absolute value of the second pulse voltage V2.

[0093] In this embodiment, before each pulse voltage is applied, the target memory cell is read and verified. By comparing the current conductance value with the preset conductance value, the pulse voltage is adjusted so that the conductance value of the target memory cell is closer to the preset conductance value. This improves the linearity of the conductance value change of the target memory cell, simplifies the peripheral circuit, and further improves the accuracy of the neural network.

[0094] The storage device operation method provided in this application applies a first pulse voltage to a target storage cell to perform a first operation on the target storage cell, and applies a second pulse voltage to the target storage cell to perform a second operation on the target storage cell. The first operation and the second operation are two consecutive operations. Since the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage, the pulse voltage gradually increases, thereby enabling continuous programming or erasing operations on the target storage cell, avoiding programming saturation and erasing saturation, that is, avoiding the phenomenon of slow change in the conductivity of the storage cell, so that the conductivity of the target storage cell has a linear change trend.

[0095] It is understood that, in order to achieve the above-mentioned functions, the storage device includes the corresponding hardware structure and / or software modules for performing each function. Those skilled in the art should readily recognize that, based on the data reading method steps described in conjunction with the embodiments herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0096] This application embodiment can divide the storage device into functional modules according to the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0097] When dividing each function into modules according to its corresponding function. Figure 11 A possible structural schematic diagram of the storage device involved in the above embodiments is shown. The storage device includes: peripheral circuitry 101 and storage cell array 102. The peripheral circuitry 101 is used to support the storage device in executing S701 in the above method embodiments, and the storage cell array 102 is used to support the storage device in executing S702 in the above method embodiments.

[0098] In terms of hardware implementation, the storage device can be... Figure 4 The storage device in the storage device, for a detailed description of the storage device, can be found in [reference needed]. Figure 4 The specific descriptions in the embodiments of this application will not be repeated here.

[0099] It should be noted that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here. The apparatus provided in this application embodiment is used to perform the corresponding functions in the above embodiments, and therefore can achieve the same effect as the above control method.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0101] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0102] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause the device to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0103] In another aspect of this application, a computer-readable storage medium is provided, which includes computer instructions that, when executed on a storage device, perform the relevant steps in the above method embodiments.

[0104] In another aspect of this application, a computer program product containing instructions is provided, which, when run on a computer device, causes a storage device to perform the relevant steps in the above method embodiments.

[0105] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for operating a storage device, characterized in that, The storage device includes: a storage cell array consisting of multiple storage strings, each storage string comprising multiple storage cells, the multiple storage cells including a first storage cell and a second storage cell, wherein the difference between the conductance of the first storage cell and the conductance of the second storage cell serves as the synaptic weight between the first neuron and the second neuron; the method includes: A first pulse voltage is applied to a target memory cell to perform a first operation on the target memory cell, wherein the target memory cell includes the first memory cell and the second memory cell; A second pulse voltage is applied to the target memory cell to perform a second operation on the target memory cell, wherein the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

2. The method according to claim 1, characterized in that, The method further includes: A third pulse voltage is applied to the target memory cell to perform a third operation on the target memory cell, wherein the time interval between the first pulse voltage and the second pulse voltage and the time interval between the second pulse voltage and the third pulse voltage are equal, and the absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage.

3. The method according to claim 2, characterized in that, After the first operation, the conductivity of the target storage cell is a first conductivity value, the conductivity of the target storage cell is the difference between the conductivity of the first storage cell and the conductivity of the second storage cell, after the second operation, the conductivity of the target storage cell is a second conductivity value, and after the third operation, the conductivity of the target storage cell is a third conductivity value. The first conductivity value, the second conductivity value, and the third conductivity value are linearly related.

4. The method according to any one of claims 1-3, characterized in that, The storage device further includes a word line connected to the target storage cell, the pulse voltage is a positive pulse voltage applied to the word line, and the operation is a programming operation.

5. The method according to any one of claims 1-3, characterized in that, The storage device further includes a word line connected to the target storage cell, the pulse voltage is a negative pulse voltage applied to the word line, and the operation is an erase operation.

6. The method according to any one of claims 1-3, characterized in that, The storage device further includes a bit line connected to the target storage cell, the pulse voltage being a positive pulse voltage applied to the bit line, and the operation being an erase operation.

7. The method according to claim 1, characterized in that, Before applying each of a plurality of pulse voltages to the target memory cell, the method further includes: Obtain the current conductivity value of the target storage cell; The pulse voltage is adjusted based on the current conductance value and the preset conductance value corresponding to the current conductance value.

8. The method according to claim 7, characterized in that, When the operation is an erasure operation, adjusting the pulse voltage according to the current conductance value and a preset conductance value corresponding to the current conductance value includes: If the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is reduced, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the reduced pulse voltage; If the current conductance value is less than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the increased pulse voltage.

9. The method according to claim 7, characterized in that, When the operation is a programming operation, adjusting the pulse voltage according to the current conductance value and a preset conductance value corresponding to the current conductance value includes: If the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the first pulse voltage after the increase; If the current conductance value is less than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is reduced, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the first pulse voltage after reduction.

10. A storage device, characterized in that, The storage device includes: a storage cell array consisting of multiple storage strings and peripheral circuitry. Each storage string includes multiple storage cells, and each storage cell includes a first storage cell and a second storage cell. The difference between the conductance of the first storage cell and the conductance of the second storage cell is used as the synaptic weight between the first neuron and the second neuron. The peripheral circuit is used to apply a first pulse voltage to the target memory cell to perform a first operation on the target memory cell, wherein the target memory cell includes the first memory cell and the second memory cell; The peripheral circuit is also used to apply a second pulse voltage to the target memory cell to perform a second operation on the target memory cell, wherein the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

11. The storage device according to claim 10, characterized in that, The peripheral circuit is also used for: A third pulse voltage is applied to the target memory cell to perform a third operation on the target memory cell, wherein the time interval between the first pulse voltage and the second pulse voltage and the time interval between the second pulse voltage and the third pulse voltage are equal, and the absolute value of the third pulse voltage is greater than the absolute value of the second pulse voltage.

12. The storage device according to claim 11, characterized in that, After the first operation, the conductivity of the target storage cell is a first conductivity value, and the conductivity of the target storage cell is the difference between the conductivity of the first storage cell and the conductivity of the second storage cell. After the second operation, the conductivity of the target storage cell is a second conductivity value. After the third operation, the conductivity of the target storage cell is a third conductivity value. The first conductivity value, the second conductivity value, and the third conductivity value are linearly related.

13. The storage device according to claim 11, characterized in that, Before applying each of the plurality of pulse voltages to the target memory cell, the peripheral circuit is further configured to: Obtain the current conductivity value of the target storage cell; The pulse voltage is adjusted based on the current conductance value and the preset conductance value corresponding to the current conductance value.

14. The storage device according to claim 13, characterized in that, When the operation is an erase operation, the peripheral circuit is also used for: If the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is reduced, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the reduced pulse voltage; If the current conductance value is less than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the increased pulse voltage.

15. The storage device according to claim 13, characterized in that, When the operation is a programming operation, the peripheral circuit is also used for: If the current conductance value is greater than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is increased, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the increased pulse voltage; If the current conductance value is less than the preset conductance value corresponding to the current conductance value, then the absolute value of the pulse voltage is reduced, and the absolute value of the next pulse voltage among the plurality of pulse voltages is greater than the absolute value of the reduced pulse voltage.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions that, when executed, perform the storage device operation method as described in any one of claims 1-9.

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