Circuit and test system for measuring device OCV parameters

Abstract

The present invention provides a circuit and a test system for measuring the OCV parameters of a device, wherein the circuit for measuring the OCV parameters of the device includes: a data delay module, a first clock delay module, a second clock delay module, a level selection module, a data selection module and a balance register, and a test clock signal is respectively provided to the data delay module, the first clock delay module and the second clock delay module, and finally a fourth data signal is output through the balance register. The present application obtains the total delay time by comparing the waveforms of the fourth data signal and the test clock signal, and obtains the delay time of the second clock delay module and the data selection module by collecting the waveforms of the signals output by the second clock delay module and the data selection module (the waveforms of the first intermediate signal and the second intermediate signal), so that the timing deviation (OCV parameter) of the circuit to be measured can be obtained by calculation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit design and testing technology, and in particular to a circuit and a testing system for measuring OCV parameters of a device. Background Art

[0002] OCV (on-chip variation) caused by factors such as manufacturing process and environment can cause the characteristics of different parts of the chip to not be exactly the same, resulting in timing deviation. This deviation cannot be analyzed and calculated by tools, so a test circuit is currently needed to accurately test integrated circuits. Summary of the invention

[0003] The present application provides a circuit and a test system for measuring the OCV parameters of a device, which can solve the problem that the timing deviation of the actual circuit on the chip cannot be analyzed and calculated.

[0004] On the one hand, an embodiment of the present application provides a circuit for measuring OCV parameters of a device, including:

[0005] A data delay module, used for receiving an externally input test clock signal and a first control signal, and performing delay processing on the test clock signal according to the first control signal to output a first delayed data signal to a subsequent stage;

[0006] A first clock delay module, used for receiving the test clock signal and a second control signal input from the outside, and delaying the test clock signal according to the second control signal to output a first delayed clock signal to a subsequent stage;

[0007] A second clock delay module, used for receiving the test clock signal and a third control signal inputted from the outside, and performing delay processing on the test clock signal according to the third control signal to output a second delayed clock signal to a subsequent stage, and outputting a first intermediate signal for measuring delay;

[0008] a level selection module, configured to receive the first delayed data signal output by the data delay module and a fourth control signal input from the outside, and perform a logic operation on the first delayed data signal according to the fourth control signal to output a second delayed data signal to a subsequent stage;

[0009] a data selection module, configured to receive a first selection signal and a second selection signal inputted from the outside, the second delayed data signal outputted by the level selection module, the first delayed clock signal outputted by the first clock delay module, and the first data signal and the second data signal outputted by the circuit to be measured, and to perform delay cancellation processing on the second delayed data signal, the first delayed clock signal, the first data signal, and the second data signal according to the first selection signal and the second selection signal to output a third data signal to a subsequent stage, and to output a second intermediate signal for measuring delay; and

[0010] a balance register, used for receiving the second delayed clock signal output by the second clock delay module and the third data signal output by the data selection module, and outputting a fourth data signal to a subsequent stage;

[0011] Among them, the total delay time is obtained by comparing the waveforms of the fourth data signal and the test clock signal, the delay time of the second clock delay module and the data selection module are obtained by collecting the waveforms of the signals output by the second clock delay module and the data selection module, and the OCV parameters of the circuit to be measured are obtained by calculation.

[0012] Optionally, in the circuit for measuring the OCV parameters of the device, the second clock delay module also includes: a first selector, at least one first inverter and at least one first delay unit, one first delay unit and one first inverter are connected in series to form a group, and the groups are connected in series in sequence, the output end of the first inverter in the last group is connected to an input end of the first selector, the other input end of the first selector receives the external input test clock signal, the output end of the first selector is connected to the input end of the first delay unit in the first group, each of the first delay units receives the third control signal, and the output end of the first delay unit in any group is connected to the input end of the balancing register to output the second delayed clock signal to the balancing register.

[0013] Optionally, in the circuit for measuring the OCV parameters of the device, the number of the first inverters and the number of the first delay units are both eight, eight groups of the first inverters and the first delay units are connected in series in sequence to form an oscillation circuit, and the period of the waveform of the first intermediate signal output from the output end of the first selector is measured, and the period of the waveform of the third control signal and the test clock signal are adjusted to obtain the delay time of the second clock delay module.

[0014] Optionally, in the circuit for measuring the OCV parameters of the device, the data selection module includes: a plurality of second selectors, a multiplexing array and a second inverter, the multiplexing array includes a plurality of input terminals and an output terminal, wherein two input terminals receive a first selection signal and a second selection signal input from the outside, and the remaining input terminals are respectively connected to the output terminals of each second selector correspondingly, the output terminal of the multiplexing array is connected to the input terminal of the second inverter, and is connected to the data input terminal of the balancing register to provide the third data signal to the balancing register, the output terminal of the second inverter is connected to an input terminal of each second selector to provide the second intermediate signal to each second selector, and the other input terminal of each second selector respectively receives the first data signal and the second data signal output by the circuit to be measured, the second delayed data signal output by the level selection module, and the first delayed clock signal output by the first clock delay module;

[0015] wherein, by controlling different test modes of the second selector, the second intermediate signal or the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal are selected to be provided to the multiplexing array via the second selector;

[0016] The delay time of the data selection module is obtained by measuring the period of the waveform of the second intermediate signal outputted from the output terminal of the second inverter.

[0017] Optionally, in the circuit for measuring the OCV parameters of the device, the multiplexing array includes: a plurality of second delay units, a plurality of multiplexing units and a plurality of logic units, the plurality of the multiplexing units are connected in sequence, the output ends of the plurality of the second delay units are connected to the plurality of input ends of the first multiplexing unit, the logic units are grouped in pairs, each group of logic units corresponds to controlling one of the multiplexing units, each group of logic units respectively receives the first selection signal and the second selection signal input from the outside, and performs logic operation processing on the first selection signal and the second selection signal to output a fourth control signal and a fifth control signal to the corresponding multiplexing unit;

[0018] Among them, the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal are respectively input by the second selector and output by the last multiplexing unit, and the number of path signals passing through the four ends of the multiplexing unit is the same to offset the delay time of the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal from input to output.

[0019] Optionally, in the circuit for measuring the OCV parameters of the device, the number of the multiplexing units is 4n, where n is an integer greater than or equal to 1.

[0020] Optionally, in the circuit for measuring the OCV parameters of the device, the level selection module includes: a third inverter and a third selector, the output end of the third inverter is connected to an input end of the third selector, the input end of the third inverter and the other input end of the third selector are connected to the output end of the data delay module to receive the first delayed data signal, and according to the fourth control signal input externally, the output end of the third selector outputs the first delayed data signal or the reverse signal of the first delayed data signal to the circuit to be measured as the second delayed data signal.

[0021] Optionally, in the circuit for measuring the OCV parameters of the device, the balancing register is a double-edge balancing register.

[0022] On the other hand, an embodiment of the present application also provides a test system, including: a trigger and a circuit for measuring the OCV parameters of the device, the output end of the level selection module in the circuit for measuring the OCV parameters of the device is connected to the D end of the trigger, the output end of the first clock delay module in the circuit for measuring the OCV parameters of the device is connected to the CLK end of the trigger, and the Q end and Q' end of the trigger are respectively connected to any two input ends of the data selection module in the circuit for measuring the OCV parameters of the device.

[0023] Optionally, in the test system, the OCV parameters of the trigger include: setup time, hold time, and CLK to Q time.

[0024] The technical solution of this application has at least the following advantages:

[0025] In the circuit for measuring the OCV parameters of the device provided by the present invention, the test clock signal is respectively provided to the data delay module, the first clock delay module and the second clock delay module, and finally the fourth data signal is output through the balance register. The present application obtains the total delay time by comparing the waveforms of the fourth data signal and the test clock signal, and obtains the delay time of the second clock delay module and the data selection module by collecting the waveforms of the signals output by the second clock delay module and the data selection module (the waveforms of the first intermediate signal and the second intermediate signal), so that the timing deviation (OCV parameter) of the circuit to be measured can be obtained by calculation.

[0026] Furthermore, the data selection module of the present application is a multiplexed array structure, which can offset the delay differences of signals passing through multiple paths of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a schematic structural diagram of a circuit for measuring OCV parameters of a device according to an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of the circuit structure of the second clock delay module of an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of the circuit structure of a data selection module according to an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of the circuit structure of a multiplexing array according to an embodiment of the present invention;

[0032] The reference numerals are described as follows:

[0033] 10-data delay module, 20-first clock delay module, 30-second clock delay module, 40-level selection module, 50-data selection module, 60-balance register, 70-circuit to be measured / trigger;

[0034] 31-first delay unit, 32-first inverter, 33-first selector;

[0035] 51 - a second selector, 52 - a multiplexing array, 53 - a second inverter;

[0036] 521 - second delay unit, 522 - multiplexing unit, 523 - logic unit. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0038] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0039] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0040] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0041] Please refer to Figure 1-Figure 4 , Figure 1 is a schematic diagram of the structure of a circuit for measuring OCV parameters of a device according to an embodiment of the present invention, Figure 2 is a schematic diagram of the circuit structure of the second clock delay module of an embodiment of the present invention, Figure 3 is a schematic diagram of the circuit structure of a data selection module according to an embodiment of the present invention, Figure 4 Schematic diagram of the circuit structure of the multiplexing array according to an embodiment of the present invention.

[0042] The present application embodiment provides a circuit for measuring the OCV parameters of a device, such as Figure 1 As shown, the circuit for measuring the OCV parameters of the device includes: a data delay module 10 , a first clock delay module 20 , a second clock delay module 30 , a level selection module 40 , a data selection module 50 and a balance register 60 .

[0043] The data delay module 10 is used to receive an externally input test clock signal TEST_CLK and a first control signal CTRL_DUT_D[9:0], and delay the test clock signal TEST_CLK according to the first control signal CTRL_DUT_D[9:0] to output a first delayed data signal to a subsequent stage;

[0044] The first clock delay module 20 is used to receive the test clock signal TEST_CLK and the second control signal CTRL_DUT_CLK[9:0] input from the outside, and delay the test clock signal TEST_CLK according to the second control signal CTRL_DUT_CLK[9:0] to output a first delayed clock signal to the next stage;

[0045] The second clock delay module 30 is used to receive the test clock signal TEST_CLK and the third control signal CTRL_SAFF_CLK[9:0] input externally, and delay the test clock signal TEST_CLK according to the third control signal CTRL_SAFF_CLK[9:0] to output a second delayed clock signal to a subsequent stage, and output a first intermediate signal DELAY_OUT for measuring delay;

[0046] The level selection module 40 is used to receive the first delayed data signal output by the data delay module 10 and the fourth control signal DUT_D_HL_SEL input from the outside, and perform logic operation processing on the first delayed data signal according to the fourth control signal DUT_D_HL_SEL to output a second delayed data signal to the next stage. Figure 1 As shown, the level selection module 40 includes: a third inverter and a third selector, the output end of the third inverter is connected to an input end of the third selector, the input end of the third inverter and the other input end of the third selector are connected to the output end of the data delay module 10 to receive the first delayed data signal, and according to the fourth control signal DUT_D_HL_SEL input externally, the output end of the third selector outputs the first delayed data signal or the reverse signal of the first delayed data signal to the circuit to be measured as the second delayed data signal;

[0047] The data selection module 50 is used to receive the first selection signal S0 and the second selection signal S1 input from the outside, the second delayed data signal output by the level selection module 40, the first delayed clock signal output by the first clock delay module 20, and the first data signal and the second data signal output by the circuit to be measured 70, and perform delay cancellation processing on the second delayed data signal, the first delayed clock signal, the first data signal and the second data signal according to the first selection signal S0 and the second selection signal S1 to output a third data signal to the subsequent stage, and output a second intermediate signal MUX_OUT for measuring delay;

[0048] The balance register 60 is used to receive the second delayed clock signal output by the second clock delay module 30 and the third data signal output by the data selection module 50, and output a fourth data signal to a subsequent stage. In this embodiment, the balance register may be a double edge balance register (SAFF).

[0049] Among them, the total delay time is obtained by comparing the waveforms of the fourth data signal and the test clock signal, the delay times of the second clock delay module 30 and the data selection module 50 are respectively obtained by collecting the waveforms of the signals output by the second clock delay module 30 and the data selection module 50, and the OCV parameters of the circuit to be measured 70 are obtained by calculation.

[0050] This embodiment takes a DFF trigger as an example of a circuit to be measured and describes in detail the working process of a circuit for measuring the OCV parameters of a device.

[0051] Further, such as Figure 2 As shown, the second clock delay module 30 also includes: a first selector 33, at least one first inverter 32 and at least one first delay unit 31, one first delay unit 31 and one first inverter 32 are connected in series to form a group, and each group is connected in series in sequence, the output end of the first inverter 32 in the last group is connected to an input end of the first selector 33, the other input end of the first selector 33 receives the external input test clock signal TEST_CLK, the output end of the first selector 33 is connected to the input end of the first delay unit 31 in the first group, each of the first delay units 31 receives the third control signal CTRL_SAFF_CLK[9:0], and the output end of the first delay unit 31 in any group is connected to the input end of the balancing register 60 to output the second delayed clock signal to the balancing register 60.

[0052] Preferably, the number of the first inverters 32 and the number of the first delay units 31 are both eight. After a first inverter 32 and a first delay unit 31 are connected in series, each group is connected in series again to form eight groups. The eight groups of the first inverters 32 and the first delay units 31 are connected in series in sequence. The selection control end of the first selector 33 receives the selection control signal DELAY_TEST_MODE to control the eight groups of the first inverters 32 and the first delay units 31 to form an oscillation circuit. By measuring the period of the waveform of the first intermediate signal DELAY_OUT outputted from the output end of the first selector 33, the period of the waveform of the third control signal CTRL_SAFF_CLK[9:0] and the test clock signal TEST_CLK is continuously adjusted, so that the delay time of the second clock delay module 30 under each input condition can be obtained.

[0053] Better, such as Figure 3 As shown, the data selection module 50 includes: a plurality of second selectors 51, a multiplexing array 52 and a second inverter 53, the multiplexing array 52 includes six input terminals and an output terminal, wherein two input terminals receive a first selection signal S0 and a second selection signal S1 inputted from outside, and the remaining four input terminals are respectively connected to the output terminals of each second selector 51 correspondingly, the output terminal of the multiplexing array 52 is connected to the input terminal of the second inverter 53, and is connected to the data input terminal (D terminal) of the balancing register 60 to provide the third data signal to the balancing register 60, the output terminal of the second inverter 53 is connected to an input terminal of each second selector 51 to provide the second intermediate signal MUX_OUT to each second selector 51, and the other input terminal of each second selector 51 receives the first data signal and the second data signal outputted by the DFF trigger, as well as the second delayed data signal outputted by the level selection module 40 and the first delayed clock signal outputted by the first clock delay module 20.

[0054] By controlling different test modes of the second selector 51, the second intermediate signal MUX_OUT or the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal are selected to be provided to the multiplexing array 52 via the second selector 51;

[0055] In this embodiment, the delay time of the data selection module 50 can be obtained by measuring the period of the waveform of the second intermediate signal MUX_OUT outputted from the output terminal of the second inverter 53 .

[0056] Further, such as Figure 4 As shown, the multiplexing array 52 includes: four second delay units 521, a plurality of multiplexing units 522 and a plurality of logic units 523. In this embodiment, the number of the multiplexing units 522 is 4n, where n is an integer greater than or equal to 1. The 4n multiplexing units 522 are connected in sequence, the output ends of the four second delay units 521 are connected to the four input ends of the first multiplexing unit, the logic units 523 are grouped in pairs, each group of logic units 523 controls one of the multiplexing units 522, and each group of logic units 523 receives the first selection signal S0 and the second selection signal S1 input from the outside, respectively, and performs logic operation processing on the first selection signal S0 and the second selection signal S1 to output the fourth control signal and the fifth control signal to the corresponding multiplexing unit.

[0057] Among them, the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal are respectively input by the second selector 51 and output by the last multiplexing unit 522, and the number of path signals passing through the four ends of the multiplexing unit 522 is the same to offset the delay time of the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal from input to output of the data selection module 50.

[0058] Furthermore, only when the delays of D, CLK, Q, and QN reaching the D end of the double edge balance register (SAFF) 60 are the same, can the setup critical value difference of SAFF be used as the test data of the setup, hold, CLK→Q and other parameters (OCV). In this embodiment, the multiplexing array 52 is used to ensure that the number of four ends of each path passing through the multiplexing unit 522 is the same, thereby offsetting the delay difference from the four input ends to the output of the data selection module 50.

[0059] Specifically, the four-terminal data transmission path of the data selection module 50 is as follows:

[0060] 1)DUT / D→OCV_DELAY→A0→A1→A2→A3→A0→······→A0→A1→A2→A3→OCV_SAFF / D;

[0061] 2)DUT / CLK→OCV_DELAY→A1→A2→A3→A0→A1→······→A1→A2→A3→A0→OCV_SAFF / D;

[0062] 3)DUT / Q→OCV_DELAY→A2→A3→A0→A1→A2→······→A2→A3→A0→A1→OCV_SAFF / D;

[0063] 4)DUT / QN→OCV_DELAY→A3→A0→A1→A2→A3→······→A3→A0→A1→A2→OCV_SAFF / D.

[0064] The delay of each end of the multiplexing array 52 can be measured and adjusted at the same time. The multiplexing array 52 can generate an oscillating waveform through the control end MODE1_sel to MODE4_sel port of the second selector (MUX_MODE1-4) 51, and the second intermediate signal MUX_OUT is output through the output port of the second inverter 53. By adjusting each of the second delay units (OCV_DELAY) 521, the delay time of the output waveform of each path can be adjusted. By changing the delay, the period of the oscillating waveform of the four ends is made the same, thereby offsetting the delay difference from the four input ends to the output of the data selection module 50.

[0065] The present application obtains the total delay time by comparing the waveforms of the fourth data signal and the test clock signal, and obtains the delay time of the second clock delay module and the data selection module by collecting the waveforms of the signals output by the second clock delay module and the data selection module (the waveforms of the first intermediate signal and the second intermediate signal), so that the timing deviation (OCV parameter) of the circuit to be measured can be obtained by calculation.

[0066] Based on the same inventive concept, the present application embodiment also provides a test system, please refer to Figure 1 The test system includes: a trigger 70 and a circuit for measuring the OCV parameters of the device, and the circuit for measuring the OCV parameters of the device includes: a data delay module 10, a first clock delay module 20, a second clock delay module 30, a level selection module 40, a data selection module 50 and a balance register 60. The output end of the level selection module 40 is connected to the D end of the trigger 70, the output end of the first clock delay module 20 is connected to the CLK end of the trigger 70, and the Q end and Q' end of the trigger 70 are respectively connected to any two input ends of the data selection module 50. The total delay time is obtained by comparing the waveforms of the fourth data signal and the test clock signal, and the delay time of the second clock delay module 30 and the data selection module 50 is obtained by collecting the waveforms of the signals output by the second clock delay module 30 and the data selection module 50, and the OCV parameters of the trigger 70 are obtained by calculation. Specifically, the OCV parameters of the trigger 70 may include: setup time, hold time and CLK to Q time. The specific delay and measurement working process of the test system can refer to the working process of the circuit system taking the DFF trigger as the circuit to be measured as an example, and will not be repeated in this embodiment.

[0067] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A circuit for measuring the OCV parameters of a device, It is characterized in that include: A data delay module, used for receiving an externally input test clock signal and a first control signal, and performing delay processing on the test clock signal according to the first control signal to output a first delayed data signal to a subsequent stage; A first clock delay module, used for receiving the test clock signal and a second control signal input from the outside, and delaying the test clock signal according to the second control signal to output a first delayed clock signal to a subsequent stage; A second clock delay module, used for receiving the test clock signal and a third control signal inputted from the outside, and performing delay processing on the test clock signal according to the third control signal to output a second delayed clock signal to a subsequent stage, and outputting a first intermediate signal for measuring delay; a level selection module, configured to receive the first delayed data signal output by the data delay module and a fourth control signal input from the outside, and perform a logic operation on the first delayed data signal according to the fourth control signal to output a second delayed data signal to a subsequent stage; a data selection module, configured to receive a first selection signal and a second selection signal inputted from the outside, the second delayed data signal outputted by the level selection module, the first delayed clock signal outputted by the first clock delay module, and the first data signal and the second data signal outputted by the circuit to be measured, and to perform delay cancellation processing on the second delayed data signal, the first delayed clock signal, the first data signal, and the second data signal according to the first selection signal and the second selection signal to output a third data signal to a subsequent stage, and to output a second intermediate signal for measuring delay; and a balance register, used for receiving the second delayed clock signal output by the second clock delay module and the third data signal output by the data selection module, and outputting a fourth data signal to a subsequent stage; The total delay time is obtained by comparing the waveforms of the fourth data signal and the test clock signal, the delay time of the second clock delay module and the data selection module are respectively obtained by collecting the waveforms of the signals output by the second clock delay module and the data selection module, and the OCV parameters of the circuit to be measured are obtained by calculation, wherein the OCV parameters include: setup time, hold time, and CLK to Q time; The data selection module includes: a plurality of second selectors, a multiplexing array and a second inverter, the multiplexing array includes a plurality of input terminals and an output terminal, wherein two input terminals receive a first selection signal and a second selection signal input from the outside, and the remaining input terminals are respectively connected to the output terminals of each second selector correspondingly, the output terminal of the multiplexing array is connected to the input terminal of the second inverter, and is connected to the data input terminal of the balancing register to provide the third data signal to the balancing register, the output terminal of the second inverter is connected to an input terminal of each second selector to provide the second intermediate signal to each second selector, and the other input terminal of each second selector receives the first data signal and the second data signal output by the circuit to be measured, the second delayed data signal output by the level selection module, and the first delayed clock signal output by the first clock delay module; wherein, by controlling different test modes of the second selector, the second intermediate signal or the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal are selected to be provided to the multiplexing array via the second selector; Wherein, the delay time of the data selection module is obtained by measuring the period of the waveform of the second intermediate signal outputted from the output terminal of the second inverter; Wherein, the multiplexing array comprises: a plurality of second delay units, a plurality of multiplexing units and a plurality of logic units, the plurality of multiplexing units are connected in sequence, the output ends of the plurality of second delay units are connected to the plurality of input ends of the first multiplexing unit, the logic units are grouped in pairs, each group of logic units controls a corresponding multiplexing unit, each group of logic units respectively receives the first selection signal and the second selection signal input from the outside, and performs logic operation processing on the first selection signal and the second selection signal to output a fourth control signal and a fifth control signal to the corresponding multiplexing unit; Among them, the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal are respectively input by the second selector and output by the last multiplexing unit, and the number of path signals passing through the four ends of the multiplexing unit is the same to offset the delay time of the first data signal, the second data signal, the second delayed data signal and the first delayed clock signal from input to output.

2. The circuit for measuring the OCV parameters of a device according to claim 1, It is characterized in that The second clock delay module also includes: a first selector, at least one first inverter and at least one first delay unit, one first delay unit and one first inverter are connected in series to form a group, and the groups are connected in series in sequence, the output end of the first inverter in the last group is connected to an input end of the first selector, the other input end of the first selector receives the external input test clock signal, the output end of the first selector is connected to the input end of the first delay unit in the first group, each of the first delay units receives the third control signal, and the output end of the first delay unit in any group is connected to the input end of the balancing register to output the second delayed clock signal to the balancing register.

3. The circuit for measuring the OCV parameters of a device according to claim 2, It is characterized in that The number of the first inverters and the number of the first delay units are both eight. Eight groups of the first inverters and the first delay units are connected in series in sequence to form an oscillation circuit. By measuring the period of the waveform of the first intermediate signal output from the output end of the first selector, the period of the waveform of the third control signal and the test clock signal is adjusted to obtain the delay time of the second clock delay module.

4. The circuit for measuring the OCV parameters of a device according to claim 1, It is characterized in that The number of the multiplexing units is 4n, where n is an integer greater than or equal to 1.

5. The circuit for measuring the OCV parameters of a device according to claim 1, It is characterized in that The level selection module includes: a third inverter and a third selector, the output end of the third inverter is connected to an input end of the third selector, the input end of the third inverter and the other input end of the third selector are connected to the output end of the data delay module to receive the first delayed data signal, and according to the fourth control signal input externally, the output end of the third selector outputs the first delayed data signal or the inverse signal of the first delayed data signal to the circuit to be measured as the second delayed data signal.

6. The circuit for measuring the OCV parameters of a device according to claim 1, It is characterized in that The balancing register is a double-edge balancing register.

7. A test system, It is characterized in that include: A trigger and a circuit for measuring device OCV parameters as described in any one of claims 1 to 5, wherein the output end of the level selection module in the circuit for measuring device OCV parameters is connected to the D end of the trigger, the output end of the first clock delay module in the circuit for measuring device OCV parameters is connected to the CLK end of the trigger, and the Q end and Q' end of the trigger are respectively connected to any two input ends of the data selection module in the circuit for measuring device OCV parameters.

8. The test system according to claim 7, It is characterized in that The OCV parameters of the trigger include: setup time, hold time, and CLK to Q time.

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