A method for generating dense false targets based on piecewise reconstruction

Abstract

The application discloses a dense false target generation method based on segmentation reconstruction, which is applied to an FPGA provided with an IIR filter, a feedback branch of the IIR filter is provided with a register, and a forward branch of the IIR filter is connected with a RAM, and the method comprises the following steps: saving signals collected by a DRFM into the RAM; according to a minimum segmentation length, signal segments at each moment are sequentially obtained from the DRFM, and after register delay and accumulation, corresponding accumulated values at each moment are obtained; after the obtained signal segments reach a given false target number M, signal segments before M moments at each moment are sequentially obtained from a starting position of the external RAM according to the minimum segmentation length, and the corresponding accumulated values at each moment are subtracted from corresponding signal segment data obtained from the external RAM, and the corresponding accumulated values at each moment are taken as data of signal segments at each moment of the dense false target signal. The application overcomes the problem that the segmentation reconstruction method consumes too much storage resource when the total delay length is large.

Description

TECHNICAL FIELD

[0001] The present application relates to radar signal processing technology, in particular to a kind of dense false target generation method based on segmentation reconstruction. BACKGROUND

[0002] Dense false target jamming is an important technology in electronic countermeasure, aiming at quickly consuming the radar resources of the other party.

[0003] The current dense false target generation method includes two ways based on non-full pulse storage and based on full pulse storage, wherein when full pulse storage method carries out false target jamming, after receiving a complete radar pulse, if only simply and continuously copying and forwarding complete waveform radar pulse signal, the interval of the generated false target is large. To realize dense false target jamming, there are three categories based on DRFM full pulse sampling to realize dense false target jamming: delay superposition method, segmentation reconstruction method and convolution method. Although the false target generated by convolution method can be closer to the real platform, since the jamming signal is partially matched with the compression network, it cannot fully obtain the signal processing benefit of radar, the compression main peak is widened, and the power will be greatly lost, which requires a large amount of storage space and complex convolution operation, so it is less used in engineering implementation. The delay superposition method has good phase correlation, but it needs to delay and superimpose the collected signal multiple times, and the false target lags behind the real target by at least one pulse width time. When facing a large time width signal, it will face the problem of insufficient storage resources, so it is suitable for narrow pulse scenarios. In addition, the delay superposition method and the convolution method for generating dense false targets occupy a large amount of storage resources and require a large number of multiplication operations.

[0004] The segmentation reconstruction method generates signals with good matching, small calculation amount, and less storage space consumption. Therefore, it is more suitable for engineering implementation. However, the storage space required by the segmentation reconstruction method is proportional to the maximum delay in the dense false target, which leads to a linear increase in the storage resources consumed by the generation of dense false targets as the total delay length increases. When the number of false targets is large and the target interval is large, a large amount of storage resources are also required. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a dense false target generation method based on segmentation reconstruction to overcome the problem of excessive storage resource consumption of the segmentation reconstruction method when the total delay length is large.

[0006] To solve the above technical problems, the technical scheme adopted by the present application is:

[0007] A dense false target generation method based on segmentation reconstruction is applied to FPGA, an IIR filter is provided in the FPGA, a register is provided in the feedback branch of the IIR filter, a RAM is connected to the forward branch of the IIR filter, and the method comprises the following steps:

[0008] S1) saving the signal collected by the DRFM into the RAM;

[0009] S2) obtaining the signal segment of each time from the DRFM according to the minimum segment length, obtaining the accumulated value corresponding to each time after register delay and accumulation, if the obtained signal segment does not reach the given number of false targets M, taking the accumulated value corresponding to each time as the data of the signal segment of each time of the dense false target signal, if the obtained signal segment reaches the given number of false targets M, obtaining the signal segment of each time before M from the starting position of the external RAM according to the minimum segment length, subtracting the corresponding signal segment data obtained from the external RAM from the accumulated value corresponding to each time, and taking the accumulated value corresponding to each time as the data of the signal segment of each time of the dense false target signal.

[0010] Further, step S2) specifically includes the following steps:

[0011] S21) obtaining the signal segment s(K) from the DRFM, writing the data of the signal segment s(K) into the register, then adding the written data and the previous accumulated value to obtain the accumulated value of the current time;

[0012] S22) if the number of signal segments obtained from the DRFM is less than the given number of false targets M, outputting the accumulated value of the current time as the data of the signal segment g(K) of the dense false target signal;

[0013] S23) if the number of signal segments obtained from the DRFM is greater than or equal to the given number of false targets M, obtaining the signal segment s(K-M) from the external RAM, then outputting the accumulated value of the current time after subtracting the data of s(K-M) as the data of the signal segment g(K) of the dense false target signal.

[0014] Further, step S2) further includes the step of determining the minimum segment length, specifically including: taking the interval L between the dense false targets as the minimum segment length.

[0015] Further, the FPGA includes a first cache area and a second cache area, the lengths of the first cache area and the second cache area are both the minimum segment length, and step S21) includes the following steps:

[0016] writing the data of the signal segment s(K) into the first cache area after register delay;

[0017] reading the data of the signal segment s(K) in the first cache area and the previous accumulated value in the second cache area, and adding the data of the signal segment s(K) and the previous accumulated value to obtain the accumulated value of the current time;

[0018] writing the accumulated value of the current time into the second cache area.

[0019] Furthermore, the register length and the minimum segment length are the same.

[0020] The present invention also proposes a radar jammer, including an FPGA, wherein the FPGA is provided with an IIR filter, the feedback branch of the IIR filter is provided with a register, the forward branch of the IIR filter is connected to RAM, and the FPGA is programmed or configured to execute any of the described dense false target generation methods based on segmented reconstruction.

[0021] The present invention also proposes a computer-readable storage medium storing a computer program programmed or configured to perform any of the described segmented reconstruction-based dense false target generation methods.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] This invention incorporates an IIR (Infinite Length Unit Impulse Response) filter within an FPGA. The feedback branch of this filter uses registers for delay, while the forward branch uses external RAM to store the acquired signal. Samples from the DRFM are read sequentially according to segment lengths and accumulated. Once the number of read segments reaches a given number of false targets, the acquired sequence is simultaneously read sequentially from the external RAM according to segment lengths. During each accumulation, the accumulated value is subtracted from the acquired sequence read from the external RAM. Compared to existing segmented reconstruction methods, this invention only requires delaying the shortest signal segment length, reducing the FPGA's internal register resource consumption to... The greater the number of dense fake targets to be generated, the greater the improvement compared to traditional methods.

[0024] This invention retains the characteristics of fast forwarding, no complex calculations, and good coherence of the signal segmentation reconstruction method. RAM data is read sequentially without any other complex address control or write-back. The reading action is initiated under the control of the internal counter. The reading rate is consistent with the signal sampling rate and the FPGA internal processing rate. Therefore, there is no complex external storage control timing. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the segmented reconstruction method.

[0026] Figure 2 This is a schematic diagram of an IIR filter.

[0027] Figure 3 This is a flowchart of an embodiment of the present invention. Detailed Implementation

[0028] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0029] Before introducing specific embodiments of the present invention, relevant concepts will be explained.

[0030] Segmented Reconstruction Method: The segmented reconstruction method aims to solve the problem of large storage requirements when generating dense pseudo-targets using the delayed superposition method, such as... Figure 1 As shown, the data of the signal to be interfered with, s(n), of length N, is divided into K segments with an interval L of dense false targets, i.e. Given M false targets, the signal s(n) data needs to be sequentially delayed by L points. This delay is repeated M times according to the interference requirements. The data from these M delays are then arranged in chronological order and accumulated to obtain the new signal data g(n), which is the dense false target signal. g(n) consists of (M+N-1) data segments. The entire process involves only addition operations, without multiplication. Furthermore, the signal reconstruction method enables rapid signal forwarding, allowing the forwarded interference signal to be as close as possible to the leading edge of the echo, thus improving the interference effectiveness.

[0031] When using the segmented reconstruction method in FPGAs, the common approach is based on FIR (Finite Impulse Response) filter banks. This involves setting up a separate delay circuit for each interference signal with a different forwarding time, and then superimposing the signals with different delays. Alternatively, a cascaded FIR filter approach can be used to polynomially combine different delays. However, regardless of the approach, both require M×L registers to achieve the maximum delay. As the number of delays M or the delay time L increases, the consumption of register resources also increases.

[0032] To control the increase in storage resource consumption as the total delay length increases, one solution is to generate dense false targets using pulse interception and superposition methods, and combine this with frequency shift modulation jamming techniques to achieve obfuscating interference with LFM radar. This method sacrifices some signal matching, and the number of signal relays and relay delay must satisfy a specific relationship, limiting its applicability to various application scenarios.

[0033] We consider reducing the register resource consumption of the signal segmentation reconstruction method by modifying the filter structure. Assuming that the dense fake targets are evenly spaced, the corresponding delay time of the jammer is equal. From a system perspective, the signal can be considered to pass through the following system:

[0034] (1)

[0035] The above expression is a geometric sequence, and its summation can be expressed as:

[0036] (2)

[0037] Formula (2) is an expression for an IIR (Infinite Impulse Response) filter, the principle of which is as follows: Figure 2 As shown, the IIR filter includes a feedback branch and a forward branch. The feedback branch completes the L-point delay and superposition reconstruction of the signal, while the forward branch completes the M-time delay of the signal. Taking the generation of 3 false targets as an example, assuming the signal is divided into 6 segments, the segmented reconstruction of the signal output by the IIR filter at each clock cycle is shown in Table 1. The table results show that the feedback branch of the IIR filter completes the successive delay and superposition reconstruction of the segmented signal, requiring only an L-stage register to complete the segmented delay. The forward branch of the IIR filter, however, involves sequentially subtracting the corresponding signal segments from the superimposed segments after clock C3, and this branch requires an M×L stage register for segmented signal delay.

[0038] Table 1. Schematic diagram of timing output delayed by 3 times.

[0039]

[0040] Example 1

[0041] This embodiment improves the forward branch of the IIR filter. Instead of using registers within the FPGA to handle the delay, the signal acquired by the DRFM (Digital Radio Frequency Memory) is stored in external RAM and read back into the FPGA after counting according to the corresponding clock. Thus, the only on-chip register consumption of the FPGA is the L-level register of the feedback branch, and the FPGA's on-chip register consumption equals the signal segment length, i.e., the minimum delay corresponding to the dense decoy spacing distance. Correspondingly, this example proposes a dense decoy generation method based on segmented reconstruction, applied to the improved FPGA, such as... Figure 3 As shown, after saving the DRFM-acquired signal to RAM, the interval L between dense fake targets is obtained as the minimum segment length. Then, samples in the DRFM are read sequentially according to the segment length, and accumulated with the previous accumulated value. The previous accumulated value is stored in a buffer of the same length, with an initial state of 0. After reaching the required number of fake targets, while continuing the segment reading and accumulation steps, the acquired sequence stored in the external RAM is read sequentially from the starting position in equal lengths. The accumulated value is subtracted from the acquired sequence segment before being output and stored, ready for the next accumulation step. These steps are repeated until the forwarding ends. Specifically, the steps include:

[0042] S1) Save the signal acquired by DRFM to the RAM of the forward branch of the IIR filter, and obtain the interval L between dense false targets as the minimum segment length;

[0043] S2) According to the minimum segment length, the signal segments at each time moment are sequentially obtained from the DRFM. After the register delay and accumulation of the IIR filter feedback branch, the cumulative value corresponding to each time moment is obtained. If the obtained signal segments do not reach the given number of false targets M, the cumulative value corresponding to each time moment is used as the data of the signal segments at each time moment of the dense false target signal. If the obtained signal segments reach the given number of false targets M, the signal segments M time moments before each time moment are also sequentially obtained from the starting position of the external RAM according to the minimum segment length. The cumulative value corresponding to each time moment is subtracted from the corresponding signal segment data obtained from the external RAM, and the cumulative value corresponding to each time moment is used as the data of the signal segments at each time moment of the dense false target signal.

[0044] Through the above steps, the method of this embodiment reduces the consumption of FPGA internal register resources compared to traditional signal segmentation reconstruction methods. The calculations within the chip are still limited to addition (subtraction), and there are no other complex calculations.

[0045] Furthermore, the forward branch delay of the filter is achieved by reading data from external RAM under the control of an internal counter. Operationally, there is only a read operation and no write-back operation; in terms of speed, the read speed is consistent with the FPGA processing speed, and there is no need to set the control clock rate separately; in terms of read and write addresses, the data stored in external RAM is read sequentially, and the address can be offset by a fixed length under clock control, without the need for complex address calculations.

[0046] like Figure 3 As shown, in this embodiment, the register of the IIR filter feedback branch is called the accumulation register. The length of the accumulation register is the same as the minimum segment length. Step S2) specifically includes the following steps:

[0047] S21) Obtain signal segment s(K) from DRFM and write the data of signal segment s(K) into the accumulation register to complete the L-point delay of the signal. Then add the written data to the previous accumulation value to obtain the current accumulation value.

[0048] S22) If the number of signal segments obtained from DRFM is less than the given number of false targets M, output the current cumulative value as the data of signal segment g(K) of dense false target signal, and return to step S21) until the forwarding ends, that is, the signal segments in DRFM are obtained.

[0049] S23) If the number of signal segments obtained from DRFM is greater than or equal to the given number of false targets M, obtain signal segment s(KM) from external RAM, subtract the data of s(KM) from the current accumulated value, and output it as the data of signal segment g(K) of dense false target signal, and return to step S21) until the forwarding ends, that is, the signal segments in external RAM are obtained.

[0050] In this embodiment, a first buffer and a second buffer are set up for the FPGA. The lengths of both the first buffer and the second buffer are the minimum segment lengths. Therefore, step S21) specifically includes the following steps:

[0051] The data of signal segment s(K) is written into the first buffer through the accumulation register;

[0052] Read the data of signal segment s(K) in the first buffer and the previous accumulated value in the second buffer, and add the data of signal segment s(K) and the previous accumulated value to obtain the current accumulated value;

[0053] The current accumulated value is written to the second buffer via the accumulated register.

[0054] Example 2

[0055] This embodiment proposes a radar jammer, including an FPGA. The FPGA is equipped with an IIR filter, the feedback branch of the IIR filter is equipped with a register, and the forward branch of the IIR filter is connected to RAM. The FPGA is programmed or configured to execute the dense false target generation method based on segmented reconstruction as described in Embodiment 1.

[0056] This embodiment also proposes a computer-readable storage medium storing a computer program programmed or configured to perform the segmented reconstruction-based dense false target generation method described in Embodiment 1.

[0057] In summary, the fundamental technology of this invention is the signal segmentation reconstruction method. Based on the timing characteristics of signal segment accumulation, the FPGA (Field-Programmable Gate Array) only needs two segment-length buffers to retain segment samples and previously accumulated values. External RAM (Random Access Memory) is used as the storage space for previous signal samples. Each calculation step iterates using the results of the previous step and prior information, thereby completing the signal segmentation reconstruction steps. Therefore, the consumption of on-chip storage resources is further reduced.

[0058] The present invention has the following advantages:

[0059] 1. The signal segmentation reconstruction method is completed by using IIR filters. The feedback branch with short delay is kept in the FPGA, while the forward branch with long delay is stored in external RAM to realize the delay. This greatly reduces the consumption of internal register resources in scenarios with a large number of dense fake targets.

[0060] 2. The sequential reading of external RAM data is controlled by an internal counter, eliminating the need for complex external storage control timing.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A method for generating dense false targets based on segmented reconstruction, characterized in that, Applied to an FPGA, wherein the FPGA is equipped with an IIR filter, the feedback branch of the IIR filter has a register, and the forward branch of the IIR filter is connected to RAM, the method includes the following steps: S1) Save the signal acquired by DRFM to RAM; S2) According to the minimum segment length, the signal segments at each time moment are obtained from the DRFM in sequence. After register delay and accumulation, the cumulative value corresponding to each time moment is obtained. If the number of signal segments obtained from the DRFM is less than the given number of false targets M, the cumulative value corresponding to each time moment is used as the data of the signal segments at each time moment of the dense false target signal. If the acquired signal segments reach the given number of false targets M, and according to the minimum segment length, the signal segments M time steps ago are acquired sequentially from the starting position of the external RAM, and the cumulative value corresponding to each time step is subtracted from the corresponding signal segment data acquired from the external RAM, and the cumulative value corresponding to each time step is used as the data of the signal segments of the dense false target signal at each time step.

2. The dense false target generation method based on segmented reconstruction according to claim 1, characterized in that, Before step S2), there is also a step of determining the minimum segment length, which specifically includes: obtaining the interval L between dense fake targets as the minimum segment length.

3. The dense false target generation method based on segmented reconstruction according to claim 1, characterized in that, The FPGA includes a first buffer and a second buffer, both of which have the minimum segment length. When obtaining the signal segments at each time step from the DRFM, and after register delay and accumulation, the cumulative value at each time step is obtained, the following steps are included: The data of signal segment s(K) is written into the first buffer through the register; Read the data of signal segment s(K) in the first buffer and the previous accumulated value in the second buffer, and add the data of signal segment s(K) and the previous accumulated value to obtain the current accumulated value; The accumulated value at the current moment is written to the second buffer via a register.

4. The method for generating dense false targets based on segmented reconstruction according to claim 1, characterized in that, The register length and the minimum segment length are the same.

5. A radar jammer, characterized in that, The method includes an FPGA, wherein the FPGA is equipped with an IIR filter, the feedback branch of the IIR filter is equipped with a register, the forward branch of the IIR filter is connected to RAM, and the FPGA is programmed or configured to execute the dense false target generation method based on segmented reconstruction as described in any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is programmed or configured to perform the dense pseudo-target generation method based on segmented reconstruction as described in any one of claims 1 to 4.

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