Filtering architecture with minimized transients

Abstract

The present disclosure relates to a filtering architecture with minimized transients. A digital microphone includes an analog-to-digital converter (ADC) and a digital filter system coupled to the ADC, where the digital filter system switches between a standard IIR filter architecture and a polyphase IIR filter architecture.

Description

[0001] Cross-references to related applications

[0002] This application is a partial continuation of U.S. Patent Application No. 18 / 494,567, filed on October 25, 2023, which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to filter architectures with minimized transients and corresponding methods. Background Technology

[0004] Digital microphones are well-known in the field. In digital microphones, customer demands for new features (such as dynamic acoustic overload point (AOP) switching) or increased signal-to-noise ratio (SNR) and reduced power consumption are increasing. In existing solutions, there is a trade-off between decompression performance (SNR / equalization noise, total harmonic distortion (THD)) and the presence of audible transients. These transients occur particularly during switching between operating modes of the digital microphone. Some existing solutions employ stronger low-pass filters (with lower cutoff frequencies), resulting in better signal reconstruction, but at the cost of longer audible transients. Summary of the Invention

[0005] According to an embodiment, the digital microphone includes: an analog-to-digital converter (ADC); and a digital filter system coupled to the ADC, wherein the digital filter system is configured to switch between a standard IIR filter architecture and a polyphase IIR filter architecture.

[0006] According to an embodiment, the digital filter system includes a switchable IIR filter configured to switch between a standard IIR filter architecture and a polyphase IIR filter architecture.

[0007] According to an embodiment, a digital filtering method for a digital microphone includes switching between a standard IIR filter architecture in a first operating mode of the digital microphone and a polyphase IIR filter architecture in a second operating mode of the digital microphone. Attached Figure Description

[0008] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0009] Figure 1A and Figure 1B It is a block diagram based on the existing logarithmic amplifier architecture;

[0010] Figure 2 This is a block diagram of an exemplary digital microphone that includes compression and decompression.

[0011] Figure 3According to the embodiments, it has a feature suitable for use Figure 2 A high-level block diagram of a digital filter for transient reduction in digital microphones;

[0012] Figure 4 , Figure 5 and Figure 6 According to the embodiments, it has a feature suitable for use Figure 2 A more detailed block diagram of the digital filter in the transient reduction circuit of a digital microphone;

[0013] Figure 7 This is the analog step response of a digital low-pass filter using a transient reduction circuit device according to an embodiment;

[0014] Figure 8 This is a block diagram of a digital filter with transient reduction circuitry, showing additional details related to the clock signal and the marking of internal circuit nodes;

[0015] Figure 9 Is with Figure 8 The sequence diagram associated with the block diagram; and

[0016] Figure 10 This is a flowchart of a digital filtering method for reducing transients in a digital microphone according to an embodiment.

[0017] Figure 11 This is a schematic diagram (L=2) of a standard filter topology used for upsampling with a digital finite impulse response (FIR) filter;

[0018] Figure 12 This is a schematic diagram (L=2) of a polyphase filter topology used for upsampling with a digital finite impulse response (FIR) filter.

[0019] Figure 13 This is a schematic diagram of a polyphase filter topology that operates at a high sampling rate;

[0020] Figure 14 This is a schematic diagram (L=2) of a switchable multiphase architecture for a finite impulse response (FIR) filter with minimized transients, according to an embodiment;

[0021] Figure 15 This is a schematic diagram (L=3) of a standard filter topology used for upsampling with a digital finite impulse response (FIR) filter;

[0022] Figure 16 This is a schematic diagram of a polyphase filter topology operating at a high sampling rate (L=3);

[0023] Figure 17This is a schematic diagram (L=3) of a switchable multiphase architecture for a finite impulse response (FIR) filter with minimized transients, according to an embodiment.

[0024] Figure 18 This is a schematic diagram of a switchable IIR filter operating in a first operating mode in a multiphase IIR filter architecture according to the first embodiment.

[0025] Figure 19 This is a schematic diagram of a switchable IIR filter operating in a second operating mode in a standard IIR filter architecture according to the first embodiment.

[0026] Figure 20 This is a schematic diagram of a switchable IIR filter according to a first embodiment, the switchable IIR filter including control circuitry for switching between a standard IIR filter architecture and a polyphase IIR filter architecture;

[0027] Figure 21 This is a schematic diagram of a switchable IIR filter operating in a first operating mode in a multiphase IIR filter architecture according to the second embodiment.

[0028] Figure 22 This is a schematic diagram of a switchable IIR filter operating in a second operating mode in a standard IIR filter architecture according to the second embodiment.

[0029] Figure 23 This is a schematic diagram of a switchable IIR filter according to a second embodiment, the switchable IIR filter including control circuitry for switching between a standard IIR filter architecture and a polyphase IIR filter architecture;

[0030] Figure 24 This is a schematic diagram of a switchable IIR filter operating in a first operating mode in a multiphase IIR filter architecture according to a third embodiment.

[0031] Figure 25 This is a schematic diagram of a switchable IIR filter operating in a second operating mode within a standard IIR filter architecture according to a third embodiment; and

[0032] Figure 26 This is a schematic diagram of a switchable IIR filter according to a third embodiment, the switchable IIR filter including control circuitry for switching between a standard IIR filter architecture and a polyphase IIR filter architecture. Detailed Implementation

[0033] The following discussion details the preparation and use of the currently preferred embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific ways of preparing and using the invention and do not limit the scope of the invention.

[0034] In the following detailed description, reference is made to the accompanying drawings, which form part of the description and illustrate, by way of illustration, specific embodiments in which the invention may be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. For example, features illustrated or described with respect to one embodiment may be used on or in combination with other embodiments to produce another embodiment. The invention is intended to include such modifications and variations. The use of specific language in the description of examples should not be construed as limiting the scope of the appended claims. The drawings are not necessarily to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same or similar elements are designated in different drawings by corresponding reference numerals.

[0035] The more stringent specifications of digital microphones led to the introduction of architectures using logarithmic amplifiers, such as... Figure 1A The logarithmic amplifier architecture 100A is shown. Figure 1A In this configuration, the analog input signal from the digital microphone is received by a logarithmic amplifier 102. The output signal of the logarithmic amplifier 102 is converted into a digital signal by an analog-to-digital converter (ADC) 104. The digital signal provided by the ADC 104 is then processed by a digital anti-logarithmic component 106. Another logarithmic amplifier architecture 100B is as follows... Figure 1B As shown, the logarithmic amplifier 102 is replaced by a summing circuit 110 and multiple linear amplifiers 108. The logarithmic amplifier architecture 100B is shown and described in more detail in co-pending U.S. Patent Application No. 17 / 660,120 entitled "Logarithmic Amplifiers in Silicon Microphones," which is incorporated herein by reference in its entirety.

[0036] In some embodiments described herein, ADC 104 may include a Σ-Δ ADC (Σ-Δ converter). According to the embodiments described in more detail below, the digital output of ADC 104 is reconstructed in the digital domain as "fast" as possible (e.g., through a low-pass filter with minimized transients), such as... Figure 2 The digital microphone 200 is depicted in block diagram format.

[0037] The digital microphone 200 includes a microelectromechanical system (MEMS) device 202 for converting sound waves into an analog output signal. In some embodiments, the MEMS device 202 includes a capacitive silicon MEMS device. The analog output signal of the MEMS device 202 is converted into a digital signal and digitally processed in an application-specific integrated circuit (ASIC) 204. The ASIC 204 includes a logarithmic amplifier 208, which may be the type described in the embodiments. Figure 1A or Figure 1B One of the logarithmic amplifiers shown is a logarithmic amplifier. The output of logarithmic amplifier 208 is coupled to the input of ADC 210, which may be a Σ-Δ ADC in the embodiments. The output of ADC 210 is coupled to the input of digital low-pass filter 212. Several embodiments of digital low-pass filter 212 are shown and described in detail below, which are specifically designed to minimize audible transients, particularly during switching operating modes of digital microphone 200. The output of digital low-pass filter 212 is coupled to the input of digital compression component 214. The output of digital compression component 214 is coupled to the input of digital filter 216. In the embodiments, digital filter 216 may be any suitable filter (e.g., offset compensation filter). In operation, digital filter 216 is used to compensate for offset. The output of digital filter 216 is coupled to the input of optional digital modulator 218, which converts the digital signal provided by digital filter 216 into a one-bit output signal on output digital bus 220. Finally, ASIC 204 receives a clock signal at node 206, which is then distributed to one or more of the aforementioned components.

[0038] The digital microphone 200 can switch operating modes during dynamic AOP switching. During switching, if no switching occurs during a zero-crossing period, a "step" can occur in the signal chain. This "step" generates transients in the digital filter chain, which degrades performance (e.g., audible artifacts). The digital low-pass filter 212 is designed to handle and reduce the effects of these audible artifacts in the various embodiments described below.

[0039] Figure 3 According to the embodiments, it has a feature suitable for use Figure 2A high-level block diagram of a transient-reducing digital filter system 300 for a digital microphone 200 is provided. The digital filter system 300 includes an input x(k) at node 310, a controlled upsampling component 302, a digital filter 304 (which may include a digital low-pass filter), a controlled downsampling component 306, and an output y(k) at node 312. The digital filter system 300 also includes a control unit 308 for receiving a trigger signal at node 314 and for generating a control signal (“ctr”) at node 316. When the trigger signal at node 314 is switched, interpolated samples are fed from the controlled upsampling component 302 to the digital filter system 300, implicitly changing the cutoff frequency of the digital filter 304. Synchronized with the interpolation, the output signal of the digital filter 304 is decimated by the controlled downsampling component 306. Generally, the length of the transient is limited by the impulse response of the digital filter 304. For example, if the length of the digital filter is “N” samples, then the length of the transient is also the maximum length of “N” samples. According to an embodiment, the digital microphone 200 exhibits reduced audible transients because the digital filter 304 is filled with interpolated samples "faster." After the filter is "filled," the control unit 308 switches back to a "normal" operating mode, in which the digital filter 304 is filled with uninterpolated samples at a normal sampling rate. In other words, according to an embodiment, interpolation (and decimation) of the digital filter system 300 is enabled until "N" samples have been applied to the digital filter 304, and then switches back to normal operating mode, in which interpolation (and decimation) is disabled.

[0040] In one embodiment, the digital filter system 300 includes a topology where the input of a controlled upsampling component 302 is a node 310 for receiving a digital input signal x(k). The output of the controlled upsampling component 302 is coupled to the input of a digital filter 304. The output of the digital filter 304 is coupled to the input of a controlled downsampling component 306. The output of the controlled downsampling component 306 is a node 312 for providing a digital output signal y(k). The input of the control unit 308 is a node 314 for receiving a trigger signal and an output for providing a control signal (“ctr”) for controlling the selective interpolation and decimation of the input signal samples. An example topology is shown below. Figure 3 As shown. Other topologies can be used to provide selective interpolation and decimation associated with digital filter 304.

[0041] exist Figure 4 The diagram illustrates an efficient implementation of the digital filter system 400. Interpolation is performed using a repeater and a multiplexer, and then the output signal of the digital filter 304 is downsampled (without additional filtering).

[0042] exist Figure 4In this configuration, the controlled upsampling component 302 includes a repeater 318A with an output coupled to a first input of a multiplexer 320. The multiplexer 320 includes a control input for receiving a "ctr" control signal. A second input of the multiplexer 320 is coupled to the input of the controlled upsampling component 302. The repeater 318A has a constant upsampling rate set by an integer "L," which specifies the number of additional samples added during interpolation. For example, L=2 means each incoming sample is forwarded once, and L=3 means each incoming sample is forwarded twice. Figure 4 In one embodiment, the integer "L" is constant during the operation modes of interpolation and decimation.

[0043] exist Figure 4 In this configuration, the controlled downsampling component 306 includes a decimation component 322A with an output coupled to a first input of a multiplexer 324. The multiplexer 324 includes a control input for receiving a "ctr" control signal. A second input of the multiplexer 320 is coupled to the input of the controlled downsampling component 306. The decimation component 322A has a constant downsampling rate, which is also set by an integer "L," in this case specifying the number of additional samples removed during decimation. For example, L=2 means that one of two forwarded samples is removed during decimation, and L=3 means that two of three forwarded samples are removed during decimation.

[0044] exist Figure 5 The diagram illustrates a variable interpolation / decimation alternative embodiment of a digital filter system 500. The digital filter system 500 includes a control unit 308 having: a first output at node 316 for providing the previously discussed “ctr” control signal; and a second output at node 326 for providing a “ctr_L” control signal, which controls the integer “L” for the variable transponder 318B and the variable decimation component 322B. For example, when the “ctr_L” signal is in a first state, “L” can assume a first value, and when the “ctr_L” signal is in a second state, “L” can assume a second value, where the first and second values ​​are different values. In this embodiment, the first value of “L” can be higher than the second value, meaning that the digital filter 304 is filled faster during the initial phase of interpolation than in subsequent phases of interpolation.

[0045] Figure 6 A digital filter system 600 is illustrated, wherein interpolation component 318C is configured to provide general interpolation components (higher-order interpolation). Higher-order interpolation may include polynomial interpolation, piecewise interpolation, "sinc" interpolation, and many other known interpolation techniques. Decimation component 322 is also configured to provide general decimation components.

[0046] exist Figure 4 , Figure 5 and Figure 6 In the embodiment shown, the information of the input signal x(k) at node 310 is interpolated to fill the digital filter 304 with “N” samples during the switching transient when switching between operating modes, and then the control unit 308 switches back to the “normal” operating mode after the switching transient when the interpolation is no longer used.

[0047] Figure 7 These are the simulated step responses of a digital low-pass filter using a transient reduction circuitry according to an embodiment, and the simulated step responses of a digital low-pass filter without a transient reduction circuitry (“Reference”). Interpolation with L=2 is used in the simulation. Figure 700 shows trace 704 associated with a digital low-pass filter without a transient reduction circuitry according to an embodiment, and trace 702 associated with a digital low-pass filter using a transient reduction circuitry. The x-axis unit is the number of samples, and the y-axis unit is an arbitrary size unit. Note that in Figure 700, trace 702 stabilizes to its final value before trace 704. In other words, using a transient reduction circuitry (controlled interpolation and controlled decimation) improves the transient response of the step function of the digital low-pass filter compared to the digital low-pass filter without a transient reduction circuitry.

[0048] Figure 8 This is a block diagram of a digital filter 800 with transient reduction circuitry, showing additional details related to the clock signal and internal circuit nodes. The digital filter system 800 and... Figure 5 The digital filter system 500 shown is essentially the same, except for additional details and marked internal circuit nodes described below. Figure 8 The diagram shows an ADC 210 with an input at node 328 and an output x(k) at node 310. The ADC 210 receives the CLK clock signal at node 206, the variable transponder 318B receives the CLK-INT clock signal at node 206A, and the variable decimation component 322B receives the CLK-DEC clock signal at node 206B. Figure 8 In the diagram, the output of digital filter 304 is labeled "z(t)" at node 330. Additionally, alternative decimation component 306A is as follows: Figure 8 As shown, this component is a unit delay component represented by Z-transform notation, where a delay of one sample (L=2) is used. In some embodiments, an alternative decimation component 306A can be used instead of the variable decimation component 322B. The operation of the digital filter system 800 is simulated using clock signals and all signals and nodes in the marked internal circuit nodes, and the corresponding timing diagram is as follows. Figure 9 As shown and described below.

[0049] Figure 9 Is with Figure 8 The timing diagram 900 associated with the block diagram illustrates various clock signals and internal node voltages during three operating modes of the digital microphone according to an embodiment. The three selectable modes include a first operating mode, which can be a low-power mode (low SNR mode) or a high-power mode (high SNR mode) occurring before time t1. The second operating mode is a transition mode in which controlled interpolation and controlled decimation occur in response to a trigger signal. The transition mode begins at time t1, continues through time t2, and ends at time t3. A first sub-transition mode begins at time t1 and ends at time t2. In a variable interpolation embodiment, the first sub-transition mode is associated with interpolation performed at a first rate. The second sub-transition mode begins at time t2 and ends at time t3. In a variable interpolation embodiment, the second sub-transition mode is associated with interpolation performed at a second rate lower than the first rate. A third operating mode, which can be a low-power mode (low SNR mode) or a high-power mode (high SNR mode), occurs before time t3.

[0050] The waveform below is as follows Figure 9 As shown: CLK-INT 206A' associated with node 206A, CTR-MUX 316' associated with node 316, CTR-L326' associated with node 326, CLK 206' associated with node 206, CLK-DEC 206B' associated with node 206B, TRIGGER 314' associated with node 314, X(t)310' associated with node 310, Z(t)330' associated with node 330, and Y(t)312' associated with node 312.

[0051] CLK-INT 206A' is shown at a relatively low clock rate in the first and third operating modes. During the first sub-transition mode, CLK-INT 206A' is shown at a first relatively high clock rate, and during the second sub-transition mode, CLK-INT 206A' is shown at a second relatively high clock rate, lower than the first relatively high clock rate. CTR-MUX 316' is shown low in the first and third operating modes, and high in the transition mode. CLK 206' and CLK-DEC 206B' are shown at relatively low clock rates in all operating modes. (In the embodiment, the output y[k] is always at a relatively low clock rate, and decimation is implemented via timing of register 306A.) The TRIGGER 314' signal is shown low in the first operating mode, but becomes high during the first operating mode, remains low in the transition mode, and becomes low in the third operating mode. X(t)310', Z(t)330', and Y(t)312' are complex digital signals, illustrating the effects of interpolation and decimation on digital data.

[0052] Figure 10 This is a flowchart of a digital filtering method 1000 for reducing transients in a digital microphone according to an embodiment. The method includes: in step 1002, in a first operating mode, upsampling a digital input signal to provide an interpolated digital signal, filtering the interpolated digital signal, and downsampling the interpolated digital signal to provide a digital output signal; and in step 1004, in a second operating mode, filtering the digital input signal to provide a digital output signal without upsampling or downsampling the digital input signal. In the digital filtering method 1000, the second operating mode includes a low-power operating mode or a high-power operating mode, and the first operating mode is a transition mode between the low-power operating mode and the high-power operating mode. In the digital filtering method 1000, upsampling the digital input signal includes constant or variable upsampling, and downsampling the interpolated digital signal includes constant or variable upsampling.

[0053] In another embodiment, Figure 14 and Figure 17 A digital filter structure, including a switchable FIR filter, is shown and described in more detail below to avoid the need for increased sampling frequencies. Figure 14 and Figure 17 The filter embodiment shown replaces Figures 1 to 12. Figure 10 As shown and about Figure 1 to Figure 10The described digital filter system is also an alternative to these digital filter systems. In transient operating mode, the switchable FIR filter is switched to a polyphase FIR filter architecture, and in low-power or high-power operating mode, the switchable FIR filter is switched to a standard FIR filter architecture. In embodiments, the switchable polyphase FIR filter uses a modified polyphase architecture to minimize the number of registers used in the filter.

[0054] To minimize transients, Figure 4 The digital filter system 400 operates at a sampling frequency L times higher for a finite time (based on the "ctr" control signal). The output signal of the digital filter system is decimated by L, and the sampling frequency is changed back to the standard sampling frequency based on the control signal.

[0055] In the embodiments, implementation Figure 4 The efficient switchable topology shown is implemented based on a fifth-order FIR filter, and as... Figure 14 and Figure 17 As shown and described in detail below. Advantageously, Figure 14 and Figure 17 The implementation does not require a higher sampling frequency.

[0056] Figure 11 An exemplary implementation of the difference (upsampled by a factor of L=2) depicted in a standard FIR filter system 1100 is shown. The standard FIR filter system 1100 includes a transponder 1108 coupled to an input x[k] and multiple unit delay components 1102A, 1102B, 1102C, 1102D, and 1102E, indicated by Z-transform notation. The multiple unit delay components are coupled to multiple multipliers 1104A(h0), 1104B(h1), 1104C(h2), 1104D(h3), 1104E(h4), and 1104F(h5). The output of each multiplier is the product of the input and the coefficients written into the multiplier. The multipliers are coupled to an adder 1106, whose output y[k] is the sum of all its inputs.

[0057] However, to avoid using higher sampling frequencies for digital FIR filters, it is common to use... Figure 6The digital FIR filter system 1200 shown is a multiphase topology. The digital FIR filter system 1200 includes a first filter section comprising unit delay components 1202A and 1202B, multipliers 1204A(h0), 1204B(h2), and 1204C(h4), and adder 1206A. The digital FIR filter system 1200 also includes a second filter section comprising unit delay components 1202C and 1202D, multipliers 1204D(h1), 1204E(h3), and 1204F(h5), and adder 1206B. The output of adder 1206A is coupled to transponder 1208A, and the output of adder 1206B is coupled to transponder 1208B. The output of transponder 1208A is coupled to adder 1210, and the output of transponder 1208B is coupled to adder 1210 via unit delay component 1202E. The output of adder 1210 is the output y[k] of digital FIR filter system 1200.

[0058] exist Figure 13 The digital FIR filter system 1300 illustrates a multiphase topology operating at a high sampling rate. The digital FIR filter system 1300 utilizes... Figure 12 The digital FIR filter system 1200 shown has the same unit delay components, multipliers, and adders. However, transponders 1208A and 1208B are not used. Instead, transponder 1302 is inserted between the input x[k] and the inputs of the first and second filter sections.

[0059] A potential drawback of the digital FIR filter system 1300 compared to the standard FIR filter system 1100 is that the number of registers required is doubled, resulting in relatively lower efficiency.

[0060] Figure 14 This illustrates the efficient switchable architecture of the switchable FIR filter 1400, which achieves... Figure 4 This functionality allows for avoiding higher sampling frequencies with minimal registers. To implement... Figure 4 The function shown, according to an embodiment, allows the switchable FIR filter 1400 to advantageously and efficiently switch between polyphase topologies and standard FIR filter implementations, thereby avoiding the use of higher clock frequencies.

[0061] The switchable FIR filter 1400 includes delay and multiplexer circuitry, comprising unit delay components (or registers) 1402A, 1402B, 1402C, and 1402D, and multiplexers 1408A, 1408B, 1408C, and 1408D. The input of multiplexer 1408A is coupled between the input and output of unit delay component 1402A. The input of multiplexer 1408B is coupled between the input and output of unit delay component 1402B. The input of multiplexer 1408C is coupled to the outputs of unit delay components 1402A and 1402C. The input of multiplexer 1408D is coupled to the outputs of unit delay components 1402B and 1402D.

[0062] The first filter section of the switchable FIR filter 1400 includes multipliers 1404A (h0), 1404B (h2), and 1404C (h4), and adder 1406A. Multiplier 1404A is coupled between unit delay component 1402A and adder 1406A, multiplier 1404B is coupled between unit delay component 1402B and adder 1406A, and multiplier 1404C is coupled between multiplier 1408D and adder 1406A. The second filter section of the switchable FIR filter 1400 includes multipliers 1404D (h1), 1404E (h3), and 1404F (h5), and adder 1406B. Multiplier 1404D is coupled between unit delay component 1402A and adder 1406B, multiplier 1404E is coupled between unit delay component 1402B and adder 1406B, and multiplier 1404F is coupled between multiplier 1408D and adder 1406B.

[0063] The switchable FIR filter 1400 also includes a unit delay component 1402E, a multiplexer 1408E, an adder 1410, and a control unit 1412. The input to the control unit 1412 receives a trigger signal at node 1414 and provides a “ctr” control signal at node 1416. The control inputs of multiplexers 1408A, 1408B, 1408C, 1408D, and 1408E are coupled to node 1416 to receive the trigger signal. The output of adder 1406A is coupled to the first input of adder 1410, and the output of multiplexer 1408E is coupled to the second input of adder 1410. The output of adder 1410 is the output y[k] of the switchable FIR filter 1400. The output of adder 1406B is directly coupled to the first input of multiplexer 1408E, and indirectly coupled to the second input of multiplexer 1408E through unit delay component 1402E.

[0064] In fast transient mode (L=2), half of the registers of the switchable FIR filter 1400 are bypassed but preloaded accordingly. In fast transient mode, multiplexer 1408C takes the output of register 1402A (thus bypassing register 1402C), and multiplexer 1408A takes the input signal [x] and preloads register 1402C. This also applies to registers 1402D and 1402E. In normal operating mode (low power mode or high power mode), the preloaded registers are switched in, and this configuration represents the function of the FIR filter. In other words, in fast transient mode, the following components are bypassed: registers 1402C, 1402D, and 1402E. In this way, a polyphase FIR filter architecture is provided. In normal operating mode, none of these registers are bypassed. In this way, a standard FIR filter architecture is provided.

[0065] The switchable FIR filter 1400 advantageously provides a topology that reduces the transients of the digital FIR filter, thereby avoiding higher sampling frequencies. This, in turn, advantageously results in relatively low power consumption, as the clock tree of the corresponding digital microphone can be designed based on a single down-clocked clock signal.

[0066] exist Figure 14 The switchable FIR filter architecture is described for an interpolation factor L=2. The switchable FIR filter architecture can be generalized to include other interpolation factors, such as L=3. Other higher interpolation factors, such as L=4 or L=5, can also be used, or even larger interpolation factors if desired.

[0067] Figure 15 This is a schematic diagram (L=3) of a standard filter topology used for upsampling with a Universal Digital Finite Impulse Response (FIR) Filter System 1500. The Universal Digital FIR Filter System 1500 is... Figure 4 The standard implementation of the function shown. The general-purpose digital FIR filter system 1500 includes an interpolation component 1508 having an interpolation factor of L=3 for receiving a digital input signal x[k]. The interpolation component 1508 is coupled to a standard topology digital filter, which includes unit delay components 1502A, 1502B, ..., 1502C and 1502D, and multipliers 1504A(h0), 1504B(h1), 1504C(h2), 1504D(h3), ..., 1504D(h40 ... N-2 ), 1504E(h N-1 ) and 1504F(h N ), and adder 1506, for providing digital output signal y[k].

[0068] Figure 16 This is a schematic diagram (L=3) of a polyphase FIR filter 1600 with a polyphase FIR filter topology operating at a high sampling rate. The polyphase FIR filter 1600 is an intermediate implementation operating at a high sampling frequency, and Figure 17 The switchable FIR filter topology is shown. The polyphase FIR filter 1600 includes three branches and three inter-coefficient delays. These two parameters (the number of branches and the number of inter-coefficient delays) are generally limited by the interpolation factor L = 3. The first branch includes unit delays 1602A, ..., 1602B, multipliers 1604A(h0), 1604B(h3), and 1604A(h400). N-2 The second branch includes unit delays 1602C, ..., 1602D, multipliers 1604D(h1), 1604E(h4), and 1604F(h2). N-1 The third branch includes unit delays 1602E, ..., 1602F, multipliers 1604G(h2), 1604H(h5), and 1604I(h6). N Adder 1606A and adder 1606C. The output of adder 1606A is coupled to adder 1610A, which in turn provides a digital output signal y[k]. The output of adder 1606B is coupled to adder 1610B, which in turn is coupled to adder 1610A via unit delay component 1602G. The output of adder 1606C is coupled to unit delay component 1602H, which in turn is coupled to adder 1610B.

[0069] Figure 17 This is a schematic diagram (L=3) of a switchable multiphase architecture for a finite impulse response (FIR) filter with minimized transients, according to an embodiment. Figure 17 The switchable FIR filter 1700 shown includes a multiplexer and delay circuitry coupled to three filter branches. In transient operation mode, the switchable FIR filter 1700 simulates a polyphase FIR filter topology without requiring a relatively high clock frequency. In normal operation mode, the switchable FIR filter 1700 simulates a standard FIR filter topology. Using control unit 1717, which generates a “ctr” control signal in response to a trigger signal at node 1714, the state of the multiplexer in the multiplexer and delay circuitry is altered. The state of the multiplexer then determines the specific topology of the switchable FIR filter 1700.

[0070] The multiplexer and delay circuitry includes unit delay components (or registers) 1702A, 1702B, and 1702C, which are coupled to multiplexers 1708A, 1708B, and 1708C. Each multiplexer receives a “ctr” control signal at its control input. Sub-circuits of unit delay components 1702A, 1702B, and 1702C, as well as multiplexers 1708A, 1708B, and 1708C, are repeated according to the interpolation factor requirements of the filter. For example, in a switchable FIR filter 1700, the multiplexer and delay sub-circuitry are repeated once and include unit delay components 1702D, 1702E, and 1702F, which are coupled to multiplexers 1708D, 1708E, and 1708F.

[0071] The switchable FIR filter 1700 includes a first filter branch, which includes multipliers 1704A(h0), 1704B(h3), and 1704C(h4). N-2 The second filter branch includes multipliers 1704D(h1), 1704E(h4), and 1704F(h1). Adder 1706A is coupled to adder 1710A. N-1 The third filter branch includes multipliers 1704G(h2), 1704H(h5), and 1704I(h6). Adder 1706B is coupled to adder 1710B. N Adder 1710A and adder 1706C are coupled together via multiplexer 1708H and unit delay component 1702H. In this embodiment, the output of adder 1710A provides a y[k] digital output signal. Adders 1710A and 1710B are coupled together via multiplexer 1708G and unit delay component 1702G. Adders 1710B and 1710C are coupled together via multiplexer 1708H and unit delay component 1702H.

[0072] In transient operating mode, the FIR Filter 1700 can be switched to simulate a standard FIR filter topology, and no registers are bypassed. In normal operating mode (low power mode or high power mode), the FIR Filter 1700 can be switched to simulate a polyphase FIR filter topology, and the following registers are bypassed: 1702B, 1702C, 1702E, 1702F, 1702G, and 1702H.

[0073] In short, Figure 14 and Figure 17 An embodiment of a switchable FIR filter topology is shown, which advantageously does not require a high clock frequency during transient modes, but provides... Figure 4The illustrated audible transient reduction circuit demonstrates full transient reduction functionality. Additionally, compared to a fully polyphase filter topology, the number of registers can be reduced, thereby also reducing power. The clock tree of a digital microphone incorporating a switchable FIR filter topology can also be simplified.

[0074] Figures 18 to 26 This is a schematic diagram of a switchable IIR filter that can switch between a transient operating mode (first operating mode) and a normal operating mode (second operating mode) to provide the same transient reduction function described above. The switchable IIR filter can be used for, for example... Figure 2 This is part of the filter system of the digital microphone 200 shown. In some digital microphone embodiments using the switchable IIR filter described below, the logarithmic amplifier 208 may be omitted.

[0075] Figure 18 This is a schematic diagram of a switchable infinite impulse response (IIR) filter 1800 operating in a first operating mode within a polyphase IIR filter architecture according to a first embodiment. The filter 1800 includes a first polyphase stage (polyphase "0") 1802, a second polyphase stage (polyphase "1") 1804, and a feedforward stage 1806. The filter 1800 configured in the polyphase IIR filter architecture includes a constant upsampling rate of 2.

[0076] The first multiphase stage 1802 includes an adder 1808 having a first input coupled to the filter input x[k], a second input coupled to the multiplier 1812 (-a2), and a third input coupled to the multiplier 1810 (-a1). The input of the multiplier 1810 is coupled to the y_p1[k]_del1 node. The first multiphase stage 1802 also includes a unit delay component 1814 coupled between the output of the adder 1808 (which is also the y_p0[k] node) and the input of the multiplier 1812.

[0077] The second multiphase stage 1804 includes an adder 1822 having a first input coupled to the filter input x[k], a second input coupled to the multiplier 1818 (-a1), and a third input coupled to the multiplier 1820 (-a2). The input of the multiplier 1818 is coupled to the y_p0[k] node, and the input of the multiplier 1820 is coupled to the y_p1[k]_del1 node. The second multiphase stage 1804 also includes a unit delay component 1816 coupled between the output of the adder 1822 (also at the y_p1[k] node) and the input of the multiplier 1820.

[0078] The feedforward stage 1806 includes an adder 1830 having a first input coupled to multiplier 1824(b0), a second input coupled to multiplier 1826(b1), and a third input coupled to multiplier 1828(b2). The input of multiplier 1824 is coupled to the y_p1[k] node, the input of multiplier 1826 is coupled to the y_p0[k] node, and the input of multiplier 1818 is coupled to the y_p1[k]_del1 node. The output of adder 1830 is coupled to the y[k] output of filter 1800.

[0079] Figure 19 This is a schematic diagram of a switchable IIR filter 1900 operating in a second operating mode within a standard IIR filter architecture according to the first embodiment. The filter 1900 includes only adders 1808, 1830, 1810, 1812, 1824, 1826, 1828, unit delay components 1814 and 1816, all of which have been previously described.

[0080] Figure 20 This is a schematic diagram of a switchable IIR filter 2000 according to a first embodiment. The switchable IIR filter 2000 includes control circuitry for switching between a standard IIR filter architecture and a polyphase IIR filter architecture. The control circuitry includes a control unit 1832 for receiving a trigger signal, wherein the control unit is coupled to at least one multiplexer, which is coupled to at least one multiplexer in each filter stage.

[0081] The first multiphase stage 1802 includes a multiplexer 1834 having a first input coupled to a multiplier 1810, a second input coupled to the output of an adder 1808, a control input coupled to a control unit 1832, and an output coupled to a unit delay component 1814.

[0082] The second multiphase stage 1804 includes a multiplexer 1836 having a first input coupled to the output of multiplier 1808, a second input coupled to the output of adder 1822, a control input coupled to control unit 1832, and an output coupled to unit delay component 1816.

[0083] The feedforward stage 1806 includes: a first multiplexer 1838 having a first input coupled to the output of adder 1808, a second input coupled to the output of adder 1822, and an output coupled to multiplier 1824; a second multiplexer 1840 having a first input coupled to the y_p1[k]_del1 node, a second input coupled to the y_p0[k] node, and an output coupled to multiplier 1826; and a third multiplexer 1842 having a first input coupled to multiplier 1812, a second input coupled to the y_p1[k]_del1 node, and an output coupled to multiplier 1828. Multiplexers 1838, 1840, and 1842 each include a control input coupled to control unit 1832. Each of the other components in the switchable IIR filter 2000 has been described above and is as follows. Figure 18 As shown.

[0084] Figure 21 This is a schematic diagram of a switchable infinite impulse response (IIR) filter 2100 operating in a first operating mode within a polyphase IIR filter architecture according to a second embodiment. The filter 2100 includes a first polyphase stage (polyphase "0") 2102, a second polyphase stage (polyphase "1") 2104, and a feedforward stage 2106. The filter 2100 configured in the polyphase IIR filter architecture includes a constant upsampling rate of 3.

[0085] The first multiphase stage 1802 includes an adder 2108 having a first input coupled to the filter input x[k], a second input coupled to multiplier 2114 (-a3), a third input coupled to multiplier 2112 (-a2), and a fourth input coupled to multiplier 2110 (-a1). The input of multiplier 2110 is coupled to the y_p1[k]_del1 node, and the input of multiplier 2112 is coupled to the y_p0[k]_del1 node. The first multiphase stage 1802 also includes a unit delay component 2116 coupled between the output of adder 2108 (also the y_p0[k] node) and the input of multiplier 2112.

[0086] The second multiphase stage 2104 includes an adder 1822 having a first input coupled to the filter input x[k], a second input coupled to multiplier 2122(-a1), a third input coupled to multiplier 2124(-a2), and a fourth input coupled to multiplier 2126. The inputs of multiplier 2122 are coupled to the y_p0[k] node, the inputs of multiplier 2124 are coupled to the y_p1[k]_del1 node, and the inputs of multiplier 2126 are coupled to the y_p0[k]_del1 node. The second multiphase stage 2104 also includes a unit delay component 2118 coupled between the output of adder 2128 and the y_p1[k]_del1 node. The second multiphase stage 2104 also includes a unit delay component 2120 coupled between the y_p1[k]_del1 node and the input of adder 2114.

[0087] The feedforward stage 2106 includes an adder 2138 having a first input coupled to multiplier 2130 (b0), a second input coupled to multiplier 2132 (b1), a third input coupled to multiplier 2134 (b2), and a fourth input coupled to multiplier 2136 (b3). The inputs of multiplier 2130 are coupled to the y_p1[k] node, the input of multiplier 2132 is coupled to the y_p0[k] node, the input of multiplier 2134 is coupled to the y_p1[k]_del1 node, and the input of multiplier 2136 is coupled to the y_p0[k]_del1 node. The output of adder 2138 is coupled to the y[k] output of filter 2100.

[0088] Figure 22 This is a schematic diagram of a switchable IIR filter 2200 operating in a second operating mode within a standard IIR filter architecture according to a second embodiment. The filter 2200 includes only adders 2108, 2138, multipliers 2110, 2112, 2114, 2130, 2132, 2134, 2136, unit delay components 2116, 2118, and 2120, all of which have been previously described.

[0089] Figure 23 This is a schematic diagram of a switchable IIR filter 2300 according to a second embodiment. The switchable IIR filter 2300 includes control circuitry for switching between a standard IIR filter architecture and a polyphase IIR filter architecture. The control circuitry includes a control unit 2107 for receiving a trigger signal, wherein the control circuitry is coupled to at least one multiplexer, which is coupled to at least one multiplexer in each filter stage.

[0090] The first multiphase stage 2102 includes a multiplexer 2140 having a first input coupled to a multiplier 2110, a second input coupled to the output of an adder 2108, a control input coupled to a control unit 2107, and an output coupled to a unit delay component 2116.

[0091] The second multiphase stage 2104 includes a multiplexer 2142 having a first input coupled to the output of adder 2108, a second input coupled to the output of adder 2128, a control input coupled to control unit 2107, and an output coupled to unit delay component 2118. The second multiphase stage 2104 also includes a multiplexer 2143 having a first input coupled to node y_p0[k]_del1, a second input coupled to node y_p1[k]_del1, a control input coupled to control unit 2107, and an output coupled to unit delay component 2120.

[0092] The feedforward stage 1806 includes: a first multiplexer 2144 having a first input coupled to the output of adder 2108, a second input coupled to the output of adder 2128, and an output coupled to multiplier 2130; a second multiplexer 2146 having a first input coupled to node y_p1[k]_del1, a second input coupled to node y_p0[k], and an output coupled to multiplier 2132; a third multiplexer 2148 having a first input coupled to node y_p0[k]_del1, a second input coupled to node y_p1[k]_del1, and an output coupled to multiplier 2134; and a fourth multiplexer 2150 having a first input coupled to multiplier 2114, a second input coupled to node y_p0[k]_del1, and an output coupled to multiplier 2136. Multiplexers 2144, 2146, 2148, and 2150 each include a control input coupled to control unit 2107. Each of the other components in the switchable IIR filter 2300 has been described above and as follows... Figure 21 As shown.

[0093] Figure 24 This is a schematic diagram of a switchable infinite impulse response (IIR) filter 2400 operating in a first operating mode within a polyphase IIR filter architecture according to a third embodiment. The filter 2400 includes a first polyphase stage (polyphase "0") 2402, a second polyphase stage (polyphase "1") 2404, a third polyphase stage (polyphase "2") 2406, and a feedforward stage 2408. The filter 2400 configured in the polyphase IIR filter architecture includes a constant upsampling rate of 3.

[0094] The first multiphase stage 2402 includes an adder 2410 having a first input coupled to a filter input x[k], a second input coupled to a multiplier 2416 (-a3), a third input coupled to a multiplier 2414 (-a2), and a fourth input coupled to a multiplier 2412 (-a1). The input of multiplier 2412 is coupled to the y_p2[k]_del1 node, the input of multiplier 2414 is coupled to the y_p1[k]_del1 node, and the input of multiplier 2416 is coupled to the y_p0[k]_del1 node. The first multiphase stage 2402 also includes a unit delay component 2418 coupled between the output of adder 2410 and the input of multiplier 2416.

[0095] The second multiphase stage 2404 includes an adder 2428 having a first input coupled to the filter input x[k], a second input coupled to multiplier 2422 (-a1), a third input coupled to multiplier 2424 (-a2), and a fourth input coupled to multiplier 2426 (-a3). The input of multiplier 2422 is coupled to the y_p0[k] node, the input of multiplier 2424 is coupled to the y_p2[k]_del1 node, and the input of multiplier 2426 is coupled to the y_p2[k]_del1 node. The second multiphase stage 2404 also includes a unit delay component 2420 coupled between the output of adder 2428 (also at the y_p1[k] node) and the y_p1[k]_del1 node.

[0096] The third multiphase stage 2406 includes an adder 2438 having a first input coupled to the filter input x[k], a second input coupled to multiplier 2432 (-a1), a third input coupled to multiplier 2434 (-a2), and a fourth input coupled to multiplier 2436 (-a3). The input of multiplier 2432 is coupled to the y_p0[k] node, and the input of multiplier 2434 is coupled to the y_p2[k]_del1 node. The third multiphase stage 2406 also includes a unit delay component 2430 coupled between the output of adder 2438 and the input of multiplier 2436.

[0097] The feedforward stage 2408 includes an adder 2448 having a first input coupled to multiplier 2440(b0), a second input coupled to multiplier 2442(b1), a third input coupled to multiplier 2444(b2), and a fourth input coupled to multiplier 2446(b3). The inputs of multiplier 2440 are coupled to the y_p2[k] node, the inputs of multiplier 2442 are coupled to the y_p1[k] node, the inputs of multiplier 2444 are coupled to y_p0[k], and the inputs of multiplier 2446 are coupled to the y_p0[k]_del1 node. The output of adder 2448 is coupled to the y[k] output of filter 2400.

[0098] Figure 25 This is a schematic diagram of a switchable IIR filter 2500 operating in a second operating mode within a standard IIR filter architecture according to a third embodiment. The filter 2500 includes only adders 2410, 2448, 2412, 2414, 2416, 2440, 2442, 2444, 2446, unit delay components 2418, 2420, and 2430, all of which have been previously described.

[0099] Figure 26 This is a schematic diagram of a switchable IIR filter 2600 according to a third embodiment. The switchable IIR filter 2600 includes control circuitry for switching between a standard IIR filter architecture and a polyphase IIR filter architecture. The control circuitry includes a control unit 2409 for receiving a trigger signal, wherein the control unit is coupled to at least one multiplexer, which is coupled to at least one multiplexer in each filter stage.

[0100] The first multiphase stage 2402 includes a multiplexer 2450 having a first input coupled to the y_p1[k]_del1 node, a second input coupled to the output of the adder 2410, a control input coupled to the control unit 2409, and an output coupled to the unit delay component 2418.

[0101] The second multiphase stage 2404 includes a multiplexer 2452 having a first input coupled to the y_p2[k]_del1 node, a second input coupled to the output of the adder 2428, a control input coupled to the control unit 2409, and an output coupled to the unit delay component 2420.

[0102] The third multiphase stage 2406 includes a multiplexer 2454 having a first input coupled to the y_1[k] node, a second input coupled to the output of the adder 2438, a control input coupled to the control unit 2409, and an output coupled to the unit delay component 2430.

[0103] The feedforward stage 2408 includes: a first multiplexer 2456 having a first input coupled to the output of adder 2410, a second input coupled to the output of adder 2438, and an output coupled to multiplier 2440; a second multiplexer 2458 having a first input coupled to node y_p2[k]_del1, a second input coupled to node y_p1[k], and an output coupled to multiplier 2442; a third multiplexer 2460 having a first input coupled to node y_p1[k]_del1, a second input coupled to node y_p0[k], and an output coupled to multiplier 2444; and a fourth multiplexer 2462 having a first input coupled to node y_p0[k]_del1, a second input coupled to node y_p0[k]_del1, and an output coupled to multiplier 2446. Each of the multiplexers in filter 2600 includes a control input coupled to control unit 2409. Each of the other components in switchable IIR filter 2000 is described above and as follows: Figure 24 As shown.

[0104] In short, Figures 18 to 26 This is a schematic diagram of an example of a switchable IIR filter with a specific filter order and a specific upsampling factor. It is important to note that other embodiments can be used to provide any desired upsampling factor or any order of switchable IIR filter. Those skilled in the art will recognize that the example of a switchable IIR filter can be extended to provide upsampling factors and filter orders other than those specifically described.

[0105] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entirety of the description and claims set forth herein.

[0106] Example 1. According to an embodiment, a digital microphone includes: a logarithmic amplifier; an analog-to-digital converter (ADC) coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; and a digital filter coupled to the digital decompression component, wherein the digital filter includes: a controlled upsampling component coupled to the input of the digital filter; and a controlled downsampling component coupled to the output of the digital filter.

[0107] Example 2. The digital microphone according to Example 1 also includes a controller having an input configured to receive a trigger signal and having a first output.

[0108] Example 3. A digital microphone according to any of the examples above, wherein the upsampling component includes a multiplexer having a control input coupled to a first output of a controller.

[0109] Example 4. A digital microphone according to any of the examples above, wherein the downsampling component includes a multiplexer having a control input coupled to a first output of a controller.

[0110] Example 5. A digital microphone based on any of the examples above, wherein the controller further includes a second output.

[0111] Example 6. A digital microphone according to any of the examples above, wherein the upsampling component includes a repeater having a control input coupled to a second output of a controller.

[0112] Example 7. A digital microphone according to any of the examples above, wherein the downsampling component includes a decimation component having a control input coupled to a second output of the controller.

[0113] Example 8. A digital microphone according to any of the examples above, wherein the upsampling component includes a constant interpolation transponder, a variable interpolation transponder, or a general interpolation component.

[0114] Example 9. A digital microphone according to any of the examples above, wherein the downsampling component includes a constant decimation component, a variable decimation component, or a general decimation component.

[0115] Example 10. A digital microphone according to any of the examples above, wherein the ADC includes a sigma-delta converter.

[0116] Example 11. According to an embodiment, a digital filter system includes: a controlled upsampling component coupled to an input of a digital filter; a digital filter having an input coupled to an output of the controlled upsampling component; a controlled downsampling component coupled to the output of the digital filter; and a controller having a trigger signal input and a first output coupled to a first control input of the controlled upsampling component and a first control input of the controlled downsampling component.

[0117] Example 12. A digital filter system according to Example 11, wherein the controller further includes a second output coupled to a second control input of a controlled upsampling component and a second control input of a controlled downsampling component.

[0118] Example 13. A digital filter system according to any of the examples above, wherein the upsampling component includes a constant interpolation transponder, a variable interpolation transponder, or a general interpolation component.

[0119] Example 14. A digital microphone according to any of the examples above, wherein the downsampling component includes a constant decimation component, a variable decimation component, or a general decimation component.

[0120] Example 15. A digital microphone according to any of the examples above, wherein at least one of the upsampling component and the downsampling component includes a multiplexer.

[0121] Example 16. According to an embodiment, the method includes: in a first operating mode, upsampling a digital input signal to provide an interpolated digital signal, filtering the interpolated digital signal, and downsampling the interpolated digital signal to provide a digital output signal; and in a second operating mode, filtering the digital input signal to provide a digital output signal without upsampling or downsampling the digital input signal.

[0122] Example 17. According to the method of Example 16, the second operating mode includes a low-power operating mode or a high-power operating mode.

[0123] Example 18. The method according to any of the above examples, wherein the first operating mode is a transition mode between a low-power operating mode and a high-power operating mode.

[0124] Example 19. The method according to any of the above examples, wherein upsampling of the digital input signal includes constant or variable upsampling.

[0125] Example 20. The method according to any of the examples above, wherein downsampling of the interpolated digital signal includes constant or variable upsampling.

[0126] Example 21. According to an embodiment, a digital filter system includes a switchable IIR filter configured to switch between a standard FIR filter architecture and a polyphase FIR filter architecture.

[0127] Example 22. A digital filter system according to Example 21, wherein the FIR filter includes a multiplexer switching circuit.

[0128] Example 23. A digital filtering method for a digital microphone, the method comprising: switching between a standard FIR filter architecture in a first operating mode of the digital microphone and a polyphase FIR filter architecture in a second operating mode of the digital microphone.

[0129] Example 24. A digital filtering method according to Example 23, wherein the FIR filter includes a multiplexer switching circuit for switching between a first operating mode and a second operating mode.

[0130] Example 25. A digital filtering method according to any of the examples above, wherein the multiplexer switching circuit includes a plurality of multiplexers, and wherein each of the plurality of multiplexers includes a control input for receiving a control signal.

[0131] Example 1A. According to an embodiment, a digital microphone includes: an analog-to-digital converter (ADC); and a digital filter system coupled to the ADC, wherein the digital filter system is configured to switch between a standard IIR filter architecture and a polyphase IIR filter architecture.

[0132] Example 2A. The digital microphone according to Example 1A also includes a controller having an input configured to receive a trigger signal and a first output coupled to a digital filter system.

[0133] Example 3A. A digital microphone according to any of the examples above, wherein the multiphase IIR filter architecture includes two or three constant upsampling rates.

[0134] Example 4A. A digital microphone according to any of the examples above, wherein the multiphase IIR filter architecture includes a first multiphase stage, a second multiphase stage, and a feedforward stage, the feedforward stage being coupled to the first multiphase stage and the second multiphase stage.

[0135] Example 5A. A digital microphone according to any of the examples above, wherein the multiphase IIR filter architecture includes a third multiphase stage, and wherein a feedforward stage is coupled to a first multiphase stage, a second multiphase stage, and a third multiphase stage.

[0136] Example 6A. A digital microphone according to any of the examples above, wherein the first multiphase stage, the second multiphase stage, and the feedforward stage each include at least one multiplexer.

[0137] Example 7A. A digital microphone based on any of the examples above, where each multiplexer is coupled to a controller.

[0138] Example 8A. According to an embodiment, a digital filter system includes a switchable IIR filter configured to switch between a standard IIR filter architecture and a polyphase IIR filter architecture.

[0139] Example 9A. A digital filter system according to Example 8A, wherein the switchable IIR filter includes a multiplexer switching circuit.

[0140] Example 10A. The digital filter system according to any of the above examples further includes a controller coupled to the multiplexer switching circuit.

[0141] Example 11A. A digital filter system according to any of the examples above, wherein the polyphase IIR filter architecture includes two or three constant upsampling rates.

[0142] Example 12A. A digital filter system according to any of the above examples, wherein the polyphase IIR filter architecture includes a second-order IIR filter architecture or a third-order IIR filter architecture.

[0143] Example 13A. A digital filter system according to any of the examples above, wherein the multiphase IIR filter architecture includes a feedforward stage and multiple multiphase stages.

[0144] Example 14A. A digital filter system according to any of the examples above, wherein a feedforward stage is coupled to each of a plurality of multiphase stages.

[0145] Example 15A. According to an embodiment, a digital filtering method for a digital microphone includes switching between a standard IIR filter architecture in a first operating mode of the digital microphone and a polyphase IIR filter architecture in a second operating mode of the digital microphone.

[0146] Example 16A. A digital filtering method according to Example 15A, wherein the polyphase IIR filter architecture includes a multiplexer switching circuit for switching between a first operating mode and a second operating mode.

[0147] Example 17A. A digital filtering method according to any of the examples above, wherein the multiplexer switching circuit includes a plurality of multiplexers, and wherein each of the plurality of multiplexers includes a control input for receiving a control signal.

[0148] Example 18A. A digital filtering method according to any of the examples above, wherein the polyphase IIR filter architecture includes two or three constant upsampling rates.

[0149] Example 19A. A digital filtering method according to any of the examples above, wherein the polyphase IIR filter architecture includes a second-order IIR filter architecture or a third-order IIR filter architecture.

[0150] Example 20A. A digital filtering method according to any of the examples above, wherein the multiphase IIR filter architecture includes a feedforward stage and multiple multiphase stages.

[0151] While the invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limited sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon referring to the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A digital microphone, comprising: Analog-to-digital converter (ADC); as well as A digital filter system is coupled to the ADC, wherein the digital filter system is configured to switch between a standard IIR filter architecture and a polyphase IIR filter architecture.

2. The digital microphone of claim 1 further includes a controller having an input configured to receive a trigger signal and a first output coupled to the digital filter system.

3. The digital microphone of claim 1, wherein the multiphase IIR filter architecture comprises a constant upsampling rate of two or three.

4. The digital microphone of claim 1, wherein the multiphase IIR filter architecture comprises a first multiphase stage, a second multiphase stage, and a feedforward stage, the feedforward stage being coupled to the first multiphase stage and the second multiphase stage.

5. The digital microphone of claim 4, wherein the multiphase IIR filter architecture includes a third multiphase stage, and wherein the feedforward stage is coupled to the first multiphase stage, the second multiphase stage, and the third multiphase stage.

6. The digital microphone of claim 4, wherein each of the first multiphase stage, the second multiphase stage, and the feedforward stage comprises at least one multiplexer.

7. The digital microphone of claim 6, wherein each multiplexer is coupled to a controller.

8. A digital filter system including a switchable IIR filter configured to switch between a standard IIR filter architecture and a polyphase IIR filter architecture.

9. The digital filter system according to claim 8, wherein the switchable IIR filter includes a multiplexer switching circuit.

10. The digital filter system of claim 9 further includes a controller coupled to the multiplexer switching circuit.

11. The digital filter system of claim 8, wherein the polyphase IIR filter architecture comprises a constant upsampling rate of two or three.

12. The digital filter system according to claim 8, wherein the polyphase IIR filter architecture includes a second-order IIR filter architecture or a third-order IIR filter architecture.

13. The digital filter system of claim 8, wherein the multiphase IIR filter architecture includes a feedforward stage and multiple multiphase stages.

14. The digital filter system of claim 13, wherein the feedforward stage is coupled to each of the plurality of multiphase stages.

15. A method of digital filtering for a digital microphone, the method comprising: Switching between a standard FIR filter architecture in the first operating mode of the digital microphone and a polyphase FIR filter architecture in the second operating mode of the digital microphone.

16. The digital filtering method according to claim 15, wherein the polyphase IIR filter architecture includes a multiplexer switching circuit for switching between the first operating mode and the second operating mode.

17. The digital filtering method according to claim 16, wherein the multiplexer switching circuit comprises a plurality of multiplexers, and each of the plurality of multiplexers includes a control input for receiving a control signal.

18. The digital filtering method of claim 15, wherein the polyphase IIR filter architecture comprises a constant upsampling rate of two or three.

19. The digital filtering method according to claim 15, wherein the polyphase IIR filter architecture includes a second-order IIR filter architecture or a third-order IIR filter architecture.

20. The digital filtering method according to claim 15, wherein the polyphase IIR filter architecture includes a feedforward stage and multiple polyphase stages.

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